Semiconductor device

Abstract

The present application provides a semiconductor device capable of improving load variation damage resistance. A plurality of cells arranged in a first direction on a surface of a substrate each include at least one unit transistor. A collector electrode is arranged between two cells adjacent to each other. A first cell as at least one of the plurality of cells includes a plurality of unit transistors arranged in the first direction. The plurality of unit transistors are connected in parallel to each other. In the first cell, base electrodes and emitter electrodes of the plurality of unit transistors are arranged in the first direction, and the arrangement order of the base electrodes and the emitter electrodes is the same among the plurality of unit transistors. When one first cell is focused on, a maximum value of a distance in the first direction of the emitter electrodes of two unit transistors adjacent to each other within the first cell focused on is shorter than 1 / 2 of a shorter distance among distances in the first direction between the first cell focused on and cells adjacent thereto.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] As a transistor constituting a power amplifier module of a mobile body communication device, for example, a heterojunction bipolar transistor (HBT) is used. A higher collector voltage is applied to a bipolar transistor applied to an amplification circuit adopting an envelope tracking (ET) method which has attracted attention in recent years according to an envelope of a waveform of an input signal. In addition, in a process of popularization of a fifth generation mobile communication system (5G), a tendency of high output of a power amplifier becomes remarkable.

[0003] In order to realize introduction of the ET method and high output of the power amplifier, it is necessary to cause the bipolar transistor to operate at a high voltage. It is required to suppress damage caused by load variation even under a condition where the collector voltage is high. In Patent Documents 1 and 2 described below, an HBT having improved thermal stability is disclosed.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2005-101402

[0005] Patent Document 2: Japanese Patent Application Laid-Open No. 2006-185990

[0006] In the conventional HBT having improved thermal stability, although unstable operation called thermal runaway can be suppressed, damage resistance (load variation damage resistance) at the time when a load variation occurs under a condition where the collector voltage is high cannot be said to be sufficient. It is desired to further improve the load variation damage resistance under the condition where the collector voltage is high. SUMMARY

[0007] An object of the present application is to provide a semiconductor device capable of improving load variation damage resistance.

[0008] According to an aspect of the present application, there is provided a semiconductor device including:

[0009] a substrate;

[0010] a plurality of transistor units arranged along a first direction on a surface of the substrate, each of the transistor units including at least one unit transistor; and

[0011] collector electrodes arranged between two transistor units adjacent to each other, respectively,

[0012] a first transistor unit of the plurality of transistor units includes a plurality of unit transistors arranged along the first direction,

[0013] the plurality of unit transistors are connected in parallel to each other,

[0014] Each of the plurality of unit transistors includes a collector layer, a base layer disposed above the collector layer, an emitter layer disposed above the base layer, a base electrode electrically connected to the base layer, and an emitter electrode electrically connected to the emitter layer,

[0015] The collector electrode is electrically connected to the collector layer of the unit transistor included in the transistor unit adjacent in the first direction,

[0016] In the first transistor unit,

[0017] The base electrodes and the emitter electrodes of the plurality of unit transistors are arranged in the first direction, and the arrangement order of the base electrodes and the emitter electrodes is the same among the plurality of unit transistors,

[0018] When one of the first transistor units is focused on, a maximum value of an emitter electrode pitch is shorter than 1 / 2 of a shorter one of cell pitches, the emitter electrode pitch being a distance in the first direction between the emitter electrodes of two unit transistors adjacent to each other within the first transistor unit focused on, the cell pitch being a distance in the first direction between the first transistor unit focused on and a transistor unit adjacent to the first transistor unit focused on.

[0019] If the emitter electrode pitch and the cell pitch are set as described above, the thermal influence between the plurality of unit transistors within one first transistor unit increases, so the temperature of the collector layer easily rises. Therefore, when the collector current instantaneously increases due to a load variation, the ionization rate based on the impact ionization decreases, and the generation of electron-hole pairs is suppressed. As a result, it is possible to obtain excellent effects of suppressing further increase of the collector current and improving damage resistance at the time of a load variation. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a cross-sectional view of one transistor unit of the semiconductor device of the first embodiment.

[0021] Figure 2 is a view showing the planar positional relationship of each constituent element of one transistor unit of the semiconductor device of the first embodiment.

[0022] Figure 3 is a view showing the planar positional relationship of each constituent element of the semiconductor device of the first embodiment.

[0023] Figure 4 is an equivalent circuit diagram of the semiconductor device of the first embodiment.

[0024] Figure 5Fig. 1 is a plan view showing a positional relationship of a transistor unit of a semiconductor device of the first embodiment and collector electrodes on both sides thereof.

[0025] Figure 6 Fig. 2 is a plan view showing a positional relationship of each constituent element of a semiconductor device of a modification of the first embodiment.

[0026] Figure 7 Fig. 3 is a plan view showing a positional relationship of each constituent element of a semiconductor device of the second embodiment.

[0027] Figure 8 Fig. 4 is a plan view showing a positional relationship of each constituent element of a transistor unit of the semiconductor device of the second embodiment.

[0028] Figure 9 Fig. 5 is a plan view showing a positional relationship of each constituent element of a semiconductor device of a modification of the second embodiment.

[0029] Figure 10 Fig. 6 is a plan view showing a positional relationship of each constituent element of a transistor unit of the semiconductor device of the third embodiment.

[0030] Figure 11 Fig. 7 is a sectional view taken along the single-dot chain line 11-11 of Fig. 6. Figure 10

[0031] Figure 12A Figure 12B Figure 12C Figure 12D Figs. 8, 9, and 10 are graphs each showing one example of a distribution of a doping concentration (dopant concentration) in a depth direction of a collector layer.

[0032] Figure 13 Fig. 11 is a sectional view of a semiconductor device of a modification of the third embodiment.

[0033] Figure 14 Fig. 12 is a plan view showing a positional relationship of each constituent element of a semiconductor device of the fourth embodiment.

[0034] Figure 15 Fig. 13 is a plan view showing a positional relationship of each constituent element of a semiconductor device of the fifth embodiment.

[0035] Figure 16 Fig. 14 is a plan view showing a positional relationship of each constituent element of a semiconductor device of the sixth embodiment.

[0036] Figure 17 Fig. 15 is a plan view schematically showing a positional relationship of each constituent element of a semiconductor device of the seventh embodiment.

[0037] Figure 18 ​​​​Fig. 7 is a diagram schematically showing positional relations among the respective constituent elements of the semiconductor device of a modification of the seventh embodiment in plan view.

[0038] BRIEF DESCRIPTION OF THE DRAWINGS 20... transistor unit, 20A... first transistor unit, 20B... second transistor unit, 21... unit transistor, 21B... base layer, 21BM... base mesa, 21C... collector layer, 21CA... high concentration collector layer, 21CB... low concentration collector layer, 21CC... middle concentration collector layer, 21E... emitter layer, 21EM... emitter mesa, 21P... cap layer, 21T... contact layer, 22B... base electrode, 22BA... main portion of base electrode, 22BB... contact portion of base electrode, 22C... collector electrode, 22E... emitter electrode, 23... alloyed region, 25... step difference, 26... insulating region, 31B... base wiring of first layer, 31BW... base wiring widening portion, 31C... collector wiring of first layer, 31CC... collector common wiring, 31DB... direct current bias input wiring, 31E... emitter wiring of first layer, 31R... resistive element, 32C... collector wiring of second layer, 32E... emitter wiring of second layer, 32S... high frequency signal input wiring, 33C... collector bump, 33E... emitter bump, 35... capacitive element, 40... substrate, 41A... sub-collector layer, 41B... element separation region, 50... power supply circuit, 51... bias circuit, 52... inductor, 53... high frequency signal input port, 54... high frequency signal output port, Dl... first direction, D2... second direction, Lc... unit pitch, Le... emitter electrode pitch. DETAILED DESCRIPTION

[0039] [First Embodiment]

[0040] REFERENCE Figures 1-4 The semiconductor device of the first embodiment will be described with reference to the drawings.

[0041] Figure 1 Fig. 1 is a sectional view of one transistor unit 20 of the semiconductor device of the first embodiment. A semiconductor layer is epitaxially grown on a substrate 40 composed of a semiconductor. A part of the semiconductor layer becomes a sub-collector layer 41A having n-type conductivity, and the remaining part becomes an element separation region 41B which is insulated by impurity implantation. Two base mesas 21BM are disposed on the sub-collector layer 41A. The base mesa 21BM includes a collector layer 21C composed of an n-type semiconductor, a base layer 21B composed of a p-type semiconductor disposed on the collector layer 21C, and an emitter layer 21E composed of an n-type semiconductor disposed on the base layer 21B. An HBT is formed by the collector layer 21C, the base layer 21B, and the emitter layer 21E.

[0042] An emitter mesa 21EM is disposed on a part of the region of the base mesa 21BM. The emitter mesa 21EM includes a cap layer 21P made of an n-type semiconductor and a contact layer 21T made of an n-type semiconductor disposed on the cap layer 21P.

[0043] A base electrode 22B is disposed in a region of the upper surface of the base mesa 21BM in which the emitter mesa 21EM is not disposed. The base electrode 22B is electrically connected to the base layer 21B via an alloyed region 23 that penetrates the emitter layer 21E and reaches the base layer 21B. Further, a part of the emitter layer 21E can be removed to expose a part of the base layer 21B, and the base electrode 22B can be brought into ohmic contact with the exposed base layer 21B. An emitter electrode 22E is disposed on the emitter mesa 21EM. The emitter electrode 22E is electrically connected to the emitter layer 21E via the contact layer 21T and the cap layer 21P.

[0044] The emitter electrode 22E is projected in a brim shape from the edge of the emitter mesa 21EM in the lateral direction (a direction orthogonal to the thickness direction of the substrate 40). The structure in which the emitter electrode 22E is projected in a brim shape is formed, for example, by a self-alignment process.

[0045] A collector electrode 22C is disposed on each of the sub-collector layers 41A on both sides of the region in which the two base mesas 21BM are disposed. The collector electrode 22C is electrically connected to the collector layer 21C through the sub-collector layer 41A. One collector electrode 22C, two base mesas 21BM, and another collector electrode 22C are arranged in one direction.

[0046] The base mesa 21BM, the emitter mesa 21EM, the emitter electrode 22E, and the base electrode 22B constitute a unit transistor 21. One transistor unit 20 includes two unit transistors 21.

[0047] A first-layer emitter wiring 31E is disposed on the two emitter electrodes 22E. The emitter wiring 31E is electrically connected to the two emitter electrodes 22E. First-layer collector wirings 31C are disposed on the two collector electrodes 22C, respectively. The collector wirings 31C are electrically connected to the collector electrodes 22C directly below, respectively. An interlayer insulating film (omitted from the drawing in Figure 3

[0048] ​Next, one example of the material and thickness of the substrate 40, the sub-collector layer 41A, and each semiconductor layer of the unit transistor 21 will be described. As the substrate 40, semi-insulating GaAs is used. The sub-collector layer 41A is formed of Si with a doping concentration of 2 x 10 18 cm －3 or more and 4 x 10 18 cm －3 or less. The n-type GaAs below has a thickness of 400 nm or more and 1000 nm or less. Instead of Si, Te can be used as a dopant. The element isolation region 41B is formed by ion-implanting B, O, or He into the n-type GaAs layer to insulate it.

[0049] The collector layer 21C is formed of n-type GaAs doped with Si, and has a thickness of 500 nm or more and 2000 nm or less. The doping concentration of Si varies in the thickness direction. The doping concentration of the shallowest region is on the order of 10 15 cm －3 or 10 16 cm －3 , and the doping concentration of the deepest region is on the order of 10 18 cm －3 or more.

[0050] The base layer 21B is formed of p-type GaAs, InGaAs, GaInAsN, GaAsSb, or the like, and has a C doping concentration of 1 x 10 19 cm －3 or more and 5 x 10 19 cm －3 or less. The thickness of the base layer 21B is 50 nm or more and 150 nm or less. The sheet resistance of the base layer 21B is 130 Ω / D or more and 400 Ω / D or less.

[0051] The emitter layer 21E is formed of n-type InGaP with a Si doping concentration of 2 x 10 17 cm －3 or more and 5 x 10 17 cm －3 or less, and has a thickness of 20 nm or more and 50 nm or less. The cap layer 21P is formed of n-type GaAs with a Si doping concentration of 2 x 10 18 cm －3 or more and 4 x 10 18 cm －3 or less, and has a thickness of 50 nm or more and 200 nm or less. The contact layer 21T is formed of n-type GaAs with a Si doping concentration of 1 x 10 19 cm －3 or more and 3 x 10 19 cm －3The n-type InGaAs below has a thickness of 100 nm or more and 200 nm or less.

[0052] The sub-collector layer 41A, the collector layer 21C, the base layer 21B, and the emitter layer 21E can also be composed of a plurality of layers of different semiconductor materials or different compositions according to their respective roles and functions.

[0053] Figure 2 is a plan view showing the plan position relationship of the respective constituent elements of one transistor unit 20 of the semiconductor device of the first embodiment. Figure 2 The cross-sectional view at the single-dot chain line 1-1 of Figure 1 In Figure 2 In

[0054] Two base mesas 21BM are arranged in the first direction D1 inside the rectangular sub-collector layer 41A. Each base mesa 21BM has a shape that is longer in a second direction D2 orthogonal to the first direction D1. An emitter mesa 21EM is arranged inside each base mesa 21BM. The emitter mesa 21EM also has a shape that is longer in the second direction D2, and is arranged at a position that is biased toward the first direction D1 with respect to the base mesa 21BM.

[0055] The emitter electrode 22E is arranged so as to substantially overlap the emitter mesa 21EM, and the emitter electrode 22E also has a shape that is longer in the second direction D2, like the emitter mesa 21EM. As Figure 3 indicated, the emitter electrode 22E slightly expands to the outside from the edge of the emitter mesa 21EM. The shapes and sizes of the two emitter electrodes 22E are the same when viewed from above.

[0056] The base electrode 22B is arranged inside the base mesa 21BM and outside the emitter mesa 21EM. The base electrode 22B is composed of a main portion 22BA that is longer in the second direction D2, and a contact portion 22BB connected to one end of the main portion 22BA. The shapes and sizes of the two base electrodes 22B are the same when viewed from above. The main portions 21BA of the base electrodes 22B and the emitter electrodes 22E of the respective unit transistors 21 are arranged in the first direction D1, and the arrangement order of the main portions 21BA of the base electrodes 22B and the emitter electrodes 22E is the same between the two unit transistors 21.

[0057] In the second direction D2, the range in which the emitter electrode 22E is arranged is included in the range in which the main portion 22BA of the base electrode 22B is arranged. The contact portion 22BB of the base electrode 22B is arranged outside the range in which the emitter electrode 22E is arranged in the second direction D2.

[0058] The two base mesas 21BM corresponding to the two unit transistors 21 are separated apart by a space in the first direction Dl. Therefore, the emitter layer 21E, the base layer 21B, and the collector layer 21C of one unit transistor 21 are separated apart from the emitter layer 21E, the base layer 21B, and the collector layer 21C, respectively, of the other unit transistor 21. Figure 1

[0059] The first layer emitter wiring 31E overlaps the two emitter electrodes 22E, connecting the two emitter electrodes 22E to each other. In Figure 2 , the openings of the interlayer insulating film provided between the emitter electrodes 22E and the emitter wiring 31E are shown by dotted lines. The openings of the interlayer insulating film provided in the regions where the collector electrodes 22C and the base electrodes 22B are disposed are also shown by dotted lines.

[0060] The two collector electrodes 22C are disposed at positions sandwiching the two unit transistors 21 in the first direction Dl. Each collector electrode 22C also has a shape longer in the second direction D2. The two collector wirings 31C partially overlap the two collector electrodes 22C, respectively. The collector wirings 31C extend to the outside of the sub-collector layer 41A toward one side (in Figure 2 , the right side) of the second direction D2.

[0061] The two first layer base wirings 31B are connected to the contact portions 22BB of the two base electrodes 22B, respectively. The base wirings 31B extend to the outside of the sub-collector layer 41A toward one side (in Figure 2 , the left side) of the second direction D2 from the contact portions 22BB.

[0062] Next, one example of the dimensions of each constituent element in plan view will be described. The dimensions (widths) of the emitter mesa 21EM and the emitter electrodes 22E in the first direction Dl are 1 μm or more and 8 μm or less, and the dimensions (lengths) in the second direction D2 are 5 μm or more and 60 μm or less. The dimensions (widths) of the main portions 22BA of the base electrodes 22B in the first direction Dl are 0.5 μm or more and 1.5 μm or less. The interval between the emitter electrodes 22E and the main portions 22BA of the base electrodes 22B is 0.5 μm or more and 1.5 μm or less. The interval between the two base mesas 21BM is 5 μm or more and 10 μm or less. The interval between the two emitter electrodes 22E within the transistor unit 20 is 6 μm or more and 12 μm or less.

[0063] Figure 3 is a diagram showing the planar positional relationship of each constituent element of the semiconductor device of the first embodiment. In Figure 3 , the same as Figure 2 ​The emitter electrode 22E, the base electrode 22B, and the collector electrode 22C are similarly added with hatching. Four transistor units 20 are arranged in the first direction D1. The number of transistor units 20 is not limited to four, and can be two, three, or more than five.

[0064] The shape and size of the emitter electrode 22E of the unit transistor 21 included in the plurality of transistor units 20 are the same. The shape and size of the base electrode 22B of the unit transistor 21 included in the plurality of transistor units 20 are also the same. The arrangement order of the base electrode 22B and the emitter electrode 22E of the unit transistor 21 in the first direction D1 is the same among the plurality of transistor units 20.

[0065] Two collector electrodes 22C are arranged between the transistor units 20 adjacent to each other. One collector electrode 22C is arranged in the sub-collector layer 41A including one transistor unit 20, and the other collector electrode 22C is arranged in the sub-collector layer 41A including the other transistor unit 20. The collector electrodes 22C are arranged outside the transistor units 20 arranged at both ends in the first direction D1, respectively. The collector electrode 22C is electrically connected to the collector layer 21C of the unit transistor 21 included in the transistor unit 20 adjacent in the first direction D1. Figure 1

[0066] The first-layer collector wiring 31C extends from the collector electrode 22C toward one side in the second direction D2. The collector wirings 31C extending from the two collector electrodes 22C arranged between the transistor units 20 adjacent to each other are concentrated into one.

[0067] The first-layer collector common wiring 31CC is arranged on one side of the unit column in which the plurality of transistor units 20 are arranged. The plurality of collector wirings 31C are connected to the collector common wiring 31CC. The collector common wiring 31CC is arranged in the same metal wiring layer as the collector wiring 31C in the first layer.

[0068] The second-layer collector wiring 32C is arranged so as to overlap the collector common wiring 31CC. The second-layer collector wiring 32C is connected to the first-layer collector common wiring 31CC through an opening of the interlayer insulating film arranged thereunder. The collector bump 33C is arranged so as to overlap the second-layer collector wiring 32C. The collector bump 33C is connected to the second-layer collector wiring 32C through an opening of the protective film arranged thereunder.

[0069] ​The second-layer emitter wiring 32E is configured to contain, in plan view, a plurality of first-layer emitter wirings 31E corresponding to the plurality of transistor units 20. The second-layer emitter wiring 32E is connected to the plurality of first-layer emitter wirings 31E through openings of the interlayer insulating film provided thereunder. The emitter bump 33E is configured to overlap the second-layer emitter wiring 32E. The emitter bump 33E is connected to the second-layer emitter wiring 32E through an opening of the protective film provided thereunder.

[0070] The plurality of base wirings 31B extending from each unit transistor 21 in the second direction D2 reach the outside of the second-layer emitter wiring 32E, and each of the front ends is connected to the common DC bias input wiring 31DB via the resistive element 31R. The base wiring 31B contains a widened portion 31BW in which the width is enlarged in the middle. The common high-frequency signal input wiring 32S overlaps the widened portions 31BW of the plurality of base wirings 31B. A capacitive element 35 is formed in each of the overlapping portions of the plurality of widened portions 31BW and the high-frequency signal input wiring 32S.

[0071] A distance in the first direction D1 between the two emitter electrodes 22E within one transistor unit 20 is referred to as an emitter electrode pitch Le. As the emitter electrode pitch Le, a distance between mutually corresponding positions of the two emitter electrodes 22E, such as a distance in the first direction D1 between edges on the same side extending in the second direction D2, a distance in the first direction D1 between the geometric centers of the two emitter electrodes 22E, and the like, can be adopted. The emitter electrode pitch Le is the same among the plurality of transistor units 20.

[0072] A certain distance (described below) in the first direction D1 of adjacent transistor units 20 is referred to as a unit pitch Lc. As the unit pitch Lc (the certain distance), a distance in the first direction D1 between mutually corresponding positions of the two transistor units 20, such as a distance in the first direction D1 between edges on the same side extending in the second direction D2 of mutually corresponding emitter electrodes 22E within the two transistor units 20, a distance in the first direction D1 between the geometric centers of the plurality of emitter electrodes 22E of the transistor units 20, respectively, and the like, can be adopted. The unit pitch Lc of the two adjacent transistor units 20 is the same throughout. That is, the plurality of transistor units 20 are arranged at equal pitches in the first direction D1.

[0073] When one transistor unit 20 is focused on, the emitter electrode pitch Le of the emitter electrodes 22E of the focused transistor unit 20 is shorter than 1 / 2 of the unit pitch Lc between the focused transistor unit 20 and the transistor unit 20 adjacent thereto.

[0074] Figure 4This is an equivalent circuit diagram of the semiconductor device according to the first embodiment. Each of the plurality of transistor units 20 includes two unit transistors 21. The plurality of unit transistors 21 are connected in parallel. A semiconductor device in which multiple heterojunction bipolar transistors (HBTs) are connected in parallel is sometimes referred to as a multi-finger HBT. Specifically, the emitters of the plurality of unit transistors 21 are connected to a common emitter wiring 32E, and the collectors are connected to a common collector wiring 32C.

[0075] The bases of multiple unit transistors 21 are connected to a common DC bias input wiring 31DB via resistors 31R. Base bias is supplied to the bases of the unit transistors 21 from the bias circuit 51 via the DC bias input wiring 31DB and resistors 31R. The bases of the multiple unit transistors 21 are also connected to a common high-frequency signal input wiring 32S via capacitors 35. A high-frequency signal is input to the bases of the unit transistors 21 from the high-frequency signal input port 53 via the high-frequency signal input wiring 32S and capacitors 35.

[0076] A power supply voltage is supplied to the collectors of multiple unit transistors 21 via a power supply circuit 50, an inductor 52, and collector wiring 32C. The power supply circuit 50 is, for example, an envelope tracking power supply circuit, applying a power supply voltage to the collectors that varies according to the envelope of the waveform of the high-frequency input signal. The high-frequency signal, amplified by the multiple unit transistors 21, is output from the high-frequency signal output port 54 via collector wiring 32C.

[0077] Next, the superior effects of the first embodiment will be explained.

[0078] The damage to the unit transistor 21 under load variations when a high collector voltage is applied is caused by impact ionization (surge ionization). If a large number of electron-hole pairs are generated due to impact ionization, the collector current will increase. The increase in collector current leads to a further increase in electron-hole pairs, resulting in component damage caused by avalanche amplification.

[0079] Impact ionization in collector layer 21C ( Figure 1 The region with a high electric field intensity becomes significant. The ionization rate based on impact ionization depends on the temperature of the region with a high electric field intensity; as the temperature increases, the ionization rate decreases. The collector current of transistor 21 is mainly related to the emitter current of transistor 22E when viewed from above. Figure 3The overlapping region of the current flows, and this region becomes a heat source. In the semiconductor device of the first embodiment, the emitter electrode spacing Le is shorter than half of the cell spacing Lc. That is, the heat sources within the transistor cell 20 are arranged close to each other. Because the temperature of the heat source in one unit transistor 21 rises due to the heat generated by the heat source in that unit transistor 21, the temperature of the heat source tends to rise. That is, the temperature of the region through which the collector current mainly flows tends to rise.

[0080] As the collector current increases, the temperature rises, and the ionization rate decreases in the region of increased temperature. Consequently, avalanche amplification caused by impact ionization is less likely to occur, and component damage is less likely. Therefore, excellent performance is achieved with improved load variation damage resistance.

[0081] In the first embodiment, although the temperature of the heat source of the unit transistor 21 is prone to rise, as will be explained below, the instability of the operation that causes thermal runaway of the unit transistor 21 will not increase.

[0082] To suppress thermal runaway, the heat generated by the heat source of unit transistor 21 is transmitted through the emitter electrode 22E. Figure 1 ), first layer emitter wiring 31E ( Figure 1 ), second layer emitter wiring 32E ( Figure 3 ), emitter bump 33E ( Figure 3 The heat is dissipated through a heat conduction path to the mounting substrate. Therefore, even when the two emitter electrodes 22E within the transistor cell 20 are brought close together, sufficient heat dissipation is ensured to suppress thermal runaway. In addition, the additional resistive element 31R to the base electrode 22B of the unit transistor 21 also contributes to the suppression of thermal runaway.

[0083] Next, regarding Figure 5 The superior performance of the semiconductor device shown in the comparative example compared to the first embodiment will be explained.

[0084] Figure 5 This is a top-view diagram showing the positional relationship of a transistor cell 20 and its two collector electrodes 22C on either side of the semiconductor device of the comparative example. Figure 5 In the comparative example shown, each transistor unit 20 includes a unit transistor 21. The unit transistor 21 includes two emitter electrodes 22E spaced apart in the first direction D1. A main portion 22BA of a base electrode 22B is disposed between the two emitter electrodes 22E. Similar to the first embodiment, the base electrode 22B includes a contact portion 22BB. Two collector electrodes 22C are configured to sandwich the unit transistor 21 in the first direction D1.

[0085] In the comparative example, if a positional shift in the first direction Dl occurs between the emitter electrode 22E and the base electrode 22B depending on the alignment accuracy of the manufacturing process, the main portion 22BA of the base electrode 22B and the intervals of the emitter electrodes 22E on both sides thereof differ from each other. That is, the symmetry of the first direction Dl is broken. Due to the breaking of the symmetry, the current tends to concentrate on one emitter electrode 22E. Therefore, even if the collector voltage is low, impact ionization is likely to occur, and the load fluctuation breakdown resistance decreases.

[0086] On the contrary, in the first embodiment, the arrangement order of the first direction Dl of the base electrode 22B and the emitter electrode 22E is the same between the plurality of unit transistors 21 Figure 3 ). Therefore, even if a positional shift in the first direction Dl occurs between the emitter electrode 22E and the base electrode 22B, it is possible to keep the intervals between the emitter electrodes 22E and the main portions 22BA of the base electrodes 22B constant among all the unit transistors 21. Therefore, current concentration on a particular unit transistor 21 does not occur due to the positional shift. As a result, in the semiconductor device of the first embodiment, an excellent effect that the load fluctuation breakdown resistance is sufficiently high even if a positional shift occurs can be obtained.

[0087] There is a case where a high-frequency signal amplification circuit is constituted of two stages of an input stage amplifier and an output stage amplifier. The input stage amplifier does not need a high load fluctuation breakdown resistance, but a high gain is desired. The output stage amplifier requires a high load fluctuation breakdown resistance. The semiconductor device of the first embodiment is expected to be particularly applied to the output stage amplifier.

[0088] It is known that a technique of making the layer stack structure of the semiconductor layer different between an HBT of the input stage amplifier which requires a high gain and an HBT of the output stage amplifier which requires a high load fluctuation breakdown resistance to realize an HBT having characteristics conforming to various requirements. If this technique is applied, two kinds of HBTs having different layer stack structures of the semiconductor layer are formed on one semiconductor substrate. As a result, the manufacturing process becomes complicated, and the manufacturing cost increases. On the contrary, in the first embodiment, the load fluctuation breakdown resistance is improved by optimizing the positional relationship in plan view of each constituent element of the semiconductor device. Therefore, the layer stack structure of the semiconductor layer of the HBT of the input stage amplifier and the HBT of the output stage amplifier can be common. As a result, it is possible to suppress the increase in the manufacturing cost.

[0089] Next, the semiconductor device of the first embodiment will be described with reference to Figure 6 A semiconductor device of a modification example of the first embodiment will be described.

[0090] Figure 6is a view showing the positional relationship in plan view of each constituent element of the semiconductor device of the modification of the first embodiment. In the first embodiment, two collector electrodes 22C are arranged between two transistor units 20 adjacent to each other. Figure 3 ) are connected with the unit transistors 21 of the one transistor unit 20 adjacent to each other, respectively. Further, the sub-collector layer 41A is provided per transistor unit 20.

[0091] On the other hand, in the modification shown in Figure 6 , four transistor units 20 are contained in a common sub-collector layer 41A in plan view. One collector electrode 22C is arranged between two transistor units 20 adjacent to each other. The collector electrode 22C is shared by the transistor units 20 on both sides thereof and connected with the collector layers 21C Figure 1 ) of the unit transistors 21 on both sides.

[0092] As in the present modification, the collector electrode 22C arranged between two transistor units 20 adjacent to each other can be one, and the collector electrode 22C is shared by the transistor units 20 on both sides.

[0093] [Second Embodiment]

[0094] Next, the semiconductor device of the second embodiment will be described with reference to Figure 7 and Figure 8 . Hereinafter, the description of the same constitution as the semiconductor device of the first embodiment Figures 1-4 ) will be omitted.

[0095] Figure 7 is a view showing the planar positional relationship of each constituent element of the semiconductor device of the second embodiment. Figure 8 is a view showing the planar positional relationship of each constituent element of one transistor unit 20 of the semiconductor device of the second embodiment. In Figure 7 and Figure 8 , the hatching is added to the emitter electrode 22E, the base electrode 22B and the collector electrode 22C as in Figure 2 and Figure 3 .

[0096] In the first embodiment, the plurality of transistor units 20 respectively contain two unit transistors 21. On the other hand, in the second embodiment, the plurality of transistor units 20 respectively contain three unit transistors 21. The three unit transistors 21 are arranged at a constant emitter electrode pitch Le along the first direction Dl. Further, the plurality of transistor units 20 are arranged at a constant unit pitch Lc along the first direction Dl. In the second embodiment, as in the first embodiment, the emitter electrode pitch Le is 1 / 2 or less of the unit pitch Lc.

[0097] Also, as in the first embodiment, the arrangement order of the main portion 22BA of the base electrode 22B and the first direction Dl of the emitter electrode 22E is the same among all the unit transistors 21.

[0098] Next, the excellent effects of the second embodiment are described. In the second embodiment, the emitter electrode pitch Le is also 1 / 2 or less of the cell pitch Lc, so as in the first embodiment, the excellent effects of the load variation damage resistance improvement can be obtained. Also, since the arrangement order of the main portion 22BA of the base electrode 22B and the first direction Dl of the emitter electrode 22E is the same among all the unit transistors 21, even if the positional shift occurs, sufficiently high load variation damage resistance can be ensured.

[0099] Next, the excellent effects of the second embodiment are described. In the second embodiment, the emitter electrode pitch Le is also 1 / 2 or less of the cell pitch Lc, so as in the first embodiment, the excellent effects of the load variation damage resistance improvement can be obtained. Also, since the arrangement order of the main portion 22BA of the base electrode 22B and the first direction Dl of the emitter electrode 22E is the same among all the unit transistors 21, even if the positional shift occurs, sufficiently high load variation damage resistance can be ensured. Figure 9 The semiconductor device of the second embodiment is described.

[0100] Figure 9 is a view showing the planar positional relationship of each constituent element of the semiconductor device of the second embodiment. In Figure 9 , the hatching is added to the emitter electrode 22E, the base electrode 22B, and the collector electrode 22C as in Figure 7 .

[0101] In the second embodiment, one transistor cell 20 includes three unit transistors 21 Figure 7 , Figure 8 , but in the present modification example, one transistor cell 20 includes four unit transistors 21. In each of the plurality of transistor cells 20, the four unit transistors 21 are arranged in the first direction Dl at a constant emitter electrode pitch Le. The emitter electrode pitch Le is 1 / 2 or less of the cell pitch Lc as in the second embodiment.

[0102] In the modification example shown in Figure 9 , as in the second embodiment, the excellent effects of the load variation damage resistance improvement can be obtained.

[0103] Next, another modification example of the second embodiment is described. The number of unit transistors 21 included in one transistor cell 20 is two in the first embodiment Figure 3 , three in the second embodiment Figure 7 , and four in the modification example of the second embodiment Figure 9 . As another configuration, the number of unit transistors 21 included in one transistor cell 20 can be five or more.

[0104] [Third Embodiment]

[0105] Next, a semiconductor device of a third embodiment will be described with reference to the drawings. Figures 10-12D Figures 1-4 ) is omitted.

[0106] Figure 10 is a plan view showing the positional relationship in plan of each constituent element of one transistor unit 20 of the semiconductor device of the third embodiment. Figure 11 is a sectional view taken at the single-dot chain line 11-11 of Figure 10 . In Figure 10 , hatching is added to the emitter electrode 22E, the base electrode 22B, and the collector electrode 22C as in Figure 2 .

[0107] In the first embodiment, a step difference reaching the upper surface of the sub-collector layer 41A is formed between the two base mesas 21BM Figure 1 ) within one transistor unit 20, and the collector layers 21C of the two unit transistors 21 are separated from each other. In contrast, in the third embodiment, the collector layers 21C of the two unit transistors 21 are continuous in the lower layer portion.

[0108] More specifically, the collector layer 21C is composed of a lower high-concentration collector layer 21CA and a high-concentration collector layer 21CB thereon. The doping concentration of the low-concentration collector layer 21CB is lower than that of the high-concentration collector layer 21CA. The step difference 25 of the base mesa 21BM reaches the lower surface of the low-concentration collector layer 21CB but does not reach the lower surface of the high-concentration collector layer 21CA. That is, the low-concentration collector layers 21CB of the two unit transistors 21 are separated from each other, but the high-concentration collector layers 21CA are continuous.

[0109] Figures 12A-12D are graphs each showing one example of the distribution of the doping concentration in the depth direction of the collector layer 21C. The horizontal axis represents the depth from the upper surface of the base layer 21B in units of "μm", and the vertical axis represents the doping concentration (dopant concentration) in units of "cm －3 ".

[0110] In the example shown in Figure 12A , the doping concentration of each of the high-concentration collector layer 21CA and the low-concentration collector layer 21CB is constant in the depth direction, and changes in a step-like manner at the interface therebetween. The amount of change in the doping concentration at the interface between the high-concentration collector layer 21CA and the low-concentration collector layer 21CB is one digit or more.

[0111] In the example shown in Figure 12B ​In the example shown, the low-concentration collector layer 21CB is composed of two layers with different doping concentrations. The doping concentration of the layer closer to the base layer 21B is lower than that of the layer closer to the high-concentration collector layer 21CA. In this case, it is also consistent with... Figure 12A The example shown is similar, with the doping concentration varying stepwise at the interface between the low-concentration collector layer 21CB and the high-concentration collector layer 21CA, and the variation in doping concentration being in the single digits.

[0112] exist Figure 12C In the example shown, Figure 12B In the low-concentration collector layer 21CB shown, the doping concentration of the layer closest to the high-concentration collector layer 21CA gradually increases from the base layer 21B toward the high-concentration collector layer 21CA. In this case, the doping concentration also changes stepwise at the interface between the low-concentration collector layer 21CB and the high-concentration collector layer 21CA, with the change in doping concentration being in the single digits.

[0113] exist Figure 12D In the example shown, a medium-concentration collector layer 21CC, with an intermediate doping concentration, is disposed between the low-concentration collector layer 21CB and the high-concentration collector layer 21CA. In the depth direction, the doping concentration gradually increases from the middle of the low-concentration collector layer 21CB toward the high-concentration collector layer 21CA. Similarly, in the high-concentration collector layer 21CA, the doping concentration gradually increases from the medium-concentration collector layer 21CC toward the sub-collector layer 41A.

[0114] Although the doping concentration varies stepwise at the interface between the high-concentration collector layer 21CA and the medium-concentration collector layer 21CC, the variation is less than one order of magnitude. The low-concentration collector layer 21CB is defined as having a doping concentration at least one order of magnitude lower than the minimum doping concentration of the high-concentration collector layer 21CA. Figure 12D In the example shown, the minimum doping concentration of the high-concentration collector layer 21CA is 1 × 10⁻⁶. 18 cm －3 Therefore, the doping concentration is 1×10 17 cm －3 The following range corresponds to the low-concentration collector layer 21CB.

[0115] Next, the reasons why even in a structure where the high-concentration collector layer 21CA spans two unit transistors 21 consecutively, the load variation damage resistance can be improved in the same way as in the first embodiment will be explained.

[0116] The base-collector voltage is mainly applied to the low-concentration collector layer 21CB, and no large voltage is applied to the high-concentration collector layer 21CA. That is, the electric field is easily concentrated in the low-concentration collector layer 21CB. Therefore, in the state of a high collector voltage, impact ionization mainly occurs in the low-concentration collector layer 21CB, and impact ionization hardly occurs in the high-concentration collector layer 21CA. Thus, a large number of electron-hole pairs are generated in the low-concentration collector layer 21CB.

[0117] The operation in the case where a relatively large collector current flows in one unit transistor 21, and a relatively large number of electron-hole pairs are generated in the low-concentration collector layer 21CB, which is continuous between two unit transistors 21, will be described. A relatively large number of holes flow into the base layer 21B of the one unit transistor 21 in which a relatively large number of electron-hole pairs are generated. This inflow acts in a direction in which the base current decreases.

[0118] If the base current decreases, the voltage drop amount based on the resistance element 31R( Figure 4 ) decreases, and the base voltage rises. The collector current increases as the base voltage rises. The increase in the collector current promotes impact ionization. Therefore, a positive feedback in which the collector current of the unit transistor 21 through which a relatively large collector current flows further increases acts.

[0119] In the unit transistor 21 through which a relatively large collector current flows, the voltage drop amount of the collector potential due to the collector resistance increases in accordance with the amount of increase in the collector current. Thus, the collector potential of the unit transistor 21 through which a relatively small collector current flows becomes relatively high. Since the resistance value of the low-concentration collector layer 21CB is higher than that of the high-concentration collector layer 21CA, the difference in the collector potential is maintained. The holes generated in the low-concentration collector layer 21CB of the unit transistor 21 whose collector potential is relatively high are stolen by the unit transistor 21 whose collector potential is relatively low. Therefore, in the unit transistor 21 through which a relatively small collector current flows, the above-described positive feedback does not act. Thus, the collector current of the unit transistor 21 through which a relatively small collector current flows does not increase.

[0120] As a result, if an imbalance in the collector current occurs between two unit transistors 21, concentration of the collector current to the unit transistor 21 through which a relatively large collector current flows occurs. Thus, the unit transistor 21 in which the collector current is concentrated is damaged.

[0121] In contrast, in the third embodiment, the low-concentration collector layer 21CB is separated between the two unit transistors 21, so holes do not move between the two low-concentration collector layers 21CB. The two unit transistors 21 operate independently of each other, so it is less likely for a concentration of collector current to occur in one unit transistor 21. As a result, excellent effects such as suppressing damage to the unit transistors 21 can be achieved.

[0122] Furthermore, in the third embodiment, compared to the first embodiment, the step difference 25 ( ) of the base mesa 21BM Figure 11 The temperature is relatively low. Therefore, the two base mesa 21BM can be brought close to each other. If the two base mesa 21BM are close, the two emitter electrodes 22E are also close to each other. If the two emitter electrodes 22E are close, the thermal effect between the two unit transistors 21 increases, and the temperature of the low-concentration collector layer 21CB tends to rise. As the temperature of the low-concentration collector layer 21CB rises, the ionization rate based on impact ionization decreases, which further improves the resistance to load variation damage.

[0123] Next, the preferred relationship between the doping concentrations of the low-concentration collector layer 21CB and the high-concentration collector layer 21CA will be explained.

[0124] To prevent holes generated by impact ionization in the collector layer 21C of one unit transistor 21 from affecting another unit transistor 21, it is preferable to suppress the generation of holes based on impact ionization within a continuous high-concentration collector layer 21CA from one unit transistor 21 to another. For this purpose, it is preferable to set the doping concentration such that the electric field is mainly concentrated in the low-concentration collector layer 21CB, and no electric field is actually applied to the high-concentration collector layer 21CA. By making the doping concentration of the low-concentration collector layer 21CB less than 1 / 10 of the lowest value of the doping concentration in the high-concentration collector layer 21CA, the electric field can be concentrated in the low-concentration collector layer 21CB.

[0125] Next, refer to Figure 13 A modified example of the semiconductor device of the third embodiment will be described.

[0126] Figure 13 This is a cross-sectional view of a semiconductor device according to a variation of the third embodiment. In the third embodiment, by means of a semiconductor device disposed on the base mesa 21BM ( Figure 11 The step difference 25, the low concentration collector layer 21CB, base layer 21B and emitter layer 21E are separated.

[0127] In contrast, Figure 13In the modification shown, in one transistor unit 20, the emitter layer 21E, the base layer 21B, the low-concentration collector layer 21CB, and the high-concentration collector layer 21CA are formed by a portion of the semiconductor layer disposed across a plurality of unit transistors 21, respectively. The semiconductor layer between each of the emitter layer 21E, the base layer 21B, and the low-concentration collector layer 21CB of mutually adjacent unit transistors 21 is insulating by addition of impurities. As the impurities for insulating, B, O, or He, etc. can be used. The emitter layer 21E, the base layer 21B, and the low-concentration collector layer 21CB of mutually adjacent unit transistors 21 are electrically separated from each other by the insulating regions 26 insulating by impurity implantation, respectively.

[0128] As in this modification, the emitter layer 21E, the base layer 21B, and the low-concentration collector layer 21CB can be electrically insulated between a plurality of unit transistors 21 by forming the insulating regions 26 instead of the step difference 25. In this modification, compared to the first embodiment ( Figure 1 ), the two emitter electrodes 22E can be brought closer to each other.

[0129] In Figure 13 the modification shown, the insulating regions 26 reach the middle of the thickness direction of the high-concentration collector layer 21CA and do not reach the sub-collector layer 41A, but the insulating regions 26 can also be configured to reach the interface of the collector layer 21C and the sub-collector layer 41A. In this case, as in the first embodiment ( Figure 1 ), the collector layer 21C can be configured not to be explicitly divided into a low-concentration layer and a high-concentration layer.

[0130] [Fourth Embodiment]

[0131] Next, the semiconductor device of the fourth embodiment will be described with reference to Figure 14 . Hereinafter, the description of the same configuration as the semiconductor devices of the second embodiment ( Figure 7 , Figure 8 ) and the modification of the second embodiment ( Figure 9 ) will be omitted.

[0132] Figure 14 is a view showing the positional relationship in plan view of each constituent element of the semiconductor device of the fourth embodiment. In Figure 14 , the hatching is added to the emitter electrode 22E, the base electrode 22B, and the collector electrode 22C as in Figure 2 . In the second embodiment ( Figure 7 , Figure 8 ) and the modification of the second embodiment ( Figure 9) in each of the transistor units 20, the emitter electrode pitch Le is constant. In contrast, in the fourth embodiment, in each of the transistor units 20, the emitter electrode pitch Le is not constant but has a variation.

[0133] For example, in Figure 14 , two transistor units 20 each include four unit transistors 21. The emitter electrode pitch Le of the two unit transistors 21 on the inner side among the four unit transistors 21 is longer than the emitter electrode pitch Le between the unit transistors 21 on the both ends and the unit transistors 21 adjacent thereto.

[0134] When one of the transistor units 20 is focused on, the maximum value of the emitter electrode pitch Le of the plurality of emitter electrodes 22E within the focused transistor unit 20 is less than 1 / 2 of the cell pitch Lc between the focused transistor unit 20 and the transistor unit 20 adjacent thereto.

[0135] Next, the excellent effects of the fourth embodiment will be described.

[0136] In the fourth embodiment, as in the second embodiment and the modified example thereof, the temperature of the collector layer 21C is increased by the sufficient heat influence between the plurality of unit transistors 21 within the transistor unit 20. Thereby, the ionization rate due to the impact ionization can be reduced, and the load fluctuation damage resistance can be improved.

[0137] In addition, by making the emitter electrode pitch Le within one of the transistor units 20 not uniform, the heat influence between the plurality of unit transistors 21 can be made close to uniform. For example, in Figure 14 , the two unit transistors 21 on the inner side among the four unit transistors 21 are influenced by the heat from the unit transistors 21 on the both sides thereof. In contrast, the unit transistors 21 on the both ends are influenced by the heat from only one of the unit transistors 21. By making the emitter electrode pitch Le of the two unit transistors 21 on the inner side longer than the other emitter electrode pitches Le, the heat influence on the two unit transistors 21 on the inner side can be reduced, and the heat influence on the four unit transistors 21 can be averaged.

[0138] Next, a modified example of the fourth embodiment will be described. Although in the fourth embodiment, the emitter electrode pitch Le of the two unit transistors 21 on the inner side among the four unit transistors 21 is made relatively long, the plurality of emitter electrode pitches Le can be set to appropriate values according to the temperature distribution assumed at the time of operation.

[0139] [Fifth Embodiment]

[0140] Next, with reference to Figure 15 The semiconductor device of the fifth embodiment will be described. Hereinafter, the semiconductor device of the first embodiment (Figures 1-4 ) the same configuration is omitted.

[0141] Figure 15 is a view showing positional relation of each constituent element of the semiconductor device of the fifth embodiment in plan view. In Figure 15 , hatching is added to the emitter electrode 22E, the base electrode 22B, and the collector electrode 22C as in Figure 2 . In the first embodiment, the number of the unit transistors 21 included in each of the plurality of transistor units 20 is the same among all the transistor units 20. In contrast, in the fifth embodiment, the number of the unit transistors 21 included in each of the plurality of transistor units 20 is different among the plurality of transistor units 20. For example, in the embodiment shown in Figure 15 , four transistor units 20 are arranged in the first direction Dl, and the two inner transistor units 20 each include two unit transistors 21, and the two outer transistor units 20 each include three unit transistors 21.

[0142] As a reference for measuring the cell pitch Lc between two transistor units 20 adjacent to each other, the geometric center of the plurality of emitter electrodes 22E included in the transistor unit 20 in plan view can be used.

[0143] Next, the excellent effects of the fifth embodiment are described.

[0144] In the fifth embodiment, as in the first embodiment, the load variation damage resistance can be improved by making the emitter electrode pitch Le shorter than 1 / 2 of the cell pitch Lc.

[0145] Next, a modification of the fifth embodiment is described. In the fifth embodiment, the transistor unit 20 including two unit transistors 21 and the transistor unit 20 including three unit transistors 21 are mixed, but the transistor unit 20 including four or more unit transistors 21 can be further mixed.

[0146] [Sixth Embodiment]

[0147] Next, the semiconductor device of the sixth embodiment is described with reference to Figure 16 . Hereinafter, the same configuration as the semiconductor device of the first embodiment (the first embodiment) is omitted. Figures 1-4

[0148] Figure 16 is a view showing positional relation of each constituent element of the semiconductor device of the sixth embodiment in plan view. In Figure 16 , hatching is added to the emitter electrode 22E, the base electrode 22B, and the collector electrode 22C as in Figure 2 the first embodiment (the first embodiment) and the fifth embodiment (the fifth embodiment).​Figure 3 ) In the first embodiment, the cell pitch Lc is the same in all combinations of two transistor units 20 adjacent to each other. In contrast, in the sixth embodiment, the cell pitch Lc is deviated. In Figure 16 the sixth embodiment shown in FIG. 6, four transistor units 20 are arranged in the first direction Dl. The cell pitch Lc of the two transistor units 20 on the inner side is longer than the cell pitch Lc between the transistor units 20 on the both ends and the transistor units 20 adjacent thereto.

[0149] In the case where one transistor unit 20 is focused on, the emitter electrode pitch Le of the two unit transistors 21 in the focused transistor unit 20 is shorter than 1 / 2 of the shorter cell pitch Lc among the cell pitch Lc between the focused transistor unit 20 and the transistor unit 20 adjacent thereto.

[0150] Next, the excellent effects of the sixth embodiment will be described.

[0151] In the sixth embodiment, as in the first embodiment, the load variation damage resistance can be improved. In addition, by relatively lengthening the cell pitch Lc at a position that becomes high temperature relatively easily at the time of operation, the averaging of the temperature at the time of operation can be achieved. Thus, the element damage caused by thermal runaway can be suppressed.

[0152] [Seventh Embodiment]

[0153] Next, the semiconductor device of the seventh embodiment will be described with reference to Figure 17 The semiconductor device of the seventh embodiment will be described. Hereinafter, the description of the same configuration as the semiconductor device of the first embodiment (FIG. 1) will be omitted. Figures 1-4

[0154] Figure 17 is a diagram schematically showing the positional relationship at the time of plan view of each constituent element of the semiconductor device of the seventh embodiment. In Figure 17 , the description of the base electrode and the collector electrode is omitted, and the hatching is added to the emitter electrode 22E. In the first embodiment (FIG. 1), Figure 3 all the transistor units 20 include the two unit transistors 21 shown in FIG. 2. In contrast, in the seventh embodiment, two kinds of transistor units 20 having different positional relationships at the time of plan view of the emitter electrode 22E and the base electrode 22B are mixed. Figure 2 One kind of transistor unit 20 (hereinafter, referred to as first transistor unit 20A) includes the two unit transistors 21 shown in FIG. 2 as in the first embodiment. Another kind of transistor unit 20 (hereinafter, referred to as second transistor unit 20B) includes the two unit transistors 21 shown in FIG. 7.

[0155] Figure 2 Figure 5 ​​​The unit transistor 21 of the comparative example shown. Four transistor units 20 are arranged in the first direction Dl, and two second transistor units 20B are arranged at both ends, and two first transistor units 20A are arranged at the inner side. In the first transistor unit 20A, base wirings 31B are drawn from two unit transistors 21, respectively. In the second transistor unit 20B, one base wiring 31B is drawn from one unit transistor 21.

[0156] As a reference for measuring the cell pitch Lc of the two first transistor units 20A, the cell pitch Lc of the two second transistor units 20B, and the cell pitch Lc between the first transistor unit 20A and the second transistor unit 20B, the geometric center in plan view of the plurality of emitter electrodes 22E included in the first transistor unit 20A or the second transistor unit 20B can be used. The emitter electrode pitch Le of the two unit transistors 21 in the first transistor unit 20A is shorter than 1 / 2 of the shorter one of the cell pitch Lc between the first transistor unit 20A and the first transistor unit 20A or the second transistor unit 20B adjacent thereto.

[0157] Next, the excellent effects of the seventh embodiment will be described.

[0158] In the first transistor unit 20A of the semiconductor device of the seventh embodiment, the load variation damage resistance can be improved as in the first embodiment. In a semiconductor device including a plurality of transistor units 20, there is a case where a specific transistor unit 20 is easily damaged due to load variation. In such a case, it is sufficient to make the transistor unit 20 which is easily damaged due to load variation a first transistor unit 20A, and to make the other transistor units 20 second transistor units 20B.

[0159] Next, the seventh embodiment will be described with reference to Figure 18 A modification of the seventh embodiment will be described.

[0160] Figure 18 is a view schematically showing the positional relationship in plan view of each constituent element of the semiconductor device of the modification of the seventh embodiment. In the seventh embodiment Figure 17 ), two second transistor units 20B are arranged at both ends in the first direction Dl, and two first transistor units 20A are arranged at the inner side. In contrast, in the present modification, first transistor units 20A are arranged at both ends in the first direction Dl, and two second transistor units 20B are arranged at the inner side.

[0161] Generally, in a case where a plurality of transistor units 20 are arranged in one direction, there is a tendency that the temperature of the unit transistor 21 of the transistor unit 20 at both ends is lower than the temperature of the unit transistor 21 of the transistor unit 20 at the inner side at the time of operation. If the temperature at the time of operation is lower, the ionization rate of the collision ionization becomes higher, so damage caused by load variation is easily generated. In the present modification example, the transistor unit 20 at a position where the temperature tends to be relatively low is made the first transistor unit 20A, so the improvement of the load variation damage resistance is particularly effective.

[0162] Further, there is also a case where damage caused by load variation is easily generated in the transistor unit 20 at the inner side depending on the structure of the wiring, bump around the region where a plurality of transistor units 20 are arranged. As long as the transistor unit 20 arranged at a position where damage caused by load variation is easily generated among the plurality of transistor units 20 is made the first transistor unit 20A.

[0163] The above-described each embodiment is an example, and of course, substitution or combination of the parts of the configuration shown in different embodiments can be performed. The same effect brought by the same configuration of a plurality of embodiments is not mentioned in each embodiment in turn. Further, the present application is not limited to the above-described embodiments. For example, various changes, improvements, combinations, and the like can be explicitly performed by those skilled in the art.

Claims

1. A semiconductor device, wherein, have: substrate; Multiple transistor units are arranged along a first direction on the surface of the substrate, each transistor unit comprising at least one unit transistor; and The collector electrodes are respectively disposed between two adjacent transistor units. The first transistor unit, which is at least one of the aforementioned transistor units, comprises a plurality of unit transistors arranged along the aforementioned first direction. The aforementioned multiple unit transistors are connected in parallel with each other. Each of the aforementioned multiple unit transistors includes a collector layer, a base layer disposed on the collector layer, an emitter layer disposed on the base layer, a base electrode electrically connected to the base layer, and an emitter electrode electrically connected to the emitter layer. The aforementioned collector electrode is electrically connected to the collector layer of the unit transistor included in the transistor cell adjacent in the aforementioned first direction. In the aforementioned first transistor unit, The base electrode and emitter electrode of each of the aforementioned plurality of unit transistors are arranged along the first direction, and the arrangement order of the base electrode and emitter electrode is the same among the aforementioned plurality of unit transistors. When focusing on one of the aforementioned first transistor units, the maximum value of the emitter electrode spacing is shorter than half of the shorter unit spacing among the unit spacings. The emitter electrode spacing is the distance in the first direction between the emitter electrodes of two adjacent unit transistors within the aforementioned first transistor unit. The unit spacing is a specific distance in the first direction between the aforementioned first transistor unit and the transistor units adjacent to the aforementioned first transistor unit.

2. The semiconductor device according to claim 1, wherein, In the first transistor unit, the spacing in the first direction between the emitter electrode and the base electrode of each of the plurality of unit transistors is the same among the plurality of unit transistors.

3. The semiconductor device according to claim 1, wherein, Each of the aforementioned transistor units contains an equal number of unit transistors. The distance between the emitter electrodes is constant in all combinations of two adjacent emitter electrodes within the aforementioned transistor units, and the distance between the units of the aforementioned transistor units is also constant.

4. The semiconductor device according to claim 1, wherein, The emitter and base layers of each of the aforementioned unit transistors are separated from the emitter and base layers of other unit transistors when viewed from above.

5. The semiconductor device according to claim 4, wherein, The collector layers of each of the aforementioned unit transistors are separated from the collector layers of other unit transistors when viewed from above.

6. The semiconductor device according to claim 4, wherein, Each of the aforementioned unit transistors comprises a low-concentration collector layer and a high-concentration collector layer. The low-concentration collector layer is disposed between the high-concentration collector layer and the base layer. The doping concentration of the low-concentration collector layer is less than 1 / 10 of the doping concentration of the high-concentration collector layer. When viewed from above, the low-concentration collector layer is separated from the low-concentration collector layers of other unit transistors.

7. The semiconductor device according to any one of claims 4 to 6, wherein, The emitter and base layers of the aforementioned multiple unit transistors are separated from the emitter and base layers of other unit transistors when viewed from above by a step difference from the edges of the emitter and base layers toward the substrate.

8. The semiconductor device according to any one of claims 4 to 6, wherein, Each of the aforementioned unit transistors has an emitter layer and a base layer that are each composed of a portion of a semiconductor layer that spans the aforementioned unit transistors. The semiconductor layers between the emitter layers and base layers of adjacent unit transistors are insulated by the addition of impurities.

9. The semiconductor device according to any one of claims 1 to 6, wherein, Also includes: High-frequency signal input wiring is provided on the aforementioned substrate and is supplied with high-frequency signals. A DC bias input wiring is disposed on the aforementioned substrate and is supplied with DC bias; and The capacitors and resistors are configured according to the base electrode of each of the aforementioned multiple unit transistors. The aforementioned capacitor element connects its corresponding base electrode to the aforementioned high-frequency signal input wiring. The aforementioned resistor element connects the corresponding base electrode to the aforementioned DC bias input wiring.

10. The semiconductor device according to any one of claims 1 to 6, wherein, The top-view positional relationship between the emitter electrode and base electrode of the unit transistor in the second transistor unit, which is a transistor unit other than the first transistor unit among the aforementioned plurality of transistor units, is different from the top-view positional relationship between the emitter electrode and base electrode of the unit transistor in the first transistor unit.

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