Dynamic random access memory and forming method thereof

Abstract

The present invention discloses a dynamic random access memory (DRAM) and a method for forming the same, wherein the DRAM comprises a substrate, a plurality of word line groups, a plurality of bit line structures, a plurality of capacitors, a plurality of capacitor contact windows, and a plurality of air gaps. The substrate has a plurality of active regions. The word line groups extend along the Y direction and are disposed in the substrate. The bit line structures extend along the X direction and are disposed on the substrate, crossing the plurality of word line groups. The capacitors are disposed at the two end points of the plurality of active regions, respectively. The capacitor contact windows are disposed between the capacitors and the active regions, respectively. The air gaps are disposed in a plurality of spaces enclosed by the bit line structures and the capacitor contact windows, respectively. A method for forming the DRAM is also provided.

Description

Technical Field

[0001] The present invention relates to a storage element and a forming method thereof, and in particular to a dynamic random access memory and a forming method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory composed of multiple memory cells. Specifically, each memory cell is primarily composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to each other via word lines and bit lines. To increase the integration density of DRAM, speed up the operation of components, and meet consumer demand for miniaturized electronic devices, buried word line DRAM has been developed in recent years to meet these various needs.

[0003] With technological advancements, all types of electronic products are trending towards becoming thinner, lighter, and smaller. However, this trend is also driving down the critical dimensions of DRAM, which presents numerous challenges to the DRAM manufacturing process. For example, as DRAM integration continues to increase, crosstalk between memory cells, or bitline coupling, is becoming increasingly severe, impacting DRAM operation. Summary of the Invention

[0004] The present invention provides a dynamic random access memory and a method for forming the same, which can reduce parasitic capacitance between adjacent bit line structures to improve coupling interference between adjacent bit line structures, thereby enhancing the reliability of the dynamic random access memory.

[0005] The present invention provides a memory element comprising: a substrate, multiple word line groups, multiple bit line structures, multiple capacitors, multiple capacitor contact windows, and multiple air gaps. The substrate has multiple active regions. The word line groups extend along the Y direction and are disposed within the substrate. The bit line structures extend along the X direction and are disposed on the substrate, crossing the multiple word line groups. The capacitors are disposed at two end points of the multiple active regions. The capacitor contact windows are disposed between the capacitors and the multiple active regions. The air gaps are disposed in multiple spaces enclosed by the multiple bit line structures and the multiple capacitor contact windows.

[0006] In one embodiment of the present invention, each word line group includes two buried word lines.

[0007] In one embodiment of the present invention, the width of each air gap is within the width of the corresponding word line group.

[0008] In one embodiment of the present invention, each capacitor includes: a lower electrode in a cup shape; an upper electrode disposed on the lower electrode; and a capacitor dielectric layer disposed between the lower electrode and the upper electrode.

[0009] In one embodiment of the present invention, two adjacent capacitors share the same upper electrode.

[0010] The present invention provides a method for manufacturing a storage element, comprising: providing a substrate having multiple active regions; forming multiple bit line structures on the substrate; forming a sacrificial layer between the multiple bit line structures; forming a first dielectric layer on the sacrificial layer; forming multiple grooves in the first dielectric layer to expose the sacrificial layer; performing a first etching process to remove the sacrificial layer to form multiple air gaps below the first dielectric layer between the multiple bit line structures; forming spacers on the sidewalls of the multiple grooves to seal the multiple air gaps; forming multiple capacitor contact windows at the two end points of the multiple active regions respectively; and forming multiple capacitors on the multiple capacitor contact windows respectively.

[0011] In one embodiment of the present invention, forming the above-mentioned spacers includes: filling a second dielectric layer in a plurality of trenches; and performing a second etching process to remove a portion of the second dielectric layer to expose the top surface of the substrate, wherein the spacers cover the sidewalls of the plurality of trenches and extend to below the first dielectric layer.

[0012] In one embodiment of the present invention, before forming the plurality of bit line structures, the method further includes forming a plurality of word line groups in the substrate, wherein each word line group includes two buried word lines.

[0013] In one embodiment of the present invention, before forming the plurality of word line groups, the method further includes forming a plurality of isolation structures in the substrate to separate the substrate into a plurality of active regions, wherein the plurality of active regions are configured in a strip shape and arranged in an array.

[0014] In one embodiment of the present invention, forming the capacitor contact windows includes: forming a plurality of conductor layers in a plurality of trenches, wherein top surfaces of the plurality of conductor layers are lower than a top surface of a first dielectric layer; forming a third dielectric layer to conformally cover the first dielectric layer and the plurality of conductor layers, wherein the third dielectric layer has a continuous concave-convex structure; performing a third etching process to form a plurality of openings exposing a plurality of isolation structures, wherein the plurality of openings separate the plurality of conductor layers into a plurality of capacitor contact windows; and forming a plurality of dielectric structures in the plurality of openings to connect to the plurality of isolation structures.

[0015] Based on the above, the embodiment of the present invention forms air gaps between the bit line structures to effectively reduce the parasitic capacitance between the bit line structures, thereby improving the coupling interference between the bit line structures and enhancing the reliability of the dynamic random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1N is a top view schematically illustrating a manufacturing process of a memory element according to an embodiment of the present invention;

[0017] Figures 2A to 2N They are Figures 1A to 1N Schematic cross-sectional view of tangent line II;

[0018] Figures 3A to 3N They are Figures 1A to 1N Schematic cross-sectional view of the tangent line II-II;

[0019] Figures 4A to 4N They are Figures 1A to 1N A schematic cross-sectional view of the tangent line III-III;

[0020] Figure 5 FIG. 4 is a cross-sectional schematic diagram of a memory element according to another embodiment of the present invention.

[0021] Explanation of symbols

[0022] 12, 16: Grooves

[0023] 14: Channel

[0024] 18: Opening

[0025] 20: Capacitor opening

[0026] 100: Base

[0027] 101: Isolation Structure

[0028] 102: Bit line structure

[0029] 104, 210, 238, 244: Conductor layer

[0030] 106: Top cover layer

[0031] 108, 214: gap wall

[0032] 110: Sacrificial layer

[0033] 112, 114, 212, 220, 240: Dielectric layer

[0034] 202: Character line group

[0035] 202a, 202b: buried character lines

[0036] 204a, 204b: Gate

[0037] 206a, 206b: gate dielectric layer

[0038] 207: Silicon oxide layer

[0039] 208: Silicon nitride layer

[0040] 210a: Conductor column

[0041] 212r: Recessed opening

[0042] 216: Dielectric Materials

[0043] 216a: Dielectric Structures

[0044] 230: Capacitor

[0045] 232: Lower electrode

[0046] 234: Capacitor dielectric layer

[0047] 236: Upper electrode

[0048] 242: Metal plug

[0049] AA: Active area

[0050] AC1, AC2: Active zone

[0051] AG: Air Gap

[0052] BC: bit line contact window

[0053] CC1, CC2: capacitor contact windows

[0054] D1, D2: distance

[0055] R1: First Zone

[0056] R2: Second Zone

[0057] X, Y: direction DETAILED DESCRIPTION

[0058] The present invention will be more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. Identical or similar reference numerals denote identical or similar elements, and detailed descriptions will not be repeated in the following paragraphs.

[0059] Figures 1A to 1N FIG. 1 is a top view schematically illustrating a manufacturing process of a memory element according to an embodiment of the present invention. Figures 2A to 2N According to Figures 1A to 1N Schematic cross-sectional view of tangent line II. Figures 3A to 3N According to Figures 1A to 1N Schematic cross-sectional view of the tangent line II-II. Figures 4A to 4N According to Figures 1A to 1N Schematic cross-sectional view of the tangent line III-III.

[0060] Please refer to Figure 1A 、 Figure 2A 、 Figure 3A as well as Figure 4A First, an initial structure is provided, including: a substrate 100 , a plurality of isolation structures 101 , a plurality of active areas AA, a plurality of bit line structures 102 and a plurality of word line groups 202 .

[0061] Specifically, if Figure 1A As shown, the substrate 100 includes a plurality of first regions R1 and a plurality of second regions R2. The first regions R1 and the second regions R2 are arranged alternately along the X direction. An isolation structure 101 is configured in the substrate 100 to define a plurality of active areas AA in the substrate 100. In other words, an isolation structure 101 is provided between two adjacent active areas AA. In one embodiment, a memory cell is formed on an active area AA, and each memory cell is separated by the isolation structure 101 to effectively reduce interference problems between the memory cells. The active area AA is configured in a strip shape and arranged in an array. In this embodiment, the active area AA is arranged into two active area columns AC1 and AC2, and the two adjacent active area columns AC1 and AC2 are in a mirror configuration.

[0062] The word line group 202 is disposed in the substrate 100 in the first region R1. The word line group 202 extends along the Y direction and is arranged along the X direction. In one embodiment, the X direction and the Y direction are substantially perpendicular to each other. Each word line group 202 has two buried word lines 202a and 202b. Figure 2A As shown, each buried word line 202a includes a gate 204a and a gate dielectric layer 206a. The gate dielectric layer 206a surrounds the gate 204a to electrically isolate the gate 204a from the substrate 100. In one embodiment, the material of the gate 204a includes a conductive material, which can be a metal material (e.g., tungsten), a barrier metal material (e.g., TiN), or a combination thereof. The material of the gate dielectric layer 206a can be, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The gate dielectric layer 206a can be a single-layer structure, a double-layer structure, or a multi-layer structure. Similarly, another buried word line 202b also includes a gate 204b and a gate dielectric layer 206b. The gate dielectric layer 206b surrounds the gate 204b to electrically isolate the gate 204b from the substrate 100. In addition, the initial structure also includes a silicon oxide layer 207 and a silicon nitride layer 208. Specifically, the silicon nitride layer 208 is disposed on the buried word lines 202 a and 202 b to seal the buried word lines 202 a and 202 b . The silicon oxide layer 207 is disposed beside the silicon nitride layer 208 and covers the top surface of the substrate 100 and the top surface of the isolation structure 101 .

[0063] The bit line structures 102 extend along the X direction and are arranged along the Y direction. Figure 1A As shown, the bit line structure 102 crosses the first region R1 and the second region R2. Figure 4A As shown, the bit line structure 102 is configured on the substrate 100. Each bit line structure 102 includes a conductive layer 104 and a cap layer 106 located on the conductive layer 104. In one embodiment, the conductive layer 104 can be made of a metal material, such as tungsten. The cap layer 106 can be made of silicon nitride. In this embodiment, the conductive layer 104 can be regarded as a bit line. Figure 3A As shown, the bit line 104 is electrically isolated from the substrate 100 by the silicon oxide layer 207 and is electrically isolated from the word line group 202 by the silicon nitride layer 208. In addition, the bit line structure 102 can be electrically connected to the active area AA (e.g., the source / drain doped region in the substrate 100) through the bit line contact window BC. Figure 1A As shown, the bit line contact window BC is located at the intersection of the active area AA and the bit line structure 102, and is located between the two buried word lines 202a and 202b. In one embodiment, the material of the bit line contact window BC can be a metal material (such as tungsten), a semiconductor material (such as epitaxial silicon or SiGe), or a combination thereof.

[0064] Please refer to Figure 1B 、 Figure 2B 、 Figure 3B as well as Figure 4B After the bit line structure 102 is defined, spacers 108 are formed on both sides of the bit line structure 102 so that the distance D1 ( Figure 4A ) is reduced to a distance D2( Figure 4B In one embodiment, the material of the spacer 108 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. Figure 4B Only a single-layer spacer 108 is shown, but the present invention is not limited thereto. In other embodiments, the spacer 108 may be a double-layer structure or a multi-layer structure to adjust the distance D2 between adjacent bit line structures 102 .

[0065] Please refer to Figure 1C 、 Figure 2C 、 Figure 3C as well as Figure 4C , a sacrificial layer 110 is formed on the substrate 100. Figure 4CAs shown, a sacrificial layer 110 fills the gaps between the bitline structures 102. The top surface of the sacrificial layer 110 may be lower than the top surface of the bitline structure 102, and the top surface of the sacrificial layer 110 may be higher than the top surface of the conductive layer 104. In one embodiment, the material of the sacrificial layer 110 includes polysilicon. However, the present invention is not limited to this. In other embodiments, any material that has a high etching selectivity relative to silicon oxide and silicon nitride and can be removed using a wet etch method is considered to be a material for the sacrificial layer 110 of the present invention. Furthermore, for clarity, the sacrificial layer 110 is omitted from the top view.

[0066] Please refer to Figure 1D 、 Figure 2D 、 Figure 3D as well as Figure 4D , a dielectric layer 112 (also referred to as a first dielectric layer) is formed on the sacrificial layer 110. Figure 4D As shown, dielectric layer 112 fills the gaps between bitline structures 102 and extends to cover the top surfaces of bitline structures 102 and top surfaces of spacers 108. In one embodiment, dielectric layer 112 comprises an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0067] Please refer to Figure 1E 、 Figure 2E 、 Figure 3E as well as Figure 4E , a plurality of trenches 12 are formed in the dielectric layer 112 of the second region R2. Figure 1E As shown, the trenches 12 extend along the Y direction and expose the top surface of the sacrificial layer 110 in the second region R2. In one embodiment, the steps of forming the plurality of trenches 12 include: forming a photoresist pattern on the dielectric layer 112 in the second region R2; removing a portion of the dielectric layer 112 using the photoresist pattern as a mask; and removing the photoresist pattern.

[0068] Please refer to Figure 1F 、 Figure 2F 、 Figure 3F as well as Figure 4F , a first etching process is performed to remove the sacrificial layer 110. In this case, Figure 1F and Figure 2FAs shown, the sacrificial layer 110 in the first region R1 is hollowed out to form a channel 14 between adjacent bit line structures 102. From another perspective, the channel 14 is located between the word line group 202 and the dielectric layer 112 in the first region R1. In one embodiment, the first etching process includes a wet etching process. Specifically, the etching solution used in the first etching process can contact the sacrificial layer 110 along the groove 12 and hollow out the sacrificial layer 110 below the dielectric layer 112. In this embodiment, the sacrificial layer 110 has a high etching selectivity to the dielectric layer 112. That is, the etching solution used in the first etching process can completely remove the sacrificial layer 110 without removing or removing a small amount of the dielectric layer 112.

[0069] Please refer to Figure 1G 、 Figure 2G 、 Figure 3G as well as Figure 4G , using the dielectric layer 112 as a mask, the silicon oxide layer 207 below the trench 12 is removed to expose the top surface of the substrate 100 and the top surface of the isolation structure 101. In this case, Figure 2G As shown, the groove 12 extends downward to form a groove 16 having a greater depth.

[0070] Please refer to Figure 1H 、 Figure 2H 、 Figure 3H as well as Figure 4H After forming the trench 16, a dielectric layer 114 (also referred to as a second dielectric layer) is formed on the substrate 100. Specifically, as Figure 2H As shown, the dielectric layer 114 fills the trench 16 and extends to cover the top surface of the dielectric layer 112. In addition, part of the dielectric layer 114 extends into the channel 14 below the dielectric layer 112 to seal the channel 14, thereby forming an air gap AG between adjacent bit line structures 102. Figure 1H However, the present invention is not limited thereto. In other embodiments, the dielectric layer 114 may not extend into the channel 14 (or the air gap AG). In one embodiment, the material of the dielectric layer 114 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0071] Please refer to Figure 1I 、 Figure 2I 、 Figure 3I as well as Figure 4I , a second etching process is performed to remove a portion of the dielectric layer 114 to expose the top surface of the substrate 100 in the second region R2. Figure 2IAs shown, the remaining dielectric layer 214 covers the sidewalls of the trench 16 in the form of spacers. Therefore, the dielectric layer 214 will be referred to as the spacer 214 below. At this time, the spacer 214 still seals both sides of the air gap AG. In one embodiment, the second etching process includes a dry etching process or an anisotropic etching process, such as a reactive ion etching (RIE) process.

[0072] Please refer to Figure 1J 、 Figure 2J 、 Figure 3J as well as Figure 4J , forming a conductive layer 210 in the trench 16. In one embodiment, the steps of forming the conductive layer 210 include: forming a conductive material in the trench 16; and etching back the conductive material so that the top surface of the conductive layer 210 is lower than the top surface of the dielectric layer 112. In this embodiment, the conductive material comprises polysilicon. For clarity, the conductive layer 210 is omitted from the top view.

[0073] Please refer to Figure 1K 、 Figure 2K 、 Figure 3K as well as Figure 4K , a dielectric layer 212 (also referred to as a third dielectric layer) is formed on the substrate 100. The dielectric layer 212 is conformally formed on the conductive layer 210 and the dielectric layer 112. Since there is a height difference between the top surface of the conductive layer 210 and the top surface of the dielectric layer 112, the top surface of the dielectric layer 212 can be, for example, a continuous concave-convex structure. The dielectric layer 212 located on the dielectric layer 112 is a convex portion; while the dielectric layer 212 located on the conductive layer 210 is a concave portion. Figure 2K As shown, the dielectric layer 212 on the substrate 100 in the second region R2 has a recessed opening 212r corresponding to the isolation structure 101 in the substrate 100. In one embodiment, the material of the dielectric layer 212 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0074] Please refer to Figure 1L 、 Figure 2L 、 Figure 3L as well as Figure 4L , a third etching process is performed to remove a portion of the dielectric layer 212 and a portion of the conductive layer 210 to form an opening 18 in the conductive pillar 210a and the dielectric pillar 212a of the second region R2. The opening 18 exposes the surface of the isolation structure 101 of the second region R2. In addition, the third etching process also includes removing the dielectric layer 212 of the first region R1 to expose the top surface of the dielectric layer 112. On the other hand, the opening 18 removes a conductive layer 210 ( Figure 2K) is separated into two conductive pillars 210a. In one embodiment, because the opening 18 can be aligned with the isolation structure 101 in the second region R2 without using a photolithography process, the opening 18 can be considered a self-aligned opening. In one embodiment, the third etching process includes a dry etching process, such as an RIE process.

[0075] Please refer to Figure 1M 、 Figure 2M 、 Figure 3M as well as Figure 4M , a dielectric material 216 is formed on the substrate 100. The dielectric material 216 fills the opening 18 and covers the top surface of the dielectric pillar 212a and the top surface of the dielectric layer 112. In one embodiment, the dielectric material 216 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0076] Please refer to Figure 1N 、 Figure 2N 、 Figure 3N as well as Figure 4N , a planarization process is performed to remove a portion of the dielectric material 216, a portion of the dielectric layer 112, a portion of the spacer 214, and the dielectric pillar 212a to expose the top surface of the conductive pillar 210a. In one embodiment, the planarization process can be a chemical mechanical polishing (CMP) process. In this case, Figure 2N As shown, the remaining dielectric material (also referred to as dielectric structure) 216a is aligned with the isolation structure 101 below to form a self-aligned isolation structure. This self-aligned isolation structure separates the two conductive pillars 210a so that the two conductive pillars 210a are respectively disposed at the two ends of the active area AA. In this embodiment, the two adjacent conductive pillars 210a can be regarded as capacitor contact windows CC1 and CC2. Figure 1N As shown, the capacitor contact window CC1 is disposed at one end of the active region AA to electrically connect the active region AA with the subsequently formed capacitor 230 (eg, Figure 5 The capacitor contact window CC2 is disposed at the other end of the active region AA to electrically connect the active region AA with another capacitor 230 (as shown in FIG. Figure 5 shown).

[0077] It is worth noting that as the integration level of dynamic random access memory continues to increase, the coupling interference between the bit line structures 102 will also increase. In order to solve the above problem, Figure 4N As shown, in this embodiment, an air gap AG (with a dielectric constant k=1) can be formed between the bit line structures 102 by the above-mentioned formation method. The top surface of the air gap AG can be higher than or equal to the top surface of the bit line 104 in the bit line structure 102, thereby effectively reducing the parasitic capacitance between the bit line structures 102, thereby improving the coupling interference between the bit line structures 102 and enhancing the reliability of the dynamic random access memory. Figure 1N As shown, air gaps AG can be disposed in the space enclosed by the bitline structure 102 and the capacitor contacts CC1 and CC2. In this embodiment, the width of each air gap AG is within the width of the corresponding wordline group 202. In other words, air gaps AG do not extend beyond the wordline group 202. Furthermore, air gaps AG also do not extend beyond the adjacent bitline structure 102.

[0078] Figure 5 is a cross-sectional schematic diagram of a memory element according to another embodiment of the present invention.

[0079] Please refer to Figure 5 , continuing the above Figure 2N In the structure of the present invention, after forming capacitor contact windows CC1 and CC2, a dielectric layer 220 is formed on the substrate 100. Thereafter, a plurality of capacitor openings 20 are formed in the dielectric layer 220, and a plurality of capacitors 230 are respectively formed in the capacitor openings 20. The capacitors 230 are electrically connected to the active area AA through the capacitor contact windows CC1 and CC2, respectively. Specifically, each capacitor 230 includes a lower electrode 232, an upper electrode 236 and a capacitor dielectric layer 234. The lower electrode 232 is cup-shaped and is electrically connected to the capacitor contact windows CC1 and CC2, respectively. The capacitor dielectric layer 234 is arranged between the lower electrode 232 and the upper electrode 236 and extends conformally along the inner surface of the lower electrode 232. In one embodiment, the top surface of the capacitor dielectric layer 234 is higher than the top surface of the lower electrode 232 to electrically separate the lower electrode 232 and the upper electrode 236. The upper electrode 236 extends from the capacitor opening 20 to cover the top surface of the dielectric layer 220. That is, two adjacent capacitors 230 share the same upper electrode 236. In one embodiment, the material of the lower electrode 232 includes a conductive material, such as Ti, TiN or a combination thereof. The capacitor dielectric layer 234 may include a high dielectric constant material layer (i.e., a dielectric material with a dielectric constant greater than 4), the material of which may be, for example, an oxide of the following elements, such as hafnium, zirconium, aluminum, titanium, lanthanum, yttrium, gadolinium or tantalum, or aluminum nitride, or any combination thereof. The material of the upper electrode 236 includes a conductive material, such as polysilicon. The material of the dielectric layer 220 may include silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.

[0080] After forming capacitor 230, the following steps are also performed: forming a conductive layer 238 on top electrode 236; forming a dielectric layer 240 on conductive layer 238; forming a metal plug 242 in dielectric layer 240; and forming a conductive layer 244 on metal plug 242. In one embodiment, conductive layer 238 may be made of a metal material, such as tungsten. Dielectric layer 240 may be made of silicon oxide. Metal plug 242 may be made of a metal material, such as tungsten. Conductive layer 244 may be made of a metal material, such as aluminum, copper, aluminum-copper, or a combination thereof. In this embodiment, conductive layer 244 may be considered a first metal layer (Metal 1), which is electrically connected to top electrode 236 via metal plug 242 and conductive layer 238.

[0081] In summary, the embodiments of the present invention form air gaps between bit line structures to effectively reduce parasitic capacitance between the bit line structures, thereby improving coupling interference between the bit line structures and enhancing the reliability of the dynamic random access memory.

Claims

1. A dynamic random access memory, characterized in that: include: A substrate having a plurality of active regions, wherein the plurality of active regions are configured in a strip shape and arranged in an array; a plurality of word line groups extending along the Y direction and arranged in the substrate; a plurality of bit line structures extending along the X direction and disposed on the substrate and crossing the plurality of word line groups; a plurality of capacitors, respectively disposed at two end points of the plurality of active regions; a plurality of capacitor contact windows, respectively disposed at the two end points of the plurality of active regions and located between the capacitor and the plurality of active regions; as well as A plurality of air gaps are respectively arranged in a plurality of spaces surrounded by the plurality of bit line structures and the plurality of capacitor contact windows, wherein each of the plurality of air gaps is located between two adjacent ones of the plurality of capacitor contact windows in the X direction.

2. The dynamic random access memory of claim 1, wherein each word line group comprises two buried word lines.

3. The dynamic random access memory of claim 1, wherein a width of each air gap is within a width of a corresponding word line group.

4. The dynamic random access memory of claim 1 , wherein each capacitor comprises: The lower electrode is cup-shaped; an upper electrode, disposed on the lower electrode; as well as The capacitor dielectric layer is disposed between the lower electrode and the upper electrode.

5. The dynamic random access memory as claimed in claim 4, wherein two adjacent capacitors share a same upper electrode.

6. A method for forming a dynamic random access memory, comprising: Providing a substrate having a plurality of active regions, wherein the plurality of active regions are configured in strips and arranged in an array; forming a plurality of bit line structures on the substrate; forming a sacrificial layer between the plurality of bit line structures; forming a first dielectric layer on the sacrificial layer; forming a plurality of trenches in the first dielectric layer to expose the sacrificial layer; performing a first etching process to remove the sacrificial layer to form a plurality of air gaps below the first dielectric layer between the plurality of bit line structures; forming spacers on sidewalls of the plurality of trenches to seal the plurality of air gaps; forming a plurality of capacitor contact windows at two end points of the plurality of active regions respectively; as well as forming a plurality of capacitors on the plurality of capacitor contact windows respectively; Each of the plurality of air gaps is located between two adjacent ones of the plurality of capacitor contact windows in an extending direction of the plurality of bit line structures.

7. The method for forming a dynamic random access memory according to claim 6 , wherein forming the spacer comprises: filling a second dielectric layer in the plurality of trenches; as well as A second etching process is performed to remove a portion of the second dielectric layer to expose a top surface of the substrate, wherein the spacers cover the sidewalls of the plurality of trenches and extend to below the first dielectric layer.

8. The method for forming a dynamic random access memory according to claim 6, further comprising: A plurality of word line groups are formed in the substrate, wherein each word line group includes two buried word lines.

9. The method for forming a dynamic random access memory according to claim 8, further comprising: before forming the plurality of word line groups; A plurality of isolation structures are formed in the substrate to separate the substrate into the plurality of active regions.

10. The method for forming a dynamic random access memory according to claim 9, wherein forming the plurality of capacitor contact windows comprises: forming a plurality of conductor layers in the plurality of trenches, wherein top surfaces of the plurality of conductor layers are lower than a top surface of the first dielectric layer; forming a third dielectric layer to conformally cover the first dielectric layer and the plurality of conductor layers, wherein the third dielectric layer has a continuous concave-convex structure; performing a third etching process to form a plurality of openings exposing the plurality of isolation structures, wherein the plurality of openings separate the plurality of conductor layers into the plurality of capacitor contact windows; as well as A plurality of dielectric structures are formed in the plurality of openings to connect with the plurality of isolation structures.

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