Three-dimensional non-volatile memory cell device structure and manufacturing method thereof
By constructing a three-dimensional non-volatile memory cell device structure on a silicon substrate, using components such as the selector tube polysilicon gate, source-end polysilicon gate and isolation dielectric layer, the problem of excessive storage cell structure in the prior art is solved, and the more High chip integration.
Patent Information
- Application Number
- CN202111186005.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-10-12
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2041-10-12
AI Technical Summary
In the prior art, non-volatile memory cells formed by select gate structures and memory gate structures laminated on a silicon substrate have a large structure, which is not conducive to the requirements of chip integration.
Provide a three-dimensional non-volatile memory cell device structure and its manufacturing method. By forming a memory cell trench on a silicon substrate, selecting tube polysilicon gate, source-end polysilicon gate and isolation dielectric layer are sequentially constructed, combining the interlayer dielectric layer and The polysilicon gate of the storage tube forms a three-dimensional memory cell structure, reducing the space occupancy of the memory cell device.
It effectively reduces the space usage of memory cell devices and improves chip integration.
Smart Images
Figure CN114093875B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a three-dimensional non-volatile memory cell device structure and a manufacturing method thereof. Background Art
[0002] Memory is the main medium for storing data in computers. Non-volatile memory is widely used because the information stored in it can still exist for a long time after the power is turned off and is not easily lost.
[0003] The non-volatile memory cell in the related art includes a select gate structure and a storage gate structure arranged on a silicon substrate. The select gate structure, in conjunction with a bit line voltage, can select and turn on a specific memory cell in a memory array, thereby laying a foundation for writing or reading the selected memory cell.
[0004] However, in the prior art, the non-volatile memory cell formed by stacking a selection gate structure and a storage gate structure on a silicon substrate has a relatively large structure, which is not conducive to the requirement of chip integration. Summary of the invention
[0005] The present application provides a three-dimensional non-volatile memory unit device structure and a manufacturing method thereof, which can solve the problem that the related technology is not conducive to the chip integration requirement.
[0006] In order to solve the technical problems described in the above background technology, the first aspect of the present application provides a method for manufacturing a three-dimensional non-volatile memory cell device structure, the manufacturing method comprising the following steps performed in sequence:
[0007] Providing a silicon substrate with a memory cell trench formed thereon, so that at least a first oxide layer is formed on the surface of the memory cell trench; defining a pattern of the memory cell trench by a hard mask layer located on the silicon substrate;
[0008] Forming a selection tube polysilicon gate on two opposite side walls of the memory cell trench respectively, wherein the selection tube polysilicon gate extends upward to cover the side wall of the pattern;
[0009] Etching and removing the first oxide layer at the position of the storage unit trench not covered by the polysilicon gate of the selection tube, so that the remaining first oxide layer forms the selection tube oxide layer;
[0010] On the side walls of the two selection tube polysilicon gates, source end polysilicon gates are formed respectively; the bottom ends of the two source end polysilicon gates are in contact with the bottom surface of the storage unit trench, and an isolation space is formed between the two source end polysilicon gates, and the bottom end of the isolation space extends downward from the bottom surface of the storage unit trench by etching;
[0011] The isolation space is filled with an isolation dielectric layer;
[0012] Removing the hard mask layer, so that after removing the hard mask layer, the upper end of the selection tube polysilicon gate, the upper end of the source end polysilicon gate and the upper end of the isolation dielectric layer are exposed from the storage unit trench to form an exposed portion;
[0013] Growing and forming an interlayer dielectric layer so that the interlayer dielectric layer wraps the exposed portion;
[0014] A storage tube polysilicon gate is formed on the silicon substrate outside the two side walls of the exposed portion; a charge storage layer is formed between the storage tube polysilicon gate and the interlayer dielectric layer located on the exposed portion.
[0015] Optionally, the step of providing a silicon substrate having a memory cell trench formed thereon, so that at least a first oxide layer is formed on a surface of the memory cell trench; and defining a pattern of the memory cell trench by a hard mask layer located on the silicon substrate comprises:
[0016] Providing a silicon substrate, wherein a pad oxide layer and a hard mask layer are sequentially formed on the upper surface of the silicon substrate from bottom to top;
[0017] The hard mask layer defines a pattern of a storage unit trench through a photolithography and etching process, so that the silicon substrate at the pattern position is etched to form a storage unit trench;
[0018] A first oxide layer is formed on the surface of the memory cell trench.
[0019] Optionally, the step of forming a selection tube polysilicon gate on two opposite side walls of the memory cell trench, respectively, and the selection tube polysilicon gate extending upward to cover the side wall of the pattern includes:
[0020] Growing first polysilicon so that the first polysilicon at least covers the surface of the memory cell trench and the pattern;
[0021] An etching process is performed to remove the first polysilicon covering the front surface, so that the remaining first polysilicon covers the side surface of the storage unit trench and the side surface of the pattern, thereby forming a polysilicon gate of the selection tube.
[0022] Optionally, the step of forming source end polysilicon gates on the side walls of the two selection tube polysilicon gates respectively; the bottom ends of the two source end polysilicon gates are in contact with the bottom surface of the memory cell trench, an isolation space is formed between the two source end polysilicon gates, and the bottom end of the isolation space is extended downward from the bottom surface of the memory cell trench by etching, comprises:
[0023] Sinking the second polysilicon to the bottom, so that the second polysilicon at least covers the side wall of the polysilicon gate of the selection tube and the bottom surface of the memory cell trench;
[0024] An etching process is performed to remove the second polysilicon covering the front surface, so that the remaining second polysilicon covers the side walls of the polysilicon gates of the two selection tubes to form source end polysilicon gates respectively.
[0025] Optionally, the step of forming a storage tube polysilicon gate on the silicon substrate outside the two side walls of the exposed portion; and forming a charge storage layer between the storage tube polysilicon gate and the interlayer dielectric layer located on the exposed portion includes:
[0026] Growing and forming a dielectric layer so that the dielectric layer covers the surface of the exposed portion and the surface of the silicon substrate;
[0027] Growing and forming a third polysilicon layer, so that the third polysilicon layer covers the dielectric layer;
[0028] The third polysilicon layer and the dielectric layer are etched by a self-aligned etching process, so that the remaining third polysilicon layer covers the silicon substrate outside the two side walls of the exposed portion to form a storage tube polysilicon gate, and the remaining dielectric layer is located at the storage tube polysilicon gate to form a charge storage layer.
[0029] Optionally, the silicon substrate includes a storage area, and the storage unit trench is arranged in the storage area.
[0030] Optionally, the silicon substrate further includes a peripheral logic region. After the three-dimensional non-volatile memory cell device structure manufacturing method is completed, the following steps are further performed:
[0031] A peripheral logic device is formed in the peripheral logic region.
[0032] In order to solve the technical problem described in the background technology, the second aspect of the present application provides a three-dimensional non-volatile memory cell device structure, wherein the three-dimensional non-volatile memory cell device structure is manufactured according to the three-dimensional non-volatile memory cell device structure manufacturing method described in the first aspect of the present application;
[0033] The three-dimensional non-volatile memory cell device structure is formed in a corresponding memory cell trench, and the corresponding memory cell trench extends downward from the upper surface of the silicon substrate;
[0034] The three-dimensional non-volatile memory cell device structure comprises:
[0035] A selection tube polysilicon gate is formed on two opposite side walls of the memory cell trench, respectively; the selection tube polysilicon gate is separated from the surface of the memory cell trench by a selection tube oxide layer;
[0036] A source end polysilicon gate is formed on the side wall of each of the selection tube polysilicon gates; the bottom end of the source end polysilicon gate contacts the bottom surface of the storage unit trench, an isolation space is formed between the source end polysilicon gates, and the bottom end of the isolation space extends downward from the bottom surface of the storage unit trench by etching;
[0037] an isolation dielectric layer, wherein the isolation dielectric layer completely fills the isolation space;
[0038] The selection tube polysilicon gate, the source end polysilicon gate and the isolation dielectric layer extend upward to expose the storage unit trench to form an exposed portion;
[0039] Also includes:
[0040] an interlayer dielectric layer, the interlayer dielectric layer covering the surface of the exposed portion;
[0041] The storage tube polysilicon gate is formed on the silicon substrate outside the two side walls of the exposed part; a charge storage layer is formed between the storage tube polysilicon gate and the interlayer dielectric layer located on the exposed part.
[0042] The technical solution of the present application includes at least the following advantages: the three-dimensional non-volatile memory cell device structure and the manufacturing method thereof provided by the present application place the selection tube polysilicon gate and the source end polysilicon gate in the memory cell trench to realize the three-dimensionalization of the non-volatile memory cell device, thereby effectively reducing the space area occupied by the memory cell device. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0044] Figure 1 A flow chart of a method for manufacturing a three-dimensional non-volatile memory cell device structure provided by an embodiment of the present application is shown;
[0045] Figure 1a A schematic cross-sectional structure diagram of the silicon substrate provided in step S111 is shown;
[0046] Figure 1b A schematic diagram of a cross-sectional structure of the device after step S112 is completed is shown;
[0047] Figure 1cA schematic diagram of a cross-sectional structure of the device after step S113 is completed is shown;
[0048] Figure 2 Shown in Figure 1c Based on the device structure shown, a schematic diagram of a device cross-sectional structure after completing step S121;
[0049] Figure 3 Shown in Figure 2 On the basis of, a schematic diagram of a cross-sectional structure of the device after completing step S13;
[0050] Figure 4a A schematic diagram of a cross-sectional structure of the device after step S141 is completed is shown;
[0051] Figure 4b Shown in Figure 4a On the basis of this, a schematic diagram of a cross-sectional structure of the device after completing step S142;
[0052] Figure 5 Shown in Figure 4b On the basis of, a schematic diagram of a cross-sectional structure of the device after completing step S15;
[0053] Figure 6 Shown in Figure 5 On the basis of, a schematic diagram of a cross-sectional structure of the device after completing step S16;
[0054] Figure 7 Shown in Figure 6 On the basis of, a schematic diagram of a cross-sectional structure of the device after completing step S17;
[0055] Figure 8a Shown based on Figure 7 The structure shown is a schematic diagram of a cross-sectional structure of the device after completing step S181;
[0056] Figure 8b Shows Figure 8a The structure shown is a schematic diagram of a cross-sectional structure of the device after completing step S182;
[0057] Figure 8c Shown based on Figure 8b The structure shown is a schematic diagram of a cross-sectional structure of the device after completing step S183;
[0058] Fig. 9 A cross-sectional structural schematic diagram of a three-dimensional non-volatile memory cell device structure provided by an embodiment of the present application is shown. DETAILED DESCRIPTION
[0059] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0060] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0061] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0062] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0063] Figure 1 A flowchart of a method for manufacturing a three-dimensional non-volatile memory cell device structure according to an embodiment of the present application is shown. Figure 1 The method for manufacturing a three-dimensional non-volatile memory cell device structure includes the following steps S11 to S18 performed in sequence:
[0064] Step S11: providing a silicon substrate with a memory cell trench formed thereon, so that at least a first oxide layer is formed on the surface of the memory cell trench; and defining a pattern of the memory cell trench by a hard mask layer located on the silicon substrate.
[0065] For step S11, steps S111 to S113 may be performed in sequence to obtain the silicon substrate having the memory cell trenches formed thereon.
[0066] Wherein, step S111: providing a silicon substrate, a pad oxide layer and a hard mask layer are sequentially formed on the upper surface of the silicon substrate from bottom to top.
[0067] Reference Figure 1a , which shows a schematic cross-sectional structure diagram of the silicon substrate provided in step S111, from Figure 1a As can be seen in FIG. 1 , the silicon substrate 100 includes an upper surface and a lower surface relative to each other, a pad oxide layer 103 is grown on the upper surface of the silicon substrate 100, and a hard mask layer 200 is grown on the pad oxide layer 103. Optionally, the material of the hard mask layer 200 can be a nitride such as silicon nitride.
[0068] Step S112: the hard mask layer is used to define a pattern of a storage unit trench by a photolithography and etching process, so that the silicon substrate at the pattern position is etched to form a storage unit trench.
[0069] Reference Figure 1b , which shows a schematic diagram of the cross-sectional structure of the device after step S112 is completed, from Figure 1b As can be seen in FIG. 1 , the silicon substrate includes a storage area 101 and a peripheral logic area 102. The storage area 101 is used to form a plurality of three-dimensional non-volatile memory cell device structures arranged in an array. The formed memory cell trench 110 is located at the storage area 101 of the silicon substrate 100.
[0070] Step S113: forming a first oxide layer on the surface of the memory cell trench.
[0071] Reference Figure 1c , which shows a schematic diagram of the cross-sectional structure of the device after step S113 is completed, from Figure 1c It can be seen from the figure that a first oxide layer 131 is formed on the surface of the silicon substrate 100 in the memory cell trench 110 .
[0072] After forming the first oxide layer on the surface of the memory cell trench, the following steps are also performed:
[0073] Step S12: forming a selection tube polysilicon gate on two opposite side walls of the memory cell trench respectively, wherein the selection tube polysilicon gate extends upward to cover the side wall of the pattern.
[0074] The step of forming the polysilicon gate of the selection tube includes the following steps S121 to S122 performed in sequence, wherein:
[0075] Step S121: growing first polysilicon so that the first polysilicon at least covers the surface of the memory cell trench and the pattern.
[0076] Reference Figure 2 , which shows that in Figure 1cBased on the device structure shown in FIG. 1 , a schematic diagram of a device cross-sectional structure after completing step S121 is shown. Figure 2 As can be seen from the figure, the grown first polysilicon 211 covers the surface of the memory cell trench 110, the surface of the pattern 210 and the surface of the remaining hard mask layer 200. The first polysilicon 211 covers the side and bottom of the memory cell trench 110.
[0077] Step S122: performing an etching process to remove the first polysilicon covering the front surface, so that the remaining first polysilicon covers the side surfaces of the memory cell trench and the side surfaces of the pattern, thereby forming a polysilicon gate of the selection tube.
[0078] Optionally, anisotropic etching can be performed so that the etching rate of the first polysilicon on the front side is faster than the etching rate of the first polysilicon on the side side, so that the remaining first polysilicon covers the side of the memory cell groove and the side of the pattern to form a polysilicon gate of the selection tube.
[0079] After forming the selection tube polysilicon gates on two opposite side walls of the memory cell trench respectively, the following steps are further performed:
[0080] Step S13: etching and removing the first oxide layer at the position of the storage unit trench not covered by the polysilicon gate of the selection tube, so that the remaining first oxide layer forms the selection tube oxide layer.
[0081] Reference Figure 3 , which shows that in Figure 2 Based on the above, the schematic diagram of the device cross-sectional structure after step S13 is completed. Figure 3 It can be seen that the select tube oxide layer 130 is located between the select tube polysilicon gate 120 and the surface of the memory cell trench 110. And located in the memory cell trench 110, the bottom surface of the memory cell trench 110 between the two select tube polysilicon gates 120 is exposed.
[0082] Step S14: forming source end polysilicon gates on the side walls of the two selection tube polysilicon gates respectively; the bottom ends of the two source end polysilicon gates are in contact with the bottom surface of the storage unit trench, and an isolation space is formed between the two source end polysilicon gates, and the bottom end of the isolation space is extended downward from the bottom surface of the storage unit trench by etching.
[0083] The step of forming source-end polysilicon gates on the side walls of the two selection tube polysilicon gates respectively comprises the following steps S141 to S142 performed in sequence, wherein:
[0084] Step S141: depositing second polysilicon so that the second polysilicon at least covers the sidewalls of the polysilicon gate of the selection tube and the bottom surface of the memory cell trench.
[0085] Reference Figure 4a , which shows a schematic diagram of the cross-sectional structure of the device after step S141 is completed, from Figure 4a As can be seen in FIG. 1 , the second polysilicon 212 covers the sidewalls of the selection tube polysilicon gate 120 , the bottom surface of the memory cell trench 110 , and the front surface of the remaining hard mask layer 200 . The second polysilicon 212 contacts the bottom surface of the memory cell trench 110 .
[0086] Step S142: performing an etching process to remove the second polysilicon covering the front surface, so that the remaining second polysilicon covers the side walls of the two selection tube polysilicon gates to form source end polysilicon gates respectively.
[0087] An anisotropic etching process can be used to make the etching rate of the second polysilicon 212 covering the front surface of the hard mask layer 200 and the second polysilicon 212 covering the bottom surface of the storage unit trench 110 faster, while the etching rate of the second polysilicon 212 covering the side wall of the selection tube polysilicon gate 120 is slower, so that after step S142 is completed, the remaining second polysilicon 212 covers the side wall of the selection tube polysilicon gate 120.
[0088] In the process of etching the second polysilicon 212 , the second polysilicon 212 covering the bottom surface of the memory cell trench 110 is removed by etching and then the silicon substrate 100 is continuously etched downward, so that the etching stop surface is located in the silicon substrate 100 .
[0089] Reference Figure 4b , which shows that in Figure 4a Based on this, a schematic diagram of the device cross-sectional structure after completing step S142 is obtained. Figure 4b It can be seen that the bottom end of the formed source polysilicon gate 140 contacts the bottom surface of the memory cell trench 110, and an isolation space 150 is formed between the source polysilicon gate 140 in the memory cell trench 110, and the bottom end of the isolation space 150 extends downward from the bottom surface of the memory cell trench 110.
[0090] After forming the source end polysilicon gate, the following steps are performed:
[0091] Step S15: Filling the isolation space with an isolation dielectric layer.
[0092] Reference Figure 5 , which shows that in Figure 4b Based on the above, the schematic diagram of the device cross-sectional structure after completing step S15 is as follows: Figure 5 As can be seen in FIG. 1 , the formed isolation dielectric layer 160 fills up the isolation space 150. The surface of the isolation dielectric layer 160 can be planarized by a chemical mechanical polishing process.
[0093] Step S16: removing the hard mask layer, so that after removing the hard mask layer, the upper end of the selection tube polysilicon gate, the upper end of the source end polysilicon gate and the upper end of the isolation dielectric layer are exposed from the storage unit trench to form an exposed portion.
[0094] Reference Figure 6 , which shows that in Figure 5 Based on the above, the schematic diagram of the device cross-sectional structure after completing step S16 is as follows: Figure 6 It can be seen that after removing the hard mask layer, the upper end of the selector polysilicon gate 120 , the upper end of the source polysilicon gate 140 and the upper end of the isolation dielectric layer 160 are exposed from the memory cell trench 110 to form an exposed portion 600 .
[0095] Step S17: growing an interlayer dielectric layer so that the interlayer dielectric layer wraps the exposed portion.
[0096] Reference Figure 7 , which shows that in Figure 6 Based on the above, the schematic diagram of the device cross-sectional structure after step S17 is completed. Figure 7 It can be seen that the interlayer dielectric layer 170 wraps the exposed portion 600, so that the selection tube polysilicon gate 120, the source end polysilicon gate 140 and the isolation dielectric layer 160 in the exposed portion 600 are prevented from being exposed.
[0097] Optionally, you can make Figure 6 The device structure shown in FIG. 1 is formed by growing an interlayer dielectric layer, and then etching the interlayer dielectric layer to form the remaining interlayer dielectric layer as shown in FIG. Figure 7 The structure shown.
[0098] Step S18: forming a storage tube polysilicon gate on the silicon substrate outside the two side walls of the exposed portion; and forming a charge storage layer between the storage tube polysilicon gate and the interlayer dielectric layer located on the exposed portion.
[0099] Optionally, the charge storage layer may be an ONO multi-layer structure, including an oxide layer, a nitride layer and an oxide layer stacked in sequence.
[0100] The step of forming a polysilicon gate of a storage tube on the silicon substrate outside the two side walls of the exposed portion may include the following steps S181 to S183:
[0101] Step S181: growing a dielectric layer so that the dielectric layer covers the surface of the exposed portion and the surface of the silicon substrate.
[0102] Reference Figure 8a , which shows that based on Figure 7 The structure shown is a schematic diagram of the cross-sectional structure of the device after completing step S181. Figure 8a It can be seen from the figure that the formed dielectric layer 800 covers the surface of the exposed portion 600 and the surface of the silicon substrate 100 .
[0103] Step S182: growing and forming a third polysilicon layer, so that the third polysilicon layer covers the dielectric layer.
[0104] Reference Figure 8b , which shows Figure 8a The structure shown is a schematic diagram of the device cross-sectional structure after completing step S182. Figure 8b It can be seen that the formed third polysilicon layer 810 covers the dielectric layer 800 .
[0105] Step S183: Etch the third polysilicon layer and the dielectric layer through a self-aligned etching process, so that the remaining third polysilicon layer covers the silicon substrate outside the two side walls of the exposed portion to form a storage tube polysilicon gate, and the remaining dielectric layer is located on the storage tube polysilicon gate to form a charge storage layer.
[0106] Reference Figure 8c , which shows that based on Figure 8b The structure shown in FIG. 1 is a schematic diagram of a cross-sectional structure of the device after completing step S183. Figure 8c It can be seen from the figure that a storage tube polysilicon gate 180 is formed on the silicon substrate 100 outside the two side walls of the exposed portion 600 , and the storage tube polysilicon gate 180 is arranged on the charge storage layer 190 .
[0107] After the three-dimensional non-volatile memory cell device is manufactured by the above-mentioned three-dimensional non-volatile memory cell device structure manufacturing method, a peripheral logic device can also be manufactured in the peripheral logic region 102 of the silicon substrate 100 .
[0108] Fig. 9 FIG. 2 shows a cross-sectional structural diagram of a three-dimensional non-volatile memory cell device structure provided by an embodiment of the present application. Figure 1 The three-dimensional non-volatile memory cell device structure is manufactured by the manufacturing method.
[0109] from Fig. 9 It can be seen that the three-dimensional non-volatile memory cell device structure is arranged in a silicon substrate 100, and the silicon substrate 100 includes a storage area 101 and a peripheral logic area 102; the storage area 101 is provided with a plurality of three-dimensional non-volatile memory cell device structures arranged in an array, and the peripheral logic area 102 is formed with a peripheral logic device 900.
[0110] Each three-dimensional non-volatile memory cell device structure is disposed in a corresponding memory cell trench 110 , and a portion of the memory cell device structure is exposed from the memory cell trench 110 . The memory cell trench 110 extends downward from the upper surface of the silicon substrate 100 .
[0111] Each three-dimensional non-volatile memory cell device structure includes: a selection tube polysilicon gate 120 , a source end polysilicon gate 140 , an isolation dielectric layer 160 , an interlayer dielectric layer 170 , and a storage tube polysilicon gate 180 .
[0112] For the selection tube polysilicon gate 120; the selection tube polysilicon gate 120 is formed on two opposite side walls of the memory cell trench 110 respectively, and the selection tube polysilicon gate 120 extends upward to expose the memory cell trench 110, and the selection tube polysilicon gate 120 is separated from the surface of the memory cell trench 110 by the selection tube oxide layer 130.
[0113] For the source polysilicon gate 140; a source polysilicon gate 140 is formed on the side wall of each of the two selection tube polysilicon gates 120, and the source polysilicon gate 140 is attached to the surface of the selection tube polysilicon gate 120, and the bottom end of the source polysilicon gate 140 is in contact with the bottom surface of the storage cell trench 110, and the upper end of the source polysilicon gate 140 is exposed to the storage cell trench 110, and an isolation space 150 is formed between two adjacent source polysilicon gates 140, and the bottom end of the isolation space 150 is extended downward by a depth h from the bottom surface of the storage cell trench 110 by etching, and the upper end of the isolation space 150 is exposed to the storage cell trench 110.
[0114] The isolation dielectric layer 160 completely fills the isolation space 150, and the upper end of the isolation dielectric layer 160 is also exposed from the memory cell trench 110. Optionally, the isolation dielectric layer 160 may be made of silicon dioxide.
[0115] The selection tube polysilicon gate 120, the source end polysilicon gate 140 and the isolation dielectric layer 160 extend upward to expose the memory cell trench 110 to form an exposed portion.
[0116] As for the interlayer dielectric layer 170 , the interlayer dielectric layer 170 wraps around the surface of the exposed portion.
[0117] The storage tube polysilicon gate 180 is formed on the silicon substrate 100 outside the two side walls of the exposed portion; a charge storage layer 190 is formed between the storage tube polysilicon gate 180 and the interlayer dielectric layer 170 located on the exposed portion.
[0118] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for manufacturing a three-dimensional non-volatile memory cell device structure, It is characterized in that The manufacturing method comprises the following steps performed in sequence: Providing a silicon substrate with a memory cell trench formed thereon, so that at least a first oxide layer is formed on the surface of the memory cell trench; defining a pattern of the memory cell trench by a hard mask layer located on the silicon substrate; Forming a selection tube polysilicon gate on two opposite side walls of the memory cell trench respectively, wherein the selection tube polysilicon gate extends upward to cover the side wall of the pattern; Etching and removing the first oxide layer at the position of the storage unit trench not covered by the polysilicon gate of the selection tube, so that the remaining first oxide layer forms the selection tube oxide layer; On the side walls of the two selection tube polysilicon gates, source end polysilicon gates are formed respectively; the bottom ends of the two source end polysilicon gates are in contact with the bottom surface of the storage unit trench, and an isolation space is formed between the two source end polysilicon gates, and the bottom end of the isolation space extends downward from the bottom surface of the storage unit trench by etching; The isolation space is filled with an isolation dielectric layer; Removing the hard mask layer, so that after removing the hard mask layer, the upper end of the selection tube polysilicon gate, the upper end of the source end polysilicon gate and the upper end of the isolation dielectric layer are exposed from the storage unit trench to form an exposed portion; Growing and forming an interlayer dielectric layer so that the interlayer dielectric layer wraps the exposed portion; A storage tube polysilicon gate is formed on the silicon substrate outside the two side walls of the exposed portion; a charge storage layer is formed between the storage tube polysilicon gate and the interlayer dielectric layer located on the exposed portion.
2. The method for manufacturing a three-dimensional non-volatile memory cell device structure according to claim 1, It is characterized in that The step of providing a silicon substrate having a memory cell trench formed thereon, at least forming a first oxide layer on a surface of the memory cell trench; The step of defining the pattern of the storage unit trench through a hard mask layer located on the silicon substrate comprises: Providing a silicon substrate, wherein a pad oxide layer and a hard mask layer are sequentially formed on the upper surface of the silicon substrate from bottom to top; The hard mask layer defines a pattern of a storage unit trench through a photolithography and etching process, so that the silicon substrate at the pattern position is etched to form a storage unit trench; A first oxide layer is formed on the surface of the memory cell trench.
3. The method for manufacturing a three-dimensional non-volatile memory cell device structure according to claim 1, It is characterized in that The step of forming a selection tube polysilicon gate on two opposite side walls of the memory cell trench, respectively, wherein the selection tube polysilicon gate extends upward to cover the side wall of the pattern, comprises: Growing first polysilicon so that the first polysilicon at least covers the surface of the memory cell trench and the pattern; An etching process is performed to remove the first polysilicon covering the front surface, so that the remaining first polysilicon covers the side surface of the storage unit trench and the side surface of the pattern, thereby forming a polysilicon gate of the selection tube.
4. The method for manufacturing a three-dimensional non-volatile memory cell device structure according to claim 1, It is characterized in that The steps of forming source end polysilicon gates on the side walls of the two selection tube polysilicon gates respectively; the bottom ends of the two source end polysilicon gates are in contact with the bottom surface of the storage unit trench, forming an isolation space between the two source end polysilicon gates, and extending the bottom end of the isolation space downward from the bottom surface of the storage unit trench by etching, include: Depositing second polysilicon so that the second polysilicon at least covers the sidewalls of the polysilicon gate of the selection tube and the bottom surface of the memory cell trench; An etching process is performed to etch away the second polysilicon covering the front surface, so that the remaining second polysilicon covers the side walls of the polysilicon gates of the two selection tubes to form source end polysilicon gates respectively.
5. The method for manufacturing a three-dimensional non-volatile memory cell device structure according to claim 1, It is characterized in that The steps of forming a storage tube polysilicon gate on the silicon substrate outside the two side walls of the exposed portion; and forming a charge storage layer between the storage tube polysilicon gate and the interlayer dielectric layer located on the exposed portion include: Growing and forming a dielectric layer so that the dielectric layer covers the surface of the exposed portion and the surface of the silicon substrate; Growing and forming a third polysilicon layer, so that the third polysilicon layer covers the dielectric layer; The third polysilicon layer and the dielectric layer are etched by a self-aligned etching process, so that the remaining third polysilicon layer covers the silicon substrate outside the two side walls of the exposed portion to form a storage tube polysilicon gate, and the remaining dielectric layer is located at the storage tube polysilicon gate to form a charge storage layer.
6. The method for manufacturing a three-dimensional non-volatile memory cell device structure according to claim 1, It is characterized in that The silicon substrate includes a storage area, and the storage cell trench is arranged in the storage area.
7. The method for manufacturing a three-dimensional non-volatile memory cell device structure according to claim 1, It is characterized in that The silicon substrate also includes a peripheral logic area. After the three-dimensional non-volatile memory cell device structure manufacturing method is completed, the following steps are further performed: A peripheral logic device is formed in the peripheral logic region.
8. A three-dimensional non-volatile memory cell device structure, It is characterized in that The three-dimensional non-volatile memory cell device structure is manufactured according to the three-dimensional non-volatile memory cell device structure manufacturing method according to any one of claims 1 to 7; The three-dimensional non-volatile memory cell device structure is formed in a corresponding memory cell trench and is arranged so that the corresponding memory cell trench extends downward from the upper surface of the silicon substrate; The three-dimensional non-volatile memory cell device structure comprises: A selection tube polysilicon gate is formed on two opposite side walls of the memory cell trench, respectively; the selection tube polysilicon gate is separated from the surface of the memory cell trench by a selection tube oxide layer; A source end polysilicon gate is formed on the side wall of each of the selection tube polysilicon gates; the bottom end of the source end polysilicon gate contacts the bottom surface of the storage unit trench, an isolation space is formed between the source end polysilicon gates, and the bottom end of the isolation space extends downward from the bottom surface of the storage unit trench by etching; an isolation dielectric layer, wherein the isolation dielectric layer completely fills the isolation space; The selection tube polysilicon gate, the source end polysilicon gate and the isolation dielectric layer extend upward to expose the storage unit trench to form an exposed portion; Also includes: an interlayer dielectric layer, the interlayer dielectric layer covering the surface of the exposed portion; The storage tube polysilicon gate is formed on the silicon substrate outside the two side walls of the exposed part; a charge storage layer is formed between the storage tube polysilicon gate and the interlayer dielectric layer located on the exposed part.