Clock duty cycle adjustment circuit, method and electronic equipment

Abstract

The present application relates to a clock duty cycle adjustment circuit, method and electronic device, belonging to the field of electronic circuit technology. The clock duty cycle adjustment circuit includes a differential clock circuit, a control signal circuit, and a duty cycle adjustment circuit. The differential clock circuit is used to output a first differential clock signal and a second differential clock signal; the control signal circuit is used to detect the high level width and low level width of the first clock signal according to the first differential clock signal and the second differential clock signal, and generate a control signal for adjusting the clock duty cycle according to the difference between the high level width and the low level width; the duty cycle adjustment circuit is used to adjust the duty cycle of the first clock signal according to the control signal, so that the duty cycle of the adjusted first clock signal approaches 50%, and outputs the adjusted first clock signal. The clock duty cycle adjustment circuit has the advantages of simple circuit structure, fast response speed, and small area occupied after the layout design is completed.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuit technology, and specifically relates to a clock duty cycle adjustment circuit, method and electronic equipment. Background Art

[0002] In integrated circuits, clock signals drive the sequential logic devices throughout the chip and control the operating frequency of the entire chip, so clock signal quality is crucial. The clock duty cycle refers to the ratio of the clock signal's high-level width to the total clock signal width. Typically, when the clock signal's high-level width and low-level width are equal, the clock signal's duty cycle is 50%.

[0003] However, during clock signal transmission, due to device delays, the clock signal's duty cycle can deviate from 50%. This imbalance in the width of the clock signal's high and low levels can cause poor clock signal quality. For high-speed clock circuits, where the chip's operating frequency is very high, this deviation can significantly impact overall chip performance and even cause functional errors. Therefore, during clock signal transmission, signals with a duty cycle that deviates from 50% must be readjusted to 50% to ensure clock signal quality during transmission.

[0004] Existing clock duty cycle adjustment circuits are typically implemented using analog circuits. First, the clock duty cycle adjustment circuit adjusts the input clock signal to generate an adjusted clock. A divide-by-two circuit is also designed to generate a clock with a 50% duty cycle, which serves as a reference clock. Next, a duty cycle voltage conversion circuit is designed to convert the adjusted clock to generate the duty cycle integral voltage of the clock to be adjusted. Simultaneously, the reference clock is converted to generate the reference clock duty cycle integral voltage. An analog voltage comparator then compares the input clock duty cycle integral voltage with the reference clock duty cycle integral voltage, generating a comparison signal. Finally, a logic control circuit controls the clock duty cycle adjustment circuit to achieve the desired adjustment target.

[0005] Although the clock duty cycle adjustment circuit can achieve clock duty cycle adjustment, it requires repeated operations to adjust the clock duty cycle to a relatively ideal state (clock duty cycle close to 50%); secondly, the circuit design is complex and there are many sub-circuit modules, which makes the circuit power consumption larger, and after the layout design is completed, it occupies a large area in the chip. Summary of the Invention

[0006] In view of this, the purpose of this application is to provide a clock duty cycle adjustment circuit, method and electronic device to improve the problems of complex circuit design, slow response speed and large area occupied after layout design of existing clock duty cycle adjustment circuits.

[0007] The embodiment of the present application is implemented as follows:

[0008] In the first aspect, an embodiment of the present application provides a clock duty cycle adjustment circuit, comprising: a differential clock circuit, a control signal circuit, and a duty cycle adjustment circuit; the differential clock circuit is used to output a first differential clock signal and a second differential clock signal for detecting the high level width and the low level width of the first clock signal based on the input first clock signal and the divided-by-two clock signal of the first clock signal; the control signal circuit is connected to the differential clock circuit, and is used to detect the high level width and the low level width of the first clock signal based on the input first differential clock signal and the second differential clock signal, and to generate a control signal for adjusting the clock duty cycle based on the difference between the high level width and the low level width; the duty cycle adjustment circuit is connected to the control signal circuit, and is used to adjust the duty cycle of the first clock signal according to the control signal, so that the duty cycle of the adjusted first clock signal approaches 50%, and output the adjusted first clock signal. In the embodiment of the present application, a differential clock circuit is used to generate a first differential clock signal (and a second differential clock signal) for detecting the high level width and low level width of the first clock signal. Then, the control signal circuit detects the high level width and low level width of the first clock signal according to the first differential clock signal and the second differential clock signal, and generates a control signal for adjusting the clock duty cycle according to the difference between the detected high level width and the low level width. Then, the duty cycle adjustment circuit adjusts the duty cycle of the first clock signal according to the control signal. If the duty cycle of the first clock signal is greater than 50%, the duty cycle of the first clock signal is 0%. , the high-level width of the first clock signal is reduced, and the output clock duty cycle is adjusted toward 50%. If the duty cycle is less than 50%, the high-level width of the first clock signal is increased, and the clock duty cycle is adjusted toward 50%, so that the duty cycle of the adjusted first clock signal approaches 50%. In this way, the clock duty cycle can be quickly adjusted to an ideal state close to 50%, without the need to repeat the operation multiple times like the method of the prior art to adjust the clock duty cycle to a relatively ideal state; in addition, it has the advantages of simple circuit structure and small area occupied after the layout design is completed.

[0009] In combination with a possible implementation manner of the embodiment of the first aspect, the control signal circuit includes: a sense amplifier SA and a latch circuit; the sense amplifier SA is connected to the differential clock circuit, a precharge terminal of the sense amplifier is used to receive an SA precharge signal, and the SA precharge signal is used to charge a first signal line and a second signal line inside the sense amplifier; an enable terminal of the sense amplifier is used to receive an SA enable signal, and the sense amplifier, under the action of the SA enable signal and the SA precharge signal, is used to: control the voltage discharge on the first signal line inside the sense amplifier according to the first differential clock signal and the second differential clock signal at a first moment, wherein the residual voltage on the first signal line is related to the high-level width of the first clock signal; control the voltage discharge on the second signal line inside the sense amplifier according to the first differential clock signal and the second differential clock signal at a second moment, wherein the residual voltage on the second signal line is related to the low-level width of the first clock signal; and detect the difference between the residual voltage on the first signal line and the residual voltage on the second signal line according to the first differential clock signal and the second differential clock signal at a third moment, and output an intermediate signal based on the difference. A latch circuit is connected to the sense amplifier and is configured to latch the intermediate signal under the control of an enable signal of the latch circuit to obtain the control signal, wherein the enable signal of the latch circuit is consistent with the SA enable signal of the sense amplifier. In an embodiment of the present application, the sense amplifier SA and the latch circuit of the digital circuit are used to detect the high-level width and low-level width of the first clock signal, and generate a control signal for adjusting the clock duty cycle based on the difference between the detected high-level width and low-level width. Due to the simple structure and fast response speed of the digital circuit, the high-level and low-level widths of the input clock signal can be quickly detected, and the duty cycle adjustment signal can be generated to adjust the duty cycle of the input clock signal.

[0010] In combination with a possible implementation method of the first aspect, at the first moment, the first clock signal is high, the first differential clock signal is high and the high-level width is consistent with the high-level width of the first clock signal, and the second differential clock signal, the SA pre-charge signal, and the SA enable signal are low; at the second moment, the first clock signal, the SA pre-charge signal, the SA enable signal, and the first differential clock signal are low, and the second differential clock signal is high and the high-level width is consistent with the low-level width of the first clock signal; at the third moment, the first clock signal, the SA pre-charge signal, and the SA enable signal are high, and the first differential clock signal and the second differential clock signal are low. In the embodiment of the present application, by adopting the timing signal with the above characteristics, SA can accurately detect the high-level width and the low-level width, so that the control signal generated can adjust the duty cycle of the first clock signal towards 50% as much as possible.

[0011] In combination with a possible implementation manner of the embodiment of the first aspect, the control signal circuit also includes: a first logic circuit, wherein the two input ends of the first logic circuit respectively receive the first clock signal and the divided-by-two clock signal, the output end of the first logic circuit is connected to the pre-charge end of the sensitive amplifier, and the first logic circuit is used to generate the SA pre-charge signal according to the first clock signal and the divided-by-two clock signal; a second logic circuit, wherein the two input ends of the second logic circuit respectively receive the first clock signal and the divided-by-two clock signal, the output end of the second logic circuit is connected to the enable end of the sensitive amplifier and the enable end of the latch circuit, and the second logic circuit is used to generate the SA enable signal according to the first clock signal and the divided-by-two clock signal. In an embodiment of the present application, a first logic circuit is used to generate an SA pre-charge signal based on a first clock signal and a divided-by-two clock signal, and a second logic circuit is used to generate an SA enable signal based on the first clock signal and the divided-by-two clock signal, so that timing signals such as the SA pre-charge signal, the SA enable signal, the first differential clock signal, and the second differential clock signal can all be generated based on the first clock signal and the divided-by-two clock signal. This can greatly simplify the cost of generating the timing signals and quickly obtain the required timing signals.

[0012] In combination with a possible implementation of the embodiment of the first aspect, the differential clock circuit includes: a first branch and a second branch; the first branch is used to AND the input first clock signal and the two-frequency clock signal, and output the first differential clock signal; the second branch is used to AND the input two-frequency clock signal and the inverted clock signal of the first clock signal, and output the second differential clock signal; wherein the delay of the first branch is consistent with the delay of the second branch. In the embodiment of the present application, the delay of the first branch generating the first differential clock signal is consistent with the delay of the second branch generating the second differential clock signal, so as to ensure that the first rising edge of the first differential clock signal is aligned with the first rising edge of the second differential clock signal, or to ensure that the first falling edge of the first differential clock signal is aligned with the first falling edge of the second differential clock signal.

[0013] In conjunction with a possible implementation of the embodiment of the first aspect, the duty cycle adjustment circuit includes: a first-stage inverter and a second-stage inverter; the control terminal of the first-stage inverter is used to receive an inverted clock signal of the first clock signal; the second-stage inverter is connected in series with the first-stage inverter, the internal control terminal of the second-stage inverter is connected to the control terminal of the first-stage inverter, the external control terminal of the second-stage inverter is used to receive the control signal, and the output terminal of the first-stage inverter is connected to the output terminal of the second-stage inverter; the size of the first-stage inverter is smaller than the size of the second-stage inverter, the channel of the first-stage inverter is in a normally open state, and the second-stage inverter controls the closing or opening of its own channel according to the control signal, thereby adjusting the duty cycle of the first clock signal so that the duty cycle of the adjusted clock signal approaches 50%, and outputs the adjusted clock signal. In the embodiment of the present application, since the first-stage inverter does not have an adjustment function, the size of the first-stage inverter is smaller than the size of the second-stage inverter, so that the adjustment effect is more obvious and the response speed is faster.

[0014] In combination with a possible implementation of the embodiment of the first aspect, the second-stage inverter includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; the first end of the first transistor is connected to a power supply, the second end of the first transistor is connected to the first end of the second transistor, the second end of the second transistor is connected to the second end of the third transistor, the first end of the third transistor is connected to the second end of the fourth transistor, the first end of the fourth transistor is grounded, the control end of the first transistor and the control end of the fourth transistor are connected to the control signal, the control end of the second transistor and the control end of the third transistor are used to receive an inverted clock signal of the first clock signal, and the second end of the second transistor is connected to the output end of the first-stage inverter. In the embodiment of the present application, common transistors are used to form the second-stage inverter, so that while realizing the duty cycle adjustment function, it can also further save costs and reduce circuit complexity.

[0015] In combination with a possible implementation of the embodiment of the first aspect, the clock duty cycle adjustment circuit further includes: a divide-by-two circuit, connected to the differential clock circuit, for generating the divide-by-two timing signal based on the first clock signal, the duty cycle of the divide-by-two clock signal being 50%, and the first rising edge of the divide-by-two clock signal being aligned with the first rising edge of the first clock signal, or the first falling edge of the divide-by-two clock signal being aligned with the first falling edge of the first clock signal. In the embodiment of the present application, the clock duty cycle adjustment circuit further includes a divide-by-two circuit, so that the clock duty cycle adjustment circuit itself can generate the divide-by-two circuit required for duty cycle adjustment, making the clock duty cycle adjustment circuit more independent.

[0016] In combination with a possible implementation of the embodiment of the first aspect, the clock duty cycle adjustment circuit further includes: a selection circuit, wherein the first input end of the selection circuit is used to receive the initial clock signal, the second input end of the selection circuit is connected to the output end of the duty cycle adjustment circuit, the selection end of the selection circuit is used to receive a selection signal, and the selection circuit is used to select and output the initial clock signal or the adjusted first clock signal according to the selection signal, wherein the first clock signal is the clock signal obtained by ANDing the initial clock signal with the selection signal. In the embodiment of the present application, the clock duty cycle adjustment circuit can directly output the initial clock signal when duty cycle adjustment is not required, and can output the adjusted clock signal when adjustment is required, which is more practical.

[0017] In a second aspect, embodiments of the present application further provide a clock duty cycle adjustment circuit, comprising multiple clock duty cycle adjustment circuits as provided in the embodiments of the first aspect and / or any possible implementation method in combination with the embodiments of the first aspect, wherein the multiple clock duty cycle adjustment circuits are connected in series. In the embodiments of the present application, a multi-stage clock duty cycle adjustment circuit is used to adjust the duty cycle of the clock signal. After multiple continuous adjustments, the duty cycle of the final output clock signal can be further approached to 50%.

[0018] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a clock module for generating an initial clock signal and a clock duty cycle adjustment circuit provided by the above-mentioned first aspect embodiment and / or any possible implementation method in combination with the first aspect embodiment, or a clock duty cycle adjustment circuit provided by the above-mentioned second aspect embodiment; the clock duty cycle adjustment circuit is used to adjust the duty cycle of the initial clock signal so that the adjusted clock duty cycle approaches 50%.

[0019] In a fourth aspect, an embodiment of the present application also provides a clock duty cycle adjustment method, comprising: generating a first differential clock signal and a second differential clock signal for detecting the high level width and the low level width of the first clock signal based on a first clock signal and a divided-by-two clock signal of the first clock signal; detecting the high level width and the low level width of the first clock signal based on the first differential clock signal and the second differential clock signal, and generating a control signal for adjusting the clock duty cycle based on the difference between the high level width and the low level width; adjusting the duty cycle of the first clock signal based on the control signal so that the adjusted duty cycle of the first clock signal approaches 50%.

[0020] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or understood by practicing the embodiments of the present application. The objectives and other advantages of the present application can be achieved and obtained through the structures particularly pointed out in the written description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. The above and other purposes, features and advantages of the present application will be more clearly shown in the accompanying drawings. The same reference numerals indicate the same parts throughout the drawings. The drawings are not intentionally scaled to actual size, and the focus is on illustrating the main purpose of the present application.

[0022] Figure 1 A schematic structural diagram of a clock duty cycle adjustment circuit provided in an embodiment of the present application is shown.

[0023] Figure 2 A circuit diagram of a differential clock circuit provided in an embodiment of the present application is shown.

[0024] Figure 3 A schematic diagram of timing waveforms of a first clock signal, a divided-by-two clock signal, a first differential clock signal, and a second differential clock signal provided in an embodiment of the present application is shown.

[0025] Figure 4 A circuit diagram of a control signal circuit provided in an embodiment of the present application is shown.

[0026] Figure 5 A circuit diagram of the internal structure of an SA provided in an embodiment of the present application is shown.

[0027] Figure 6 A schematic diagram showing timing waveforms involved in a clock duty cycle adjustment circuit provided by the present application and embodiments is shown.

[0028] Figure 7 A circuit diagram of another control signal circuit provided by the present application and embodiments is shown.

[0029] Figure 8 A circuit diagram of a duty cycle adjustment circuit provided by the present application and embodiments is shown.

[0030] Figure 9 A circuit diagram of another duty cycle adjustment circuit provided by the present application and embodiments is shown.

[0031] Figure 10 A circuit schematic diagram showing a duty cycle adjustment circuit connected to a selection circuit provided in the present application and embodiments is shown.

[0032] Figure 11 A circuit schematic diagram showing a two-frequency divider circuit connected to a differential clock circuit provided by the present application and embodiments is shown.

[0033] Figure 12 A circuit diagram of another clock duty cycle adjustment circuit provided by the present application and embodiments is shown.

[0034] Figure 13 A schematic structural diagram of a clock duty cycle adjustment circuit provided by the present application and embodiments is shown.

[0035] Figure 14 A flow chart of a clock duty cycle adjustment method provided by the present application and embodiments is shown. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0037] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in the subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "comprise a..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0038] Furthermore, the term "and / or" in this application is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0039] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integral connection; they can also refer to electrical connection; they can refer to direct connection, indirect connection through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0040] First embodiment

[0041] In view of the defects of the existing clock duty cycle adjustment circuit, the embodiment of the present application provides a new clock duty cycle adjustment circuit based on digital circuits, which does not use analog circuits but uses all digital circuits to complete the duty cycle adjustment function. It has the advantages of simple circuit structure, fast response speed, and small area occupied after the layout design is completed. Through this clock duty cycle adjustment circuit, the clock duty cycle can be quickly adjusted to an ideal state close to 50%.

[0042] The following will be combined Figure 1, the clock duty cycle adjustment circuit provided in the embodiment of the present application is described. The clock duty cycle adjustment circuit includes a differential clock circuit, a control signal circuit and a duty cycle adjustment circuit. The differential clock circuit is connected to the control signal circuit, and the control signal circuit is connected to the duty cycle adjustment circuit. By utilizing the differential clock circuit to generate a first differential clock signal (such as represented by a CLKA signal) and a second differential clock signal (such as represented by a CLKB signal) for detecting the high level width and low level width of the first clock signal (such as represented by a CLKI signal), the control signal circuit then detects the high level width and low level width of the first clock signal according to the first differential clock signal and the second differential clock signal, and generates a control signal (such as represented by an ENP signal and an ENN signal) for adjusting the clock duty cycle according to the difference between the detected high level width and the low level width, and then the duty cycle adjustment circuit is based on The control signal is used to adjust the duty cycle of the first clock signal. If the duty cycle of the first clock signal is greater than 50%, the high-level width of the first clock signal is reduced, and the output clock duty cycle is adjusted toward 50%. If the duty cycle is less than 50%, the high-level width of the first clock signal is increased, and the clock duty cycle is also adjusted toward 50%, so that the adjusted duty cycle of the first clock signal approaches 50%. In this way, the clock duty cycle can be quickly adjusted to an ideal state close to 50%, without the need to repeat the operation multiple times like the method in the prior art to adjust the clock duty cycle to a relatively ideal state.

[0043] The differential clock circuit is configured to output a first differential clock signal and a second differential clock signal for detecting the high-level width and low-level width of the first clock signal based on the input first clock signal and a clock signal divided by two (e.g., represented by the CLKD2 signal). The differential clock circuit receives the first clock signal and the clock signal divided by two as input, and outputs the first differential clock signal and the second differential clock signal.

[0044] In one embodiment, a differential clock circuit includes: a first branch and a second branch. The first branch is used to perform an AND operation on an input first clock signal and a divided-by-two clock signal, outputting a first differential clock signal. The second branch is used to perform an AND operation on the input divided-by-two clock signal and an inverted clock signal of the first clock signal, outputting a second differential clock signal. The delay of the first branch is consistent with the delay of the second branch to ensure that the first rising edge of the first differential clock signal is aligned with the first rising edge of the second differential clock signal, or to ensure that the first falling edge of the first differential clock signal is aligned with the first falling edge of the second differential clock signal.

[0045] Optionally, the first branch includes a normally-open transmission gate and a first logic device. The input of the normally-open transmission gate is used to receive a first clock signal, the output of the normally-open transmission gate is connected to the first input of the first logic device, the second input of the first logic device is used to receive a divided-by-two clock signal, and the first logic device is used to AND the first clock signal with the divided-by-two clock signal to output a first differential clock signal. The second branch includes a second logic device and a third logic device. The input of the third logic device is used to receive the first clock signal, the output of the third logic device is connected to the first input of the second logic device, and the third logic device is used to output an inverted clock signal of the first clock signal. The second input of the second logic device is used to receive the divided-by-two clock signal, and the output of the second logic device is used to output a second differential clock signal.

[0046] The first logic device and the third logic device are logic devices of the same type, such as AND gates, and their delays are consistent. The delay of opening the transmission gate is consistent with the delay of the second logic device to ensure that the delays of the first branch and the second branch are consistent. The second logic device can be an inverter. Since the clock signal in this application is a digital signal, the second logic device can also be a NOT gate. In this case, the circuit of the differential clock circuit is as follows: Figure 2 shown.

[0047] In one embodiment, the normally open transmission gate can be replaced by a buffer or a delay. In this case, the first branch includes the buffer or the delay and the first logic device. Figure 2 The circuit schematic shown is understood to be a limitation of the differential clock circuit.

[0048] For ease of understanding, the timing waveforms of the first clock signal (CLKI signal), the divided-by-two clock signal (CLKD2 signal), the first differential clock signal (CLKA signal), and the second differential clock signal (CLKB signal) are shown in FIG. 1 . In one embodiment, the timing waveforms of the first clock signal, the divided-by-two clock signal, the first differential clock signal, and the second differential clock signal are shown in FIG. Figure 3 At time T1 and T2, only one of the CLKA signal and the CLKB signal is at a high level, and at time T3, both the CLKA signal and the CLKB signal are at a low level.

[0049] It should be noted that Figure 3 The timing waveform shown is only an example. Figure 3The CLKI waveform in FIG. 1 is a schematic diagram illustrating a waveform in which the CLKI signal has a duty cycle greater than 50%. Alternatively, the CLKI duty cycle can be less than 50%. Furthermore, the waveforms of the CLKA and CLKB signals can be swapped. After this swap, at time T1, the CLKA signal is low and the CLKB signal is high. At time T2, the CLKA signal is high and the CLKB signal is low.

[0050] Among them, the clock duty cycle of the divided-by-two clock signal is 50%, that is, the high level width and the low level width of the clock signal are equal, and the first rising edge of the divided-by-two clock signal is aligned with the first rising edge of the first clock signal, or the first falling edge of the divided-by-two clock signal is aligned with the first falling edge of the first clock signal.

[0051] The control signal circuit is connected to the differential clock circuit, and is used to detect the high level width and low level width of the first clock signal based on the input first differential clock signal and the second differential clock signal, and generate a control signal for adjusting the clock duty cycle based on the difference between the high level width and the low level width.

[0052] In one embodiment, the control signal circuit includes a sense amplifier (SA) and a latch circuit, the schematic diagram of which is shown as follows: Figure 4 As shown. The sense amplifier SA is connected to the differential clock circuit and the latch circuit. The SAPCHX precharge terminal of the sense amplifier is used to receive the SA precharge signal (such as represented by the SAPCHX signal). The SA precharge signal is used to charge the first signal line and the second signal line within the sense amplifier. The SAEN enable terminal of the sense amplifier is used to receive the SA enable signal (such as represented by the SAEN signal). The CLKA signal input terminal of the sense amplifier SA is used to receive the CLKA signal, and the CLKB signal input terminal is used to receive the CLKB signal.

[0053] Under the influence of the SA enable signal and the SA precharge signal, the sense amplifier is configured to control the discharge of the voltage on the first signal line within the sense amplifier according to the first differential clock signal and the second differential clock signal at a first moment (time T1). The residual voltage on the first signal line is related to the high-level width of the first clock signal. The longer the high-level width, the longer the discharge time, and thus the smaller the residual voltage on the first signal line.

[0054] Under the action of the SA enable signal and the SA pre-charge signal, the sensitive amplifier is used to control the voltage discharge on the second signal line inside the sensitive amplifier according to the first differential clock signal and the second differential clock signal at the second moment (moment T2). The residual voltage on the second signal line is related to the low-level width of the first clock signal, and the residual voltage on the second signal line is related to the low-level width of the first clock signal. The wider the low-level width, the longer the discharge time, and thus the smaller the amount of residual voltage on the first signal line.

[0055] Under the influence of the SA enable signal and the SA precharge signal, the sense amplifier is configured to detect the difference between the residual voltage on the first signal line and the residual voltage on the second signal line based on the first differential clock signal and the second differential clock signal at a third moment (moment T3), and output an intermediate signal (e.g., represented by an OH signal and an OL signal) based on the difference. Since the residual voltage on the first signal line is related to the high-level width of the first clock signal, and the residual voltage on the second signal line is related to the low-level width of the first clock signal, the difference between the residual voltage on the first signal line and the residual voltage on the second signal line represents the difference between the high-level width and the low-level width of the first clock signal.

[0056] At the fourth moment (T4), the sense amplifier performs pre-charging under the action of the SA enable signal and the SA pre-charge signal, and charges the first signal line and the second signal line in the SA to a high level.

[0057] Among them, a complete clock duty cycle adjustment needs to go through 4 moments:

[0058] At time T1, the control signal circuit uses SA to detect the high level width (or low level width) of the CLKI signal; at time T1, the first clock signal is high, the first differential clock signal is high and the high level width is consistent with the high level width of the first clock signal, and the second differential clock signal, SA precharge signal, and SA enable signal are low. It should be noted that the low level width of the CLKI signal can also be detected at time T1, that is, when Figure 3 After the CLKA signal and the CLKB signal are swapped, at time T1 , the CLKA signal is at a low level and the CLKB signal is at a high level. At this time, the low level width of the CLKI signal is detected at time T1 .

[0059] At time T2, the control signal circuit uses SA to detect the low-level width (or high-level width) of the CLKI signal; at time T2, the first clock signal, SA precharge signal, SA enable signal, and first differential clock signal are at a low level, and the second differential clock signal is at a high level, and the high-level width is consistent with the low-level width of the first clock signal. It should be noted that the high-level width of the CLKI signal can also be detected at time T2, that is, when Figure 3 After the CLKA signal and the CLKB signal are swapped, at time T2, the CLKA signal is at a high level and the CLKB signal is at a low level. At this time, the high level width of the CLKI signal is detected at time T2.

[0060] At time T3, the control signal circuit generates the duty cycle adjustment control signal ENP and ENN signals according to the difference in the high and low level widths of the CLKI signal to adjust the duty cycle of the input clock; at time T3, the first clock signal, SA pre-charge signal, and SA enable signal are high, and the first differential clock signal and the second differential clock signal are low.

[0061] At time T4, SA is precharged to charge the first signal line and the second signal line in SA to a high level. Due to SA precharge, the first signal line and the second signal line need to be maintained at a low level.

[0062] In order to better understand the working principle of SA at the above four moments, Figure 5 The SA circuit schematic diagram shown in FIG. 1 illustrates the above process.

[0063] When the SAPCHX signal is at a low level, transistors P0 and P1 are turned on, pulling up the internal signal lines SAT and SAC to a high level. Among them, transistors P0 and P1 are relatively large in size, and when the SAPCHX signal is set to 0, the signal lines SAT and SAC can be quickly pulled up to a high level. When the SAEN signal is at a low level, the pull-up transistors P2 and P3 are driven to turn on, pulling up the internal signal lines Int and Inc to a high level. Since both the signal lines Int and Inc are pulled up to a high level, the OH port of SA outputs a high level signal, and the OL port outputs a low level signal. Among them, the OH port and the OL port are connected to Figure 4 The latch circuit in .

[0064] The following combination Figure 6The signal timing waveform shown is used to illustrate that at moment T1, SA detects the high-level width of the CLKI signal. At moment T1, the SAPCHX signal flips to a high-level signal, transistors P0 and P1 are turned off, the internal signal lines SAT and SAC are in a high-level floating state, the CLKA signal flips to a high level, and the CLKB signal flips to a low level. The high-level width of the CLKA signal is equal to the high-level width of the CLKI signal. The CLKA signal is at a high level, driving the NMOS transistor N1 and transistor N2 to turn on, so that the voltage on the signal line SAT is discharged, and the voltage on the internal signal line SAT will be slowly pulled down. When designing the circuit, a large capacitor will be loaded on the SAT signal line. At the same time, the size of transistors N1 and N2 is small, and transistors N1 and N2 are in series. This design can ensure that the voltage on SAT is only pulled down to an intermediate level value higher than 0, which is greater than the turn-on threshold of transistor T1. The waveform diagram of the signal line SAT is shown as follows. Figure 6 As shown. At T1, the CLKB signal is at a low level, driving the NMOS transistor N3 and transistor N4 to turn off, and the internal signal SAC is maintained at a high level. At the same time, at T1, the SAEN signal is maintained at a low level, the transistor T0 is turned off, and the signal line Int and the signal line Inc are still maintained at a high level. At this time, the OH port outputs a high level and the OL port outputs a low level. The waveform diagram is shown as follows Figure 6 As shown, accordingly, the ENP signal and the ENN signal are at a low level.

[0065] At time T2, SA detects the low-level width of the CLKI signal. At time T2, the CLKA signal flips to a low level, and the CLKB signal flips to a high level. The high-level width of the CLKB signal is equal to the low-level width of the CLKI signal. The CLKB signal is at a high level, driving transistors N3 and N4 to turn on, slowly pulling down the internal signal line SAC. In the circuit design, the loads of signal lines SAC and SAT are designed to be symmetrical. Furthermore, transistors N3 and N4 are the same size as transistors N1 and N2, and are connected in series. This design ensures that the voltage on signal line SAC is only pulled down to an intermediate level greater than 0, which is greater than the turn-on threshold of transistor T2. At time T2, the CLKA signal is at a low level, and transistors N1 and N2 are turned off, so SAT maintains the level at time T1. At the same time, at T2, the SAEN signal maintains a low level, the transistor T0 is turned off, the signal line Int and the signal line Inc still maintain a high level, at this time the OH port outputs a high level, and the OL port outputs a low level. The waveform diagram is shown as follows: Figure 6 As shown, accordingly, the ENP signal and the ENN signal are at a low level.

[0066] At time T3, the CLKA and CLKB signals simultaneously flip to a low level, turning off transistors N1, N2, N3, and N4. The SAEN signal flips to a high level, turning off transistors P2 and P3 and turning on transistor T0. Initially, internal signal lines Int and Inc are in a high-level floating state, turning on transistors T3 and T4. Because signal lines SAT and SAC are pulled down to intermediate levels greater than 0 at times T1 and T2, respectively, and driver transistors T1 and T2 are turned on, the levels of signal lines Int and Inc are pulled down to a low level through the pull-down path.

[0067] Assuming that the duty cycle of the CLKI signal is greater than 50%, the high-level width of the CLKA signal is greater than the high-level width of the CLKB signal, so that the level value after the signal line SAT is pulled down is smaller than the level value after the signal line SAC is pulled down, that is, the gate voltage of transistor T1 is smaller than the gate voltage of transistor T2, which means that the operating speed of transistor T1 is slower than that of transistor T2, and the speed at which the signal line Inc is pulled down to a low level is faster than the speed at which the signal line Int is pulled down to a low level. This will cause the signal line Inc to be pulled down to a low level earlier than the signal line Int, causing transistor T5 to turn on earlier than transistor T6, and transistor T3 to turn off earlier than transistor T4, which will pull the signal line Int back up to a high level. Ultimately, the signal line Inc flips to a low level, the signal line Int still maintains a high level, the output signal of the OL port flips to a high level, and the output signal of the OH port remains at a high level. The waveform diagram is shown as follows: Figure 6 As shown by the OH and OL signals in FIG, correspondingly, the ENP signal and the ENN signal are high level.

[0068] Assuming the duty cycle of the CLKI signal is less than 50%, the high-level width of the CLKA signal is shorter than the high-level width of the CLKB signal. Consequently, the level of signal line SAC after being pulled down is lower than the level of signal line SAT after being pulled down. This means that the gate voltage of transistor T2 is lower than the gate voltage of transistor T1, meaning that transistor T2 operates slower than transistor T1. Consequently, signal line Int is pulled down to a low level faster than signal line Inc. This causes signal line Int to be pulled down to a low level before signal line Inc, causing transistor T6 to turn on before transistor T5 and transistor T4 to turn off before transistor T3, ultimately pulling signal line Inc back up to a high level. Ultimately, signal line Int flips to a low level, while signal line Inc remains high. The output signal of the OH port flips to a low level, while the output signal of the OL port remains low. Accordingly, the ENP and ENN signals are low.

[0069] At time T4, the CLKA and CLKB signals remain low, and transistors N1, N2, N3, and N4 are all turned off. The SAPCHX signal flips to a low level, driving transistors P0 and P1 to turn on, and signal lines SAC and SAT are recharged from the intermediate level to the high level. The SAEN signal flips to a low level, driving transistor T0 to turn off, transistors P2 and P3 to turn on, and signal lines Int and Inc are recharged to the high level. SA's output signals OH and OL return to their initial levels.

[0070] Among them, the intermediate signals (OL signal and OH signal) output by SA are generated into ENP signal and ENN signal through the latch circuit. Among them, the latch circuit includes two memories, and the enable signal of the latch is the same as the SAEN signal, so that the ENP signal and ENN signal can be maintained at the adjustment signal value after the T3 moment. The ENP signal and ENN signal are connected to Figure 1 The ENP control port and ENN control port of the duty cycle adjustment circuit.

[0071] The SA pre-charge signal and SA enable signal can be generated based on the first clock signal and the divided clock signal. For example, the first clock signal and the divided clock signal are ORed to obtain the SA pre-charge signal, which ensures that the SAPCHX signal is flipped to a low level only at time T4 and remains at a high level at other times. The inverted clock signal of the divided clock signal is ANDed with the first clock signal to obtain the SA enable signal, which ensures that the SA enable signal is flipped to a high level only at time T3 and remains at a low level at other times.

[0072] In an optional embodiment, the control signal circuit includes, in addition to the sense amplifier and the latch circuit, a first logic circuit and a second logic circuit, the circuit diagram of which is shown in FIG. Figure 7 As shown. The two input ends of the first logic circuit receive the first clock signal and the divided-by-two clock signal respectively, the output end of the first logic circuit is connected to the pre-charge end (SAPCHX) of the sense amplifier, and the first logic circuit is used to generate an SA pre-charge signal according to the first clock signal and the divided-by-two clock signal. Optionally, the first logic circuit includes an OR gate for ORing the first clock signal and the divided-by-two clock signal. The two input ends of the second logic circuit receive the first clock signal and the divided-by-two clock signal respectively, the output end of the second logic circuit is connected to the enable end (SAEN) of the sense amplifier and the enable end (EN) of the latch circuit, and the second logic circuit is used to generate an SA enable signal according to the first clock signal and the divided-by-two clock signal. Optionally, the first logic circuit includes an AND gate and an inverter (the inverter can also be replaced by a NOT gate).

[0073] The duty cycle adjustment circuit is connected to the control signal circuit and is used to adjust the duty cycle of the first clock signal according to the control signal so that the duty cycle of the adjusted first clock signal approaches 50%, and output the adjusted first clock signal. In one embodiment, the duty cycle adjustment circuit includes: a first-stage inverter and a second-stage inverter. The second-stage inverter is connected in series with the first-stage inverter, and the output end of the first-stage inverter is connected to the output end of the second-stage inverter. The control end of the first-stage inverter is used to receive an inverted clock signal of the first clock signal (such as represented by the CLKIB signal), the internal control end of the second-stage inverter is connected to the control end of the first-stage inverter, and the external control end of the second-stage inverter is used to receive the control signal.

[0074] Among them, the size of the first-stage inverter is smaller than that of the second-stage inverter. The channel of the first-stage inverter is in a normally open state and has no adjustment capability. The second-stage inverter controls the closing or opening of its own channel according to the control signal (ENN signal and ENP signal), thereby adjusting the duty cycle of the first clock signal so that the duty cycle of the adjusted clock signal approaches 50%, and outputs the adjusted clock signal. The second-stage inverter has the ability to adjust, so the second-stage inverter is larger in size and the adjustment effect is more obvious. For ease of understanding, the following is combined with Figure 8 The duty cycle adjustment circuit shown in the figure illustrates the adjustment process. Optionally, the second-stage inverter includes: a first transistor M1, a second transistor M6, a third transistor M3, and a fourth transistor M4. The first end of the first transistor M1 is connected to the power supply, the second end of the first transistor M1 is connected to the first end of the second transistor M2, the second end of the second transistor M2 is connected to the second end of the third transistor M3, the first end of the third transistor M3 is connected to the second end of the fourth transistor M4, the first end of the fourth transistor M4 is grounded, the control end of the first transistor M1 and the control end of the fourth transistor M4 are connected to the control signal, the control end of the second transistor M2 and the control end of the third transistor M2 are used to receive the inverted clock signal of the first clock signal, and the second end of the second transistor is connected to the output end of the first-stage inverter.

[0075] The first-stage inverter includes: a transistor M5 and a transistor M6. The first terminal of the transistor M5 is connected to a power supply, the second terminal of the transistor M5 is connected to the second terminal of the transistor M6, the first terminal of the transistor M6 is grounded, and the control terminal of the transistor M5 is connected to the control terminal of the transistor M6, and is used to receive an inverted clock signal of the first clock signal.

[0076] The inverted clock signal of the first clock signal (such as represented by the CLKIB signal) is input into the duty cycle adjustment circuit at time T3. That is, the inverted clock signal of the first clock signal is input into the duty cycle adjustment circuit at time T3 after a delay of a period of time.

[0077] If the duty cycle of CLKI is greater than 50%, the ENP and ENN signals are high (ENP = 1, ENN = 1). Because ENP = 1, the pull-up transistor M1 driven by the ENP signal is turned off. When CLKIB falls, the pull-up path of the first-stage inverter is enabled, while the pull-up path of the second-stage inverter is disabled. The delay from the falling edge of CLKIB to the rising edge of CLKG remains unchanged. When CLKIB rises, because ENN = 1, the pull-down transistor M4 driven by ENN is turned on. The pull-down paths of the first-stage and second-stage inverters are simultaneously enabled, reducing the delay from the rising edge of CLKIB to the falling edge of CLKG. After this adjustment, the delay from the rising edge of CLKI to the rising edge of CLKG remains unchanged, while the delay from the falling edge of CLKI to the falling edge of CLKG is reduced. Compared to the input CLKI signal, the high-level width of CLKG is reduced, bringing the duty cycle of CLKG close to 50%.

[0078] If the duty cycle of the CLKI signal is less than 50%, the control signal circuit generates control signals ENP = 0 and ENN = 0. Because ENN = 0, the pull-down transistor M4 driven by the ENN signal is turned off. Upon the rising edge of CLKIB, the pull-down path of the first-stage inverter is enabled, while the pull-down path of the second-stage inverter is disabled. The delay from the rising edge of CLKIB to the falling edge of CLKG remains unchanged. Upon the falling edge of CLKIB, because ENP = 0, the pull-up transistor P1 driven by ENP is turned on, simultaneously enabling the pull-up paths of the first-stage and second-stage inverters. The delay from the falling edge of CLKIB to the rising edge of CLKG is reduced. After adjustment, the delay from the falling edge of CLKI to the falling edge of CLKG remains unchanged, while the delay from the rising edge of CLKI to the rising edge of CLKG is reduced. Compared to the input CLKI signal, the high-level width of CLKG becomes longer, and the duty cycle of CLKG approaches 50%. After duty cycle adjustment, the duty cycle of CLKG approaches 50%.

[0079] In one embodiment, the duty cycle adjustment circuit may further include an inverter or a delayer in addition to the first-stage inverter and the second-stage inverter, wherein the delayer is used to delay the first clock signal or the inverted clock signal of the first clock signal. After the first clock signal passes through the inverter, the inverted clock signal of the first clock signal is obtained. The schematic diagram is shown as follows: Figure 9 shown.

[0080] In an optional implementation, Figure 1The clock duty cycle adjustment circuit shown may further include: a selection circuit, wherein a first input terminal of the selection circuit is used to receive an initial clock signal (which can be represented by a CLK signal), a second input terminal of the selection circuit is connected to an output terminal of the duty cycle adjustment circuit, and a selection terminal of the selection circuit is used to receive a selection signal (which can be represented by a DCA signal). The selection circuit is used to select and output the initial clock signal or the adjusted first clock signal according to the selection signal, wherein the first clock signal is a clock signal obtained by ANDing the initial clock signal with the selection signal. The circuit diagram thereof is shown in FIG. Figure 10 When DCA=0, the selection circuit selects to output the initial clock signal. At this time, the duty cycle of CLKO is equal to the duty cycle of the first clock signal, that is, CLKO=CLKI. When DCA=1, the selection circuit selects to output the adjusted first clock signal, CLKO=CLKG.

[0081] The selection circuit includes a selector (MUX) and an AND gate. The first input of the AND gate is used to receive the initial clock signal (CLK signal), and the second input of the AND gate is used to receive the selection signal (DCA signal). The first input of the selector is used to receive the initial clock signal (CLK signal), the second input is connected to the output of the duty cycle adjustment circuit, and the selection end is used to receive the selection signal (which can be represented by the DCA signal).

[0082] In an optional implementation, Figure 1 The clock duty cycle adjustment circuit shown may also include: a frequency divider circuit, which is connected to the differential clock circuit and is used to generate a frequency divider timing signal according to the first clock signal. The connection diagram of the frequency divider circuit and the differential clock circuit is shown in FIG. Figure 11 As shown in Figure 1. The CLKI signal is the clock input signal for the divide-by-two circuit, the DCA signal is the input enable signal, and the CLKD2 signal is the output signal of the divide-by-two circuit. When DCA = 0, the divide-by-two circuit is disabled, and the CLKD2 port outputs a low-level signal. When DCA = 1, the divide-by-two clock circuit is enabled, outputting the divided-by-two clock signal of CLKI to the CLKD2 port.

[0083] In an optional implementation manner, the circuit schematic diagram of the clock duty cycle adjustment circuit can be as follows: Figure 12As shown. In this embodiment, the clock duty cycle adjustment circuit includes: a differential clock circuit, a divide-by-two circuit, a control signal circuit, a duty cycle adjustment circuit, and a selection circuit. When DCA = 0, the internal signal CLKI remains low, CLKIB remains high, and the duty cycle adjustment circuit is in the off state. The DCA signal controls the selector (MUX, multiplexer) to directly output CLK to the CLKO port. At this stage, the entire circuit does not have a duty cycle adjustment function, and the duty cycle of the output signal CLKO is equal to the duty cycle of the input signal CLK. When the clock duty cycle adjustment circuit is powered on, that is, when DCA = 1, the circuit's duty cycle adjustment function is enabled. If the duty cycle of the CLK signal is greater than 50%, the control signal circuit generates control signals ENP = 1 and ENN = 1, which control transistor M4 in the second-stage inverter to turn on. The delay time from the rising edge of CLKIB to the falling edge of CLKG becomes shorter, ultimately reducing the high-level width of CLKO and adjusting the duty cycle of the output clock CLKO signal toward 50%. If the duty cycle of CLKI is less than 50%, the control signal circuit generates control signals ENP=0, ENN=0, which controls the transistor M1 in the second-stage inverter to turn on. The delay time from the falling edge of CLKIB to the rising edge of CLKG becomes shorter, which eventually increases the high-level width of CLKO and adjusts the duty cycle of the output clock CLKO signal toward 50%.

[0084] Second embodiment

[0085] Based on the same inventive concept, an embodiment of the present application provides a clock duty cycle adjustment circuit, which includes multiple clock duty cycle adjustment circuits shown in the first embodiment, and multiple clock duty cycle adjustment circuits are connected in series in sequence, as shown in the schematic diagram. Figure 13 As shown in the figure, the output of the first-stage clock duty cycle adjustment circuit serves as the input of the second-stage clock duty cycle adjustment circuit, and the output of the second-stage clock duty cycle adjustment circuit serves as the input of the third-stage clock duty cycle adjustment circuit, and so on. Multiple clock duty cycle adjustment circuits are used to adjust the initial clock signal so that the duty cycle of the final output clock signal is as close to 50% as possible.

[0086] Among them, the clock duty cycle adjustment circuit in the above figure has the same implementation principle and technical effects as the clock duty cycle adjustment circuit in the aforementioned first embodiment. For the sake of brief description, for parts not mentioned in the second embodiment, reference can be made to the corresponding contents in the aforementioned first embodiment.

[0087] Third embodiment

[0088] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes the above-mentioned clock module and the above-mentioned clock duty cycle adjustment circuit (which can be the clock duty cycle adjustment circuit in the first embodiment or the clock duty cycle adjustment circuit in the second embodiment).

[0089] The clock module is used to generate an initial clock signal; the clock duty cycle adjustment circuit is used to adjust the duty cycle of the initial clock signal so that the adjusted clock duty cycle approaches 50%.

[0090] The electronic device may include a processor or a memory, or the electronic device is the processor or the memory. The processor may be an integrated circuit chip having signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0091] The memory may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0092] The implementation principle and technical effects of the clock duty cycle adjustment circuit in the third embodiment are the same as those of the clock duty cycle adjustment circuit in the aforementioned first embodiment. For the sake of brief description, for parts not mentioned in the third embodiment, reference may be made to the corresponding contents in the aforementioned first embodiment.

[0093] Fourth embodiment

[0094] Based on the same inventive concept, the embodiment of the present application also provides a clock duty cycle adjustment method, which will be combined with Figure 14 , the clock duty cycle adjustment method provided in the embodiment of the present application is described.

[0095] S1: Generate a first differential clock signal and a second differential clock signal for detecting a high level width and a low level width of the first clock signal according to a first clock signal and a divided-by-two clock signal of the first clock signal.

[0096] In one embodiment, the clock duty cycle adjustment method is applied to the above-mentioned clock duty cycle adjustment circuit, and can be to utilize the above-mentioned differential clock circuit to generate a first differential clock signal and a second differential clock signal for detecting the high level width and low level width of the first clock signal based on a first clock signal and a two-divided clock signal of the first clock signal.

[0097] S2: Detecting the high level width and the low level width of the first clock signal according to the first differential clock signal and the second differential clock signal, and generating a control signal for adjusting the clock duty cycle according to the difference between the high level width and the low level width.

[0098] In one embodiment, the above-mentioned control signal circuit can be used to detect the high level width and low level width of the first clock signal based on the first differential clock signal and the second differential clock signal, and generate a control signal for adjusting the clock duty cycle based on the difference between the high level width and the low level width.

[0099] S3: Adjusting the duty cycle of the first clock signal according to the control signal, so that the adjusted duty cycle of the first clock signal approaches 50%.

[0100] In one implementation, the duty cycle adjustment circuit may be used to adjust the duty cycle of the first clock signal according to the control signal, so that the adjusted duty cycle of the first clock signal approaches 50%.

[0101] The clock duty cycle adjustment method provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned clock duty cycle adjustment circuit embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference may be made to the corresponding contents in the aforementioned clock duty cycle adjustment circuit embodiment.

[0102] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0103] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A clock duty cycle adjustment circuit, characterized in that: include: a differential clock circuit, configured to output a first differential clock signal and a second differential clock signal for detecting a high-level width and a low-level width of the first clock signal based on an input first clock signal and a divided-by-two clock signal; wherein the first differential clock signal is a clock signal obtained by performing an AND operation on the first clock signal and the divided-by-two clock signal, and the second differential clock signal is a clock signal obtained by performing an AND operation on the inverted clock signal of the first clock signal and the divided-by-two clock signal; a control signal circuit connected to the differential clock circuit, configured to detect a high-level width and a low-level width of the first clock signal based on the input first differential clock signal and the second differential clock signal, and generate a control signal for adjusting a clock duty cycle based on a difference between the high-level width and the low-level width; A duty cycle adjustment circuit is connected to the control signal circuit, and is used to adjust the duty cycle of the first clock signal according to the control signal, so that the duty cycle of the adjusted first clock signal approaches 50%, and output the adjusted first clock signal.

2. The clock duty cycle adjustment circuit according to claim 1, wherein: The control signal circuit includes: A sense amplifier SA is connected to the differential clock circuit. A precharge terminal of the sense amplifier is used to receive an SA precharge signal. The SA precharge signal is used to charge the first signal line and the second signal line inside the sense amplifier. An enable terminal of the sense amplifier is used to receive an SA enable signal. Under the action of the SA enable signal and the SA precharge signal, the sense amplifier is used to: controlling the discharge of the voltage on the first signal line inside the sense amplifier according to the first differential clock signal and the second differential clock signal at a first moment, wherein the residual voltage on the first signal line is related to the high level width of the first clock signal; controlling the discharge of the voltage on the second signal line inside the sense amplifier according to the first differential clock signal and the second differential clock signal at the second moment, wherein the residual voltage on the second signal line is related to the low level width of the first clock signal; detecting a difference between a residual voltage on the first signal line and a residual voltage on the second signal line according to the first differential clock signal and the second differential clock signal at a third moment, and outputting an intermediate signal according to the difference; and A latch circuit is connected to the sense amplifier and is used to latch the intermediate signal under the control of an enable signal of the latch circuit to obtain the control signal, wherein the enable signal of the latch circuit is consistent with the SA enable signal of the sense amplifier.

3. The clock duty cycle adjustment circuit according to claim 2, wherein: At the first moment, the first clock signal is at a high level, the first differential clock signal is at a high level and the high level width is consistent with the high level width of the first clock signal, and the second differential clock signal, the SA precharge signal, and the SA enable signal are at a low level; At the second moment, the first clock signal, the SA precharge signal, the SA enable signal, and the first differential clock signal are at a low level, and the second differential clock signal is at a high level, and the high level width is consistent with the low level width of the first clock signal; At the third moment, the first clock signal, the SA precharge signal, and the SA enable signal are at a high level, and the first differential clock signal and the second differential clock signal are at a low level.

4. The clock duty cycle adjustment circuit according to claim 2, wherein: The control signal circuit further includes: a first logic circuit, wherein two input terminals of the first logic circuit respectively receive the first clock signal and the divided-by-two clock signal, an output terminal of the first logic circuit is connected to a precharge terminal of the sense amplifier, and the first logic circuit is configured to generate the SA precharge signal according to the first clock signal and the divided-by-two clock signal; A second logic circuit, wherein the two input ends of the second logic circuit respectively receive the first clock signal and the two-divided clock signal, the output end of the second logic circuit is connected to the enable end of the sensitive amplifier and the enable end of the latch circuit, and the second logic circuit is used to generate the SA enable signal according to the first clock signal and the two-divided clock signal.

5. The clock duty cycle adjustment circuit according to claim 1, wherein: The differential clock circuit comprises: A first branch is configured to perform an AND operation on the input first clock signal and the divided-by-two clock signal to output the first differential clock signal; a second branch, configured to perform an AND operation on the input divided-by-two clock signal and an inverted clock signal of the first clock signal, and output the second differential clock signal; The delay of the first branch is consistent with the delay of the second branch.

6. The clock duty cycle adjustment circuit according to claim 1, wherein: The duty cycle adjustment circuit includes: A first-stage inverter, wherein a control terminal of the first-stage inverter is used to receive an inverted clock signal of the first clock signal; a second-stage inverter connected in series with the first-stage inverter, an internal control terminal of the second-stage inverter connected to the control terminal of the first-stage inverter, an external control terminal of the second-stage inverter for receiving the control signal, and an output terminal of the first-stage inverter connected to the output terminal of the second-stage inverter; The size of the first-stage inverter is smaller than that of the second-stage inverter. The channel of the first-stage inverter is in a normally open state. The second-stage inverter controls the closing or opening of its own channel according to the control signal, thereby adjusting the duty cycle of the first clock signal so that the duty cycle of the adjusted clock signal approaches 50%, and outputs the adjusted clock signal.

7. The clock duty cycle adjustment circuit according to claim 6, wherein: The second-stage inverter includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; The first end of the first transistor is connected to a power supply, the second end of the first transistor is connected to the first end of the second transistor, the second end of the second transistor is connected to the second end of the third transistor, the first end of the third transistor is connected to the second end of the fourth transistor, the first end of the fourth transistor is grounded, the control end of the first transistor and the control end of the fourth transistor are connected to the control signal, the control end of the second transistor and the control end of the third transistor are used to receive an inverted clock signal of the first clock signal, and the second end of the second transistor is connected to the output end of the first-stage inverter.

8. The clock duty cycle adjustment circuit according to claim 1, wherein: The clock duty cycle adjustment circuit further includes: A divide-by-two circuit is connected to the differential clock circuit and is used to generate the divided-by-two clock signal based on the first clock signal, wherein the duty cycle of the divided-by-two clock signal is 50%, and the first rising edge of the divided-by-two clock signal is aligned with the first rising edge of the first clock signal, or the first falling edge of the divided-by-two clock signal is aligned with the first falling edge of the first clock signal.

9. The clock duty cycle adjustment circuit according to claim 1, wherein: The clock duty cycle adjustment circuit further includes: A selection circuit, wherein the first input end of the selection circuit is used to receive an initial clock signal, the second input end of the selection circuit is connected to the output end of the duty cycle adjustment circuit, the selection end of the selection circuit is used to receive a selection signal, and the selection circuit is used to select and output the initial clock signal or the adjusted first clock signal according to the selection signal, wherein the first clock signal is a clock signal obtained by ANDing the initial clock signal with the selection signal.

10. A clock duty cycle adjustment circuit, characterized in that: The invention comprises a plurality of clock duty cycle adjustment circuits according to any one of claims 1 to 9, wherein the plurality of clock duty cycle adjustment circuits are connected in series in sequence.

11. An electronic device, characterized in that: include: A clock module and a clock duty cycle adjustment circuit according to any one of claims 1 to 10; The clock module is used to generate an initial clock signal; The clock duty cycle adjustment circuit is used to adjust the duty cycle of the initial clock signal so that the adjusted clock duty cycle approaches 50%.

12. A clock duty cycle adjustment method, characterized in that: include: generating, based on a first clock signal and a divided-by-two clock signal, a first differential clock signal and a second differential clock signal for detecting a high-level width and a low-level width of the first clock signal; wherein the first differential clock signal is a clock signal obtained by performing an AND operation on the first clock signal and the divided-by-two clock signal, and the second differential clock signal is a clock signal obtained by performing an AND operation on the inverted clock signal of the first clock signal and the divided-by-two clock signal; detecting a high-level width and a low-level width of the first clock signal according to the first differential clock signal and the second differential clock signal, and generating a control signal for adjusting a clock duty cycle according to a difference between the high-level width and the low-level width; The duty cycle of the first clock signal is adjusted according to the control signal, so that the adjusted duty cycle of the first clock signal approaches 50%.

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