Converter circuit, corresponding device, and method

Abstract

Embodiments of the present disclosure relate to converter circuits, corresponding devices, and methods. A converter circuit includes first and second electronic switches coupled at an intermediate node, wherein an inductor is coupled between the intermediate node and an output node. A switching drive control circuit device causes the first and second electronic switches to switch between a conductive state and a non-conductive state. The drive control circuit device includes a first feedback signal path to control the switching of the first and second electronic switches based on the difference between a first feedback signal generated at the output node and a first reference value. A second feedback signal path includes a low-pass filter, which is coupled to the output node and is configured to provide a low-pass filtered feedback signal generated by low-pass filtering the output signal. The second feedback signal path will compensate the feedback signal based on the difference between the low-pass filtered feedback signal and the corresponding reference value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Italian patent application No. 102020000019546, filed on August 6, 2020, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] This specification relates to converter circuits.

[0004] For example, one or more embodiments may be applied to a DC-DC converter. Background Art

[0005] DC-DC converters are used in a wide variety of applications, for example to provide supply voltage "rails" in complex systems.

[0006] These applications require good efficiency and compliance with performance specifications.

[0007] The efficiency of these converters decreases due to increased switching losses at high switching frequencies, especially at light load conditions.

[0008] For example, efficiency under light load conditions can negatively impact the battery life of mobile devices.

[0009] This has led to improved solutions, such as control schemes using pulse frequency modulation (PFM), which are believed to facilitate solving these problems.

[0010] PFM-based solutions employ various control loop approaches: constant on-time, constant off-time, ripple-based, and hysteresis are exemplary conventional control schemes used in PFM-based DC-DC converters.

[0011] There is a need in the art to provide further improved solutions to address the above-discussed issues. Summary of the Invention

[0012] One or more embodiments may be directed to circuitry.

[0013] One or more embodiments may be directed to corresponding devices. A device or system including a power rail based on the circuits discussed herein may be exemplified as such a device.

[0014] One or more embodiments may be directed to a corresponding method.

[0015] One or more embodiments may provide one or more of the following advantages:

[0016] A closed-loop solution is provided, which facilitates compensation for output deviations from a desired set point that may be related to process, voltage, and temperature (PVT) variations, aging, component degradation, and similar phenomena, independent of operating parameters;

[0017] The impact on the overall current consumption is low and practically negligible: the additional consumption is (only) related to the op amp and the additional PMOS acting as a controlled current source; the overall efficiency and power consumption of the DC-DC converter are essentially unaffected;

[0018] Compared to conventional DC-DC converter or power management integrated circuit (PMIC) arrangements, the difference in system complexity and occupied semiconductor area is small, and the small amount of added complexity is largely compensated by the improved performance;

[0019] A matched layout can be used to reduce the possible mismatch between the two feedback voltage dividers, and a diffused resistor with good matching performance can also be used;

[0020] By mitigating the effects of possible residual mismatch between the two feedback dividers and the operational amplifier through a trimming action, known techniques (e.g., chopping) may be employed to provide an error amplifier with reduced offset and negligible mismatch, thereby facilitating high accuracy; and

[0021] Without particular limitation, one or more embodiments may be used with various types of DC-DC converters using PFM operation: ripple-based, hysteretic, constant on-time (COT), advanced or adaptive constant on-time (ACOT), and (R) ), time-based, etc.

[0022] In an embodiment, a circuit includes: a first electronic switch and a second electronic switch through which a current path is coupled at an intermediate node; an inductor having a first terminal coupled to the intermediate node and a second terminal coupled to an output node at which an output signal is generated; and a drive control circuit arrangement configured to control switching of the first and second electronic switches between a conductive state and a non-conductive state, wherein the first electronic switch provides for current flow between an input node and the intermediate node during the conductive state, and the second electronic switch provides for current flow between the intermediate node and ground during the conductive state. The drive control circuit arrangement includes: a first feedback signal path coupled to the output node and configured to control switching of the first and second electronic switches between the conductive state and the non-conductive state based on a difference between a feedback signal indicative of the output signal and a first reference value; and a second feedback signal path including a low-pass filter coupled to the output node, the low-pass filter configured to provide a low-pass filtered feedback signal, the second feedback signal path configured to compensate the feedback signal based on a difference between the low-pass filtered feedback signal and a second reference value. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0024] Figure 1A and Figure 1B is an exemplary illustration of the possible behavior of losses and efficiency with respect to load current in pulse width modulation (PWM) mode and pulse frequency modulation (PFM) mode converters.

[0025] Figure 2 is an exemplary illustration of possible inductor current waveforms in a PFM mode converter.

[0026] Figure 3 This is a circuit diagram of a PFM controller for a step-down DC-DC converter.

[0027] Figure 4 Included are exemplary diagrams of possible temporal behavior of corresponding steady-state waveforms.

[0028] Figure 5 is an exemplary circuit diagram of a possible implementation of hysteresis in a PFM controller; and

[0029] Figure 6 and Figure 7 is an exemplary circuit diagram according to an embodiment of the present description. DETAILED DESCRIPTION

[0030] In the following description, one or more specific details are provided to provide a deeper understanding of the embodiments of the present specification. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not described or explained in detail so as not to obscure certain aspects of the embodiments.

[0031] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.

[0032] Furthermore, particular conformations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0033] The headings / reference numbers used herein are for convenience only and do not define the scope of protection or the scope of the embodiments.

[0034] As mentioned previously, DC-DC converters are used in a wide variety of applications, for example, to provide power "rails" in complex systems.

[0035] Efforts to achieve compliance with performance specifications and efficiency (which has been found to degrade at high switching frequencies, particularly under light load conditions, negatively impacting battery life in mobile devices, for example) have led to improved solutions such as pulse frequency modulation (PFM) control schemes (using constant on-time, constant off-time, ripple-based, hysteresis, to name a few) that are believed to contribute to resolving these issues.

[0036] In fact, the loss mechanisms of pulse width modulation (PWM) controlled DC-DC converters can be roughly divided into three categories, namely conduction loss, switching loss and static loss due to the quiescent current consumed by the controller and other auxiliary circuit devices.

[0037] For a fixed switching frequency F SW , the switching loss and static loss components are constant, while the conduction loss increases with the increase of load current.

[0038] This is Figure 1A This is reflected in the curve.

[0039] These curves are on a common horizontal axis scale (load current I LOAD ) represents: switching loss S, static (quiescent) loss Q and conduction loss C, as shown in the upper curve; and efficiency η, as shown in the lower curve.

[0040] Figure 1A It is shown that conduction loss C and switching loss S dominate at high load and light load, respectively.

[0041] The quiescent current loss Q affects efficiency at (very) light loads and is not a major source of concern.

[0042] The switching loss S is found to increase with increasing switching frequency and can be calculated by scaling F SW to reduce.

[0043] To this end, PFM control can be operated in discontinuous conduction mode (DCM) and the F SW As the load current I LOAD , which facilitates achieving improved light load efficiency.

[0044] This is Figure 1B This is reflected in the curve.

[0045] The curves are again plotted on a common abscissa scale (load current I LOAD ) represents: switching loss S, static (quiescent) loss Q and conduction loss C, as shown in the upper curve; and efficiency η, as shown in the lower curve, reference I LOAD Below threshold I TH The PFM mode to be applied.

[0046] It should be noted that the efficiency of PFM mode is LOAD It decreases at larger values of TH The converter operates in PWM mode.

[0047] Figure 2 The diagram in Figure 1 is an example of output voltage regulation of a buck converter in PFM mode (this can be considered representative of various types of DC-DC topologies), with reference to the inductor current I for simplicity. L .

[0048] like Figure 2 As shown, the load current I LOAD The output capacitor is discharged, and the charge lost in the process is passed through the F SW,PFM =1 / T PFM The PFM rate (frequency) is dumped to the output node with a value of Q PFM The charge packet is used to compensate, where T PFM Indicates the period of PFM modulation.

[0049] Assuming a fixed inductor peak current I L,pk , Q PFM =1 / 2*I L,pk* (TON,PFM +T OFF,PFM ), where T ON,PFM and T OFF,PFM is the inductor current I L The rise and fall times are equal to:

[0050] T ON,PFM =(L*I L,pk ) / (V IN -V O ),and

[0051] T OFF,PFM =(L*I L,pk ) / V O ,

[0052] Where V IN and V O are the input (supply) and output voltages of the converter.

[0053] Output voltage V O You can set F SW,PFM To adjust the charge transfer rate to the output to be equal to I LOAD .

[0054] This can be expressed in mathematical terms as:

[0055] F SW,PFM =(I LOAD / Q PFM )=(2*I LOAD ) / (I L,pk *(T ON,PFM +T OFF,PFM )).

[0056] It should be noted that F SW,PFM Can be used with I according to expectations LOAD changes proportionally to reduce switching losses.

[0057] Figure 3 FIG. 1 is a circuit diagram of a step-down DC-DC converter 100 including a PFM controller 10 .

[0058] This converter is provided as an example to represent various types of DC-DC topologies. Otherwise, those skilled in the art will understand that the basic principles of the embodiments shown herein are applicable to other types of switching converters, such as, by way of non-limiting example, boost converters (or boost choppers), buck-boost, and other converter topologies.

[0059] like Figure 3 As shown, the converter 100 includes two electronic switches M P and M N(field effect transistors, such as P-MOS and N-MOS), two electronic switches M P and M N The current path (drain-source in the case of a field effect transistor such as a mosfet) is arranged to pass through it. P and M N The middle node A is coupled to one end of the inductor (coil) L. The other end of the inductor L is coupled to the output node V O (eg via a stabilizing output capacitor C), and is configured to supply a load LD.

[0060] It should be noted that the two electronic switches M P and M N The selection of P-MOS and N-MOS transistors, respectively, is not mandatory for the embodiments. For example, in some embodiments, the "high side" MOSFET can be an N-channel MOSFET.

[0061] Additionally, in some asynchronous converters, a diode can be used as the low-side electronic switch Mn instead of a transistor such as a power MOSFET.

[0062] exist Figure 3 In the illustrated arrangement, two electronic switches M P and M N Switching between the "on" state (switch conducting) and the "off" state (switch not conducting) can be achieved by driving the circuit stages 101 and 102 to the M P and M N As a result of applying a drive signal to the control terminal (gate in the case of a field effect transistor (such as a power MOSFET)) of the drive circuit stages 101 and 102, the drive circuit stages 101 and 102 are in turn driven by the controller 10 via the control signal HS ON ("High-side" switch M P ) and LS ON ("Low-side" switch M N )control.

[0063] When "on" (conducting), the two electronic switches M P and M N At the input (power supply) node V IN Corresponding current flow paths are provided between the intermediate node A and the ground.

[0064] Figure 3 The structure and operation of the illustrated converter 100 are well known to those skilled in the art, and therefore no detailed description is necessary here.

[0065] Additionally, it will be appreciated that throughout this specification, for simplicity, the same names may be used to designate a node / line and a signal appearing at that node (e.g., see the previously discussed V IN and V O ).

[0066] In addition, it can be understood that the load LD can be an element different from that in the embodiment.

[0067] like Figure 3 As shown, controller 10 includes PFM logic circuitry 12, which may be implemented as dedicated logic, a finite state machine (FSM) synthesized within an ASIC, an FPGA, or a microcontroller (μC) / microprocessor (μP).

[0068] like Figure 3 As shown, the PFM logic circuit device 12 can be configured (in a manner known per se to a person skilled in the art) to generate the switching signal for the switch M according to the following terms: P and M N The driving signal HS ON and LS ON :

[0069] Timing signal ON-TIME from the “on” time generator 14.

[0070] The drive enable signal EN from the comparator 16 DRV The comparator 16 receives at its input an output (voltage) signal V O (or a scaled version thereof obtained, for example, via a voltage divider) and a reference voltage V REF ;as well as

[0071] The zero-crossing signal ZCD from the zero-crossing detector 18 is applied to the switch M. P and M N The current I at the middle node A L Zero-crossing sensitivity.

[0072] Figure 3 Also shown is a block 160 representing a circuit arrangement configured to convert the output voltage V O is passed to the (inverting) input of comparator 16. The structure and operation of this circuit arrangement will be described below with Figure 6 and Figure 7 Discuss together.

[0073] exist Figure 3 In the controller 10 illustrated in FIG. 1 , without considering block 160 for the moment, the comparator 16 monitors the output voltage V O (or a scaled version thereof obtained via a feedback voltage divider, such as a resistor divider), and provides a signal EN based on the following criteria DRV :

[0074] When V O Higher than V REF EN DRV =0 (e.g., a “low” logic level), i.e., in a state where the inductor L is not excited to transfer charge to the converter output;

[0075] When V O Lower than V REF EN DRV =1 (e.g., "high" logic level), that is, in a state where the inductor L is excited to transfer charge to the converter output, because the output voltage V O Lower than the desired adjustment value.

[0076] As EN DRV =1, the logic circuit device 12 is the switch M P and M N Generate driving signal HS ON and LS ON .

[0077] Otherwise, those skilled in the art will understand that the logic values indicated here are merely exemplary: depending on the (logic) circuitry implemented, the same types of operations discussed here may in fact be obtained with different logic values.

[0078] exist Figure 3 In the controller 10 shown, HS ON The duration of the active or "on" state is T ON (See Figure 3 The ON-TIME signal in the control scheme can be selected according to the type of PFM control scheme implemented. This control scheme can be selected from various schemes known to those skilled in the art (for example, in some schemes, T can be directly controlled). ON duration, while in other schemes the T OFF ). It should be noted that the embodiments discussed herein are very "transparent" to the control options selected, and therefore, this will not be discussed in detail herein.

[0079] As discussed in this paper, it can be assumed that LS ON With HS ON Complementary (ie: LS ON =1, HS ON =0 and LS ON =0,HS ON =1), and when I L When returning to zero in a PFM converter operating in discontinuous conduction mode or DCM, LS ON With HS ON Can be reset.

[0080] To this end, the zero current detector block 18 monitors I L , and generates a signal ZCD, which causes the logic circuit device 12 to turn off the low-side power transistor Mn (LS ON =0), as T OFF The result of the end.

[0081] The zero current detector 18 (sometimes also referred to as a discontinuous mode detector DMD) may be implemented as a comparator or a more complex current sensor.

[0082] As mentioned above, in some asynchronous converters, a diode can be used as the low-side electronic switch Mn instead of a transistor such as a power MOSFET. In this case, the zero current detector 18 can be omitted: the presence of the diode (current can only flow in one direction, for example, to the output node V O , rather than the other way around) is essentially forcing the fight against CCM (Continuous Conduction Mode) with zero / low current.

[0083] Figure 4 Shown as Figure 3 Possible steady-state behavior of the system is shown (again ignoring block 160).

[0084] Figure 4 The curves in FIG. 1 illustrate, from top to bottom, for a common time scale (abscissa scale t) and at arbitrary values, the possible time behavior of the reference voltage V REF The output voltage V O ; Reference load current I LOAD The current I through the inductor L L ; Signal EN from comparator 16 DRV ; and a signal ZCD from the zero crossing detector 18.

[0085] exist Figure 3 and Figure 4 In the example, the on-time T ON (See signal ON-TIME from generator 14) The choice may be determined by a trade-off between efficiency and output ripple.

[0086] For example, assuming other operating conditions and / or parameters, such as V IN 、V O , L, etc. remain unchanged, choose the longer T ON Value and higher I L,pk The increased excitation of the inductor or coil L (i.e., the increased charge delivered to the converter output) results in a higher voltage ripple. Conversely, the output load LD takes longer to load the output V ODischarging to a level that triggers comparator 16, the frequency will be reduced, resulting in improved efficiency.

[0087] Figure 3 and Figure 4 A disadvantage of the arrangement illustrated in (again disregarding block 160 for the moment) is that the output ripple is not tightly controlled.

[0088] Therefore, the output ripple may depend on various converter parameters, such as the inductance of the inductor L, the capacitance of the capacitor C, the input voltage V IN , output voltage V O , load current I LOAD and on-time T ON .

[0089] That is, the output ripple will vary for different operating conditions. In addition, the non-ideal behavior of the comparator 16 may significantly affect the output ripple.

[0090] It should be noted that one can attempt to address these issues by employing a “sufficiently large” hysteresis at comparator 16 so that the amount of charge transferred, QPFM, produces an increase in the output voltage that is less than the comparator hysteresis.

[0091] In this way, the converter can maintain regulation by delivering two or more "packets" of charge.

[0092] This approach provides the advantage of a more controlled output ripple determined by the hysteresis in comparator 16, which is amplified by the inverse (e.g., the reciprocal) of the feedback divider ratio (for simplicity, Figure 3 The converter output voltage V O Directly applied to comparator 16: In actual implementation, comparator 16 does not directly monitor the converter output voltage V O , since the feedback divider is used for this purpose).

[0093] In this way, the output ripple no longer depends on L, C, V IN 、V O , I LOAD and T ON , and remains basically unchanged under different operating conditions.

[0094] Figure 5 The diagram of FIG illustrates a possible implementation of hysteresis in the comparator 16, which is shown receiving the output voltage V at its (inverting) input via the resistor divider R1, R2 on the feedback line FB. O , where the reference value is at a high value V REF H and low value V REF L changes between, where the reference value of the comparator changes according to its state.

[0095] For example, in EN DRV At the rising edge of V REF H can be applied to the (non-inverting) input of comparator 16; while at EN DRV At the falling edge of V REF L may be applied to the (non-inverting) input of comparator 16 .

[0096] It is also understandable that Figure 3 In comparison, Figure 3 Medium V REF Refers to the output voltage V applied directly to the comparator 16 O , Figure 5 V exemplified in REF H and V REF The value of L is sufficiently scaled to take into account the voltage divider comprising R1 and R2 to the output voltage V O Applied feedback factor R1 / (R1+R2).

[0097] Therefore, the output ripple ΔV can be expressed as.

[0098] ΔV=((R1+R2) / R1)*(V REF HV REF L)

[0099] Where (V REF HV REF L) is the hysteresis of the comparator, and (R1+R2) / R1 is the reciprocal of the feedback factor R1 / (R1+R2) of the voltage divider comprising R1 and R2.

[0100] As an example only, with a feedback factor of 0.5 and a "rated" reference value of V REF In the case of a center 8mV hysteresis, the ΔV value can reach 16mV.

[0101] A possible disadvantage of this "hysteresis" approach may lie in the (very) strict design of the comparator, which ultimately puts a floor on the output ripple amplitude (that is, the output ripple cannot be reduced below a given value, and it cannot be chosen arbitrarily).

[0102] In summary, the above analysis and description (again ignoring the possible structure and operation of block 160, which will be discussed below) show that in a PFM DC-DC converter, a comparator can be used to compare the reference signal V that indicates the desired output regulation set point. REF Monitor output signal V O .

[0103] In steady state, such an arrangement increases the offset relative to the desired set point (e.g., Figure 4 This is explained in ) to regulate the output voltage.

[0104] Therefore, the average output voltage (i.e., its DC value) may not be equal to the desired set point V REF , because a systematic error (offset) is introduced.

[0105] This error is related to the EN DRV =1 is (strongly) related to the behavior / performance (ie delay, offset, hysteresis, etc.) of the PFM comparator for the signal.

[0106] As discussed, such problems cannot be completely solved using comparators designed with sufficient hysteresis: due to the non-idealities of such comparators, eg, the comparator's behavior and performance are affected by PVT variations, a certain output regulation offset still exists.

[0107] Various applications place stringent demands on the precision and accuracy of the output regulated voltage from the converter.

[0108] Therefore, this uncontrolled / pale offset is undesirable in the real world, mainly due to its impact on the converter parameters (V IN 、V O , I LOAD 、T ON etc.), comparator non-idealities and performance / behavior, contributing to the converter’s output regulation and performance regardless of possible variations (e.g., due to process spread, temperature, component degradation, and other events that may occur after final test, packaging, and assembly (i.e., aging, soldering, etc.)

[0109] In theory, one might consider trimming and adjusting the reference voltage V monitored at the (non-inverting) input of comparator 16. REF ; That is, compensating for undesired output deviations by changing the desired regulation set point.

[0110] Additionally, you might consider trimming the coupling to V O The feedback divider can be adjusted (e.g., by adjusting the values of R1 and / or R2) in order to adjust the feedback ratio for proper output regulation.

[0111] It should be noted that both approaches may have drawbacks that may affect their feasibility in practical applications.

[0112] For example, these are open-loop solutions that make it difficult to take into account temperature variations, aging and other possible phenomena: the trimming action is performed at a given time under specific conditions and is sufficient (output offsets are compensated) only under these specific conditions.

[0113] After the trimming procedure, changes in any parameters / components in the system can in turn lead to undesired shifts in the output regulation: one can simply consider the case of a comparator, whose behavior and performance can be affected by temperature, aging, etc.

[0114] Furthermore, these possible solutions are not suitable for DC-DC operating conditions (such as V IN 、V O , I LOAD 、T ON ) is not robust to possible changes in

[0115] As discussed in the first PFM embodiment discussed above, according to V IN , I LOAD 、T ON The changing output ripple causes the output voltage V O The corresponding change in the mean value of .

[0116] Additionally, in specific applications, the output regulation set point may not be fixed: the user may select (possibly instantaneously) the desired set point; in this case, implementing any "trimming" scheme becomes almost infeasible.

[0117] From an industrial production and high-volume manufacturing perspective, pruning is inherently expensive: it is time-consuming (an iterative process that requires time to reach convergence) and involves both human resources (operators) and technical resources (automatic test equipment or ATE tools, instruments, and machinery).

[0118] It should be noted that these drawbacks are related to the inherent open-loop nature of the pruning action.

[0119] In contrast, one or more embodiments may rely on the robustness of the closed-loop system to compensate for converter output offsets.

[0120] To this end, one or more embodiments may rely on compensation via an (analog) feedback loop (negative loop) configured to act on a feedback divider, as previously discussed with respect to Figure 5 The resistors R1 and R2 are related.

[0121] This approach is suitable for implementation within the framework of converter topologies, such as Figure 3 The circuit arrangement represented by block 160 is configured to provide the output voltage V O The circuit arrangement is delivered to the (inverting) input of the comparator 16 .

[0122] In short, one or more embodiments may contemplate injecting current into the tap point of the voltage divider R1, R2 (coupled to the input of the comparator 16 via the node FB) to fix / change the voltage at the tap point of the voltage divider (i.e., at the node FB monitored by the comparator 16).

[0123] In this way, the converter 100 can regulate the output voltage V O , without the offset discussed previously. The amount of injected current can be automatically adjusted via a negative feedback loop.

[0124] Figure 6 and Figure 7 An embodiment relying on this approach is illustrated in the circuit diagram of .

[0125] As mentioned earlier, Figure 6 and Figure 7 Basically, the diagram shows Figure 3 A possible embodiment of the circuit arrangement is represented by block 160 in FIG.

[0126] For simplicity and ease of understanding, Figure 6 and Figure 7 In the figures, parts or elements that are the same as those discussed in the previous figures are indicated by like reference symbols; for the sake of brevity, the corresponding description will not be repeated.

[0127] exist Figure 6 In one embodiment, the circuit arrangement 160 includes a "replica" feedback voltage divider comprising two resistors R3 and R4, which are connected between V O and ground GND, and at its tap point (by FB REPLICA V is provided at designated O The feedback replica is equal to V O *R4 / (R3+R4).

[0128] exist Figure 6 In the embodiment, the division ratio of the voltage divider including R3 and R4 is equal to the division ratio of the voltage divider including resistors R1 and R2, and its tap node FB is coupled to the (inverting) input of the comparator 16, that is, R4 / (R3+R4)=R2 / (R1+R2).

[0129] exist Figure 6 In the embodiment illustrated in FIG, the node FB REPLICA The signal at is provided to a low pass filter (LPF) 162. The filter 162 provides a feedback voltage V O *The average value of R4 / (R3+R4), where the ripple is essentially removed, thus providing a O Valuable information.

[0130] exist Figure 6In the embodiment illustrated in FIG, the filtered output voltage V from the low-pass filter 162 is FILT is applied to the (inverting) input of the error amplifier 164. The amplifier 164 may include an operational amplifier configured to operate as an error amplifier, which receives a reference voltage V at its other (non-inverting) input. REF , and provides an (analog) signal at its output for driving a voltage-controlled current source 166.

[0131] exist Figure 6 In the embodiment illustrated in FIG, the reference voltage V is scaled to take into account the feedback factor (ie, R4 / (R3+R4)=R2 / (R1+R2)). REF Applied to the (non-inverting) inputs of both 16 and 164.

[0132] exist Figure 6 In the embodiment illustrated in FIG, the operational amplifier 164 can be designed (as long as the loop gain of the feedback loop is high enough, which is because the amplifier 164 can be designed to have a high enough gain at low frequencies) to maintain V REF =V FILT , acting on the current injected into the feedback node FB through the voltage-controlled current source 166.

[0133] like Figure 6 As shown, this can be implemented as a transconductance stage, comprising a transistor (eg, a field effect transistor, such as a P-channel power MOSFET).

[0134] In such Figure 6 In the embodiment shown, node FB REPLICA The signal at FB conveys different information.

[0135] However, in Figure 6 In the embodiment shown, the signal at the node FB is controlled by the REPLICA The compensation effect of the signal driven by the low-pass filtered signal at 162 is eliminated, so the signal at node FB no longer carries only the output voltage V regulated by the converter 100. O Related information.

[0136] exist Figure 6 In the embodiment illustrated in FIG, the voltage at node FB is automatically adjusted by a compensation loop including a low-pass filter 162 to eliminate output regulation offset.

[0137] Therefore, in Figure 6 In one or more of the illustrated embodiments, such a feedback loop facilitates compensating for output offsets (in steady state) regardless of the reference voltage V REF Indicates the desired set point value.

[0138] Such a compensation loop may be designed to have a bandwidth that is (much) smaller than the converter bandwidth, in order to manage output variations due to load and line transients.

[0139] Therefore, the output offset compensation loop discussed in this article does not affect the DC-DC regulation operation: such a compensation loop has a (much) smaller bandwidth and therefore cannot "see" the fast changes that the converter is expected to manage and may react to them undesirably (that is, these changes are too fast for the offset compensation loop, which simply filters them out).

[0140] exist Figure 6 In the embodiment shown, the offset compensation loop slowly adjusts the steady-state output regulation value, continuously integrating the node FB REPLICA The signal and reference voltage V REF The remaining error between .

[0141] The low-pass filter 162 can be a simple structure (such as a first-order RC low-pass filter) with a sufficiently high input impedance (with a high impedance from the node FB REPLICA Looking back at the impedance of the replica voltage divider R3, R4) shows a favorable characteristic.

[0142] Taking into account the bandwidth specification of the offset compensation loop, such an input impedance can be obtained in a relatively easy manner: for example, in the case of a first-order RC low-pass filter, the resistor value R can easily be chosen up to 1 MΩ or more.

[0143] The compensation loop discussed herein facilitates mitigating shortcomings noted in the behavior and performance of converters such as 100 discussed in the introductory portion of this specification. The performance of the converter, such as in terms of precision and accuracy of output regulation, is ultimately improved.

[0144] Figure 7 The circuit diagram shows Figure 6 The replica feedback divider R3, R4 is eliminated in the embodiment, Figure 7 Components or elements similar to those already discussed above are denoted by similar reference symbols so that the corresponding description will not be repeated for the sake of brevity.

[0145] In one or more embodiments, Figure 7 As shown, the compensation loop can directly monitor the (regulated) output voltage V by referring to the (non-inverting) operational amplifier 164. O And is "turned off", the reference value V REF-FS is applied to the (non-inverting) reference op amp 164, the reference value V REF-FS By putting V REFThe scaling factor is obtained by taking into account the division ratio of the voltage divider R1 and R2.

[0146] In fact: Figure 6 In the embodiment shown, the error amplifier 164 is biased to a reference voltage V REF Monitor V FILT , V FILT It is node FB REPLICA =V O *R4 / (R3+R4)=V O * A low-pass filtered version of the signal at R2 / (R1+R2); Figure 7 In the embodiment shown, the error amplifier 164 is REF-FS =V REF *(R1+R2) / R2 monitors V FILT , V FILT It is V O A low-pass filtered version of .

[0147] like Figure 7 The illustrated embodiment may take advantage of the fact that in various DC-DC and PMIC arrangements, the regulation set point is generated from a higher reference source (such as a higher voltage source) via a resistor divider (or similar circuit arrangement).

[0148] In such an arrangement, a reference voltage such as V REF Such scaled values and such as with V O Aligned V REF-FS Such a "full scale" value may already be available, so in Figure 7 In the illustrated embodiment, when generating the reference voltage V REF-FS No additional circuitry may be involved.

[0149] Figure 6 and Figure 7 One or more embodiments illustrated in FIG. 1 rely on an error amplifier (such as 164) that monitors the desired output set point V REF (May be by V REF-FS Provides) and output signal V O The difference between the average values of and is calculated and the feedback (voltage) signal observed by the PFM comparator 16 is adjusted via a controlled current source (eg, 166).

[0150] As discussed, Figure 6 and Figure 7One or more of the embodiments illustrated in the foregoing provide a closed-loop solution with the associated benefit of being able to compensate (as long as the compensation loop has sufficiently high gain) for output offsets due to factors such as process, voltage, temperature (PVT) variations, aging, component degradation, and similar phenomena, with the output offset compensation being inversely proportional to the desired set point V REF and operating parameters (such as T ON , I LOAD and V IN ) etc.

[0151] The effect on the overall current consumption is negligible, since the additional consumption is only associated with the operational amplifier 164 and the additional transistor 166 acting as a controlled current source. Neither efficiency nor power consumption is significantly affected.

[0152] Compared to conventional DC-DC or PMIC solutions, the differences in system complexity and area consumption are small and largely proportional to the resulting advantages.

[0153] In those cases where two feedback dividers are used (R1, R2 and R3, R4: see e.g. Figure 6 ), a matched topology can be utilized to minimize the mismatch between the two. Diffused resistors can be advantageous because such devices generally offer good performance in terms of matching. If (high) accuracy is desired, trimming can be beneficial to mitigate the effects of the mismatch between the two feedback dividers and the offset in the operational amplifier 164. Such an error amplifier can be designed (e.g., using known techniques such as chopping) to operate with reduced offset and essentially negligible mismatch.

[0154] The (converter) circuit (eg 100) exemplified herein may include: a first electronic switch (eg M P ) and a second electronic switch (eg, M N ), through which a current path (e.g., source-drain in the case of a field effect transistor such as a power MOSFET) is coupled at an intermediate node (e.g., A between the first electronic switch MP and the second electronic switch MN); an inductor (or coil, e.g., L), a first end of the inductor being coupled to the intermediate node and a second end (e.g., through a capacitor C) being coupled to an output node (e.g., V O), the output node is configured to be coupled to an electric load (e.g., LD, which may be an element different from that of the present embodiment) to apply an output signal thereto; and a driving circuit device (e.g., 101, 102, 12, 14, 16, 18) of the first electronic switch and the second electronic switch, the driving circuit device being configured to switch the first electronic switch and the second electronic switch between a conductive state and a non-conductive state, wherein the first electronic switch provides a current flow line between the input node and the intermediate node during its conductive state, and the second electronic switch provides a current flow line between the intermediate node and ground (e.g., GND) during its conductive state.

[0155] It should be understood that describing the drive circuit arrangement as being configured to cause the first electronic switch and the second electronic switch to switch between a conducting state and a non-conducting state does not necessarily imply a forward driving action on both switches: in fact, as mentioned above, in some asynchronous converters a diode may be used as the low-side electronic switch Mn instead of a transistor such as a power MOSFET, which diode is able to switch between a conducting state and a non-conducting state even in the absence of a forward forced driving action.

[0156] In the circuits exemplified herein, the driver circuit device may include: a first feedback signal path (e.g., R1, R2, 16) coupled to the output node and configured to control (e.g., EN 16) based on a difference between a feedback signal indicating (e.g., via voltage dividers R1, R2) the output signal at the output node and a reference value. DRV , HS ON LS ON ) The switching time (“on” and / or “off” time, e.g., by T ON ); and a second feedback signal path (e.g., R3, R4, 162, 164, 166, 16), including a low-pass filter (e.g., 162), the low-pass filter (e.g., 162) being coupled to the output node and configured to provide a low-pass filtered feedback signal (e.g., V FILT ), the second feedback signal path is configured (eg, see 164, 166) according to the low-pass filtered feedback signal (eg, V FILT ) and the corresponding reference values (e.g. Figure 6 V in REF or Figure 7 V in REF-FS ) to compensate the feedback signal.

[0157] In the circuits illustrated herein, the second feedback signal path may include a differential circuit (eg, 164) coupled to the low-pass filter to receive the low-pass filtered feedback signal (V FILT ), and is configured to generate a difference signal indicating the difference between the low-pass filtered feedback signal and the corresponding reference value; and a signal generator (e.g., 166) driven by the differential circuit, which is configured to generate a compensation signal for the feedback signal based on the difference signal and inject the compensation signal into the feedback signal.

[0158] In the circuits illustrated herein, the signal generator may comprise a transconductance circuit, optionally a transistor, such as a power MOSFET transistor, driven by the difference circuit.

[0159] In the circuits illustrated herein, the first feedback signal path may include a voltage divider (e.g., R1, R2) coupled to the output node to provide the feedback signal indicative of the output signal at the output node for comparison with the reference value.

[0160] In the circuits illustrated herein, the second feedback signal path may include a corresponding voltage divider (eg, R3 , R4 ) between the output node and the low-pass filter.

[0161] In the circuits exemplified herein, the voltage divider and the corresponding voltage divider may have matching division ratios, and / or include diffused resistors.

[0162] In the circuits exemplified herein, the second feedback signal path may include a path to the output node (directly, see Figure 7 ) connected to the low-pass filter.

[0163] In the circuits illustrated herein, the first and second electronic switches may comprise transistors, optionally power MOSFET transistors, having respective control electrodes (eg gates in the case of field effect transistors such as power MOSFETs) driven by said drive circuitry.

[0164] As mentioned repeatedly, this does not represent a mandatory feature but is provided as an example to illustrate that in some asynchronous converters a diode can be used as the low-side electronic switch Mn instead of a transistor such as a power MOSFET.

[0165] The apparatus exemplified herein may include: a circuit exemplified herein (eg, 100 ); and an electrical load (eg, LD) coupled to the output node (eg, via a smoothing capacitor C) to receive the output signal therefrom.

[0166] The methods of operating a circuit or device exemplified herein may include applying a power supply signal to the input node; and collecting a converted output signal at the output node.

[0167] Without affecting the essential principles, the details and embodiments may vary, even significantly, with respect to what has been described purely by way of example, without departing from the scope of protection.

[0168] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: a first electronic switch and a second electronic switch, a current path through the first electronic switch and the second electronic switch being coupled at an intermediate node; an inductor having a first terminal coupled to the intermediate node and a second terminal coupled to an output node at which an output signal is generated; a drive control circuit arrangement configured to control switching of the first electronic switch and the second electronic switch between a conductive state and a non-conductive state, wherein the first electronic switch provides a current flow between an input node and the intermediate node during the conductive state, and wherein the second electronic switch provides a current flow between the intermediate node and ground during the conductive state; The drive control circuit device comprises: a first feedback signal path coupled to the output node through a first voltage divider circuit and configured to control switching of the first electronic switch and the second electronic switch between the conductive state and the non-conductive state based on a difference between a feedback signal generated by the first voltage divider circuit and a first reference value; and a second feedback signal path comprising a low pass filter, the low pass filter coupled to the output node via a second voltage divider circuit and configured to provide a low pass filtered feedback signal, the second feedback signal path configured to compensate the feedback signal based on a difference between the low pass filtered feedback signal and a second reference value, the second reference value being the same as the first reference value; The first voltage divider circuit and the second voltage divider circuit have equal division ratios.

2. The circuit of claim 1 , wherein the second feedback signal path comprises: a difference circuit coupled to receive the low-pass filtered feedback signal from the low-pass filter and configured to generate a difference signal indicative of the difference between the low-pass filtered feedback signal and the second reference value; as well as A signal generator is driven by the differential circuit, and is configured to generate a compensation signal according to the difference signal and inject the compensation signal into the feedback signal.

3. The circuit of claim 2, wherein the signal generator comprises a transconductance circuit driven by the differential circuit.

4. The circuit of claim 3, wherein the transconductance circuit is a transistor having a control terminal driven by the difference signal. The circuit of claim 1 , wherein the first voltage divider and the second voltage divider have matched division ratios.

6. The circuit of claim 1, wherein the first voltage divider and the second voltage divider comprise diffused resistors.

7. The circuit of claim 1, wherein the first electronic switch and the second electronic switch comprise transistors having respective control electrodes driven by the drive control circuitry.

8. The circuit of claim 1, further comprising a load connected to the output node.

9. A circuit comprising: a first electronic switch and a second electronic switch, a current path through the first electronic switch and the second electronic switch being coupled at an intermediate node; an inductor having a first terminal coupled to the intermediate node and a second terminal coupled to an output node at which an output signal is generated; a drive control circuit arrangement configured to control switching of the first electronic switch and the second electronic switch between a conductive state and a non-conductive state, wherein the first electronic switch provides a current flow between an input node and the intermediate node during the conductive state, and wherein the second electronic switch provides a current flow between the intermediate node and ground during the conductive state; The drive control circuit device comprises: a first feedback signal path coupled to the output node through a voltage divider circuit and configured to control switching of the first electronic switch and the second electronic switch between the conductive state and the non-conductive state based on a difference between a feedback signal generated by the voltage divider circuit and a first reference value; and a second feedback signal path comprising a low-pass filter, the low-pass filter being directly electrically connected to the output node and configured to provide a low-pass filtered feedback signal, the second feedback signal path being configured to compensate the feedback signal based on a difference between the low-pass filtered feedback signal and a second reference value; The second reference value is different from the first reference value.

10. The circuit of claim 9, wherein the second feedback signal path comprises: a difference circuit coupled to receive the low-pass filtered feedback signal from the low-pass filter and configured to generate a difference signal indicative of the difference between the low-pass filtered feedback signal and the second reference value; as well as A signal generator is driven by the differential circuit, and is configured to generate a compensation signal according to the difference signal and inject the compensation signal into the feedback signal.

11. The circuit of claim 10, wherein the signal generator comprises a transconductance circuit driven by the differential circuit.

12. The circuit of claim 11, wherein the transconductance circuit is a transistor having a control terminal driven by the difference signal.

13. The circuit of claim 9, wherein the voltage divider comprises a diffused resistor.

14. The circuit of claim 9, wherein the first and second electronic switches comprise transistors having respective control electrodes driven by the drive control circuitry.

15. The circuit of claim 9, further comprising a load connected to the output node. 16 . The circuit according to claim 9 , wherein the first reference value and the second reference value have a scaling relationship according to a division ratio of the voltage divider circuit.

17. A circuit comprising: a first electronic switch and a second electronic switch, a current path through the first electronic switch and the second electronic switch being coupled at an intermediate node; an inductor having a first terminal coupled to the intermediate node and a second terminal coupled to an output node at which an output signal is generated; a drive control circuit arrangement configured to control switching of the first electronic switch and the second electronic switch between a conductive state and a non-conductive state, wherein the first electronic switch provides a current flow between an input node and the intermediate node during the conductive state, and wherein the second electronic switch provides a current flow between the intermediate node and ground during the conductive state; The drive control circuit device comprises: a comparator circuit having a first input configured to receive a first reference value, a second input, and an output; a first voltage divider circuit connected to the output node and having a first tap node configured to generate a feedback voltage that is applied directly to the second input of the comparator circuit; a transistor having a source-drain path and a gate terminal, the source-drain path coupled to provide a compensation current directly to the second input of the comparator circuit; a differential amplifier circuit having a first input coupled to receive a second reference value, a second input, and an output coupled to drive the gate terminal; A low pass filter circuit has its input coupled to the output node and its output coupled to the second input of the differential amplifier circuit.

18. The circuit of claim 17, wherein the input of the low-pass filter is directly connected to the output node, and the first reference value and the second reference value are different.

19. The circuit of claim 17, wherein the input of the low-pass filter is coupled to the output node through a second voltage divider circuit, and the first reference value and the second reference value are the same.

20. The circuit of claim 17, wherein the first and second electronic switches comprise transistors having respective control electrodes driven by the drive control circuitry.

21. The circuit of claim 17, further comprising a load connected to the output node.

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