Reconfigurable System-on-Chip

Abstract

This invention relates to a System-on-a-Chip (SOC), comprising: a first subcircuit having a defined interface and defined fixed hardware functions; a second reconfigurable subcircuit signalably connected to the first subcircuit via the interface to exchange signals with it; and (iii) one or more terminals for electrically connecting the SOC to its peripheral devices. The second subcircuit is configured as an interface circuit between the one or more terminals and the first subcircuit. The first subcircuit is divided into a plurality of individual first circuit blocks, and the second subcircuit is divided into a plurality of individual second circuit blocks. Furthermore, at least one of the first circuit blocks is signalably connected to one or more other first circuit blocks or one or more terminals via one or more signal connections, each signal connection extending through one or more of the second circuit blocks. One or more of the signal connections can be reconfigured by means of a corresponding one or more second circuit blocks belonging to the corresponding signal connection, preferably dynamically and / or reversibly, such that the SOC can be reconfigured before or during its operation by reconfiguring at least one of the second circuit blocks.

Description

[0001] This invention relates to the field of integrated circuits (ICs), and more particularly to reconfigurable system-on-a-chip (SoC). Specifically, without limitation, this invention is applicable to use in automotive applications.

[0002] In many modern applications, particularly in automotive applications, the System-on-Chips (SOC) plays a crucial role in enabling these applications. For example, modern vehicle engines (e.g., automotive engines), air conditioning, safety systems, braking systems, and many other vehicle subsystems rely on and are controlled by control units that incorporate one or more SOCs (such as, for example, microcontrollers).

[0003] Many SoCs have functionally fixed hardware defined by the corresponding IC design and then fixed (hardwired) during the manufacturing process of that IC. This also applies to many SoCs with integrated software-programmable cores, such as CPUs or microcontroller units (MCUs), where the reconfigurability of the SoC is strictly software-based based on the fixed hardware implementation.

[0004] On the other hand, reconfigurable hardware circuitry is known, such as so-called Field Programmable Gate Arrays (FPGAs), which allow for dynamic hardware-level reconfiguration of circuitry, or "rerouting," based on corresponding FPGA programming. However, FPGAs also have significant disadvantages compared to ICs with fixed hardware implementations, particularly including lower implementability and larger footprint for the same functionality, and consequently higher cost.

[0005] Typically, at the end of the integrated circuit (especially SoC) manufacturing process, the produced IC undergoes comprehensive testing to verify its compliance with specifications. This testing usually includes verifying the IC's correct electrical performance as well as its environmental and mechanical properties. However, in some applications, including automotive applications, such ICs need to withstand varying and sometimes harsh environmental conditions, which can impact their reliability.

[0006] Current testing and qualification processes (particularly including the aforementioned tests at the end of a typical production process) are often not quick enough to adapt to the evolving application-specific requirements of such demanding applications, particularly those in automotive environments. While some currently available on-chip test solutions offer a variety of test functions, these functions cannot be extended or modified (especially calibrated) once the manufacturing process for such a chip is complete. In particular, known solutions do not provide the possibility of adapting or modifying test functions in response to operational or environmental events while the IC is in use and subject to changing environmental conditions and associated operational loads and challenges.

[0007] Therefore, manufacturers of systems that include one or more of these ICs face scenarios where either they need to mitigate or accept the risks arising from existing testing and qualification gaps through additional measurements—such as adding (further) redundancy (which could lead to overdesign)—or where using such an IC is not feasible, for example in safety-related applications. The latter scenario is typically applicable to automotive applications, which can negatively impact the availability or performance of vehicles that will be introduced based on the characteristics of vehicles using such ICs.

[0008] Therefore, considering the functionality, reliability, and / or testability of integrated circuits throughout their entire lifespan, the object of this invention is to further improve the reconfigurability of integrated circuits, particularly ICs with high performance requirements.

[0009] The teachings of claim 1 provide a solution to this problem. The teachings of the dependent claims provide various preferred embodiments of the invention.

[0010] One aspect of the present invention relates to a System-on-a-Chip (SOC), comprising: (i) a first subcircuit having a defined interface and defined fixed hardware functions; (ii) a second reconfigurable subcircuit signalably connected to the first subcircuit via the interface to exchange signals with it; and (iii) one or more terminals for electrically connecting the SOC to its peripheral devices. The second subcircuit is configured as an interface circuit between the one or more terminals and the first subcircuit. The first subcircuit is divided into a plurality of individual first circuit blocks, and the second subcircuit is divided into a plurality of individual second circuit blocks. Furthermore, at least one of the first circuit blocks is signalably connected to one or more other first circuit blocks or one or more terminals via one or more signal connections, each signal connection extending through one or more of the second circuit blocks. One or more of the signal connections can be reconfigured by means of a corresponding one or more second circuit blocks belonging to the corresponding signal connection, preferably dynamically and / or reversibly, such that the SOC can be reconfigured before or during its operation by reconfiguring at least one of the second circuit blocks.

[0011] As used herein, the term "subcircuit" refers to a multi-element (e.g., multiple interconnected transistors or other electronic components) circuit portion of a System-on-a-Chip (SoC) that exists in an integrated form, i.e., integrated within the SoC. Specifically, without limitation, a subcircuit may consist of or include one or more semiconductor IP cores, i.e., reusable units of logic or function, or units or layout designs of building blocks designed to be integrated into various different integrated circuits. For example, such semiconductor IP cores may be implementations of microprocessors or entire microcontroller systems, peripheral controllers or other communication-related functions or interfaces, encoders / decoders, memory cells, signal filters, or mixed-signal blocks (such as A / D converters or D / A converters). IP cores may even originate from different vendors and may be sold or otherwise distributed, particularly as soft cores or hard cores.

[0012] As used herein, the term "fixed hardware function" refers to a hardware function of an integrated circuit or its sub-circuits that is implemented in hardware in such a way that it cannot be modified, i.e., "rewired," through normal operation of the IC. For example, and without limitation, the circuitry (i.e., hardware) of a microprocessor or microcontroller device typically has fixed hardware functions (i.e., CPU, registers, caches, etc.), although the overall functionality of the microprocessor or microcontroller device (including functionality implemented in software firmware) can, of course, be changed by replacing or modifying the firmware or software executed thereon. Conversely, hardware functions of hardware that can be operatively reconfigured (e.g., "rewired") to change their functionality (e.g., hardware functions of field-programmable gate arrays (FPGAs) or other hardware reconfigurable logic blocks) are not considered "fixed hardware functions." Therefore, as used herein, the term "reconfigurable" strictly refers to this reconfigurability of circuitry at the hardware level (e.g., in the case of an FPGA), while flexibility provided only at the software level should not be considered "reconfigurable."

[0013] The SOC according to the first aspect of the invention offers numerous advantages over conventional SOC designs. In particular, it combines the advantages of fixed hardware design blocks (especially fixed hardware design blocks in the first sub-circuit) with the flexibility provided by reprogrammable circuitry portions in a second sub-circuit within a single IC. While it is an advantage that these two sub-circuits are thus combined within the same SOC so that they can be handled, distributed, and operated as a single device, the second sub-circuit can still be designed as reconfigurable circuit blocks that can be reused in conjunction with a variety of different DUTs.

[0014] Therefore, this solution allows for the use of the advantages of both predetermined fixed hardware circuitry and flexible (i.e., reprogrammable) circuitry. While fixed hardware circuitry can typically be implemented at a very high level of integration and thus with high performance and space efficiency (small form factor and low cost), the flexibility that can be specifically provided in the second sub-circuit forms the basis for many different advanced features of the overall SOC, as will be described in detail below with respect to various embodiments.

[0015] The overall architecture of the SOC provides, on the one hand, a reconfigurable interconnect structure between various individual fixed hardware circuit blocks, so that their respective functions and characteristics can be dynamically combined in a variety of different ways depending on the current application-specific requirements and operational requirements of the SOC, and on the other hand, it provides a reconfigurable interconnect structure between these first circuit blocks and the terminals of the SOC, and thus with the peripheral devices of the SOC.

[0016] Although the design layout of the first sub-circuit is divided into multiple individual first circuit blocks, each of which implements one or more specific functions of the first sub-circuit, the overall functionality of the first sub-circuit, which can specifically correspond to one or more reusable semiconductor IP cores, is maintained.

[0017] Another advantage of this solution is that the configuration of the SOC's terminals (i.e., its pinouts) can remain unchanged across multiple versions or even multiple generations of the SOC, even though these different versions or generations contain at least different versions of the first sub-circuits, and their interfaces can even change from one version or generation to another.

[0018] Preferred embodiments of the SOC are described below. These embodiments can be combined with each other in any way, unless such combination is explicitly excluded, for example when certain embodiments are described only as alternatives to each other or when they are technically impossible.

[0019] According to some embodiments, the fixed hardware function of the first sub-circuit is a vehicle-specific function. For example, and without limitation, such a function may relate to engine control, braking control, control of one or more safety systems or features, air conditioning, infotainment systems, lighting systems, head unit, communication systems, body control systems, safety features (e.g., in the context of long-term upgradeability of the selected system), or the vehicle's human-machine interface.

[0020] According to some embodiments, the SOC is adapted to dynamically reconfigure itself during operation by reconfiguring the at least one second circuit block according to a machine learning-based reconfiguration process. Specifically, in some related embodiments, the SOC is adapted to apply the machine learning-based reconfiguration process to dynamically determine a corresponding optimized configuration from a set of multiple possible configurations of two or more of the second circuit blocks for an operating scenario, based on the values ​​of one or more input parameters that define the current or upcoming operating scenario of the SOC. Thus, in this way, the interconnect structure of the SOC provided by the set of second circuit blocks can be automatically adapted to a specific operating scenario and therefore to the requirements that the SOC needs to meet. These operating scenarios may specifically involve application-specific requirements or the operating requirements of the SOC itself, such as thermal management, self-testing, etc.

[0021] Therefore, input parameters can correspond to technical parameters characterizing these respective requirements. For example, in the case of operational requirements, input parameters can reflect self-test measurements, such as temperature distribution across the SOC, or current or voltage levels at specific locations within the SOC. In the case of application-specific requirements, input parameters can, for example, reflect a different set of current priorities assigned to different functions within a first sub-circuit or the entire SOC, allowing the SOC to configure interconnect structures such that low-priority circuit blocks are disconnected or switched to low-power modes, while higher-priority circuit blocks remain connected. Specifically, this can be performed in such a way that first circuit blocks that need to cooperate to perform a particular application become interconnected or remain interconnected through one or more intermediate second circuit blocks. Using one or more machine learning-based reconfiguration processes enables solutions that are adaptable to a wide range of operational scenarios, including those not anticipated during the SOC's design or those that change over time (e.g., based on the aging process of the SOC itself or its peripherals).

[0022] According to some embodiments, a first subset of the second circuit blocks is implemented as corresponding fixed hardware circuit blocks, and a disjoint second subset of the second circuit blocks is implemented as corresponding reconfigurable circuit blocks, such as FPGA blocks. In this way, the functionality of the second sub-circuit itself is based on the concept of a hybrid hardwired (i.e., fixed hardware) circuit block and a reconfigurable circuit block. For example, a library of different predefined functions of the second sub-circuit can be implemented by a set of hardwired second circuit blocks, each implementing one or more library elements, while the reconfigurable second circuit blocks provide an interconnection structure within the second sub-circuit itself that allows the second circuit blocks to be flexibly interconnected with each other, and in particular allows individual library elements to be switched on or off depending on the current operating scenario applied to the second sub-circuit.

[0023] According to some embodiments, the second sub-circuit is further configured as an integrated test unit for testing the fixed hardware function of the first sub-circuit by applying one or more input signals to the first circuit and evaluating the compliance of one or more output signals received from the first sub-circuit via the interface in response to the one or more input signals with one or more predetermined test criteria.

[0024] As used herein, the term "integrated test unit" refers to a multi-component circuit section of a System-on-a-Chip (SoC) that exists in an integrated form and has test functions for testing a first sub-circuit or at least one or more of its components.

[0025] Therefore, the SOC according to these embodiments already includes test functionality for testing the first sub-circuit, which can be performed during its operation throughout the SOC's lifetime. Thus, the first sub-circuit can be referred to as a "device under test" (DUT), which is interconnected with a second sub-circuit, which in turn has test functionality for testing the DUT via its interface. In fact, this test functionality can even be dynamically changed during the SOC's lifetime based on its reconfigurability. As will be described in detail below, the functionality of the second sub-circuit with respect to the first sub-circuit can even include various additional aspects. In particular, the functionality of the second sub-circuit can vary throughout the SOC's lifetime to adapt to specific developments during that lifetime and ensure, in many cases, extended compliance of the first sub-circuit with its defined specification lifetime.

[0026] Specifically, according to some embodiments, two or more circuit blocks in the first subset of the second circuit blocks each implement a corresponding specific test instrument for testing relevant aspects of the fixed hardware functionality of the first sub-circuit. Furthermore, two or more circuit blocks in the second subset of the second circuit blocks are reconfigurable, allowing selective connection of these test instruments to the first sub-circuit to selectively enable testing via one or more of the corresponding connected test instruments. This allows for a highly flexible, reconfigurable test setup for testing the first sub-circuit, which can be dynamically reconfigured depending on current test needs, which in turn can specifically depend on the current or upcoming operating scenario of the SOC.

[0027] Furthermore, in some related embodiments, at least one of the signal connections between the first sub-circuit and the second sub-circuit includes one or more dedicated measurement lines that are specifically configured to test, measure, or monitor the first sub-circuit or its function at corresponding predetermined measurement points within the first sub-circuit, without controlling or otherwise affecting the function.

[0028] According to some embodiments, the SOC is configured such that any signal between the SOC's first subcircuit and one or more terminals (i.e., in the forward or reverse direction, or both) is passed through a second subcircuit, thus forming a unique interface circuit between the one or more terminals and the first subcircuit. In this way, the function of the second subcircuit, performed with respect to the first subcircuit, is unaffected by any (wire-based) interaction between the first subcircuit and another entity unknown to the second subcircuit, and therefore the second subcircuit can act as a gatekeeper for any signal connections between the first subcircuit and peripheral devices of the SOC. This can be particularly advantageous, as will be described in more detail below, with regard to ensuring the integrity and security of the operation of the first subcircuit.

[0029] According to some embodiments, at least a subset of the first circuit blocks implements corresponding specific selectable predefined functional features from the feature set of the first sub-circuit. Furthermore, one or more of the second circuit blocks are reconfigurable, allowing selective connection of first circuit blocks from the said subset of the first circuit blocks to other second circuit blocks or one or more terminals, thereby selectively enabling the SOC to execute corresponding functional features of the correspondingly connected first circuit blocks. In this way, the functionality provided by the first sub-circuit can be reconfigured as needed using the second circuit blocks. Similarly, other first circuit blocks can be disconnected simultaneously.

[0030] According to some embodiments, the second subcircuit is further configured to perform one or more of the following functions with respect to the first subcircuit: measuring or monitoring one or more signal or electrical properties of the first subcircuit; and / or controlling or feedback-controlling the first subcircuit. This measurement and monitoring can be used not only to determine the current state or operation of the first subcircuit, but also to measure and monitor the interaction between the first subcircuit and the second subcircuit itself or peripheral devices of the SOC. Controlling or feedback-controlling the first subcircuit can specifically serve the purpose of making the second subcircuit act as a master of the first subcircuit, with the first subcircuit acting as a corresponding slave; or making the second subcircuit act as a master of an interface circuit that transforms inputs received via terminals from peripheral devices of the SOC into corresponding control signals conforming to the interface and capabilities of the first subcircuit, thereby controlling the first subcircuit accordingly based on these inputs.

[0031] According to some embodiments, according to the following variations (i) to (iii), the second sub-circuit is further configured to: (i) replace one or more functions of the first sub-circuit by performing one or more functions of the first sub-circuit in the second sub-circuit instead of in the first sub-circuit; (ii) replace one or more functions of the reprogrammable portion of the first sub-circuit by reprogramming a reprogrammable portion of the first sub-circuit using program data present in the second sub-circuit; or (iii) extend one or more functions of the first sub-circuit by performing one or more extensions of the functions of the first sub-circuit.

[0032] Variation (i) can be specifically applied to replace a no longer needed function in the first subcircuit with another function available in the second subcircuit, or to define a workaround solution when the function to be replaced in the first subcircuit has been found to be defective or otherwise faulty. In the latter case, although the defective or faulty part itself is not corrected, a workaround is established that can take over the function of the defective / faulty part, and thus ensures that the entire SOC continues to operate correctly (i.e., compliant with specifications) and that the function remains available.

[0033] On the other hand, if the first sub-circuit includes one or more reprogrammable parts in addition to its fixed hardware functions, and the defect / fault has its cause in one or more of these reprogrammable parts, then based on variant (ii), the actual bug fix (i.e., correction of the defect / faulty part) can be achieved by reprogramming these one or more reprogrammable parts using program data present in the second sub-circuit, for example as a backup solution or as part of the regular function of the second sub-circuit itself.

[0034] Therefore, according to some embodiments particularly relevant to variations (i) and (ii), the function to be replaced in the first sub-circuit is the function detected as defective by the SOC's error detection function. Thus, the entire SOC can thereby possess self-correcting capabilities. This is particularly useful when the SOC is used in harsh environmental or load conditions or in applications requiring a high level of reliability (e.g., safety or security-related applications). Specifically, many automotive applications present such challenging conditions and / or simultaneously have such high reliability requirements.

[0035] According to variant (iii), one or more functions implemented in the first sub-circuit can be extended by using additional resources present in the second sub-circuit. For example, the second sub-circuit may provide additional memory capacity, processing capacity, or sub-functions, such that the performance or capability of the basic functions implemented in the first sub-circuit can become enhanced functions based on the contribution of the second sub-circuit.

[0036] According to some embodiments particularly relating to variations (i) and (ii), the second subcircuit is further configured to at least partially replace or extend the test functionality implemented in the first subcircuit itself. For example, if the first subcircuit includes test units such as those for boundary scan, and one or more of these test units are detected as defective, then according to these embodiments, these defective test units can be replaced by good test units implemented in the second subcircuit (see variation (i)). Variation (ii) can also be used to correct defects, provided that the defective test units are implemented in the reprogrammable portion of the first subcircuit.

[0037] According to some embodiments, the second subcircuit further includes a programmable circuit structure comprising one or more of the following: (i) a field-programmable gate array (FPGA) and (ii) a programmable processor platform configured to emulate the functionality of the second subcircuit based on a real-time operating system running on the processor platform, at least partially and particularly with respect to the testing of at least one of the fixed hardware functions of the first subcircuit. These embodiments can be particularly used to implement reconfigurable or replaceable test instruments for testing the first subcircuit or portions thereof. Specifically, the second subcircuit may include memory containing code for implementing different test instruments, and depending on the current testing conditions, applicable code may be loaded into the programmable circuit structure for execution therefor the purpose of implementing the relevant test instrument. In this way, libraries of different test instruments can be maintained in a very compact manner in the second sub-circuit of the SOC or in a separate memory circuit or even in the first sub-circuit itself, because the same programmable circuit structure can be used to dynamically implement different test instruments at different times, and the necessary code can be stored in a very space-efficient manner in a storage device (e.g., non-volatile memory (e.g., embedded flash memory)) or even in a typically highly space-efficient read-only memory (ROM).

[0038] According to some embodiments, at least one of the signal connections between the first and second sub-circuits is an electrical connection, which includes one or more impedance matching devices configured to optimize the proper transmission of RF signals over the electrical connection. In cases where high-frequency signals (e.g., radio frequency (RF) signals) need to be exchanged between two sub-circuits, one advantage of combining both the first and second sub-circuits in a single SOC is particularly important. Transmitting such signals over long distances is often challenging due to their high sensitivity to all kinds of parasitic impedances and capacitances, requiring measures to maintain adequate signal quality. However, several advantages exist if the first and second sub-circuits are combined close to each other within a single SOC. In one aspect, the distance required for the signal to travel from one sub-circuit to the other can be very short, thereby limiting adverse effects. On the other hand, one or more suitable impedance matching devices can be provided within the signal path, configured to provide optimized transmission of RF signals over the respective electrical connection (i.e., the signal path). In this way, the reliability of the interaction between the two sub-circuits can be further enhanced, especially when the interaction is based on RF signals.

[0039] According to some embodiments, the SOC is further configured to protect data transmitted via signal connections between the first and second sub-circuits by means of data encryption. This is particularly useful if, according to some embodiments discussed above, all connections between the first sub-circuit and the SOC's peripheral devices extend through the second sub-circuit, which thus acts as a gatekeeper. Encryption of the signal connections between the second and first sub-circuit thus enhances the security concept based on this gatekeeper function, as it increases the difficulty of intercepting signal paths to and from the first sub-circuit and thereby bypassing the second sub-circuit as a gatekeeper.

[0040] According to some embodiments, the second sub-circuit further includes an access control function configured to monitor and control signals exchanged between the peripheral devices of the SOC and the first sub-circuit based on predetermined access control rules. In this way, the gatekeeping function of the second sub-circuit can be further enhanced, and the operational security of the first sub-circuit can be further increased. Specifically, according to some related embodiments, the access control function of the second sub-circuit can be configured to selectively grant or dismiss access requests from peripheral devices of the SOC, based solely on prior authentication of the requesting entity, for access to the entire first sub-circuit or one or more individual first circuit blocks thereof. In this way, it is also possible to implement different security levels for different types of access requests, and particularly for different individual first circuit blocks of the first sub-circuit.

[0041] According to some embodiments, the second subcircuit further includes an energy management function for managing the energy supply to the first subcircuit or a portion thereof. The energy management function is configured to perform one or more of the following energy control tasks in response to receiving a corresponding energy control signal, according to variations (i) to (iv): (i) selectively turning on or off a corresponding energy supply to one or more selected circuit portions (e.g., first circuit blocks) of the first subcircuit; (ii) selectively switching one or more selected circuit portions of the first subcircuit into a corresponding low-energy operating mode; (iii) selectively rerouting at least a portion of the total available energy supply to one or more selected portions (e.g., first circuit blocks) of the first subcircuit, such that the energy is available only or primarily to those selected portions, while correspondingly interrupting or reducing the energy supply to unselected portions; (iv) selectively connecting a backup energy supply, a device or circuit configured to reduce the energy supply, or an energy regulation circuit to a corresponding energy supply path of one or more selected portions (e.g., first circuit blocks) of the first subcircuit to respectively increase, decrease, or regulate the energy supply to one or more selected portions of the first subcircuit.

[0042] According to relevant embodiments, the SOC includes one or more additional sub-circuits in addition to the first and second sub-circuits. Each additional sub-circuit has a defined interface and defined fixed hardware functions. The energy management function of the second sub-circuit can be further configured to perform one or more of the following energy control tasks in response to receiving a corresponding energy control signal, according to variations (v) to (viii): (v) selectively turning on or off the corresponding energy supply to one or more additional sub-circuits; (vi) selectively switching one or more of the one or more additional sub-circuits to a corresponding low-energy operating mode; (vii) selectively reducing the supply of total available energy. (viii) At least a portion of the energy is rerouted to one or more selected sub-circuits in the first sub-circuit and the other sub-circuit, such that the energy is available only or primarily to these selected sub-circuits, while correspondingly interrupting or reducing the energy supply to unselected sub-circuits in the first sub-circuit and the other sub-circuit; (viii) a backup energy supply, a device or circuit configured to reduce the energy supply, or an energy regulation circuit is selectively connected to the corresponding energy supply path of one or more selected sub-circuits or selected portions thereof in the first sub-circuit or the other sub-circuit, to respectively increase, decrease, or regulate the energy supply to one or more selected sub-circuits or selected portions thereof in the first sub-circuit or the other sub-circuit.

[0043] While the primary effect of variants (i), (ii), (v), and (vi) (which can be used particularly during normal operation of the SOC) is to conserve energy where and when it is not currently required, variants (iii), (iv), (vii), and (viii) are particularly important in emergency situations where the necessary energy supply to the entire SOC is adversely affected, and prioritization of the remaining functions to be maintained and ensuring these functions for as long as possible are critical requirements. For example, in the case of an automotive application, if the SOC is responsible for controlling the vehicle's steering wheel in a scenario of energy supply failure (e.g., if the engine is off and the battery supply is weak or even interrupted), variants (iii) and (iv) can be used to ensure that at least the steering capability of the steering wheel (including, for example, electric power steering) is maintained for as long as possible, while other functions (such as user interfaces for controlling entertainment, telephone, or air conditioning functions) can be cut off from the energy supply. Specifically, instead of simply shutting down the energy supply to the parts of the SOC that implement the corresponding lower priority functions in a given scenario, the energy supply paths of these energy supplies can be rerouted so that these energy supplies can now supply energy to the parts of the SOC that are responsible for the higher priority functions that need to be maintained in the given scenario.

[0044] According to relevant embodiments, the SOC itself is further configured to generate an energy control signal based on measurements of the flow of electrical energy through one or more terminals or on one or more electrical connections between the second and first sub-circuits. Therefore, the SOC itself is capable of measuring or monitoring both the electrical paths external to which it is connected and the electrical paths between the first and second sub-circuits within the SOC, and generating the energy control signal based on such measurements. Specifically, depending on one or more of the foregoing, the measurements may involve measuring current, voltage, impedance, ohmic resistance, or any physical value. These measurements can particularly form the basis for improved energy management of the entire system to which the SOC belongs (e.g., a control unit for a vehicle), and for improved handling of detected errors and defects related to energy management. For example, if the measurements produce a result indicating an abnormally increased current drain at one or more of the SOC terminals, or between some of them, or in one or more energy supply or signal paths between the second and first sub-circuits, this can be interpreted as a potential fault or defect, and the energy flow through the SOC can be adjusted accordingly. This adjustment can be achieved, for example, by configuring the SOC to additionally connect one or more current-limiting devices (e.g., devices acting as resistors) to the appropriate path in order to limit the current and thereby prevent any resulting faults or defects caused by the abnormally increased current level.

[0045] Another measure to mitigate the risks associated with detected high current levels could be to shut down relevant portions of the SOC itself (e.g., selected FPGA regions or cells within a second sub-circuit), or to provide control signals at one or more terminals of the SOC to shut down or switch one or more relevant portions of the overall system to which the SOC belongs to another operating mode, such as a low-power operating mode. Alternatively, if the measurement indicates an insufficient power supply, an additional energy source (e.g., a backup power supply) or energy regulation device can be connected to the appropriate energy path to mitigate the risk that a subsequent failure or defect could adversely affect the operation and reliability of the SOC or the overall system.

[0046] According to some embodiments implemented or cumulatively implemented in alternatives, the energy management function is further configured to: (i) receive an energy control signal from the host in the form of an application-specific energy control signal when the host in the peripheral device of the SOC is executing a corresponding application; (ii) determine one or more of the energy control tasks, and the sub-circuits or portions thereof that will be affected by such one or more tasks, based on the energy control signal; and (iii) perform the determined one or more energy control tasks with respect to the determined one or more sub-circuits or portions thereof (e.g., circuit blocks). These embodiments are particularly helpful if it is desired to expand the range of different energy modes available to the SOC, because additional application-specific energy modes can be implemented at the software level in addition to a set of energy modes that may already be available based on the host hardware itself. Thus, the energy control signal can specifically indicate such an application-specific energy mode that the application running on the host desires the SOC to switch to, and a second sub-circuit can react accordingly and switch the SOC to the desired energy mode, which may be different from or may not be different from the energy modes originally supported by the host hardware itself.

[0047] Where the term "comprising" is used in this specification and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used to refer to a singular noun (e.g., "a (or an)", "the"), this includes the plural form of that noun, unless otherwise specifically stated.

[0048] The terms first, second, third, etc., used in the specification and claims are used to distinguish between similar elements and are not necessarily used to describe a sequence or temporal or spatial order. It is to be understood that the terms thus used are interchangeable where appropriate, and the embodiments of the invention described herein can operate in a different order or sequence than those described or illustrated herein. Attached Figure Description

[0049] Further advantages, features, and applications of the invention are set forth in the following detailed description and accompanying drawings, in which:

[0050] Figure 1 A basic functional diagram of an exemplary embodiment of a SOC according to the present invention is schematically illustrated, the SOC having first and second sub-circuits, wherein instead of showing the various sub-blocks of each of the first and second sub-circuits separately, the total function of the first and second sub-circuits is illustrated as a corresponding single functional block for the purpose of reducing the complexity of the illustration.

[0051] Figure 2 schematically illustrated Figure 1 An extension of the diagram, wherein, according to another exemplary embodiment, the SOC further includes a third sub-circuit;

[0052] Figure 3 This is a block diagram illustrating the structure of an exemplary SOC according to an embodiment of the present invention, showing individual circuit blocks of the first and second sub-circuits and their interconnections.

[0053] Figure 4 This is a cross-sectional view of an exemplary embodiment of a system according to the present invention, the system comprising, according to Figures 1 to 3 The SOC and another IC with similar functions to the SOC, but wherein the first and second sub-circuits are implemented in different semiconductor chips.

[0054] In the accompanying drawings, the same reference numerals are used for the same or corresponding elements of the SOC and system described herein. Detailed Implementation

[0055] refer to Figure 1 According to an embodiment of the present invention, the SOC 1 includes a first sub-circuit 2 having fixed hardware functions (e.g., a microcontroller) and a reconfigurable second sub-circuit 3. Each of the first sub-circuit 2 and the second sub-circuit 3 is implemented by a plurality of first or second circuit blocks 20 to 26 and 30 to 44, respectively, as follows: Figure 3 As shown. However, in Figure 1 In this diagram, both the first and second sub-circuits are drawn as single circuits, solely for the purpose of reducing the complexity of the figures. Specifically, the various circuit blocks of the first sub-circuit 2 are drawn as a combined single logic design 2a. The SOC 1 has a set of terminals 4 for connecting the SOC 1 to its peripheral devices, such as printed circuit boards of devices, for example, electronic control units (ECUs) in automotive applications, such as engine control, air conditioning control and infotainment systems, electronic power steering systems, or braking systems.

[0056] Each terminal 4 of SOC 1 is electrically connected to a corresponding pad 5 belonging to the second sub-circuit 3, and there is no direct connection from the first sub-circuit 2 to any terminal 4. Therefore, the second sub-circuit 3 acts as an interface circuit and gatekeeper for the first sub-circuit 2, as the latter can only be accessed from the terminal 4 and thus from the peripheral devices of SOC 1 via the second sub-circuit 3. Each of the first and second sub-circuits includes a corresponding set of interconnecting circuit blocks. However, for the sake of reducing the complexity of the illustrations, those inter-block connections and internal circuits of the various circuit blocks are not shown in the figures, except for those selected inter-block connections and internal circuits, which are specifically referenced in the following discussion of various embodiments.

[0057] Preferably, considering the gatekeeper function of the second sub-circuit 3 with respect to the first sub-circuit 2, communication on at least one signal line 6, and preferably all signal lines 6, is protected by data encryption to prevent tampering with the SOC 1. For example, tampering with the SOC 1 could be intended to bypass the gatekeeper function and gain direct access to the first sub-circuit despite the lack of authorization, for example, for illegal vehicle modification purposes. Furthermore, the second sub-circuit 3 may include access control functions provided in the corresponding functional block 3e to implement an authentication process, ensuring that access to the first sub-circuit 2 from the SOC's peripheral devices is only possible after successful authentication via one or more terminals 4.

[0058] In this non-limiting exemplary embodiment, the second sub-circuit 3 is specifically designed as a test unit for testing the hardware functionality, particularly the logic design 2a, and correspondingly the individual (second) circuit block, of the first sub-circuit 2 (which may therefore be referred to as the device under test or design, DUT) by having one or more input signals applied to the interface 2b of the first sub-circuit 2 via a set of signal lines 6 by the interface block 3d of the second sub-circuit 3, and evaluating the compliance of one or more output signals received as a return from the first sub-circuit 2 in response to the one or more input signals via the interface 2b with one or more predetermined test criteria. The interface 2b can be as simple as including only electrical contacts for connecting the second sub-circuit 3 to the first sub-circuit 2, or it can be more complex and include one or more interface functions, such as I / O functions like voltage limiters, charge pumps, signal filters, etc. It should be noted that... Figure 2 Each block shown may itself comprise multiple individual circuit blocks. Specifically, interface block 3d actually comprises multiple individual interface portions distributed across various individual (first) circuit blocks of the second sub-circuit.

[0059] Such test criteria may include, for example: (i) whether the measured potential is below or above a predetermined voltage threshold; (ii) whether the measured current is below or above a predetermined current threshold; (iii) whether the local temperature is below or above a predetermined temperature threshold; or (iv) whether the signal frequency is below or above a predetermined signal threshold. Specifically, signal line 6 designed to carry high-frequency signals (such as radio frequency (RF) signals) may include specific impedance matching devices 7 to optimize the transmission of such high-frequency signals on the corresponding signal line without unacceptable attenuation or other adverse frequency-related effects. Other possible test criteria may relate to other measurable properties and operating states of the first sub-circuit 2.

[0060] In addition to the conventional signal line 6 extending between the interface block 3d of the second sub-circuit and the interface 2b of the first sub-circuit, specific dedicated measurement lines 6a, 6b, and 6c can also extend between the interface block 3d and selected measurement locations within the logic design 2a of the first sub-circuit 2. This allows in-situ measurements at those selected locations without affecting the functionality of the first sub-circuit 2. The selected locations may specifically relate to portions of the first sub-circuit 2 that are subjected to higher stress, for example, due to above-average current, voltage, temperature, or frequency.

[0061] While this measurement could be a one-off event, such as when the SOC is started, it can instead occur regularly, for example at fixed time intervals or under specific predetermined conditions. Furthermore, essentially continuous monitoring is possible, which could be particularly useful for safety-related applications.

[0062] The function of the second sub-circuit 3 (particularly including test functions) is based on a set of functional blocks, including, for example, a reprogrammable block in the form of a field-programmable gate array (FPGA), a controller block 3b, a memory block 3c in the form of an embedded flash memory, an interface block 3d, and an access control block 3e. Furthermore, the second sub-circuit 3 may also include other blocks (not shown). As already noted, each of these blocks may itself comprise multiple individually arranged circuit blocks.

[0063] Specifically, controller block 3b may have several different functions, including, on the one hand, controlling measurements associated with the first sub-circuit 2, as discussed above. On the other hand, controller block 3b is configured to evaluate the obtained measurement results and react accordingly to maintain the desired function of the first sub-circuit 2 and thus the entire SOC 1. For this purpose, the second sub-circuit 3 may be adapted to control or feedback control the first sub-circuit 2 or portions thereof, such as specific circuit blocks associated with specific functions of the first sub-circuit 2. For example, controller block 3b may control the signals exchanged on signal line 6 between the second and first sub-circuits and change them or turn them on and off depending on the obtained measurement results.

[0064] Furthermore, if the measurement results indicate a defect in the first sub-circuit 2 related to its specific function, the controller block 3b can initiate a replacement of the defective function of the first sub-circuit 2 by the corresponding function of the second sub-circuit. This can be specifically implemented in the reprogrammable (FPGA) block 3a of the second sub-circuit 3. For this purpose, the controller block 3b can load the corresponding program mode from the memory block 3c, where it has previously been stored as an element of a library containing a set of different program modes for different purposes.

[0065] Alternatively, if a dedicated reprogrammable function block 2h exists for the first sub-circuit 2 itself and the defect can be assigned to that reprogrammable block 2h, then the controller block 3b can transmit a corresponding program pattern for fixing the defect to such block 2h. Specifically, the reprogrammable block 2h itself can define test functions for the first sub-circuit 2 itself, such as a boundary scan function. Therefore, if the test function has been found to be faulty or otherwise defective, it can be fixed by reprogramming block 2 based on a program pattern provided by the second sub-circuit 2 in response to the detection of a faulty or defective error in the SOC 1. This could be implemented in either the first or second sub-circuit 2 or 3, or even elsewhere within the SOC 1.

[0066] In addition to its testing functions, the second sub-circuit 3 also includes an energy management block 3f for managing the energy supply to the first sub-circuit 2. Specifically, the first sub-circuit 2 includes exemplary first, second, and third functional blocks 2f, 2g, and 2h in the form of circuit blocks within its logic design 2a. Each of these circuit blocks has a corresponding energy supply block 2c, 2d, and 2c, which can be, in particular, any integrated current or voltage source (such as, for example, a voltage regulator or charge pump), or simply a switching circuit or device (e.g., a transistor) capable of selectively connecting or disconnecting the corresponding functional block from the power input or other energy supply of the logic design 2a or the entire first sub-circuit 2.

[0067] The first sub-circuit 2 can specifically receive its power supply from the second sub-circuit 3 via a corresponding power supply line 9 extending between the two sub-circuits. For example... Figure 1 As shown, these power supply lines 9 can be connected to the energy supply blocks 2c, 2d, and 2e, which in turn can turn on or off, regulate, increase, or decrease the power supply to the corresponding functional blocks 2f, 2g, and 2h of the first sub-circuit 2 in response to corresponding control signals received from the energy management block 3f of the second sub-circuit 3. Specifically, in order to reduce the power supply necessary for these functional blocks, if their functions are not currently needed, or if their functions have a lower priority than other functions that need to be maintained during emergency mode in a scenario of insufficient total power supply, one or more of these functional blocks can be selectively switched to a low-power operating mode, such as a sleep mode.

[0068] The second sub-circuit 3 can then receive its power from the main power supply 8a within the SOC. The main power supply 8a may correspond to one or more power input terminals 4 of the SOC 1 or to a power supply unit within the SOC 1, such as a voltage regulator or charge pump, or other circuitry for supplying electrical power. Furthermore, the SOC 1 may include a backup power supply 8b, which is not used during normal operation of the SOC 1, but is used as a backup power supply to support emergency functions of the SOC 1 if the main power supply 8a breaks away or becomes otherwise unreliable or insufficient.

[0069] Therefore, in this scenario, the energy management block 3f can have the following function: selectively directing energy from the backup energy supply 8b only to those high-priority functional blocks of SOC 1, particularly including the corresponding high-priority circuit blocks of the first sub-circuit 2. Furthermore, the energy management block 3f can selectively reroute at least a portion of the energy supplied by the main energy supply 8a or the backup energy supply 8b (as the case may be) to ensure that the energy is provided only, or at least primarily, to those functional blocks within SOC 1 that have the highest priority in a given scenario.

[0070] For example, in the case of an automotive application (e.g., engine control), if the main energy supply 8a fails, the energy management block 3f can selectively connect the backup energy supply 8b to the selected functional blocks of the SOC 1, and particularly the first sub-circuit 2, necessary to maintain the engine's emergency functions. This is sufficient, for example, to pull the vehicle to the side of the road before the engine shuts off. Furthermore, if the main energy supply 8a has not completely ceased providing energy, the energy management block 3f can reroute the energy flow from the main energy supply 8a by disconnecting lower-priority functional blocks from that energy supply and instead directing the energy flow to higher-priority functional blocks required in the emergency scenario. Thus, those higher-priority functional blocks can not only receive their regular energy supply, but they can even be supplied with additional energy to ensure their functionality in a given scenario.

[0071] This rerouting can also be used in other non-emergency scenarios if an additional amount of energy is needed, at least temporarily. For example, this could be the case if SOC 1 includes flash memory and a flash (erase) operation is required, which would temporarily consume above-average energy, exceeding the level that the standard energy supply of the flash memory can provide.

[0072] Figure 2 Another embodiment of the SOC 1 according to the present invention is shown. This embodiment is based on Figure 1 The embodiments described herein include all of its features. However, it is different from... Figure 1 The difference in the embodiment is that SOC 1 includes an additional sub-circuit 10, hereinafter referred to as the third sub-circuit, which serves as another function of SOC 1 and is an additional DUT included therein. Therefore, the second sub-circuit 3 is adapted to perform its control, testing, energy management, access control, and other functions not only with respect to the first sub-circuit 2 (DUT1), as referenced above. Figure 1 As described, and also for the third sub-circuit 10 (DUT2) and in a similar manner, these functions are performed. Of course, the number of DUTs is not limited to two, and therefore additional sub-circuits (DUTs) may also exist. The third sub-circuit 10 and any additional sub-circuits that may exist can be implemented as a single compact design block, or, similar to the first sub-circuit, implemented as a set of individual design (circuit) blocks that can be arranged separately within the design and layout of the SOC 1.

[0073] Similar to the first sub-circuit 2, the third sub-circuit 10 includes a functional logic design 10a and an interface 10b. The functional logic design 10a includes various sub-blocks, such as, for example, sub-blocks 10e, 10f, and 10g. The interface 10b is used for communication via signal line 6a and power line 9a. Figure 2 The signal line 6 of the first sub-circuit 2 (not shown) interfaces with the second sub-circuit 3. The logic design 10a further includes power supplies 10c and 10d, which, in a manner similar to the power supply blocks 2c, 2d, and 2e of the first sub-circuit 2, can be controlled by control signals received from the second sub-circuit 3 via one or more signal lines 6a and interface 10b. However, sub-block 10g is an example of a sub-block that does not have an individually controllable power supply under the control of the second sub-circuit. For example, sub-block 10g may involve the main critical function of the logic design 10a, which must be powered under all circumstances to maintain the availability of the third sub-circuit 10 or even the entire SOC 1, and therefore does not need to be selectively deactivated or placed in a low-power mode.

[0074] refer to Figure 3An exemplary SOC 1 according to an embodiment of the present invention includes a semiconductor substrate on which first sub-circuit 2 and second sub-circuit 3 are integrated. The first sub-circuit 2 is distributed across a set of exemplary individual first circuit blocks 20 to 26, and the second sub-circuit 3 is distributed across a set of exemplary individual second circuit blocks 30 to 44. The first circuit blocks 20 to 44 are distributed across the layout of the SOC 1 and interconnected in such a way that each first circuit block is signal-connected to one or more other first circuit blocks 20 to 26 or one or more terminals 4 of the SOC 1 via one or more signal connections 6 (only one of which is marked by reference numeral 6), and each signal connection extends through one or more of the second circuit blocks 30 to 44. Furthermore, one or more of the signal connections 6 can be reconfigured by means of the corresponding one or more second circuit blocks 30 to 44 belonging to the corresponding signal connection 6, preferably dynamically and reversibly, such that the SOC 1 can be reconfigured during its operation by reconfiguring at least one of the second circuit blocks 30 to 44.

[0075] Therefore, in this exemplary embodiment, there is no direct connection between any of the first circuit blocks 20 to 26 and the pad 5, the terminal 4 correspondingly connected to the pad 5, and thus the peripheral devices of the SOC 1. Any connection between any of the first circuit blocks 20 to 26 and the terminal 4 of the SOC 1 extends through at least one of the second circuit blocks 30 to 44, thereby collectively providing gatekeeper functionality for the first sub-circuit 2. However, it should be noted that in other embodiments, one or more direct connections may additionally exist between the first circuit block and one or more other first circuit blocks and / or between one or more terminals.

[0076] While all circuit blocks are directly or indirectly connected (most connections are not shown) to the main power supply 8a of SOC 1, at least a subset of the second circuit blocks (circuit blocks 30 and 31 in this example) include power management functions for at least a subset of the first circuit blocks (circuit blocks 20 to 22 in this example), as discussed in detail above. For this purpose, circuit blocks 30, 31 are connected directly or indirectly to the main power supply 8a on one side, and are designed to selectively connect each of blocks 20 to 22 to at least one of the main power supply 8a and the additional backup power supply 8b via corresponding power lines 9, or to disconnect them from the main power supply 8a and the additional backup power supply 8b. Each of the power supplies 8a and 8b may be on-chip, for example in the form of a voltage regulator or charge pump or any other kind of voltage or current source, or alternatively off-chip, and may be connected via a subset of terminals 4 to corresponding power lines on SOC 1.

[0077] refer to Figure 4 According to embodiments of the present invention, the SOC 1 can be particularly combined with one or more other SOCs 1 within the same system, or with electronic component 13 or a group of individual electronic components, which further includes a corresponding first sub-circuit 2' and a corresponding second sub-circuit 3', each sub-circuit having the corresponding functions described herein for sub-circuits 2 and 3. Specifically, the SOC 1 and one or more of the electronic components 13 can be combined to optionally form a SIP, MCM, or system including a common substrate (e.g., PCB) with additional sub-circuits or SOCs, on which the SOC 1 and the at least one additional electronic component are mounted. In the latter case, at least one of the SOC 1 and electronic component 13 can be at least partially embedded in a recess in the common substrate, or (e.g.) Figure 4 As shown in the diagram, the SOC 1 is stacked on top of each other in a stacked package (PoP) structure. The SOC 1 includes a package substrate 11 with terminals 4 and a mold mass 12 for encapsulating the SOC 1. The electronic component 13 includes its own package substrate 11' with terminals 4', a first sub-circuit 2', and a second sub-circuit 3', which are together encapsulated by the mold mass 12'.

[0078] Such a system can have the advantage that the respective advantages of both types of embodiments (multi-chip and SOC) can be used simultaneously in a suitable partition. Specifically, components of the system—for which the corresponding second sub-circuit is preferably integrated on the same semiconductor die as the first sub-circuit, for example, if it is necessary to exchange RF signals between the two sub-circuits—can preferably be provided as a SOC embodiment. However, other components of the system, and particularly those in which the manufacturing technology of the second sub-circuit needs to be substantially different from that of the first sub-circuit, or in which frequent product updates are anticipated and necessary, may preferably be provided as a multi-chip embodiment. For example, if the second sub-circuit is not limited to logic design but also includes power circuitry or significant memory circuitry, its manufacturing technology may have to be significantly different from that of the first sub-circuit (the first sub-circuit may, for example, only require standard CMOS technology), and therefore, implementation according to the multi-chip embodiment will be necessary or at least preferred.

[0079] While at least one exemplary embodiment of the invention has been described above, it must be noted that numerous variations exist therein. Furthermore, it should be understood that the described exemplary embodiments are merely non-limiting examples illustrating how the invention can be implemented and are not intended to limit the scope, application, or configuration of the apparatus and methods described herein. Rather, the foregoing description will provide those skilled in the art with constructions for implementing at least one exemplary embodiment of the invention, wherein it must be understood that various changes can be made to the arrangement and function of the elements of the exemplary embodiments without departing from the subject matter defined by the appended claims and their legal equivalents.

[0080] Reference Symbol List

[0081] 1 SOC

[0082] 2 First Sub-circuit

[0083] 2a The functional logic design block of the first sub-circuit, such as a microcontroller.

[0084] 2b Interface of the first sub-circuit

[0085] Power supply for the first functional block of the first sub-circuit in 2c

[0086] Energy supply for the second functional block of the first sub-circuit in 2d

[0087] Power supply for the third functional block of the first sub-circuit 2e

[0088] 2f First functional block of the first sub-circuit

[0089] 2g First Sub-circuit Second Functional Block and Test Function

[0090] The third functional block of the first sub-circuit (2h) is reprogrammable.

[0091] 3 Second Sub-circuit

[0092] 3a. Reprogrammable blocks of the second sub-circuit, such as FPGA blocks.

[0093] 3b Controller block of the second sub-circuit

[0094] 3c second sub-circuit memory block, such as embedded flash memory

[0095] 3D Second Sub-Circuit Interface Block

[0096] 3e Access control block for the second sub-circuit

[0097] 3f Second Sub-circuit Energy Management Block

[0098] 4 SOC terminals

[0099] 5. Pads on the second sub-circuit

[0100] 6. Signal lines between the first sub-circuit and the second sub-circuit

[0101] 6a, b, c Dedicated measuring lines

[0102] 6d Signal lines between the first and third sub-circuits

[0103] 7 Impedance matching devices

[0104] 8a Main energy supply

[0105] 8b Backup energy supply

[0106] 9 Power supply line to the first sub-circuit

[0107] 9a Power supply line to the third sub-circuit

[0108] 10 Third Sub-circuit

[0109] Functional logic design of the third sub-circuit of 10a

[0110] 10b Interface of the third sub-circuit

[0111] Power supply of the first functional block of the third sub-circuit of 10c

[0112] Energy supply for the second functional block of the third sub-circuit of 10d

[0113] 10e Third Sub-circuit First Functional Block

[0114] The second functional block and test function of the third sub-circuit of 10f

[0115] 11, 11' Package Substrate

[0116] 12, 12' encapsulated mold block

[0117] 13 Electronic Components

[0118] 20-26 First circuit block of the first sub-circuit

[0119] 30-44 Second circuit block of the second sub-circuit

Claims

1. A system-on-a-chip (SoC), comprising: The first sub-circuit has a defined interface and defined fixed hardware functions; A second reconfigurable sub-circuit, which is signal-connected to the first sub-circuit via the interface to exchange signals with it; and One or more terminals for electrically connecting the SOC to its peripheral devices; The second sub-circuit is configured as an interface circuit between one or more terminals and the first sub-circuit; The first sub-circuit is divided into multiple individual first circuit blocks; The second sub-circuit is divided into multiple individual second circuit blocks; At least one of the first circuit blocks is signal-connected to one or more other first circuit blocks or one or more terminals via one or more signal connections, and each signal connection extends through one or more of the second circuit blocks; One or more of the aforementioned signal connections can be reconfigured by means of corresponding one or more second circuit blocks belonging to the respective signal connection, such that the SOC can be reconfigured before or during its operation by reconfiguring at least one of the second circuit blocks; and The SOC is configured such that all signals between one or more terminals and the first sub-circuit are transmitted through the second sub-circuit, without any direct connection from the first sub-circuit to any of the one or more terminals, thus making the second sub-circuit the sole interface circuit between the one or more terminals and the first circuit. The second sub-circuit is further configured as an integrated test unit for testing the fixed hardware function of the first sub-circuit during operation of the SOC by applying one or more input signals to the first circuit and evaluating the compliance of one or more output signals received from the first sub-circuit via the interface in response to the one or more input signals with one or more predetermined test criteria.

2. The SOC of claim 1, wherein the SOC is adapted to dynamically reconfigure itself during its operation by reconfiguring the at least one second circuit block according to a machine learning-based reconfiguration process.

3. The SOC of claim 2, wherein the SOC is adapted to: apply the machine learning-based reconfiguration process to dynamically determine, for the operating scenario, a corresponding optimized configuration from a set of two or more possible configurations of the second circuit block. This is based on the values ​​of one or more input parameters that define the current or upcoming operating scenario of the SOC.

4. The SOC of claim 1, wherein a first subset of the second circuit blocks is implemented as corresponding fixed hardware circuit blocks, and a disjoint second subset of the second circuit blocks is implemented as corresponding reconfigurable circuit blocks.

5. The SOC according to claim 4, wherein: Two or more circuit blocks in the first subset of the second circuit block implement corresponding specific test instruments for testing relevant aspects of the fixed hardware function of the first sub-circuit; as well as Two or more circuit blocks in the second subset of the second circuit block are reconfigurable, thereby selectively connecting these test instruments to the first sub-circuit to selectively enable testing by one or more of the corresponding connected test instruments.

6. The SOC of claim 1, wherein the signal connection between the first sub-circuit and the second sub-circuit includes one or more dedicated measurement lines, said one or more dedicated measurement lines being specifically configured to test, measure or monitor the first sub-circuit or its function at corresponding predetermined measurement points within the first sub-circuit, without controlling or otherwise affecting said function.

7. The SOC of claim 1, wherein at least a subset of the first circuit blocks implements corresponding specific selectable predefined functional features in the feature set of the first sub-circuit; and One or more of the second circuit blocks are reconfigurable, thereby selectively connecting the first circuit blocks in the subset of the first circuit blocks to other second circuit blocks or one or more terminals, so as to selectively enable the SOC to perform one or more functional features of the corresponding connected first circuit blocks.

8. The SOC of claim 1, wherein the second sub-circuit is further configured to perform one or more of the following functions with respect to the first sub-circuit: Measure or monitor one or more signals or electrical properties of the first sub-circuit; The first sub-circuit for control or feedback control; One or more functions of the first sub-circuit are performed in the second sub-circuit instead of the first sub-circuit; One or more functions of the first sub-circuit are replaced by reprogramming the reprogrammable portion of the first sub-circuit using program data present in the second sub-circuit; or The functionality of the first sub-circuit is extended by performing one or more extensions of the functionality of the first sub-circuit.

9. The SOC of claim 8, wherein the function to be replaced by the first sub-circuit is a function that is detected as defective by the error detection function of the SOC.

10. The SOC according to claim 8 or 9, wherein the second sub-circuit is further configured to at least partially replace or extend the test functions implemented in the first sub-circuit itself.

11. The SOC of claim 1, wherein at least one of the signal connections between the first sub-circuit and the second sub-circuit is an electrical connection, the electrical connection comprising one or more impedance matching devices configured to optimize the correct transmission of RF signals over the electrical connection.

12. The SOC of claim 1, wherein the SOC is further configured to: Data encryption is used to protect data transmitted between the first and second sub-circuits via signal connections; and / or The signals to be exchanged between the peripheral devices of the SOC and the first sub-circuit are monitored and controlled based on predetermined access control rules.

13. The SOC according to claim 1, wherein: The second sub-circuit further includes an energy management function for managing the energy supply to the first sub-circuit or a portion thereof; and The energy management function is configured to perform one or more of the following energy control tasks in response to receiving a corresponding energy control signal: Selectively turn on or off the corresponding power supply to one or more selected circuit sections of the first sub-circuit; Selectively convert one or more selected circuit portions of the first sub-circuit into a corresponding low-energy operating mode; Selectively reroutes at least a portion of the total available energy supply to one or more selected portions of the first sub-circuit, such that the energy is available only or primarily to those selected portions, while correspondingly interrupting or reducing the energy supply to the unselected portions; Selectively connect a backup energy supply, a device or circuit configured to reduce the energy supply, or an energy regulation circuit to a corresponding energy supply path of one or more selected portions of the first sub-circuit to respectively increase, decrease, or regulate the energy supply to one or more selected portions of the first sub-circuit.

14. The SOC of claim 13, wherein the SOC itself is further configured to generate an energy control signal based on a measurement of electrical energy flow through one or more terminals or on one or more electrical connections between the second sub-circuit and the first sub-circuit.

15. The SOC of claim 13, wherein the energy management function is further configured to: When the host in the peripheral device of the SOC is executing the corresponding application, it receives an energy control signal from the host in the form of an application-specific energy control signal; Based on the energy control signal, one or more of the energy control tasks, and the sub-circuits or circuit blocks thereof that will be affected by such one or more tasks, are determined. as well as The determined one or more sub-circuits or their circuit blocks are used to perform the determined one or more energy control tasks.

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