Decision to perform a full memory refresh during a memory subsystem power-on phase

Abstract

A system includes a plurality of memory devices and a processing device (e.g., a controller) operatively coupled to the plurality of memory devices. The processing device is to detect a power-up of the system and determine a read retry trigger rate (TR) for a subset of codewords of the plurality of memory devices during a time interval after initialization of a memory component. The processing device is further to determine whether the TR satisfies a threshold criterion. In response to the TR not satisfying the threshold criterion, the processing device is to initialize a full memory refresh of the plurality of memory devices.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to a memory subsystem, and more specifically, to determining whether to perform a full memory refresh during the power-on phase of the memory subsystem. Background Technology

[0002] A memory subsystem can be a storage device, a memory module, or a combination of a storage device and a memory module. A memory subsystem may contain one or more memory components for storing data. Memory components may be, for example, non-volatile memory components and volatile memory components. Generally, a host system can use a memory subsystem to store data at memory components and retrieve data from memory components. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed descriptions given below and from the accompanying drawings of various embodiments thereof.

[0004] Figure 1 An example computing environment including a memory subsystem is shown according to some embodiments of the present disclosure.

[0005] Figure 2A It is a graph representing the cell voltage threshold distribution density relative to the cell voltage according to an embodiment of the present disclosure, showing the short write-to-read (W2R) latency.

[0006] Figure 2B It is a graph representing the cell voltage threshold distribution density relative to the cell voltage according to an embodiment of the present disclosure, showing a moderate W2R delay.

[0007] Figure 2C It is a graph representing the cell voltage threshold distribution density relative to the cell voltage according to an embodiment of the present disclosure, showing a long W2R delay.

[0008] Figure 3A This is a timeline showing the power-on phases of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 3B This illustrates an embodiment according to the present disclosure. Figure 3A A time map of phases and time intervals is used to determine the read retry trigger rate (TR) of the memory subsystem during the time intervals.

[0010] Figure 3C This illustrates another embodiment according to the present disclosure. Figure 3A A time map of phases and time intervals is used to determine the TR of the memory subsystem during the time intervals.

[0011] Figure 4This is a flowchart of an example method for determining whether to perform a full memory refresh during the power-on phase of the memory subsystem, according to an embodiment of the present disclosure.

[0012] Figure 5 This is a flowchart of an example method for determining whether to enter a normal operating mode during the power-on phase of a system subsystem, according to an embodiment of this disclosure.

[0013] Figure 6 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0014] This disclosure relates to determining whether to perform a full memory refresh during the power-on phase of the memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may use a memory subsystem that includes one or more memory components or devices. The host system can provide data that will be stored in the memory subsystem and can request data that will be retrieved from the memory subsystem.

[0015] A memory subsystem may include multiple memory components or memory devices capable of storing data from a host system. In various embodiments, the cell voltage threshold (Vt) distribution density, representing the statistical distribution of threshold voltages of memory cells, varies over time, including voltage drift that increases over time (regardless of whether the memory subsystem is powered on). Combined with noise present when reading memory cells, a single read level may be insufficient to meet system reliability targets for read bits. In practice, multiple read levels may be employed by the memory controller (hereinafter referred to as the "controller") to recover data stored in the memory. Typically, if the first read operation fails, the read operation begins at a low voltage level and then moves to a higher voltage level on read retries. This is due to the partial write effect of the read operation to avoid distortion based solely on the Vt distribution density of read attempts.

[0016] In the disclosed embodiments, voltage state recovery (e.g., Vt distribution density recovery) within a memory cell can be performed via a cell refresh operation comprising a read operation, a write operation, or a combination thereof. A write cell refresh can be an in-bit write operation where a voltage level state is first determined (by reading), and then said state is rewritten to the same memory cell as before, resetting the cell back to its original threshold voltage. If the memory subsystem has been powered down for an extended period, the cell Vt distribution density may have migrated to a significantly higher level, which, if left unchanged, would result in a higher read retry trigger rate (TR) for subsequent read attempts. A higher TR degrades system quality of service (QoS) and the client experience when accessing the memory. TR increases with each retry of a read operation because the target data was not read, for example, error correction codes (ECC) failed to decode the data on the media retrieved by the initial read operation. Read operations may need to be retried when the initial low-voltage read attempt is too low relative to the optimal read voltage.

[0017] Conventionally, a controller (e.g., a processing device for a memory subsystem) is configured to never or always perform a full memory refresh operation when power-on of the memory subsystem is detected. A full memory refresh operation refers to the process of refreshing each cell in the memory subsystem (typically refreshing at least one codeword of the cell each time), a process that may take several minutes to tens of minutes to complete. The decision to always perform a full memory refresh can result in unnecessary memory refreshes, leading to throughput loss during power-on, additional cell wear, degraded customer experience during power-on, and potentially compromised durability and / or reliability of the memory subsystem. However, taking the opposite approach, never performing a full memory refresh operation after the memory subsystem is powered on, results in higher TR and lower QoS during operation of the memory subsystem, negatively impacting the customer experience during normal operation.

[0018] This disclosure addresses the aforementioned and other drawbacks by performing detection of the read retry trigger rate (TR) level during a fixed time period after the memory subsystem is powered on. If the TR meets an acceptable threshold criterion (e.g., within an acceptable threshold criterion), a full memory refresh is not required, and normal operation can continue with read and write operations, which may selectively perform some cell refreshes. If the TR does not meet the acceptable threshold criterion (e.g., not within an acceptable threshold criterion), a full memory refresh can be performed on the memory device before entering normal operation. To meet the threshold criterion, the TR may be less than a TR requirement value (TRreq) optionally multiplied by a scaling factor, wherein the scaling factor is less than one (“1”). In this way, a decision on whether to perform a full memory refresh on memory cells can be made at the memory component, device, or memory subsystem level after power-on operation.

[0019] In an embodiment, a memory subsystem is operatively coupled to a processing device, wherein the memory subsystem includes one or more memory devices. The processing device can detect power-on of the subsystem and determine a read retry trigger rate (TR) based on read attempts on a subset of codewords stored at the memory devices during a time interval following the initialization of the memory subsystem. A codeword is a minimal dataset individually protected by ECC. The processing device can further determine whether the TR meets a threshold criterion. In response to the TR not meeting the threshold criterion, the processing subsystem can initiate a full memory refresh of the memory components or devices. In response to the TR meeting the threshold criterion, the processing device can enter a normal operating mode without a full memory refresh.

[0020] The advantages of this disclosure include, but are not limited to, intelligently initiating a full memory refresh based on the actual condition of the memory subsystem, which is measured immediately after power-on based on the TR level of cells in a subset of codewords stored on the memory device. Avoiding an all-or-nothing approach to a full memory refresh after the power-on phase also prevents unnecessary wear on memory cells and improves system throughput, latency configuration, and overall client experience during the power-on phase and normal operation of the memory subsystem. Other advantages of the features of the memory subsystem discussed below will be apparent to those skilled in the art.

[0021] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure is illustrated. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof. Each memory device 130 or 140 may be one or more memory components.

[0022] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0023] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components or devices, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components or devices), whether wired or wireless, and includes connections such as electrical connections, optical connections, magnetic connections, etc.

[0024] Host system 120 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, embedded computer (e.g., a computer contained in a vehicle, industrial equipment, or networked business device), or such a computing device containing memory and processing devices. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM Fast (NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120.

[0025] The memory device may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be (but is not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0026] Examples of nonvolatile memory devices (e.g., memory device 130) include three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of nonvolatile memory cells. The cross-point array of nonvolatile memory can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, cross-point nonvolatile memory allows for in-bit write operations, where nonvolatile memory cells can be programmed without pre-erasing them.

[0027] Although non-volatile memory components such as 3D cross-point memory are described, memory device 130 may be based on any other type of non-volatile memory, such as NAND, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0028] Each cell may store one or more bits. In one embodiment, each of the memory devices 130 may include one or more arrays of memory cells, such as single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), or four-level cell (QLC), or combinations thereof. In some embodiments, a particular memory component or device may include an SLC portion of the memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. Each of the memory cells may store one or more data bits for use by the host system 120. Furthermore, the memory cells of the memory device 130 may be grouped into memory pages, memory blocks, or codewords, which may refer to logical units of a memory component or device used for storing data.

[0029] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The memory subsystem controller 115 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.) or other suitable processor.

[0030] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0031] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although... Figure 1 The instance memory subsystem 110 is shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0032] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical block addresses and physical addresses. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0033] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0034] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. In some embodiments, memory device 130 is a managed memory device (e.g., managed NAND) that is a native memory device combined with a local controller (e.g., local media controller 135) for memory management within the same memory device package.

[0035] In some embodiments, controller 115 includes an error correction code (ECC) encoder / decoder 111 and a full memory refresher 113. The ECC encoder / decoder 111 can perform ECC encoding and ECC decoding on data written to and read from memory device 130, respectively. ECC decoding can be performed to decode ECC codewords to verify the presence of errors in the data, and in some cases, to correct those errors.

[0036] In one embodiment, the full memory refresher 113 may be used to detect the TR of the memory device 130 and perform a comparison with a threshold criterion to determine whether to initiate a full memory refresh of the memory device. In one embodiment, the threshold criterion is that TR is less than the TR demand value (TRreq). In another embodiment, the threshold criterion is that TR is less than TRreq multiplied by a scaling factor (α), where the scaling factor is less than one (“1”). Further details regarding the operation of the full memory refresher 113 are described below.

[0037] In some embodiments, controller 115 includes at least a portion of full memory refresher 113. Additionally, controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 to perform the operations described herein. In some embodiments, full memory refresher 113 is part of host system 120, an application, or an operating system.

[0038] Figure 2AThis is a graph representing the cell voltage threshold (Vt) distribution density relative to the cell voltage according to embodiments of the present disclosure, illustrating a short write-to-read (W2R) latency. Because the Vt distribution density varies over time, a single read level is insufficient to meet the system reliability goals of the memory cell, in addition to other noise mechanisms within the memory. Multiple read levels (e.g., the three levels shown) can be combined to achieve a low bit error rate (BER). As illustrated, in one embodiment, the Vt distribution density is distributed across the cell voltage range in a manner requiring different read levels, as shown from left to right: read level one ("1") at the lowest voltage, read level two ("2") at a medium voltage, and read level three ("3") at a higher voltage. In this embodiment, the Vt distribution density is a function of the write-to-read (W2R) latency.

[0039] For example, recently refreshed and updated W2R latency may be shorter, such as Figure 2A As shown. However, these Vt distribution densities can drift over time as the W2R delay increases, for example, regardless of whether the memory subsystem is powered off. Figure 2A Compared to the short W2R latency, Figure 2B The W2R latency can be described as medium W2R latency, and Figure 2C The W2R delay can be referred to as long W2R delay. For some memories, such as crosspoint arrays of non-volatile memory, read operations on cells have a partial write effect. If the read operation voltage is too high with respect to the cell Vt distribution density, the read operation will distort the Vt distribution density and result in a higher BER for subsequent read operations. Due to this effect of read operations, memory controllers (e.g., processing devices) typically read first at the lowest voltage and then retry at a gradually increasing voltage for subsequent reads.

[0040] To improve the Vt distribution density, the memory controller can perform cell refresh operations on cells in the memory subsystem in the form of codewords, such as error correction code (ECC) words. These cell refresh operations can be performed randomly, sequentially, or using some other system approach. In some cases, cell refresh operations are performed naturally in conjunction with read operations. While partial refreshes can be performed using read operations, more complete refresh operations can be performed using in-bit writes to restore the Vt distribution density of the cells to the distribution corresponding to short W2R delays. Despite exposure to interference and noise, performing such cell refresh operations can improve the robustness of the ability to read memory cells. For example, although the initial read of the codeword attempts to use the lowest possible read voltage, the controller 115 will not need to frequently perform retry reads.

[0041] In various embodiments, cell refresh operations are performed in multiple ways. For example, the memory controller may use the current state of each corresponding cell to rewrite it to the cell, for example, in the form of a codeword via a single in-bit write or multiple in-bit writes. As a second example, the memory controller may rewrite each cell an even number of times with alternating states. Thus, if a cell has a value, the memory controller may write zero to the cell and then rewrite one to the cell. As a third example, the memory controller may read each cell, since reading can partially rewrite the data of each cell. As a fourth example, the memory controller may rewrite each cell if the cell's read statistics (e.g., fault bit count (FBC) and / or a specific error recovery stream sequence) indicate that the cell's Vt distribution density contains an unacceptably long W2R delay. The rewrite option also involves read operations on these cells, since read operations can first be used to obtain the cell's voltage state before writing the cell's contents back to those corresponding cells.

[0042] In the embodiments, for a normally operating memory subsystem, due to continuous write and read operations on the memory subsystem, the memory subsystem has a distribution density of Vt ( Figure 2A The memory exhibits normal (e.g., short) W2R latency. However, after a power outage, the memory subsystem may take a long time to power on. During this time, the cell voltage states may transition to much higher levels than normal, resulting in unacceptably high W2R latency (e.g., ...). Figure 2C Due to partial write effects, the memory controller initially performs reads at the lowest voltage. However, after a prolonged power outage, the memory subsystem is expected to exhibit high read retry trigger rates (or "TR"), reduced Quality of Service (QoS), decreased throughput, and poor latency configuration. The challenge here is that the memory subsystem lacks information indicating how long it has been powered down.

[0043] In some embodiments, during a prolonged power outage, a full memory refresh is performed to readjust the Vt distribution density caused by the long W2R delay before entering a normal operating mode with an acceptable short W2R delay. The full memory refresh can be a memory component or the entire memory subsystem 110, such as the entire memory device 130.

[0044] Figure 3A This is a timing diagram 300A illustrating the power-on stages of a memory subsystem according to some embodiments of the present disclosure. Figure 3AIn an example, host system 120 interfacing with memory subsystem 110 allows a (short) specified initialization period 303 during which the memory subsystem can initialize itself without accepting any host commands that include read operations from host system 120. Host system 120 can also allow a specified reduced execution period 305 (after the specified initialization period 303) during which memory subsystem 110 can accept host commands and the Vt distribution density can stabilize before returning to normal operation mode 307. A full memory refresh operation can be performed on the cells of memory device 130 during the duration covered by the specified initialization period 303 and / or the specified reduced execution period 305. In at least one embodiment, the duration spans a predetermined period of time immediately following the actual initialization of the memory subsystem. As will be discussed with reference to Figure 3B-3C these periods may vary in time depending on how fast the memory subsystem performs the actual initialization.

[0045] As discussed herein, before performing a full memory refresh of memory subsystem 110, controller 115 (e.g., full memory refresher 113) can determine whether the memory cell condition is worthy of performing a full memory refresh during a time interval after the actual initialization of memory subsystem 110. The time interval can be greater than or less than one second and can also be a decimal value. In one embodiment, the time interval can be between 3 - 8 seconds to provide time to track and obtain an accurate value of TR over a period of time. Whether to perform a full memory refresh can be determined by comparing the read retry trigger rate (TR) with a QoS specification of host system 120 herein referred to as the TR demand value (TRreq). In one embodiment, TRreq is a threshold criterion for comparison with the value of TR. If TR is less than TRreq (e.g., TR < TRreq), then TR meets this threshold criterion and a full memory refresh is not initiated. However, if TR is greater than or equal to TRreq, then a full system refresh is initiated.

[0046] In an embodiment, since host system 120 may not want to pass in this comparison even if the call is closed without performing a full memory refresh when needed, TRreq can be multiplied by a scaling factor (α) that is less than one and can be referred to as a guard band value. This scaling factor is to provide additional tolerance that can account for possible delayed administrative refreshes that host system 120 may issue and thus tends to make the TR value have to be lower to avoid a full memory refresh. For example, the equation to now avoid a full memory refresh can be TR < α * TRreq, where host system 120 can adjust α when setting the QoS specification depending on application requirements and the delay typically expected in administrative refreshes within memory subsystem 110.

[0047] Because TR (e.g., the TR value) will be used for comparison, controller 115 can, for example, Figure 3B and Figure 3C The TR value is determined within the time interval following the actual initialization of the memory subsystem 110, as indicated by the parentheses, and before entering normal operation mode 307. The method of determining the TR value may vary depending on the time required for actual initialization and can therefore be based on one or two host read operations issued by the host system 120, or a single cell refresh operation issued by the controller 115. A method that can be deployed during the specified system initialization period 303 is via a cell refresh operation (which initiates a separate read operation), since host read operations are not permitted until after the specified system initialization period 303. In one embodiment, the controller 115 may determine the success / failure of reads up to millions of codewords in order to determine the TR value and whether a full system refresh should be performed.

[0048] Figure 3B This illustrates an embodiment according to the present disclosure. Figure 3A The timing diagram 300B, which defines the phases and time intervals 310A, determines the read retry trigger rate (TR) of the memory subsystem 110 during these time intervals. In timing diagram 300B, the actual initialization period 308 requires less time than the time allocated by the designated initialization period 303. Furthermore, in this example, since the actual initialization period 308 completes during the designated initialization period 303, the controller 115 can still initiate a cell refresh operation during the remaining portion 303A of the designated initialization period. As shown, the time interval 310A for calculating the TR value completes during the remaining portion 303A of the designated initialization period 303. In this way, the memory subsystem 110 can even determine whether to perform a full refresh before entering the designated reduced execution period 305, thereby accelerating decisions on further improving system performance and user experience during the power-on of the memory subsystem 110.

[0049] Figure 3C This illustrates another embodiment according to the present disclosure. Figure 3A The time diagram 300C, which defines the phase and time interval 310B, determines the TR of the memory subsystem 110 during said time interval 310B. In the time diagram 300C, the time required for the actual initialization period 308 is... Figure 3BThe time in time diagram 300B. In this example, the time interval 310B used to determine TR spans the (shorter) remainder 303B of the specified initialization period 303. Therefore, controller 115 can initiate a cell refresh operation during the remainder 303B of the specified initialization period 303. Because determining the TR value and whether to perform a full memory refresh still requires additional time, time interval 310B extends to a specified reduced execution period 305. During a portion of time interval 310B within the specified reduced execution period 305, controller 115 can continue performing cell refresh operations, but can also accept and complete host read operations, as well as other host memory operations. Therefore, TR can be determined based on host read operations, cell refresh operations, or a combination of both during the specified reduced execution period 305. In one embodiment, actual initialization 308 occupies the entire specified initialization period 303, and therefore, time interval 310B will be completely shifted within the specified reduced execution period 305 (not shown). Therefore, depending on the time spent on system initialization during the power-on of the memory subsystem, the controller 115 can use different combinations of host read operations and / or cell refresh operations to determine the value of TR, and thus decide whether to perform a full memory refresh.

[0050] Continue to refer to Figure 3B-3C It should be noted that the actual initialization period and time intervals 310A and 310B are not drawn to scale compared to the specified reduced execution period 305, but are drawn for ease of interpretation. For example, time intervals 310A and 310B are typically a few seconds, while the specified reduced execution period 305 can last for several minutes. Furthermore, the duration and relative length of these different time periods may vary between systems due to factors such as design, service life, and wear levels.

[0051] Figure 4 This is a flowchart 400 of an example method for determining whether to perform a full memory refresh during the power-on phase of the memory subsystem according to embodiments of the present disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1The controller 115 (e.g., full memory refresher 113) performs the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0052] At operation 410, the processing logic detects power-on of the memory subsystem, which includes one or more memory devices. For example, power-on can be detected after a prolonged power-off, but the processing logic does not know how long the power-off period has been. Therefore, the processing logic can be configured to determine whether to perform a full memory refresh after power-on and after initialization.

[0053] At operation 420, the processing logic determines the read retry trigger rate (TR) based on one or more logic cells of the memory device during a time interval following the initialization of the memory subsystem. For example, each logic cell may contain one or more codewords. The TR can be determined as the ratio of the number of read retries invoked by a read operation to the number of read operations performed. For example, read operations typically begin at a low voltage to avoid prematurely resetting the Vt distribution density during read operations that store data. However, if the Vt distribution density shifts to a higher level, the initial low-voltage read attempt may fail. Subsequent read attempts (e.g., retries) may be performed at higher voltages, e.g., increasing by a certain amount. Each retry of a read operation due to a previous failure to read stored data contributes to the overall TR. The value of the TR can be determined based on read operations of the memory device by at least one of the following: a host system coupled to the processing device or a cell refresh operation performed by the processing logic. (See reference...) Figures 3A-3C As mentioned, during or after a specified initialization period 303 of the memory subsystem, the processing logic may perform a cell refresh operation on one or more logic cells. Furthermore, the processing logic may transfer a read operation from the host system to the memory device during a specified reduced execution period 305 following the specified initialization period 303 of the memory subsystem.

[0054] At operation 430, the processing logic determines whether TR meets a threshold criterion. In one embodiment, to meet the threshold criterion, TR will be less than the required TR value (TRreq). In another embodiment, to meet the threshold criterion, TR will be less than the required TR value multiplied by a scaling factor (TR < α * TRreq), where the scaling factor is less than one (“1”). For illustrative purposes, it is assumed that the scaling factor (α) is 0.75 while TRreq can be 1 x 10^6. -10This results in different threshold standards being available at different levels.

[0055] At operation 440, the processing logic initiates a full memory refresh (potentially mixed with host traffic) in response to TR failing to meet the threshold criterion. Host traffic may require serving memory operations from the host system. For example, an unacceptably high TR value might be 1x10. -2 1x10 -1 Or higher, indicating that one or more logic cells are being read at inappropriate voltage levels. In this case, the processing logic may initiate a full memory refresh due to failure to meet the threshold criterion. In different embodiments, a full memory refresh is performed in several ways. For example, the processing logic may use the current state of each corresponding cell, for example, to rewrite the cell of each logic cell on the memory device via a single in-bit write or multiple in-bit writes. As a second example, the processing logic may rewrite each cell an even number of times with alternating states. Thus, if a cell has a value, the processing logic may write zero to the cell and then rewrite one to the cell. As a third example, the memory controller may read each cell, since reading can partially rewrite the data of each cell in the memory. As a fourth example, the processing logic may rewrite each cell if the cell's read statistics (e.g., FBC and / or a specific error recovery stream sequence) indicate that the cell's Vt distribution density contains an unacceptably long W2R delay. The rewrite option also involves read operations on these cells, since read operations can first be used to obtain the voltage state of the cell before writing the cell's contents back to those corresponding cells.

[0056] At operation 450, the processing logic causes the memory subsystem to enter normal operating mode in response to TR meeting the threshold criterion (e.g., an operation without a full memory refresh). A low (and therefore good) value for TR can be 1x10. -4 1x10 -5 Or even lower, indicating that one or more logic units are being read at an appropriate voltage level. In these cases, the processing logic can directly enter normal operation mode because the threshold criterion is met. The values ​​of TR, TRreq, and α are for illustrative purposes only and do not in any way limit the scope of other possible embodiments of the principles discussed herein.

[0057] In this manner, the memory subsystem 110 provides intelligent initiation of a full memory refresh based on the actual condition of the memory subsystem, which is measured immediately after power-on based on the TR level of one or more logic cells. Avoiding an all-or-nothing approach to a full memory refresh after the power-on phase also prevents unnecessary wear on memory cells and improves system throughput, latency configuration, and overall customer experience during the power-on phase and normal operation of the memory subsystem.

[0058] Figure 5 This is a flowchart illustrating an example method for determining whether to enter a normal operating mode during the power-on phase of a system subsystem according to embodiments of the present disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The controller 115 (e.g., full memory refresher 113) performs the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0059] At operation 510, the processing logic detects power-on of the memory subsystem, which includes one or more memory components. For example, power-on can be detected after a prolonged power-off, but the processing logic does not know how long the power-off period has been. Therefore, the processing logic can be configured to determine whether to perform a full memory refresh after power-on and after actual initialization.

[0060] At operation 520, the processing logic initiates a cell refresh operation on cells of a subset of codewords of one or more memory components, the cell refresh operation including a read operation performed on the cell. These cell refresh operations may be performed during a specified initialization period and / or a specified reduced execution period, and may be performed to test the read retry trigger rate (TR) after the memory subsystem is powered on. Reference Figures 3A-3C These cell refresh operations will be discussed in more detail.

[0061] At operation 530, the processing logic determines TR based on read operations performed on a subset of codewords during a time interval following the actual initialization of the memory subsystem, wherein the time interval includes a specified initialization period. TR may be determined at least based on these cell refresh read operations, but may also be further determined based on second read operations issued by one or more memory components by the host system during a specified reduced execution period following the specified initialization period. TR may be fully determined during a time interval including at least a portion of the specified initialization period and the specified reduced execution period.

[0062] At operation 540, the processing logic determines whether TR meets a threshold criterion. In one embodiment, to meet the threshold criterion, TR will be less than the required TR value (TRreq). In another embodiment, to meet the threshold criterion, TR will be less than the required TR value multiplied by a scaling factor (TR < α * TRreq), where the scaling factor is less than one (“1”). For illustrative purposes, it is assumed that the scaling factor (α) is 0.75 while TRreq can be 1 x 10^6. -10 This results in different threshold standards being available at different levels.

[0063] At operation 550, the processing logic initiates a full memory refresh in response to TR failing to meet the threshold criterion (potentially mixed with host traffic). Host traffic may require serving memory operations from the host system. For example, an unacceptably high value for TR might be 1x10. -2 1x10 -1 If the voltage level is higher, it indicates that a subset of the codewords is being read at an inappropriate voltage level. In this case, the processing logic may initiate a full memory refresh because the threshold criterion has not been met.

[0064] At operation 560, the processing logic causes the memory subsystem to enter normal operating mode (e.g., without a full memory refresh operation) in response to TR meeting a threshold criterion. A low (and therefore good) value for TR can be 1x10. -4 1x10 -5 Or even lower, indicating that a subset of the codewords of the indicator unit is being read at an appropriate voltage level. In these cases, the processing logic can directly enter normal operation mode because the threshold criterion is met. The values ​​of TR, TRreq, and α are for illustrative purposes only and do not in any way limit the scope of other possible embodiments of the principles discussed herein.

[0065] In this manner, the memory subsystem 110 provides intelligent initiation of a full memory refresh based on the actual condition of the memory subsystem, which is measured immediately after power-on based on the TR level of one or more codewords of the cell. Avoiding an all-or-nothing approach to a full memory refresh after the power-on phase also avoids unnecessary wear and tear on memory cells and improves system throughput, latency configuration, and overall customer experience during the power-on phase and normal operation of the memory subsystem.

[0066] Figure 6 An example machine of computer system 600 is shown, wherein a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform operations of the controller 115 (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (Operation of the full memory refresher 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0067] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is shown, it should also be understood that the term "machine" includes any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0068] The example computer system 600 includes a processing device 602 that communicates with each other via a bus 630, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618.

[0069] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0070] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) on which one or more instruction sets 626 or software embodying any one or more of the methods or functions described herein are stored. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0071] In one embodiment, instruction 626 includes instructions for implementing a component corresponding to the error determination component (e.g., Figure 1 The machine-readable storage medium 624 (113) contains functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0072] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0073] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0074] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0075] The algorithms and demonstrations presented herein are inherently independent of any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0076] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0077] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system comprising: Multiple memory devices that store a set of codewords; as well as A processing device, operatively coupled to the plurality of memory devices, to: Detect the power supply of the system; In response to the detection of power-on of the system, during an immediate time interval following the initialization of the plurality of memory devices and before or at the start of a reduced execution period prior to the normal operation mode of the plurality of memory devices, a read retry trigger rate TR is determined based on a subset of codewords stored at the plurality of memory devices, wherein the reduced execution period is a first reduced execution period after the power-on of the system, and no full memory refresh operation is performed during the normal operation mode. Determine whether the TR meets the threshold criterion; and In response to the TR not meeting the threshold criterion, the full memory refresh operation of the plurality of memory devices is initiated.

2. The system of claim 1, wherein, In response to the TR meeting the threshold criterion, the processing device further enables the system to enter a normal operating mode without the full memory refresh operation.

3. The system according to claim 1, wherein in order to meet the threshold criterion, the TR will be less than the required TR value.

4. The system of claim 1, wherein the TR is determined based on at least one of the following: The first read operation of the plurality of memory devices includes a cell refresh operation performed by the processing device; or The second read operation of the plurality of memory devices is issued by a host system coupled to the system.

5. The system of claim 4, wherein the processing means performs the cell refresh operation on a subset of codewords during or after a specified initialization period of the plurality of memory devices in at least one of the following circumstances.

6. The system of claim 4, wherein the processing means transmits the second read operation from the host system to the plurality of memory devices during a specified reduced execution period following the initialization of the plurality of memory devices.

7. The system according to claim 1, wherein the time interval includes a period of less than one second.

8. A system comprising: Multiple memory components; as well as A processing device operatively coupled to the plurality of memory components to: Detect the power supply of the system; At least during a specified initialization period immediately following the power-on of the system, a cell refresh operation is initiated on a subset of codewords stored in the plurality of memory components, the cell refresh operation including a read operation performed on the subset of codewords; The read retry trigger rate TR is determined based on the read operation performed on the codeword subset during an immediate time interval following the actual initialization of the system, wherein the time interval overlaps with the specified initialization period, wherein the time interval includes the time period before entering the normal operating mode, and during the normal operating mode no full memory refresh operation is performed; Determine whether the TR meets the threshold criterion; and In response to the TR meeting the threshold criterion, the system enters the normal operating mode without performing the full memory refresh operation.

9. The system of claim 8, wherein, In response to the TR not meeting the threshold criterion, the processing device further initializes the full memory refresh operation of the plurality of memory components.

10. The system of claim 8, wherein in order to meet the threshold criterion, the TR will be less than the TR requirement value multiplied by a scaling factor, wherein the scaling factor is less than -1.

11. The system of claim 8, wherein the TR is further determined based on a second read operation of the plurality of memory components issued by the host system during a specified reduced execution period following the specified initialization period.

12. The system of claim 8, wherein the processing device further performs the cell refresh operation on the codeword subset after the specified initialization period.

13. A method comprising: The power supply to the memory subsystem is detected by a processing device of the memory subsystem, wherein the memory subsystem includes multiple memory devices; During the immediate time interval following the initialization of the memory subsystem and before or at the beginning of a reduced execution period prior to the normal operating mode of the plurality of memory devices, in response to the detection, the processing device determines the read retry trigger rate TR based on a plurality of logic units stored in the plurality of memory devices, wherein each logic unit includes one or more codewords, wherein the reduced execution period is the first reduced execution period after the system is powered on, and no full memory refresh operation is performed during the normal operating mode; The processing device determines whether the TR meets the threshold criterion; and In response to the TR not meeting the threshold criterion, a full memory refresh of the plurality of memory devices of the memory subsystem is initiated.

14. The method of claim 13, wherein, In response to the TR satisfying the threshold criterion, the method further includes causing the memory subsystem to enter the normal operating mode without performing the full memory refresh operation.

15. The method of claim 13, wherein satisfying the threshold criterion comprises making the TR less than a TR requirement value multiplied by a scaling factor, wherein the scaling factor is less than -1.

16. The method of claim 13, wherein determining the TR comprises determining the TR based on at least one of the following: The first read operation of the plurality of memory devices, the first read operation including a cell refresh operation performed by the processing device; or The second read operation of the plurality of memory devices is issued by a host system coupled to the memory subsystem.

17. The method of claim 16, further comprising performing the cell refresh operation on the plurality of logical cells during or after a specified initialization period of the memory subsystem at least one of the following times.

18. The method of claim 17, further comprising transferring the second read operation from the host system to the memory subsystem during a specified reduced execution period following the specified initialization period of the memory subsystem.

19. The method of claim 13, wherein the full memory refresh operation is mixed with memory operations received from the host system.

Images