Integrated circuit and test method thereof

Abstract

The present application relates to an integrated circuit and a test operation method thereof. An integrated circuit includes a test counting circuit, a test information storage circuit, a sequence control circuit and a drive circuit. The test counting circuit generates a count address signal. The test information storage circuit stores a test control value and outputs the test control value based on the count address signal. The sequence control circuit changes the output sequence of the test control value based on the sequence control signal, and outputs a final test control value based on the test control value or the target control value. The drive circuit performs a preset test operation based on the final test control value.

Description

Technical Field

[0001] Various embodiments generally relate to an integrated circuit and a test operation method thereof, and more particularly, to an integrated circuit for providing various test sequences and a test operation method of the integrated circuit. Background Art

[0002] Generally, before integrated circuits such as semiconductor devices and semiconductor memory devices are put on the market, various tests are performed on them. Traditionally, automatic test equipment (ATE) is used for testing operations on integrated circuits. ATE is a single product developed to determine whether an integrated circuit is well designed. Since the cost of ATE is relatively high, the cost of the integrated circuit is based on whether the integrated circuit is tested by the ATE. As the time required to test the integrated circuit with the ATE is longer, the cost of the integrated circuit is higher.

[0003] Based on the above problems, efforts have been made to manufacture built-in self-test circuits. The built-in self-test circuit is installed in the integrated circuit and performs test operations on the integrated circuit instead of automatic test equipment. The built-in self-test circuit shortens the overall manufacturing time and thus reduces the cost of the integrated circuit.

[0004] However, built-in self-test circuits have complex configurations, require large space, and generally only provide conventional (stereotypical) test sequences. The complex configuration leads to defects (i.e., noise) in the built-in self-test circuit. Noise can cause the built-in self-test circuit to output erroneous test result values. The need for a large space means that when designing a built-in self-test circuit, it is a great burden to install the built-in self-test circuit in an integrated circuit. Conventional test sequences do not allow any test operations other than preset operations. In the following, an integrated circuit that only provides conventional test sequences is described.

[0005] Figure 1 is a block diagram showing a conventional integrated circuit.

[0006] Reference Figure 1 The integrated circuit includes a test counting circuit 10, a test information storage circuit 20 and a driving circuit 30.

[0007] The test counting circuit 10 is configured to generate a counting address signal ADD_C that counts sequentially during a test operation. The test information storage circuit 20 is configured to output a test control value V_CTR based on the counting address signal ADD_C. Each test control value V_CTR stored in the test information storage circuit 20 corresponds to each counting address signal ADD_C. Since the test information storage circuit 20 is implemented by a read-only memory (ROM), once stored in the test information storage circuit 20, the test control value V_CTR cannot be changed. The driving circuit 30 is configured to perform a preset test operation based on the test control value V_CTR.

[0008] The test counting circuit 10 sequentially outputs the count address signal ADD_C. The test information storage circuit 20 sequentially outputs the test control value V_CTR corresponding to the count address signal ADD C. The driving circuit 30 can only perform the test operation according to the conventional test sequence based on the sequentially output test control value V_CTR. Summary of the invention

[0009] In one embodiment, the integrated circuit may include a test counting circuit, a test information storage circuit, a sequence control circuit, and a driving circuit. The test counting circuit may generate a counting address signal. The test information storage circuit may store a test control value and output the test control value based on the counting address signal. The sequence control circuit may change the output sequence of the test control value based on the sequence control signal, and output a final test control value based on the test control value or the target control value. The driving circuit may perform a preset test operation based on the final test control value.

[0010] In one embodiment, a test operation method for an integrated circuit may include the following steps: inputting change information for an output sequence of a final test control value for a test operation; generating a final test control value from a test control value or a target control value based on the output sequence; and performing a test on the integrated circuit based on the final test control value. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram showing a conventional integrated circuit.

[0012] Figure 2 is a block diagram showing a configuration of an integrated circuit according to an embodiment.

[0013] Figure 3 is a block diagram showing a configuration of an integrated circuit according to an embodiment.

[0014] Figure 4 is shown with Figure 3 An operational diagram of the integrated circuit showing operations related to a first output sequence.

[0015] Figure 5 is a block diagram showing a configuration of an integrated circuit according to an embodiment.

[0016] Figure 6 is shown with Figure 5 An operational diagram of the integrated circuit showing operations related to a second output sequence.

[0017] Figure 7 is a block diagram showing a configuration of an integrated circuit according to an embodiment.

[0018] Figure 8 is shown with Figure 7 An operational diagram of the integrated circuit showing operations related to a third output sequence.

[0019] Fig. 9 is shown with Figure 7 An operational diagram of the operations associated with the fourth output sequence of the integrated circuit is shown.

[0020] Fig.10 It is shown Figure 2 Flowchart of the test operation method of the integrated circuit shown in FIG. DETAILED DESCRIPTION

[0021] The description of the present disclosure is only an embodiment for structural and / or functional description. The scope of rights of the present disclosure should not be interpreted as being limited to the embodiments described in the specification. That is, because the embodiments can be modified in various ways and can have various forms, the scope of rights of the present disclosure should be understood to include equivalents that can realize the spirit of the technology. In addition, the purpose or effect proposed in the present disclosure does not mean that a specific embodiment should include all purposes or effects or only include these effects. Therefore, the scope of rights of the present disclosure should not be understood to be limited thereby.

[0022] The meanings of the terms used in this application should be understood as follows.

[0023] Terms such as "first" and "second" are used to distinguish one element from another element, and the scope of the present disclosure should not be limited by these terms. For example, a first element may be referred to as a second element. Likewise, a second element may be referred to as a first element.

[0024] Unless otherwise clearly stated in the context, singular expressions should be understood to include plural expressions. Terms such as "including" or "having" should be understood to indicate the existence of a group of features, values, steps, operations, elements, components or their combinations, but do not exclude the possibility of the existence or addition of one or more other features, values, steps, operations, elements, components or their combinations.

[0025] In each step, symbols (e.g., a, b, and c) are used for ease of description, and these symbols do not describe the order of the steps. Unless the context clearly describes a specific order, the steps may be performed in an order different from the order described in the context. That is, the steps may be performed according to the order described, may be performed substantially simultaneously with the order described, or may be performed in the reverse order of the order described.

[0026] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as those generally understood by those skilled in the art. Unless explicitly defined in the application, terms defined in commonly used dictionaries should be interpreted as having the same meaning as in the context of the relevant technology and should not be interpreted as having an ideal or overly formal meaning.

[0027] According to one embodiment, an integrated circuit capable of providing various test sequences and a test operation method of the integrated circuit are provided.

[0028] According to one embodiment, there is provided an integrated circuit capable of changing a test control value to a target control value when an error occurs in the test control value, and a test operation method of the integrated circuit.

[0029] According to one embodiment, various test sequences may be provided during a test operation, and thus the degree of freedom for the test operation may be improved.

[0030] According to one embodiment, it may be more accurately determined whether an integrated circuit is well-designed based on test results according to various test sequences.

[0031] According to one embodiment, when an error occurs in a test control value, the test control value may be changed to a target control value, which solves the problem of repairing or replacing a circuit storing the test control value in which the error occurs.

[0032] Figure 2 is a block diagram showing a configuration of an integrated circuit according to an embodiment.

[0033] Reference Figure 2 , the integrated circuit may include a test counting circuit 100 , a test information storage circuit 200 , a sequence control circuit 300 and a driving circuit 400 .

[0034] The test counter circuit 100 may be configured to generate a counting address signal ADD_C. As described later, a counting operation of the test counter circuit 100 may be controlled based on a counting control signal CTR_C generated from the sequence control circuit 300.

[0035] The test information storage circuit 200 may be configured to store a test control value V_OR, and may be configured to output the test control value V_OR based on the count address signal ADD_C. The test information storage circuit 200 may be implemented with a read-only memory (ROM). Each test control value V_OR stored in the test information storage circuit 200 may correspond to each count address signal ADD. Therefore, the test information storage circuit 200 may output a test control value V_OR corresponding to the count address signal ADD_C.

[0036] The sequence control circuit 300 may be configured to change the output sequence of the test control value V_OR based on the sequence control signal CTR_MD. In addition, the sequence control circuit 300 may be configured to output the final test control value V_CTR based on the test control value V_OR or the target control value. The sequence control signal CTR_MD may correspond to four output sequences to be described later.

[0037] The driving circuit 400 may be configured to perform a preset test operation based on the final test control value V_CTR. The driving circuit 400 may correspond to a semiconductor device and a semiconductor memory device. The driving circuit 400 may be configured to perform a preset test operation such as an initialization operation based on the final test control value V_CTR.

[0038] According to one embodiment, the integrated circuit can change the output sequence based on the sequence control signal CTR_MD. Therefore, the driving circuit 400 can easily perform a desired test operation based on the final test control value V_CTR corresponding to each output sequence.

[0039] The sequence control circuit 300 can control the counting operation and output operation to be described later based on the first input information INF_1 and the second input information INF_2. Therefore, the sequence control circuit 300 can output the final test control value V_CTR corresponding to various output sequences. According to one embodiment, the integrated circuit can provide four output sequences as described below based on the sequence control signal CTR_MD. Here, the sequence control signal CTR_MD can be defined as a code-typed signal (code-typed signal) that selects any one of the four output sequences. That is, the sequence control signal CTR_MD can be a code-typed signal having any one of the values ​​"00", "01", "10" and "11" corresponding to the four output sequences, respectively. Therefore, the sequence control circuit 300 can provide an output sequence for the final test control value V_CTR among the four output sequences based on the sequence control signal CTR_MD. The four output sequences may include a first output sequence, a second output sequence, a third output sequence and a fourth output sequence.

[0040] The following will refer to Figure 3 and Figure 4 Here, the first output sequence may be an output sequence that outputs a target control value instead of a test control value V_OR as a final test control value V_CTR based on a count address signal ADD_C and a target address value, the target address value being input as first input information INF_1 and the target control value being input as second input information INF_2.

[0041] Figure 3 is a block diagram showing a configuration of an integrated circuit according to an embodiment.

[0042] Reference Figure 3 , the integrated circuit may include a test counting circuit 100A, a test information storage circuit 200A, a sequence control circuit 300A and a driving circuit 400A.

[0043] The test counting circuit 100A may be configured to generate a counting address signal ADD_C. The counting address signal ADD_C may be an address signal that is counted sequentially.

[0044] The test information storage circuit 200A may be configured to store a test control value V_OR, and may be configured to output the test control value V_OR based on a count address signal ADD_C.

[0045] The sequence control circuit 300A may receive a target address value as first input information INF_1, and may receive a target control value as second input information INF_2. Based on the count address signal ADD_C and the target address value, the sequence control circuit 300A may be configured to output the target control value, rather than the test control value V_OR, as a final test control value V_CTR. The sequence control circuit 300A may include an address comparison circuit 310A and a selective output circuit 320A.

[0046] The address comparison circuit 310A may be configured to compare the target address value input as the first input information INF_1 with the counting address signal ADD_C to generate a selection control signal CTR_S. Although not shown, the address comparison circuit 310A may include a latch circuit configured to store the target address value. When the target address value is the same as the counting address signal ADD_C, the address comparison circuit 310A may generate a selection control signal CTR_S having a value of a preset logic level.

[0047] The selective output circuit 320A may be configured to selectively output a target control value input as the second input information INF_2, or a test control value V_OR, based on the selection control signal CTR_S. Although not shown, the selective output circuit 320A may include a latch circuit configured to store the target control value. Based on the selection control signal CTR_S, when the target address value is the same as the counting address signal ADD_C, the selective output circuit 320A may output the target control value as the final test control value V_CTR. In addition, based on the selection control signal CTR_S, when the target address value is different from the counting address signal ADD_C, the selective output circuit 320A may output the test control value V_OR as the final test control value V_CTR.

[0048] The driving circuit 400A may be configured to perform a preset test operation based on the final test control value V_CTR. That is, the driving circuit 400A may be configured to perform a test operation based on the first output sequence for the final test control value V_CTR.

[0049] Figure 4 is shown with Figure 3 Hereinafter, for convenience of description, it is assumed that the target address value input as the first input information INF_1 is "003" and the target control value input as the second input information INF_2 is "DAT_TM".

[0050] Reference Figure 3 and Figure 4 During the test operation, the test counting circuit 100A may generate a counting address signal ADD_C that counts sequentially. That is, the test counting circuit 100A may generate a counting address signal ADD_C that counts sequentially as "001", "002", "003", "004", and "005". For ease of description, Figure 4 Five values ​​of the count address signal ADD_C are illustrated. Then, the test information storage circuit 200A can output the test control value V_OR based on the count address signal ADD_C. Figure 4 As illustrated, the test information storage circuit 200A may output test control values ​​V_OR “DAT_1”, “DAT_2”, “DAT_3”, “DAT_4”, and “DAT_5” based on the count address signals ADD_C “001”, “002”, “003”, “004”, and “005”, respectively.

[0051] The sequence control circuit 300A may receive a target address value "003" as the first input information INF_1, and may receive a target control value "DAT_TM" as the second input information INF_2. The address comparison circuit 310A may be configured to compare the target address value with the counting address signal ADD_C to generate a selection control signal CTR_S. When the counting address signal ADD_C is the same as the target address value "003", the address comparison circuit 310A may output the selection control signal CTR_S by activating the selection control signal CTR_S to a preset logic level. Therefore, based on the selection control signal CTR_S, the selective output circuit 320A may output the target control value "DAT_TM" input as the second input information INF_2, instead of the test control value V_OR "DAT_3", as the final test control value V_CTR.

[0052] That is, when the counting address signal ADD_C is "001", "002", "004" and "005", the selective output circuit 320A can output the test control values ​​V_OR "DAT_1", "DAT_2", "DAT_4" and "DAT_5" as the final test control value V_CTR, respectively. In addition, when the counting address signal ADD_C is "003", the selective output circuit 320A can output the target control value "DAT_TM" instead of the test control value V_OR as the final test control value V_CTR.

[0053] In summary, the integrated circuit can set the first output sequence for the final test control value V_CTR based on the target address value input as the first input information INF_1 and the target control value input as the second input information INF_2. Here, when the target address value is "003", the target control value "DAT_TM" can be output as the final test control value V_CTR based on the first output sequence. Therefore, the driving circuit 400A can perform a test operation for the first output sequence based on the final test control value V_CTR.

[0054] As mentioned above, Figure 3 The test information storage circuit 200A shown can be implemented with a ROM. The data stored in the ROM is unchangeable. According to one embodiment, when there is an error in the test control value V_OR stored in the test information storage circuit 200A, the test control value V_OR in which the error occurs can be changed to a target control value through a first output sequence. Therefore, even when there is an error in the test control value V_OR stored in the test information storage circuit 200A, the test operation can be performed normally without repairing or replacing the test information storage circuit 200A.

[0055] The following will refer to Figure 5 and Figure 6 Describe the configuration and operation of the second output sequence. Here, the second output sequence may be an output sequence that outputs a target control value by controlling a counting operation based on a counting address signal ADD_C and a target address value and by inserting the target control value into a final test control value V_CTR, the target control value being input as the second input information INF_2, and the target address value being input as the first input information INF_1.

[0056] Figure 5 is a block diagram showing a configuration of an integrated circuit according to an embodiment.

[0057] Reference Figure 5 , the integrated circuit may include a test counting circuit 100B, a test information storage circuit 200B, a sequence control circuit 300B and a driving circuit 400B.

[0058] The test counter circuit 100B may be configured to generate a count address signal ADD_C. A deactivation operation and an activation operation for a count operation of the test counter circuit 100B may be controlled based on a count control signal CTR_C to be described later.

[0059] The test information storage circuit 200B may be configured to store a test control value V_OR, and may be configured to output the test control value V_OR based on the count address signal ADD_C.

[0060] The sequence control circuit 300B may receive a target address value as first input information INF_1, and may receive a target control value as second input information INF_2. Based on the count address signal ADD_C and the target address value, the sequence control circuit 300B may be configured to control the disabling operation and enabling operation of the counting operation of the test counter circuit 100B. In addition, the sequence control circuit 300B may be configured to insert the target control value into the final test control value V_CTR to output the target control value. The sequence control circuit 300B may include an address comparison circuit 310B, a count control circuit 320B, and a selective output circuit 330B.

[0061] The address comparison circuit 310B may be configured to compare the target address value input as the first input information INF_1 with the counting address signal ADD_C to generate a selection control signal CTR_S. When the target address value is the same as the counting address signal ADD_C, the address comparison circuit 310B may generate the selection control signal CTR_S having a value of a preset logic level.

[0062] The count control circuit 320B may be configured to control the count operation of the test count circuit 100B based on the selection control signal CTR_S. The count control circuit 320B may generate a count control signal CTR_C based on the selection control signal CTR_S. The enable operation or disable operation of the count operation of the test count circuit 100B may be controlled based on the count control signal CTR_C. Figure 6 As described above, the count control circuit 320B may disable the count operation of the test count circuit 100B based on the selection control signal CTR_S. In addition, the count control circuit 320B may enable the count operation of the test count circuit 100B after the target control value is output as the final test control value V_CTR.

[0063] The selective output circuit 330B may be configured to selectively output the target control value input as the second input information INF_2, or the test control value V_OR based on the count control signal CTR_C. Based on the count control signal CTR_C, when the target address value is the same as the count address signal ADD_C, the selective output circuit 330B may insert the target control value into the final test control value V_CTR to output the target control value.

[0064] The driving circuit 400B may be configured to perform a preset test operation based on the final test control value V_CTR. That is, the driving circuit 400B may be configured to perform a test operation based on the second output sequence for the final test control value V_CTR.

[0065] Figure 6 is shown with Figure 5 Hereinafter, for convenience of description, it is assumed that the target address value input as the first input information INF_1 is "003" and the target control value input as the second input information INF_2 is "DAT_TM".

[0066] Reference Figure 5 and Figure 6 During the test operation, the test counting circuit 100B may generate a counting address signal ADD_C that is counted sequentially. Then, the test information storage circuit 200B may output a test control value V_OR based on the counting address signal ADD_C.

[0067] The sequence control circuit 300B may receive a target address value "003" as the first input information INF_1, and may receive a target control value "DAT_TM" as the second input information INF_2. The address comparison circuit 310B may be configured to compare the target address value with the counting address signal ADD_C to generate a selection control signal CTR_S. When the counting address signal ADD_C is the same as the target address value "003", the address comparison circuit 310B may output the selection control signal CTR_S by activating the selection control signal CTR_S to a preset logic level. Then, the counting control circuit 320B may generate a counting control signal CTR_C based on the selection control signal CTR_S to deactivate the counting operation of the test counting circuit 100B. Therefore, the test counting circuit 100B may output a counting address signal ADD_C "003" which is the same value as the previous counting address signal ADD_C. In addition, based on the count control signal CTR_C, the selective output circuit 330B may output the target control value “DAT_TM” instead of the test control value V_OR “DAT_3” by inserting the target control value “DAT_TM” input as the second input information INF_2 into the final test control value V_CTR.

[0068] That is, when the counting address signal ADD_C is "001", "002", "003", "004" and "005", the selective output circuit 330B can output the test control values ​​V_OR "DAT_1", "DAT_2", "DAT_3", "DAT_4" and "DAT_5" as the final test control value V_CTR, respectively. In addition, the counting control circuit 320B can disable the counting operation of the test counting circuit 100B when the counting address signal ADD_C is "003". Therefore, the test counting circuit 100B can maintain the previous counting address signal ADD_C "003". In addition, the selective output circuit 330B can output the target control value "DAT_TM" corresponding to the previous counting address signal ADD_C "003" by inserting the target control value "DAT_TM" into the final test control value V_CTR. After the target control value “DAT_TM” is output, the count control circuit 320B may generate a count control signal CTR_C to enable a counting operation of the test count circuit 100B.

[0069] In summary, the integrated circuit can set the second output sequence for the final test control value V_CTR based on the target address value input as the first input information INF_1 and the target control value input as the second input information INF_2. Here, when the target address value is "003", the target control value "DAT_TM" can be inserted into the final test control value V_CTR, and the final test control value V_CTR can be output based on the second output sequence. Therefore, the driving circuit 400B can perform a test operation for the second output sequence based on the final test control value V_CTR.

[0070] The following will refer to Figures 7 to 9 The configuration and operation of the third output sequence and the fourth output sequence are described. According to one embodiment, the integrated circuit may change the count address signal ADD_C output from the test count circuit 100C to the changed address value input as the second input information INF_2, and may output the final test control value V_CTR based on the target address value input as the first input information INF_1 and based on the count address signal ADD_C. Here, the third output sequence and the fourth output sequence may be output sequences that output the final test control value V_CTR based on the count address signal ADD_C in which the changed address value is reflected.

[0071] Figure 7 is a block diagram showing a configuration of an integrated circuit according to an embodiment.

[0072] Reference Figure 7 , the integrated circuit may include a test counting circuit 100C, a test information storage circuit 200C, a sequence control circuit 300C and a driving circuit 400C.

[0073] The test counter circuit 100C may be configured to generate a count address signal ADD_C. A counting operation of the test counter circuit 100C may be controlled based on a count control signal CTR_C which will be described later.

[0074] The test information storage circuit 200C may be configured to store a test control value V_OR, and may be configured to output the test control value V_OR based on the count address signal ADD_C. Here, the test control value V_OR may correspond to a final test control value V_CTR provided to the driving circuit 400C.

[0075] The sequence control circuit 300C may receive a target address value as first input information INF_1, and may receive a change address value as second input information INF_2. The sequence control circuit 300C may be configured to control the counting operation of the test counter circuit 100C based on the count address signal ADD_C and the target address value. That is, the sequence control circuit 300C may be configured to change the count address signal ADD_C output from the test counter circuit 100C to the change address value. The sequence control circuit 300C may include an address comparison circuit 310C and a count control circuit 320C.

[0076] The address comparison circuit 310C may be configured to compare the target address value input as the first input information INF_1 with the counting address signal ADD_C to generate a selection control signal CTR_S. When the target address value is the same as the counting address signal ADD_C, the address comparison circuit 310C may generate the selection control signal CTR_S having a value of a preset logic level.

[0077] The count control circuit 320C may be configured to reflect the change address value input as the second input information INF_2 to the counting operation of the test count circuit 100C based on the selection control signal CTR_S. The count control circuit 320C may generate a count control signal CTR_C corresponding to the change address value based on the selection control signal CTR_S. The test count circuit 100C may generate a count address signal ADD_C in which the change address value is reflected based on the count control signal CTR_C. The test information storage circuit 200C may output a test control value V_OR (i.e., a final test control value V_CTR) based on the count address signal ADD_C.

[0078] The driving circuit 400C may be configured to perform a preset test operation based on the final test control value V_CTR. That is, the driving circuit 400C may be configured to perform a test operation based on the third output sequence and the fourth output sequence for the final test control value V_CTR.

[0079] Figure 8 is shown with Figure 7 Hereinafter, for convenience of description, it is assumed that the target address value input as the first input information INF_1 is "003" and the change address value input as the second input information INF_2 is "007".

[0080] Reference Figure 7 and Figure 8During the test operation, the test counting circuit 100C may generate a counting address signal ADD_C that counts sequentially. Then, the test information storage circuit 200B may output a test control value V_OR as a final test control value V_CTR based on the counting address signal ADD_C.

[0081] The sequence control circuit 300C may receive a target address value "003" as the first input information INF_1, and may receive a change address value "007" as the second input information INF_2. The address comparison circuit 310C may be configured to compare the target address value with the count address signal ADD_C to generate a selection control signal CTR_S. When the count address signal ADD_C is the same as the target address value "003", the address comparison circuit 310C may output the selection control signal CTR_S by activating the selection control signal CTR_S to a preset logic level. Then, the count control circuit 320C may generate a count control signal CTR_C for the test count circuit 100C based on the selection control signal CTR_S to count the change address value to the value "007". Therefore, the test count circuit 100C may output the change address value "007" based on the count control signal CTR_C. Furthermore, the test information storage circuit 200C may output the test control value V_OR “DAT_7” corresponding to the count address signal ADD_C “007” as the final test control value V_CTR.

[0082] That is, when the counting address signal ADD_C is "001", "002" and "003", the test information storage circuit 200C can output the test control values ​​V_OR "DAT_1", "DAT_2" and "DAT_3" as the final test control value V_CTR, respectively. In addition, when the counting address signal ADD_C output from the test counting circuit 100C is "003", the counting control circuit 320C can change the counting address signal ADD_C to the change address value "007" to output the change address value "007". Therefore, the test information storage circuit 200C can output the test control value V_OR "DAT_7" corresponding to the counting address signal ADD_C "007" as the final test control value V_CTR. After outputting the change address value "007", the test counting circuit 100C can output the counting address signal ADD_C "008" following the change address value "007". Therefore, the test information storage circuit 200C may output the test control value V_OR “DAT_8” corresponding to the count address signal ADD_C “008” as the final test control value V_CTR.

[0083] In summary, the integrated circuit can set the third output sequence for the final test control value V_CTR based on the target address value input as the first input information INF_1 and based on the change address value input as the second input information INF_2. Here, the final test control value V_CTR "DAT_7" corresponding to the change address value "007" can be output based on the third output sequence. Then, the final test control value V_CTR "DAT_8" corresponding to the count address signal ADD_C "008" following the change address value "007" can be output. Therefore, the driving circuit 400C can perform a test operation for the third output sequence based on the final test control value V_CTR.

[0084] Fig. 9 is shown with Figure 7 Hereinafter, for convenience of description, it is assumed that the target address value input as the first input information INF_1 is "003" and the change address value input as the second input information INF_2 is "007".

[0085] Similar to Figure 8 implementation method, according to Fig. 9 In the embodiment of the present invention, the final test control value V_CTR "DAT_7" corresponding to the count address signal ADD_C "007" can be output. After outputting the changed address value "007", the test counting circuit 100C can output the originally established count address signal ADD_C "004". Therefore, the test information storage circuit 200C can output the test control value V_OR "DAT_4" corresponding to the count address signal ADD_C "004" as the final test control value V_CTR.

[0086] In summary, the integrated circuit can set the fourth output sequence for the final test control value V_CTR based on the target address value input as the first input information INF_1 and based on the change address value input as the second input information INF_2. Here, the final test control value V_CTR "DAT_7" corresponding to the change address value "007" can be output based on the fourth output sequence. Then, the final test control value V_CTR "DAT_4" corresponding to the originally established count address signal ADD_C "004" can be output. Therefore, the driving circuit 400C can perform a test operation for the fourth output sequence based on the final test control value V_CTR.

[0087] Fig.10 It is shown Figure 2 Flowchart of the test operation method of the integrated circuit shown in FIG.

[0088] Reference Figure 2 and Fig.10 , the test operation method of the integrated circuit may include a step of inputting change information for an output sequence (S1100), a step of generating a final test control value (S1200), and a step of performing a test operation (S1300).

[0089] The step of inputting the change information for the output sequence (S1100) may be a step of inputting the change information for the output sequence of the final test control value V_CTR for the test operation. Here, the change information may refer to the first input information INF_1 and the second input information INF_2. Figures 3 to 9 The integrated circuit may include a first output sequence to a fourth output sequence, and the change information for each of the first output sequence to the fourth output sequence may be different from each other.

[0090] The step of generating the final test control value (S1200) may be a step of generating the final test control value V_CTR based on the output sequence, such as Figure 2 As shown, the output sequence is set based on the sequence control signal CTR_MD. Figure 4 , Figure 6 , Figure 8 and Fig. 9 As described above, the integrated circuit can set the final test control value V_CTR in different ways based on the first to fourth output sequences.

[0091] As reference Figure 4 As described above, the integrated circuit can output the target control value ("DAT_TM") instead of the test control value V_OR as the final test control value V_CTR based on the count address signal ADD_C and the target address value. That is, the final test control value V_CTR corresponding to the first output sequence can be output. Figure 6 As described above, the integrated circuit can control the enabling operation and disabling operation of the counting operation based on the counting address signal ADD_C and the target address value, and can output the target control value ("DAT_TM") by inserting the target control value ("DAT_TM") into the final test control value V_CTR. That is, the final test control value V_CTR corresponding to the second output sequence can be output. As shown in FIG. Figure 8 As described above, the integrated circuit can change the counting address signal ADD_C to the changed address value, and can output the final test control value V_CTR, and then output the final test control value V_CTR corresponding to the counting address signal ADD_C following the changed address value. That is, the final test control value V_CTR corresponding to the third output sequence can be output. As shown in FIG. Fig. 9As described above, the integrated circuit can change the counting address signal ADD_C to a changed address value, and can output a final test control value V_CTR, and then output a final test control value V_CTR corresponding to the originally established counting address signal ADD_C. That is, the final test control value V_CTR corresponding to the fourth output sequence can be output.

[0092] In summary, the integrated circuit can generate the final test control value V_CTR corresponding to the first output sequence to the fourth output sequence. Therefore, various test sequences can be provided during the test operation, and therefore, an increased degree of freedom can be provided for the test operation. In addition, it can be more accurately determined whether the integrated circuit is well designed based on the test results according to the various test sequences.

[0093] Although specific embodiments have been described above, it will be appreciated by those skilled in the art that the described embodiments are only examples. Therefore, the integrated circuit and the test operation method thereof should not be limited based on the described embodiments. On the contrary, when combined with the above description and the accompanying drawings, the integrated circuit and the test operation method thereof described herein should only be limited according to the attached claims.

[0094] CROSS-REFERENCE TO RELATED APPLICATIONS

[0095] This application claims the benefit of Korean Application No. 10-2020-0107398 filed on August 25, 2020, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as if fully set forth.

Claims

1. An integrated circuit, comprising: a test counting circuit configured to generate a counting address signal; a test information storage circuit configured to store a test control value corresponding to a preset test operation and output the test control value based on the count address signal; a sequence control circuit configured to change an output sequence of the test control value based on a sequence control signal, and configured to output a final test control value based on the test control value or a target control value; as well as A driving circuit is configured to perform the preset test operation based on the final test control value.

2. The integrated circuit according to claim 1, wherein: When the output sequence is a first output sequence based on the sequence control signal, the sequence control circuit is configured to output the target control value, instead of the test control value, as the final test control value based on the count address signal and the target address value.

3. The integrated circuit according to claim 2, wherein: The sequence control circuit comprises: an address comparison circuit configured to compare the target address value with the count address signal to generate a selection control signal; and A selective output circuit is configured to selectively output the target control value or the test control value based on the selection control signal.

4. The integrated circuit according to claim 1, wherein: When the output sequence is a second output sequence based on the sequence control signal, the sequence control circuit is configured to control the counting operation of the test counting circuit based on the counting address signal and the target address value, and is configured to insert the target control value into the final test control value to output the target control value.

5. The integrated circuit according to claim 4, wherein: The sequence control circuit comprises: an address comparison circuit configured to compare the target address value with the count address signal to generate a selection control signal; a count control circuit configured to control the count operation of the test count circuit based on the selection control signal; and A selective output circuit is configured to selectively output the target control value or the test control value based on a count control signal generated from the count control circuit.

6. The integrated circuit according to claim 5, wherein: The count control circuit is configured to disable the count operation of the test count circuit based on the selection control signal, and is configured to enable the count operation of the test count circuit after the target control value is output.

7. The integrated circuit according to claim 5, wherein: The test count circuit is configured to hold a previous count address signal based on a count control operation of the count control circuit, and Wherein, the selective output circuit is configured to output the target control value corresponding to the previous counting address signal.

8. The integrated circuit of claim 1, wherein: When the output sequence is one of a third output sequence and a fourth output sequence based on the sequence control signal, the sequence control circuit is configured to change the count address signal to a change address value based on a target address value and the count address signal output from the test count circuit.

9. The integrated circuit of claim 8, wherein: The sequence control circuit comprises: an address comparison circuit configured to compare the target address value with the count address signal to generate a selection control signal; and A count control circuit is configured to reflect the changed address value in a count operation of the test count circuit based on the selection control signal.

10. The integrated circuit of claim 9, wherein: The test count circuit is configured to output the changed address value based on a count control signal generated from the count control circuit.

11. The integrated circuit of claim 10, wherein: When the output sequence is the third output sequence, after outputting the changed address value, the test count circuit is configured to generate the count address signal subsequent to the changed address value.

12. The integrated circuit of claim 10, wherein: When the output sequence is the fourth output sequence, after outputting the changed address value, the test count circuit is configured to generate the count address signal that is originally set.

13. A test operation method for an integrated circuit, the test operation method comprising the following steps: inputting change information for an output sequence of final test control values ​​for a test operation; generating the final test control value from a test control value or a target control value corresponding to a preset test operation based on the output sequence; as well as A test is performed on the integrated circuit based on the final test control value.

14. The test operation method according to claim 13, further comprising the following steps before or after the step of inputting the change information: generating a count address signal by a count operation; and The test control value is output based on the count address signal.

15. The test operation method according to claim 14, wherein: The step of generating the final test control value includes the step of outputting the target control value, instead of the test control value, as the final test control value based on the count address signal and the target address value.

16. The test operation method according to claim 14, wherein: The step of generating the final test control value includes the steps of controlling an enabling operation and a disabling operation of the counting operation based on the counting address signal and a target address value, and inserting the target control value into the final test control value to output the target control value.

17. The test operation method according to claim 14, wherein: The step of generating the final test control value includes the steps of changing the count address signal to a change address value, outputting the final test control value, and then outputting the final test control value corresponding to the count address signal following the change address value.

18. The test operation method according to claim 14, wherein: The step of generating the final test control value includes the steps of changing the count address signal to a change address value, outputting the final test control value, and then outputting the final test control value corresponding to the count address signal originally set up.

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