True random number generator

Abstract

The application provides a true random number generating device, comprising a ring oscillator and a flip-flop connected with the ring oscillator; wherein the ring oscillator comprises at least three inverting logic units arranged in a ring, the inverting logic unit comprises a PMOS and a ReRAM unit connected with the drain of the PMOS; the gate of the PMOS serves as the input end of the inverting logic unit, the drain of the PMOS serves as the output end of the inverting logic unit, and the output end and the input end of each inverting logic unit are sequentially connected; the output end of any inverting logic unit of the ring oscillator is connected with the input end of the flip-flop, and the true random number is output through the output end of the flip-flop. By using the above application, the area ratio of the device can be reduced, and the generation quality of the true random number can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of oscillation circuit architecture, more particularly, to a generating device for generating true random numbers. BACKGROUND

[0002] Random numbers refer to a set of completely irregular number series, that is, a random event without causality is required, and random numbers can further include true random numbers and pseudo random numbers, and the main difference between the two is probability and probability, and the higher the uncertainty of random numbers, the higher the quality.

[0003] At present, a commonly used design true random number generator scheme is to use the output result of a sampling ring oscillator (RO), which can obtain stable true random numbers, but the quality of random numbers generated by a single RO ring is poor, so multiple RO rings are usually used to compress the output, and the output after compression can improve the quality of the output random numbers to a certain extent, but the required device area and power consumption are linearly increased.

[0004] It can be seen that the existing true random number generation scheme requires large area and power consumption overhead, and the overall cost is high, and it is not easy to obtain higher quality true random numbers. SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide a true random number generating device to solve the problems of large area and power consumption overhead, limited quality and the like in the existing true random number generation scheme.

[0006] The true random number generating device provided by the present application comprises a ring oscillator and a flip-flop connected with the ring oscillator, wherein the ring oscillator comprises at least three inverting logic units arranged in a ring, the inverting logic unit comprises a PMOS and a ReRAM unit connected with the drain of the PMOS, the gate of the PMOS serves as the input end of the inverting logic unit, the drain of the PMOS serves as the output end of the inverting logic unit, and the output end and the input end of each inverting logic unit are connected in sequence, the output end of any inverting logic unit of the ring oscillator is connected with the input end of the flip-flop, and the true random number is output through the output end of the flip-flop.

[0007] In addition, the output end of the ring oscillator outputs a random digital signal, the digital signal and the sampling clock signal are input into the flip-flop at the same time, and the true random number corresponding to the sampling clock signal is output through the flip-flop.

[0008] In addition, the source of the PMOS of all inverting logic units is connected with a common power supply end, and the gate of the PMOS and the ReRAM unit of all inverting logic units are connected with a common ground end.

[0009] Further, the optional technical solution is that the direction logic unit further comprises an NMOS arranged at the ReRAM unit; wherein the drain of the NMOS is connected with the corresponding ReRAM unit, and the gate of the NMOS is connected with the gate of the PMOS; the ReRAM unit and the NMOS constitute a 1T1R unit.

[0010] Further, the optional technical solution is that the source of the PMOS of all the reverse logic units is connected with a common power supply end, and the source of the NMOS of all the reverse logic units is connected with a common ground end.

[0011] Further, the optional technical solution is that the number of the reverse logic units arranged at the ring oscillator is odd.

[0012] Further, the optional technical solution is that the flip-flop comprises an RS flip-flop, a JK flip-flop, a D flip-flop and a T flip-flop.

[0013] Further, the optional technical solution is that the ring oscillator is arranged with at least one.

[0014] Further, the optional technical solution is that the number of the flip-flops arranged corresponds to the number of the strips of the ring oscillator.

[0015] Further, the optional technical solution is that when the ring oscillator is arranged with at least two strips, the output of the flip-flop corresponding to the ring oscillator is compressed through the compression unit, and the compressed true random number is obtained.

[0016] By using the above true random number generating device, the ring oscillator comprises a plurality of two reverse logic units, the reverse logic unit further comprises a PMOS and a ReRAM unit connected with the drain of the PMOS, by arranging the ReRAM unit, the jitter generated in the oscillation process of the ring oscillator can be increased, and the uncertainty of the sampled digital signal is also increased, the output end of any reverse logic unit is connected with the input end of the flip-flop, the quality of the true random number output by the flip-flop can be improved, and the overall area occupied by the device is small, and the cost is low.

[0017] To achieve the above and related objects, one or more aspects of the application include the features to be described in detail later. The following description and drawings detail certain exemplary aspects of the application. However, these aspects indicate only some of the various ways in which the principles of the application can be used. In addition, the application is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF DRAWINGS

[0018] Other objects and results of the present application will become more apparent and easy to understand by referring to the following description in conjunction with the accompanying drawings. In the drawings:

[0019] Figure 1 Circuit schematic diagram of a true random number generating device according to an embodiment of the present application;

[0020] Figure 2 Circuit schematic diagram of a true random number generating device according to another embodiment of the present application;

[0021] Figure 3 Circuit schematic diagram of a true random number generating device according to another embodiment of the present application; Figure 2 Circuit schematic diagram of a reverse logic unit.

[0022] The same reference numbers in all the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0023] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It is apparent, however, that the embodiments can be practiced without

[0024] To solve the problems of large area ratio and low quality of true random number in existing true random number generation schemes, a true random number generating device is proposed, which includes a ring oscillator and a flip-flop connected with the ring oscillator, and a reverse logic unit including a PMOS and a ReRAM unit connected with the drain of the PMOS. The jitter generated by the reverse logic unit based on the ReRAM unit during the oscillation process is greatly increased compared with the general RO ring, the uncertainty of the sampled digital signal is also greatly increased, and finally the quality of the output random number is also increased.

[0025] To describe the structure of the true random number generating device of the present application in detail, specific embodiments of the present application will be described in detail below in combination with the drawings.

[0026] Figure 1 A circuit structure of a true random number generating device according to an embodiment of the present application is shown.

[0027] As Figure 1As shown, the true random number generation device of the embodiment of the present application comprises a ring oscillator and a flip-flop connected with the ring oscillator; wherein the ring oscillator comprises at least three inverting logic units arranged in a ring shape, each inverting logic unit further comprises a PMOS and a ReRAM unit connected with the drain (D) of the PMOS, for each inverting logic unit, the gate (G) of the PMOS can be used as the input end of the inverting logic unit, and the drain of the PMOS is used as the output end of the inverting logic unit; in the same ring oscillator, the output ends and the input ends of the inverting logic units are sequentially connected in the first place, the output end of any inverting logic unit of the ring oscillator is connected with the input end of the flip-flop, and the true random number is output through the output end of the flip-flop. The circuit architecture can improve the jitter of the inverting logic unit and improve the quality of the true random number. At the same time, since the resistance wire area of the ReRAM is very small, only nanometer level, the overall area of the random number generation device can be reduced, which is conducive to the miniaturization trend of the product.

[0028] Specifically, since the plurality of inverting logic units are connected in the first place, the output end of any inverting logic unit can be used as the output end of the entire ring oscillator, and a random digital signal can be output through the ring oscillator. The digital signal and the preset sampling clock signal are input into the flip-flop at the same time, and finally the corresponding true random number is output through the flip-flop.

[0029] In this embodiment, the source (S) of the PMOS of all inverting logic units is connected with a common power supply end Vdd, and the gate of the PMOS and the ReRAM unit of all inverting logic units are connected with a common ground end Vss. It can be seen that one end of the ReRAM unit is connected with the gate of the PMOS, and the other end is connected with Vss. The working voltage of the ring oscillator is provided by Vdd and Vss. Since the resistance wire area of the ReRAM is very small and can reach nanometer level, it can reach hundreds of megaohms in the high resistance state, which can reduce the overall area overhead while increasing the instability of the ring oscillator.

[0030] It should be noted that the structure of the above inverting logic unit can also be deformed, Figure 2 The circuit structure of the true random number generation device according to another embodiment of the present application is shown.

[0031] As Figure 2As shown, in this embodiment, the reverse logic unit can also include an NMOS arranged at the ReRAM unit; wherein the drain of the NMOS is connected with the corresponding ReRAM unit, and the gate of the NMOS is connected with the gate of the PMOS; the ReRAM unit and the NMOS together constitute a 1T1R (1 transistor and 1 resistor) unit, and one 1T1R unit can be equivalent to an inverter with a large resistance in series by only adding one PMOS, and the structure can significantly improve the quality of the output true random number based on the inverter of the ReRAM ring oscillator without increasing the area.

[0032] In this specific embodiment, the source of the PMOS of all reverse logic units is connected with a common power supply end Vdd, the source of the NMOS of all reverse logic units is connected with a common ground end Vss, and the gate of the PMOS and the gate of the NMOS are connected to serve as the input end of the reverse logic unit, and the output end is still the drain of the NMOS.

[0033] Wherein, the current flows through the PMOS, and then flows through the ReRAM unit in the high resistance state, and then flows through the NMOS and is grounded, at this time, the propagation waveform of the current is similar to that of directly grounding the ReRAM unit, and the thermal noise caused by the ReRAM unit can cause large jitter of the oscillation output of the structure, and the quality of the corresponding true random number is also improved.

[0034] It should be noted that in the true random number generation device of the present application, the number of reverse logic units of the ring oscillator is odd, and the ring oscillator is formed by using an odd number of reverse logic units, so that high-quality true random numbers can be generated even in the case of a single ring oscillator. It can be seen that the ring oscillator can also be arranged in multiple, and the flip-flop is arranged corresponding to the ring oscillator, that is, the number of flip-flops is consistent with the number of ring oscillators arranged, when the ring oscillator is arranged with at least two, the output of the flip-flop corresponding to the ring oscillator is compressed by the compression unit, and the compressed true random number is obtained.

[0035] In one specific embodiment of the present application, the flip-flop can be selected from various types of flip-flops such as RS flip-flop, JK flip-flop, D flip-flop or T flip-flop, and is not limited to the specific flip-flop structure shown in the drawings.

[0036] According to the true random number generation device provided by the present application, the PMOS and the ReRAM unit connected with the drain of the PMOS are used to form the reverse logic unit, and then the ring oscillator is formed based on the reverse logic unit, which can increase the jitter generated by the ring oscillator during oscillation, and the uncertainty of the sampled digital signal also increases, thereby improving the quality of the true random number output by the flip-flop, and the overall device occupies a small area and has low cost.

[0037] The true random number generating device according to the present application is described above with reference to the drawings by way of example. However, it will be understood by those skilled in the art that various modifications can be made to the above-described true random number generating device according to the present application without departing from the scope of the present application. Therefore, the scope of the present application should be determined by the contents of the appended claims.

Claims

1. A true random number generating device, characterized by comprising: The ring oscillator comprises at least three inverting logic units arranged in a ring, and a flip-flop connected to the ring oscillator. The ring oscillator comprises at least three inverting logic units arranged in a ring, and a flip-flop connected to the ring oscillator. The gate of the NMOS is connected to the gate of the PMOS, and the ReRAM unit and the NMOS constitute a 1T1R unit. The gate of the PMOS serves as the input terminal of the inverting logic unit, the drain of the PMOS serves as the output terminal of the inverting logic unit, and the output terminal and the input terminal of each inverting logic unit are sequentially connected. The source of the PMOS of all inverting logic units is connected to a common power terminal, and the source of the NMOS of all inverting logic units is connected to a common ground terminal. The output terminal of any inverting logic unit of the ring oscillator is connected to the input terminal of the flip-flop, and a true random number is output through the output terminal of the flip-flop.

2. The true random number generation device of claim 1, wherein The output terminal of the ring oscillator outputs a random digital signal. The digital signal and a sampling clock signal are input to the flip-flop at the same time, and a true random number corresponding to the sampling clock signal is output through the flip-flop.

3. The true random number generation device of claim 1, wherein The number of inverting logic units of the ring oscillator is an odd number.

4. The true random number generation device of claim 1, wherein The flip-flop comprises an RS flip-flop, a JK flip-flop, a D flip-flop, and a T flip-flop.

5. The true random number generation device of claim 1, wherein The ring oscillator is provided with at least one.

6. The true random number generation device of claim 5, wherein The number of flip-flops corresponds to the number of rings of the ring oscillator.

7. The true random number generation device of claim 6, wherein When the ring oscillator is provided with at least two rings, the outputs of the flip-flops corresponding to the ring oscillator are compressed through a compression unit, and a compressed true random number is obtained.

Images