Data processing apparatus, method, neural network processor, chip and electronic device

Abstract

The embodiment of the application discloses a data processing device, method, neural network processor, chip and electronic equipment. The device comprises a control unit and M-level logic units, wherein M is an integer greater than 1, the M-level logic units are stacked, a first-level logic unit in the M-level logic units is connected with the control unit, and each level logic unit is internally provided with a through channel to realize a transmission channel for data transmission from the M-level logic unit to the control unit. In this way, the M-level logic unit transmits data to the control unit through the transmission channel formed in the logic unit, without the need to set an extra channel region, thereby reducing the size of the processing device, and the length of the transmission channel is less than the length of the existing channel, which can reduce the path delay and reduce the power consumption of the data processing device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic information, and particularly relates to a data processing device and method, a neural network processor, a chip and an electronic device. BACKGROUND

[0002] In recent years, the application range of artificial intelligence (AI) technology is increasingly expanding. With Kirin970 applying a neural-network processing unit (NPU) in the field of smart phones, the importance of the NPU gradually approaches that of a central processing unit (CPU) and a graphics processing unit (GPU), forming the three cores in the field of smart phones. However, the existing NPU is provided with a large number of wiring channels, which occupies too much NPU area, resulting in an excessively large NPU size. SUMMARY

[0003] To solve the above technical problems, the embodiments of the present application expect to provide a data processing device and method, a neural network processor, a chip and an electronic device.

[0004] The technical scheme of the present application is implemented as follows:

[0005] In a first aspect, a data processing device is provided, which comprises:

[0006] a control unit; and

[0007] M-level logic units, M being an integer greater than 1, the M-level logic units being stacked, and a first-level logic unit in the M-level logic units being connected to the control unit.

[0008] Each of the M-level logic units is internally provided with a through channel to realize a transmission channel for data transmission from the Mth-level logic unit to the control unit.

[0009] In a second aspect, a method for configuring a data processing device is provided, which comprises:

[0010] providing a control unit;

[0011] stacking M-level logic units, M being an integer greater than 1, and connecting a first-level logic unit in the M-level logic units to the control unit; and

[0012] providing a through channel in each of the M-level logic units to realize a transmission channel for data transmission from the Mth-level logic unit to the control unit.

[0013] In a third aspect, a neural network processor is provided, comprising the data processing apparatus of any of the preceding aspects.

[0014] In a fourth aspect, a chip is provided, comprising the neural network processor of any of the preceding aspects.

[0015] In a fifth aspect, an electronic device is provided, comprising the chip of any of the preceding aspects.

[0016] The embodiments of the present application also provide a data processing apparatus, method, neural network processor, chip and electronic device. The data processing apparatus comprises: a control unit; and M-level logic units, M being an integer greater than 1, the M-level logic units being arranged in layers, and a first-level logic unit in the M-level logic units being connected to the control unit; wherein each logic unit is internally provided with a through channel to implement a transmission channel for data transmission from the Mth-level logic unit to the control unit. In this way, the Mth-level logic unit transmits data to the control unit through the transmission channel formed in the logic unit, without the need to set an extra channel region, thereby reducing the size of the processing apparatus, and the length of the transmission channel is less than the length of the existing channel, which can reduce the path delay and reduce the power consumption of the data processing apparatus. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A process diagram for matrix multiplication and addition calculation of a convolutional neural network;

[0018] Figure 2 A physical implementation model diagram of a data processing apparatus;

[0019] Figure 3 A physical implementation model diagram of another data processing apparatus;

[0020] Figure 4 A first structure diagram of a data processing apparatus in the embodiments of the present application;

[0021] Figure 5 A component structure diagram of a logic unit in the embodiments of the present application;

[0022] Figure 6 A second structure diagram of a data processing apparatus in the embodiments of the present application;

[0023] Figure 7 A third structure diagram of a data processing apparatus in the embodiments of the present application;

[0024] Figure 8 A flow diagram of a method for configuring a data processing apparatus provided in the embodiments of the present application;

[0025] Figure 9 This is a schematic diagram of the composition structure of the neural network processor in an embodiment of this application;

[0026] Figure 10 This is a schematic diagram of the chip's structural composition in an embodiment of this application;

[0027] Figure 11 This is a schematic diagram of the composition structure of the electronic device in the embodiments of this application. Detailed Implementation

[0028] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0029] It should be noted that in this application example, terms such as "first" and "second" are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0030] Furthermore, the technical solutions described in the embodiments of this application can be combined arbitrarily without conflict.

[0031] With the increasing application of Neural Network Processing Units (NPUs) in smart terminals, the importance of NPUs is also growing. The core operation of NPUs is convolution, which is essentially matrix multiplication and addition. By accelerating matrix multiplication and addition operations through hardware, the goal of accelerating deep learning training and inference can be achieved.

[0032] Figure 1 This is a schematic diagram illustrating the matrix multiplication and addition process of a convolutional neural network, as shown below. Figure 1 As shown, since matrix multiplication and addition have the characteristics of 3D computation, a 3D hardware computing unit 101 can be designed to perform multiplication and addition on the elements of the matrix in parallel. Figure 1 The three-dimensional hardware computing unit 101 is a 4×4×4 three-dimensional computing unit. The 4×4×4 three-dimensional computing unit is used to perform multiplication and addition operations on two 4×4 matrices (matrix A and matrix B). The process of multiplication and addition of matrices by the 4×4×4 three-dimensional computing unit is as follows:

[0033] First, the 4×4×4 three-dimensional computing unit can compute the product of each element in parallel. Each unit in the 4×4×4 three-dimensional computing unit obtains the elements in matrix A and matrix B respectively, and performs multiplication calculations on the obtained elements.

[0034] Among them, matrix matrix

[0035] For example, in a 4×4×4 three-dimensional computing cell, the four cells in the 0th column of the front surface calculate A respectively. 11 ×B 11 A 21 ×B 11 A 31 ×B 11 A 41 ×B 11 The last four cells of the last column of the front surface in a 4×4×4 three-dimensional computational cell calculate A respectively. 11 ×B 14 A 21 ×B 14 A 31 ×B 14 A 41 ×B 14 The four cells in the 0th column of the upper surface of the 4×4×4 three-dimensional computational cell respectively calculate A. 14 ×B 41 A 13 ×B 31 A 12 ×B 21 A 11 ×B 11 The last four cells of the top surface in a 4×4×4 three-dimensional computational cell calculate A respectively. 14 ×B 44 A 13 ×B 34 A 12 ×B 24 A 11 ×B 14 .

[0036] Secondly, the 64 products calculated are summed along a certain dimension, for example, from the front surface to the back surface, to obtain matrix A×B, which contains 16 elements.

[0037] Finally, the resulting matrix A×B is summed with matrix C to obtain matrix A×B+C. The matrix summation can be performed in parallel.

[0038] The above describes the multiplication operation of two 4×4 matrices. However, when matrices A' and B' are both 8×8 matrices, the multiplication operation can be performed using... Figure 1 The three-dimensional hardware computing unit 101 performs two 8×8 matrix operations as follows:

[0039] Among them, matrix matrix Wherein, A'11, A'12, A'21, A'22, B'11, B'12, B'21, B'22 are all 4x4 matrices. Thus, the result of A'x B' can be obtained as: In this way, the multiplication operation of two 8x8 matrices is converted into the multiplication operation of two 4x4 matrices.

[0040] In the embodiment of the present application, the three-dimensional hardware computing unit 101 is a 4x4x4 three-dimensional computing unit, which can perform parallel multiplication operation on matrices with dimensions being multiples of 4. In other embodiments, the three-dimensional hardware computing unit 101 can be a 3x3x3 three-dimensional computing unit, which can perform parallel multiplication operation on matrices with dimensions being multiples of 3, or a 2x2x2 three-dimensional computing unit or a 5x5x5 three-dimensional computing unit, etc. The embodiment of the present application does not limit this.

[0041] In the case where the three-dimensional hardware computing unit 101 is a 4x4x4 three-dimensional computing unit, if the dimension of the matrix to be calculated is not a multiple of 4, a number of rows of 0 and a number of columns of 0 can be added to the matrix to obtain a matrix with a dimension being a multiple of 4.

[0042] In some embodiments, in order to increase the computing capacity of the NPU, the number of units in the three-dimensional hardware computing unit 101 can be increased. For example, the computing capacity of an 8x4x4 three-dimensional computing unit is one time higher than that of a 4x4x4 three-dimensional computing unit, and the computing capacity of a 16x4x4 three-dimensional computing unit is one time higher than that of an 8x4x4 three-dimensional computing unit.

[0043] Figure 2 A physical implementation model of a data processing apparatus is shown in FIG. 1. As shown in FIG. 1, the data processing apparatus can include a control module and M-level processing modules. M can be an integer greater than or equal to 3, for example, M can be 4, 8 or 16, etc. Figure 2 Each of the M-level processing modules includes a computing unit, a logic unit and a memory unit. The computing unit and the logic unit of each processing unit can communicate with each other, and the logic unit and the memory unit of each processing unit can communicate with each other. Figure 2

[0044] ​Each level of logic unit is used to acquire the calculation result data of each level and pass the calculation result data to the next level of logic unit. In this way, the last level of logic unit can acquire the M calculation result data calculated by the M level calculation units respectively. The last level of logic unit can combine the M calculation result data to obtain feature map data and transmit the feature map data to the control module so that the control module can perform corresponding control according to the feature map data.

[0045] In the embodiments of this application, the operation of any logic unit to acquire data, process data, receive data, or forward data can be accomplished by a component within that logic unit.

[0046] In the embodiments of this application, the computing unit in the level 0 processing module can be called the level 0 computing unit, the logic unit in the level 0 processing module can be called the level 0 logic unit, the storage unit in the level 0 processing module can be called the level 0 storage unit, and so on. In the embodiments of this application, they will not be listed one by one.

[0047] In some embodiments, the value of M can be related to the computing power of the NPU. For example, when the number of units in the three-dimensional hardware computing unit is 4, the value of M is 4; when the number of units in the three-dimensional hardware computing unit is 8, the value of M is 8; and when the number of units in the three-dimensional hardware computing unit is 16, the value of M is 16. Of course, the value of M can be other than that, and there are no restrictions here.

[0048] Figure 3 This is a schematic diagram of the physical implementation model of another data processing device, such as... Figure 3 As shown, to enable the last-level logic unit to send the obtained feature map data back to the control module, the engineers discovered that the (M-1)th-level logic unit needs to send data with a larger bit width to the control module. Therefore, a routing channel is reserved between the M-level logic unit and the M-level computation unit. All logic units can be multiplexed, allowing the (M-1)th-level logic unit to send feature map data to the control module through this routing channel. In this approach, the M-level logic units are identically laid out, with each unit receiving data from the top and outputting data from the bottom.

[0049] However, with this approach, technicians found that the data processing device was large in size because wiring channels needed to be reserved between the M-level logic units and the M-level computing units, as well as at the bottom of the logic units.

[0050] To address the issue of large size in data processing devices, this application proposes a data processing device. Figure 4 This is a first structural schematic diagram of the data processing device in an embodiment of this application, as shown below. Figure 4 As shown, the data processing device 400 includes: a control unit 401; and

[0051] M-stage logic units 402, M being an integer greater than 1, the M-stage logic units being stacked, a first-stage logic unit of the M-stage logic units being connected to the control unit;

[0052] Each-stage logic unit is internally provided with a through channel to form a transmission channel for data transmission from the M-stage logic unit to the control unit.

[0053] The control unit 401 is connected to a first-stage logic unit of the M-stage logic units 402, the first-stage logic unit to the M-stage logic unit being stacked in a first direction;

[0054] Each-stage logic unit is internally provided with a through channel (as shown by the shaded part in each-stage logic unit in FIG. 4), Figure 4 the through channels of adjacent-stage logic units being stacked in the first direction to form a transmission channel (the entire shaded part in FIG. 4) between the control unit and the M-stage logic unit; Figure 4

[0055] The transmission channel is used to realize data interaction between the M-stage logic unit and the control unit 401.

[0056] In some embodiments, the first-stage logic unit to the M-1-stage logic unit are respectively provided with feedthrough ports on a side facing the control unit and a side facing away from the control unit, the M-stage logic unit is provided with a feedthrough port on the side facing the control unit, and the through channels form the transmission channel via the plurality of feedthrough ports.

[0057] Here, the transmission channel can be understood as a feedthrough path. The feedthrough path can be realized by providing a feedthrough port (i.e., a feedthrough port), the feedthrough port including a feedthrough port on a side facing the control unit and a feedthrough port on a side facing away from the control unit, the two feedthrough ports being directly connected to form a through channel. The through channel is provided in each-stage logic unit, and the through channels are connected to form a transmission channel, thereby placing the wiring in the channel into the logic unit. In this way, no wiring channel needs to be reserved between the M-stage logic unit and the M-stage computing unit and at the bottom of the logic unit, thereby being able to reduce the size of the data processing device.

[0058] ​Specifically, the first connection end of the control unit is provided with an input port, the first connection end (i.e. the end facing the control unit) of the logic unit is provided with a first feed-through port of the through channel, and the second connection end (i.e. the end facing away from the control unit) is provided with a second feed-through port of the through channel; the input port of the control unit is connected with the first feed-through port of the first-level logic unit, and the first feed-through port of the former logic unit in the adjacent logic unit is connected with the second feed-through port of the latter logic unit.

[0059] Here, the first connection end of the control unit is the end surface connected with the first logic unit, and the first connection end can be any outer end surface of the control unit, and the first connection end and the second connection end of the logic unit are the end surfaces connected with the former level and the latter level, which can be two outer end surfaces in the same direction but facing opposite directions, such as Figure 4 The first connection end is the top end and the second connection end is the bottom end, or the first connection end is the left end and the second connection end is the right end. It can also be two outer end surfaces in the same direction of the logic unit, or two outer end surfaces in different directions of the logic unit.

[0060] In some embodiments, a transmission wire is arranged in the transmission channel, and the transmission wire connects the M-level logic unit and the control unit to realize data transmission from the M-level logic unit to the control unit.

[0061] That is, the transmission channel serves as a channel for the last-level logic unit to transmit data to the control unit, and the transmission wire arranged in the transmission channel is used to realize data transmission. By arranging the transmission channel inside the logic unit, there is no need to arrange a channel region outside the logic unit, thereby saving the occupied area of the channel region and reducing the size of the data processing device.

[0062] It should be noted that the control unit 401 is configured to obtain to-be-processed data and transmit the to-be-processed data to the M-level logic unit 402.

[0063] The M-level logic unit 402 is configured to perform data processing on the to-be-processed data level by level to obtain a data processing result corresponding to the to-be-processed data, and the last-level logic unit transmits the data processing result back to the control unit 401 by using the transmission wire.

[0064] Figure 5 The following is a schematic diagram of the composition structure of the logic unit in the embodiments of the present application, as shown in Figure 5 The logic unit includes a through channel 51, a first feed-through port 511 (also referred to as an output port) of the through channel 51 is located at the first connection end (i.e. the top end in Figure 5 the second feed-through port 512 (also referred to as an input port) is located at the second connection end (Figure 5 The first connecting end of the logic unit is connected with the second connecting end (i.e. the bottom end) of the logic unit of the upper level, and the second connecting end of the logic unit is connected with the first connecting end (i.e. the top end) of the logic unit of the lower level.

[0065] In some embodiments, the feed-through port of the Mth logic unit can be set in the same way as the feed-through ports of the logic units of other levels, and the feed-through port on the side opposite to the control unit of the Mth logic unit can be set in the first closed state. That is, since there is no logic unit behind the Mth logic unit, only the transmission wire needs to be connected with the data output port of the Mth logic unit, and the Mth logic unit directly outputs the data processing result of the Mth level from the data output port, without using the feed-through port on the side opposite to the control unit, so the feed-through port is specially processed.

[0066] Here, the first closed state can be understood as an unoccupied state, or the feed-through port is blocked. In actual application, the setting of the closed state can be realized by software control or by changing the hardware result. That is, in actual application, the last logic unit needs to be processed separately and specially, and all the logic units of the previous levels are completely consistent and can be standardized and processed in batches.

[0067] In some embodiments, the feed-through port of the Mth logic unit can be set in the same way as the feed-through ports of the logic units of other levels, and the feed-through port on the side opposite to the control unit of the Mth logic unit can be set in the first closed state. That is, since there is no logic unit behind the Mth logic unit, only the transmission wire needs to be connected with the data output port of the Mth logic unit, and the Mth logic unit directly outputs the data processing result of the Mth level from the data output port, without using the feed-through port on the side opposite to the control unit, so the feed-through port is specially processed.

[0068] It should be noted that the transmission channel of the present application is arranged inside the logic unit, so that the path of the Mth logic unit to the control unit is the shortest, and the transmission path is shortened compared with the prior art (). Figure 3 That is, the present application reduces the length of the transmission signal line, and since the longer the signal line is, the more buffers (relay units) are needed to drive, which greatly increases the number of buffers and further increases the power consumption of the data processing device. The present application reduces the length of the transmission signal line, which can reduce the number of buffers and reduce the power consumption of the data processing device.

[0069] In some embodiments, the first connecting end of the control unit is further provided with an output port, and the first connecting end of the logic unit is further provided with a third port, and the second connecting end is further provided with a fourth port.

[0070] The output port of the control unit is connected with the third port of the first logic unit, and the fourth port of the logic unit of the previous level is connected with the third port of the logic unit of the next level.

[0071] Specifically, the third port is configured to receive data to be processed corresponding to the current stage; and the fourth port is configured to transmit a data processing result to a next stage.

[0072] In some embodiments, the third port and the fourth port of the Mth stage logic unit can be configured in the same way as the logic units of other stages, and the fourth port of the Mth stage logic unit can be configured in the second closed state. That is, since there is no logic unit behind the Mth stage logic unit, the Mth stage logic unit does not need to transmit the data processing result to the next stage, but directly transmits the data processing result of the Mth stage to the control unit, so the fourth port of the Mth stage logic unit is specially processed.

[0073] Here, the second closed state can be understood as a state of not occupying or blocking the fourth port. In actual application, the closed state can be realized by software control or by changing the hardware result. That is, in actual application, the last stage logic unit needs to be specially processed separately, and all the logic units of the previous stages are completely consistent and can be standardized and processed in batches.

[0074] In some embodiments, the third port and the fourth port of the Mth stage logic unit can be configured in the same way as the logic units of other stages, and the fourth port of the Mth stage logic unit can be configured in the second closed state. That is, since there is no logic unit behind the Mth stage logic unit, the Mth stage logic unit does not need to transmit the data processing result to the next stage, but directly transmits the data processing result of the Mth stage to the control unit, so the fourth port of the Mth stage logic unit is specially processed.

[0075] It should be noted that the third port of the first stage logic unit obtains the data to be processed transmitted by the network control unit 401, and stores the data to be processed corresponding to the first stage logic unit to the first stage storage unit;

[0076] The first stage logic unit transmits the data to be processed to the second stage logic unit through the fourth port, the second stage logic unit stores the corresponding data to be processed to the second stage storage unit, and so on until the last stage logic unit.

[0077] Figure 6 A third structural diagram of a data processing apparatus in the embodiments of the present application is shown in FIG. 6, which includes a control unit 601 and M stage logic units 602, where M is an integer greater than 1. Figure 6

[0078] The control unit 601 is connected to the first stage logic unit among the M stage logic units 602, and the first stage logic unit to the Mth stage logic unit among the M stage logic units are arranged in a first direction.

[0079] Each stage logic unit is internally provided with a through channel, and the through channels of adjacent stage logic units are arranged in the first direction, forming a transmission channel between the control unit and the Mth stage logic unit. ​

[0080] The first connection terminal of the control unit is also provided with an output port, and the first connection terminal of each logic unit ( Figure 6 The top of the middle section also has a third port, a second connection end ( Figure 6 A fourth port is also provided at the bottom (middle and bottom);

[0081] The output port of the control unit is connected to the third port of the first-level logic unit, and the fourth port of the previous level logic unit in adjacent level logic units is connected to the third port of the next level logic unit.

[0082] It should be noted that the data received by each logic unit can include the raw data to be processed passed from the previous level and / or the data processing result from the previous level. The raw data to be processed can be understood as the data to be processed issued by the control unit. The data to be processed by each logic unit also includes the raw data to be processed passed from the previous level and / or the data processing result from the previous level. That is to say, each logic unit can process only the raw data to be processed issued by the control unit, or only the data processing result from the previous level, or both simultaneously; the data processing object can be flexibly set.

[0083] In other words, the third input port and the fourth output port can be directly connected or not connected. The logic unit uses the storage unit and the computing unit to perform logical control on the data, realizing data processing at this level and data transmission to adjacent levels.

[0084] Here, the first connection end is the top end, the second connection end is the bottom end, the top end of the logic unit includes the first feedthrough port and the third port, and the bottom end of the logic unit includes the second feedthrough port and the fourth port.

[0085] In some embodiments, the apparatus further includes an M-level computing unit and an M-level storage unit; each level of the M-level logic unit is connected to a computing unit and a storage unit respectively.

[0086] Specifically, each logic unit in the M-level logic unit is connected to a computing unit and a storage unit in the second direction.

[0087] Here, each level of computing unit, logic unit, and storage unit can form a processing module to realize the processing, storage, and transmission of data to be processed at each level.

[0088] In some embodiments, any one of the M-level computing units includes: an addition computing unit and / or a multiplication computing unit.

[0089] For the data processing unit that implements convolution processing, the M-level computation unit includes an addition computation unit and a multiplication computation unit, which perform matrix operations by multiplying and adding matrix elements.

[0090] The calculation capability of each level calculation unit is the same and / or the structural arrangement is the same. The attribute information of each level storage unit can be the same. The attribute information includes at least one of the following: size, type, storage size, data size capable of being read at one time, structure, and the like.

[0091] In some embodiments, the M-level storage unit includes one or a combination of the following: a register, a register group composed of at least two registers, a random-access memory (RAM), a read-only memory (ROM), a cache memory (CACHE), a flash memory, and a double data rate synchronous dynamic random access memory (DDR).

[0092] Specifically, the control unit is configured to acquire the to-be-processed data and transmit the to-be-processed data to the M-level logic unit.

[0093] The i-level storage unit is configured to store i-level to-be-processed data; i is a positive integer less than or equal to M.

[0094] The i-level logic unit is configured to acquire the i-level to-be-processed data from the i-level storage unit and send the i-level to-be-processed data to the i-level calculation unit.

[0095] The i-level calculation unit is configured to perform calculation processing on the i-level to-be-processed data to obtain i-level data processing results and send the i-level data processing results to the i-level logic unit.

[0096] When i is less than M, the i-level logic unit is further configured to transmit the i-level data processing results to an (i+1)-level logic unit.

[0097] When i is equal to M, the M-level logic unit is further configured to transmit the M-level data processing results to the control unit.

[0098] In some embodiments, each level calculation unit and storage unit is respectively located on two sides of the logic unit in the second direction; and the first direction and the second direction are perpendicular to each other.

[0099] That is, if the M-level logic unit is arranged in a longitudinal direction, each level logic unit, calculation unit, and storage unit is arranged in a transverse direction.

[0100] Figure 7 FIG. 4 is a fourth structural schematic diagram of a data processing apparatus in an embodiment of the present application, as shown in FIG. 4, the data processing apparatus includes a control unit, an M-level logic unit, an M-level calculation unit, and an M-level storage unit. Figure 7As shown, the data processing apparatus can include a control module (also referred to as a control unit) and M-level processing modules, where M can be an integer greater than 1, for example, Figure 7 The value of M can be 4, 8, or 16, etc. Each of the M-level processing modules includes a calculation unit, a logic unit, and a storage unit. The calculation unit and the logic unit of each level processing unit can communicate with each other, and the logic unit and the storage unit of each level processing unit can communicate with each other. A through channel is internally provided in each logic unit. The through channel includes an input port and an output port, and the input port and the output port are directly connected. The through channel is provided in each logic unit, so that the originally placed wiring in the channel is placed in the logic unit. In this way, no wiring channel needs to be reserved between the M-level logic unit and the M-level calculation unit and at the bottom of the logic unit, thereby reducing the size of the data processing apparatus. Figure 2

[0101] However, the skilled person finds that as the multiplication matrix increases from 4x4x4 to 8x8x8 or 16x16x16 or even more, that is, as the number of levels of the processing module increases from 4 levels to 8 levels or 16 levels, the timing of the last level logic unit sending feature map data to the control module is difficult to meet, for example, the transmission of data cannot be completed within one clock cycle or at least two clock cycles.

[0102] With the above technical solution, the M-level logic unit transmits data to the control unit through the transmission channel formed inside the logic unit, without the need to set up an extra channel area, thereby reducing the size of the processing apparatus, and the length of the transmission channel is less than the length of the existing channel, which can reduce the path delay and reduce the power consumption of the data processing apparatus.

[0103] Based on the same inventive concept as the above data processing apparatus, the embodiments of the present application also provide a method for configuring a data processing apparatus, Figure 8 A flowchart of a method for configuring a data processing apparatus provided by the embodiments of the present application is shown in FIG. 8, which includes the following steps: Figure 8

[0104] Step 801: setting a control unit;

[0105] Step 802: stacking M-level logic units, where M is an integer greater than 1, and connecting the first-level logic unit in the M-level logic units to the control unit; and

[0106] Step 803: providing a through channel inside each logic unit to implement a transmission channel for data transmission from the M-level logic unit to the control unit.

[0107] ​​In some embodiments, the method comprises: arranging feedthrough ports on the side of the first to M-1 logic units facing the control unit and on the side of the first to M-1 logic units facing away from the control unit, and arranging a feedthrough port on the side of the Mth logic unit facing the control unit, so that the through channel forms the transmission channel via the plurality of feedthrough ports.

[0108] Here, the transmission channel can be understood as a FeedThrough path. The FeedThrough path can be realized by arranging FeedThrough ports, i.e., feedthrough ports, including a feedthrough port on the side of the control unit and a feedthrough port on the side of the control unit facing away from the control unit, and the two feedthrough ports are directly connected to form a through channel. The through channel is arranged in each logic unit, and the through channels are connected to form a transmission channel, thereby placing the wiring in the channel into the logic unit. In this way, no wiring channel needs to be reserved between the M-level logic unit and the M-level computing unit and at the bottom of the logic unit, thereby reducing the size of the data processing device.

[0109] Specifically, the first connection end of the control unit is provided with an input port, the first connection end (i.e., the end facing the control unit) of the logic unit is provided with a first feedthrough port of the through channel, and the second connection end (i.e., the end facing away from the control unit) is provided with a second feedthrough port of the through channel; the input port of the control unit is connected to the first feedthrough port of the first logic unit, and the first feedthrough port of the previous logic unit in the adjacent logic unit is connected to the second feedthrough port of the next logic unit.

[0110] Further, the method further comprises: arranging a transmission wiring in the transmission channel, the transmission wiring connecting the Mth logic unit and the control unit to realize data transmission from the Mth logic unit to the control unit.

[0111] That is, the transmission channel serves as a channel for the last logic unit to transmit data to the control unit, and the transmission channel includes a transmission wiring arranged therein for data transmission. By arranging the transmission channel inside the logic unit, there is no need to arrange a channel region outside the logic unit, thereby saving the occupied area of the channel region, and further reducing the size of the data processing device.

[0112] In some embodiments, the device further comprises M-level computing units and M-level storage units, and each of the M-level logic units is connected to one computing unit and one storage unit, respectively.

[0113] In some embodiments, any of the M-level computing units comprises an addition computing unit and / or a multiplication computing unit.

[0114] In some embodiments, the M-level storage unit comprises one or a combination of the following: a register, a register group composed of at least two registers, a random access memory (RAM), a read-only memory (ROM), a cache memory (CACHE), a flash memory, and a double data rate synchronous dynamic random access memory (DDR).

[0115] In some embodiments, the control unit is configured to acquire the to-be-processed data and transmit the to-be-processed data to the M-level logic unit.

[0116] The i-level storage unit is configured to store i-level to-be-processed data.

[0117] The i-level logic unit is configured to acquire the i-level to-be-processed data from the i-level storage unit and send the i-level to-be-processed data to the i-level calculation unit.

[0118] The i-level calculation unit is configured to perform calculation processing on the i-level to-be-processed data to obtain an i-level data processing result and send the i-level data processing result to the i-level logic unit.

[0119] When i is less than M, the i-level logic unit is further configured to transmit the i-level data processing result to an (i+1)-level logic unit.

[0120] When i is equal to M, the M-level logic unit is further configured to transmit the M-level data processing result to the control unit.

[0121] With the above technical solution, the M-level logic unit transmits data to the control unit through the transmission channel formed inside the logic unit, without the need to set an extra channel area, thereby reducing the size of the processing device, and the length of the transmission channel is less than the length of the existing channel, which can reduce the path delay and reduce the power consumption of the data processing device.

[0122] Based on the same inventive concept as the above data processing device, the embodiments of the present application also provide a neural network processor, Figure 9 FIG. 1 is a schematic diagram of the structure of a neural network processor according to an embodiment of the present application. The neural network processor 900 comprises any one of the data processing devices 901 according to the embodiments of the present application.

[0123] The processor can implement matrix multiplication and / or addition operations. Preferably, the processor can be a neural network processing unit (NPU) for implementing convolution operations in a neural network algorithm. The structure of the data processing device provided by the present application can reduce the occupation of channel area, shorten the transmission channel, and reduce the number of buffers, which is conducive to timing convergence and effectively reduces the power consumption of the NPU.

[0124] In practical applications, the processor can also be at least one of an application specific integrated circuit (ASIC), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, and a microprocessor. It can be understood that, for different devices, the electronic device used to implement the functions of the processor can also be other devices, and the embodiments of the present application are not limited in this regard.

[0125] The embodiments of the present application also provide a chip, Figure 10 The chip 1000 includes a neural network processor 1010 for implementing any of the neural network processors according to the embodiments of the present application.

[0126] Optionally, as shown in the figure, the chip 1000 can also include a memory 1020. The neural network processor 1010 can call and run a computer program from the memory 1020 to implement the method according to the embodiments of the present application. Figure 10

[0127] The memory 1020 can be a separate device independent of the neural network processor 1010, or can be integrated in the neural network processor 1010.

[0128] The memory can be a volatile memory (such as a random access memory (RAM)), or a non-volatile memory (such as a read-only memory (ROM), a flash memory, a hard disk (HDD) or a solid state disk (SSD)), or a combination of the above types of memories, and provides instructions and data to the processor.

[0129] Optionally, the chip 1000 can also include an input interface 1030. The neural network processor 1010 can control the input interface 1030 to communicate with other devices or chips, and specifically, can obtain information or data sent by other devices or chips.

[0130] ​Optionally, the chip 1000 can further include an output interface 1040. The neural network processor 1010 can control the output interface 1040 to communicate with other devices or chips, and specifically, can output information or data to other devices or chips.

[0131] Optionally, the chip can be applied to the electronic device in the embodiments of the present application, and the chip can implement the corresponding processes realized by the electronic device in the various methods of the embodiments of the present application. For brevity, details are not repeated here.

[0132] It should be understood that the chip mentioned in the embodiments of the present application can also be referred to as a system chip, a system chip, a chip system or a system on chip, etc.

[0133] The embodiments of the present application also provide an electronic device, Figure 11 The electronic device 1100 includes any one of the chips 1110 in the embodiments of the present application.

[0134] The electronic device can include a server, a mobile phone, a tablet computer, a notebook computer, a palm computer, a personal digital assistant, a portable media player, a smart speaker, a navigation device, a display device, a smart watch, a virtual reality (VR) device, an augmented reality (AR) device, a pedometer, a digital TV, a desktop computer, a device in intelligent driving, a wireless fidelity (Wi-Fi) access point, an evolved base station, a base station of next-generation communication, such as a base station of 5G, a small station, a micro station or a transmission reception point (TRP), and can also be a relay station, an access point or a vehicle-mounted device, etc. any device capable of convolution processing on data.

[0135] It should be understood that the terms used in the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein means and includes any or all possible combinations of one or more associated listed items. In the present application, the expressions "have", "may have", "include" and "contain", or "may include" and "may contain" can be used herein to indicate the presence of a corresponding feature (for example, elements such as numerical values, functions, operations or components), but do not exclude the presence of additional features.

[0136] It should be understood that, although the terms first, second, third, etc. can be adopted in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other, and do not necessarily be used to describe a particular order or sequence. For example, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information, without departing from the scope of the present application.

[0137] The technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0138] In several embodiments provided in the present application, it should be understood that the disclosed methods, devices and equipment can be implemented by other ways. The above described embodiments are only illustrative, for example, the division of units is only a logical function division, and actual implementation can have another division way, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each component part shown or discussed can be through some interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0139] The units described above as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place or distributed on multiple network units; part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0140] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0141] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application.

Claims

1. A data processing apparatus, characterized by, The device comprises: a control unit; and M-stage logic units, M being an integer greater than 1, the M-stage logic units being arranged in a stack along a first direction, a first-stage logic unit of the M-stage logic units being connected to the control unit; M-stage computing units and M-stage storage units, each of the M-stage logic units being connected to one computing unit and one storage unit in a second direction, the first direction and the second direction being perpendicular to each other; wherein each of the M-stage logic units is internally provided with a through channel to form a transmission channel for data transmission from the M-stage logic unit to the control unit; the first connection end of the control unit is provided with an input port, the side of each of the first-stage logic unit to the M-1-stage logic unit facing the control unit and the side of each of the first-stage logic unit to the M-1-stage logic unit facing away from the control unit are respectively provided with a feedthrough port, the side of the M-stage logic unit facing the control unit is provided with a feedthrough port, and the through channel forms the transmission channel via the plurality of feedthrough ports; the first connection end of the control unit is provided with an output port, the first connection end of each of the logic units is further provided with a third port, and the second connection end is further provided with a fourth port; the output port of the control unit is connected to the third port of the first-stage logic unit, and the fourth port of a preceding-stage logic unit in adjacent logic units is connected to the third port of a following-stage logic unit.

2. The apparatus of claim 1, wherein, The transmission channel is arranged with a transmission wire, and the transmission wire connects the M-stage logic unit and the control unit to realize data transmission from the M-stage logic unit to the control unit.

3. The apparatus of claim 1, wherein, Any of the M-stage computing units comprises an addition computing unit and / or a multiplication computing unit.

4. The apparatus of claim 3, wherein, The M-stage storage units comprise one or a combination of the following: a register, a register group composed of at least two registers, a random access memory (RAM), a read-only memory (ROM), a cache memory (CACHE), a flash memory, and a double data rate (DDR).

5. The device according to claim 1, wherein the control unit is configured to obtain to-be-processed data and transmit the to-be-processed data to the M-stage logic units; an i-stage storage unit is configured to store i-stage to-be-processed data; an i-stage logic unit is configured to obtain the i-stage to-be-processed data from the i-stage storage unit and send the i-stage to-be-processed data to an i-stage computing unit; the i-stage computing unit is configured to perform calculation processing on the i-stage to-be-processed data to obtain an i-stage data processing result and send the i-stage data processing result to the i-stage logic unit; when i is less than M, the i-stage logic unit is further configured to transmit the i-stage data processing result to an i+1-stage logic unit; when i is equal to M, the M-stage logic unit is further configured to transmit an M-stage data processing result to the control unit.

6. A method of configuring a data processing apparatus, characterized by, The method comprises: providing a control unit; arranging M-stage logic units in a stack along a first direction, M being an integer greater than 1, and connecting a first-stage logic unit of the M-stage logic units to the control unit; and providing a through channel in each of the M-stage logic units to form a transmission channel for data transmission from the M-stage logic unit to the control unit. The M-level computing units and the M-level storage units are connected with one computing unit and one storage unit respectively in each of the M-level logic units in a second direction, the first direction and the second direction being perpendicular to each other; The first connection end of the control unit is provided with an input port, the side of the first-level logic unit to the (M-1)-level logic unit facing the control unit and the side of the first-level logic unit to the (M-1)-level logic unit facing away from the control unit are respectively provided with feed-through ports, the M-level logic unit is provided with a feed-through port on the side facing the control unit, and the through channel forms the transmission channel via the plurality of feed-through ports; The first connection end of the control unit is provided with an output port, the first connection end of each of the logic units is further provided with a third port, and the second connection end is further provided with a fourth port; the output port of the control unit is connected with the third port of the first-level logic unit, and the fourth port of the front-level logic unit in the adjacent logic units is connected with the third port of the rear-level logic unit.

7. The method of claim 6, wherein, The method further comprises: Arranging a transmission wire in the transmission channel, the transmission wire connecting the M-level logic unit and the control unit to realize data transmission from the M-level logic unit to the control unit.

8. A neural network processor, comprising: The processor comprises the data processing device of any one of claims 1-5.

9. A chip, characterized by The chip comprises the neural network processor of claim 8.

10. An electronic device, comprising: The electronic device comprises the chip of claim 9. The processor comprises the data processing device of any one of claims 1-5. The chip comprises the neural network processor of claim 8. The electronic device comprises the chip of claim 9.

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