Incentive Control Method Based on the Sequence Feedback Mechanism of UVM

Abstract

The present invention discloses an excitation control method based on a sequence feedback mechanism of UVM, which comprises the following steps: creating interfaces and transactions required by a device under test, where the transactions correspond to the interfaces; creating an excitation sequence and creating a first feedback task within the excitation sequence; creating a driver and creating a second feedback task in the driver; the excitation sequence generates transaction-level excitations corresponding to the transactions, and the transaction-level excitations are driven by the driver into signal-level excitations and transmitted to the device under test; the second feedback task obtains feedback information of the device under test; the first feedback task obtains feedback information from the driver and feeds it back to the excitation sequence; the excitation sequence constrains, controls, and adjusts the transaction-level excitations according to the feedback information. The present invention uses sequence feedback to obtain the state of the DUT to control the generation and sending of excitations, providing another technical route and thinking option for the generation and control of excitations. In chip verification work, the excitation control method can be flexibly selected according to the situation of the DUT and the working habits of the verification personnel.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and particularly relates to an excitation control method based on a sequence feedback mechanism of UVM. Background Art

[0002] Generally, in order to verify an RTL (Register Transfer Level) design (i.e., DUT, Device Under Test), it is necessary to apply corresponding input excitation to it, and then monitor and compare whether the output result meets the expectations. Generally, it is desired to decide what kind of excitation to apply next according to the internal state of the DUT. Therefore, in the sequence, it is necessary to know the internal state of the DUT, so that the next sequence_item can be generated according to the internal state of the DUT within the sequence.

[0003] In the prior art, there are the following two implementation methods, as shown in Figure 1 and Figure 2 .

[0004] Figure 1 The first implementation method is to encapsulate the internal state signals in the DUT into an interface, and then pass them to the verification environment through config_db. At this time, since the sequence excitation is mounted on the corresponding sequencer, the virtual interface handle of the internal state signals of the DUT can be obtained in the sequence. The sequence can monitor the values on the interface, so that finally, according to the internal state signals of the DUT, it can be decided what kind of excitation to apply to the DUT next within the sequence.

[0005] Figure 2 The second implementation method is to usually write a corresponding reference model in order to verify the correctness of the arithmetic function of the DUT, and then apply the same excitation to both to compare the output results of the two. If they are consistent, it is considered that the function meets the expectations; otherwise, there may be a problem somewhere and further debugging is required to determine. Simply put, there should also be a corresponding internal state signal in the reference model as in the DUT. Then, directly pass the handle of the reference model to the sequencer. Since the sequence is mounted on the sequencer, the sequence can obtain the handle of the reference model. Finally, according to the internal state signals of the DUT corresponding to the reference model, it can be decided what kind of excitation to apply to the DUT next. Summary of the Invention

[0006] According to an embodiment of the present invention, there is provided an excitation control method based on a sequence feedback mechanism of UVM, comprising the following steps:

[0007] Create the interfaces and transactions required by the device under test, and the transactions correspond to the interfaces;

[0008] Create an excitation sequence and create a first feedback task within the excitation sequence;

[0009] Create a driver and create a second feedback task in the driver;

[0010] The excitation sequence generates transaction-level excitations corresponding to the transactions, and the transaction-level excitations are driven by the driver into signal-level excitations and transmitted to the device under test;

[0011] The second feedback task obtains the feedback information of the device under test;

[0012] The first feedback task obtains the feedback information from the driver and feeds it back to the excitation sequence;

[0013] The excitation sequence controls and adjusts the transaction-level excitations according to the feedback information.

[0014] Furthermore, the interface includes an input interface and an output interface, and clock control blocks are respectively included in the input interface and the output interface.

[0015] Furthermore, the transaction-level excitations are constrained, controlled, and adjusted by random or directly setting values.

[0016] Furthermore, an id field is added to each transaction-level excitation to identify the transaction-level excitation and the excitation sequence corresponding to the transaction-level excitation.

[0017] Furthermore, when the driver drives the transaction-level excitations to the device under test, the feedback information is returned through the second feedback task.

[0018] According to the excitation control method based on the sequence feedback mechanism of UVM in the embodiment of the present invention, the state of the DUT is obtained by using the sequence feedback to control the generation and sending of the excitation, providing another technical route and idea selection for the generation and control of the excitation. In the actual chip verification work, different excitation control methods can be flexibly selected according to the situation of the DUT and the working habits of the verification personnel.

[0019] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further explanation of the claimed technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the principle of one of the methods for generating sequence excitations in the prior art;

[0021] Figure 2 Schematic diagram of the principle of the second method for generating sequence excitation in the prior art;

[0022] Figure 3 Flowchart of the excitation control method based on the UVM sequence feedback mechanism according to an embodiment of the present invention;

[0023] Figure 4 Block diagram of the abstracted DUT example with the precise matching module as an example;

[0024] Figure 5 For Figure 4 The verification platform corresponding to the DUT in;

[0025] Figure 6 For Figure 5 Schematic diagram of the port connection between the sequencer and the driver in; Detailed implementation manners

[0026] Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings to further elaborate the present invention.

[0027] First, in combination with Figures 3 - 6 Describe the excitation control method based on the UVM sequence feedback mechanism according to an embodiment of the present invention, which is used in chip verification and has a wide range of application scenarios.

[0028] As Figure 3 shown, the excitation control method based on the UVM sequence feedback mechanism according to an embodiment of the present invention has the following steps:

[0029] In S1, as Figure 3 shown, create the interfaces and transactions required by the device under test, and the transactions correspond to the interfaces; in this embodiment, the interfaces include an input interface and an output interface, and the input interface and the output interface respectively include a clock control block.

[0030] In S2, as Figure 3 shown, create an excitation sequence and create a first feedback task within the excitation sequence.

[0031] In S3, as Figure 3 shown, create a driver and create a second feedback task in the driver.

[0032] In S4, as Figure 3 shown, the excitation sequence generates transaction-level excitations corresponding to the transactions, and the transaction-level excitations are driven by the driver into signal-level excitations and transmitted to the device under test.

[0033] In S5, as Figure 3As shown, the second feedback task obtains feedback information of the device under test; in this embodiment, while the driver drives the transaction level stimulus to the device under test, the feedback information can be returned through the second feedback task.

[0034] In S6, Figure 3 As shown, the first feedback task obtains feedback information from the driver and feeds it back to the excitation sequence.

[0035] In S7, Figure 3 As shown, the stimulus sequence controls and adjusts the transaction-level stimulus according to the feedback information constraints. In this embodiment, the transaction-level stimulus is constrained and adjusted by randomly or directly setting a value. Further, in this embodiment, an id field is added to each transaction-level stimulus to identify the transaction-level stimulus and the stimulus sequence corresponding to the transaction-level stimulus.

[0036] Based on the excitation control method based on the sequence feedback mechanism of UVM according to the embodiment of the present invention, it can be known that in the UVM (Universal Verification Methodology) verification platform, the Sequence mechanism provides a one-way data transmission mechanism of sequence→sequencer→driver. However, in a complex verification platform, the sequence needs to determine the sequence_item (i.e., event excitation) to be sent next based on the feedback from the driver. In other words, the sequence needs to get a feedback from the driver, and the sequence mechanism happens to provide support for this feedback, which allows the driver to return a response to the sequence. Then, the present invention utilizes the sequence mechanism of UVM, and the internal state information of the DUT is returned to the sequence by the driver through the response, so that the generation and control of the input excitation can be realized.

[0037] The present invention takes the precise matching module as an example of DUT for illustrative explanation. The precise matching module is used to complete the mapping between key (addr) and pointer (data). The module is often instantiated and used in Ethernet switching chips. For the sake of example, the precise matching module can be simply understood as a typical database with basic write and read (delete) functions.

[0038] Therefore, after abstracting the DUT, its block diagram is as follows Figure 4 As shown, the verification platform corresponding to the DUT is built as follows Figure 5As shown. Its input ports are: clk: clock signal; rst_n: low-level reset signal; vld: data valid signal; cmd: 1'b0: write request signal; 1'b1: read (delete) request signal; addr: address signal; data: data signal. Its output ports are: vld: data valid signal; rslt: signal indicating whether the request is executed successfully or not; 1'b0, execution fails; 1'b1, execution succeeds; data: data corresponding to the previous read (delete) request.

[0039] The communication mechanism between the component sequencer and driver based on UVM, the port connection is as Figure 6 shown. The data port members of the uvm_driver class are: uvm_seq_item_pull_port #(REQ, RSP) seq_item_port, used to connect and communicate with the corresponding export port of the sequencer; the data port members of the uvm_sequencer class are: uvm_seq_item_pull_imp #(REQ, RSP, this_type), seq_item_export, used to connect and communicate with the corresponding port of the driver.

[0040] The communication between the sequencer and the driver is completed through the TLM bidirectional ports seq_item_port and seq_item_export. Through these two ports, the communication transmission of the stimulus request data REQ sequence_item and the feedback data RSP sequence_item can be completed. Thus, the sequencer sends the sequence_item generated in the sequence to the driver, and then the driver returns a response to the sequencer after processing, and finally the sequence receives it through the get_response() method. That is to say, the sequence will obtain the internal state information of the DUT through this received response.

[0041] In this embodiment, two points need to be noted:

[0042] (1) The sequencer and the driver are connected and communicate one-to-one. It is not possible to connect multiple sequencers to one driver, nor can one sequencer be connected to multiple drivers. This is why generally an agent will connect and encapsulate one sequencer and one driver (and of course a monitor) to complete the encapsulation of a communication protocol.

[0043] (2) The communication ports between the sequencer and the driver, in addition to the seq_item_export and seq_item_port ports used here, there are also some ports, which are represented by dotted lines in Figure 6 and will not be used here, so they will not be introduced in this patent.

[0044] The specific construction process is as follows:

[0045] Create the interface and transaction required for the above DUT. In this embodiment, the input and output ports of the DUT are divided into two interfaces for writing, and a clocking block is added to them for driving and monitoring, and the transactions corresponding to the two interfaces are created.

[0046] Create the stimulus sequence and its internal feedback task. The workflow for stimulus transmission and waiting for feedback is: (1) Call start_item() to start the transmission. Start the transmission of the sequence_item. (2) Constrain and control the sequence_item and make adjustments. Generally, by random or directly setting values. (3) Call finish_item() to wait for completion. After the finish_item() call, it will block until the driver completes its transmission. (4) Call get_response() to wait for feedback. get_response() will block until valid feedback information is obtained from the sequencer.

[0047] After creating the excitation sequence, the test excitation for the DUT is generated and controlled as follows (for illustrative purposes only): (1) First, send a write request to fill the internal memory of the DUT until a write failure occurs, that is, the memory has been filled. At this time, monitor whether the total number of data written is consistent with the expectation, so as to help determine whether the memory and the write request operation are successfully executed. (2) Then, send a read request to read out (delete) the previously written data until a read (delete) failure occurs, that is, the memory has been emptied. At this time, monitor whether the total number of data written is consistent with the expectation, and monitor and compare whether the read data is the same as the previously written data, so as to help determine whether the read and write functions are correct. In this embodiment, the generation and control of the excitation are mainly completed through two tasks, write_until_full and read_until_empty, in the sequence. The output queues data_q represent the data written into the internal storage of the DUT and the data read (deleted) from the internal storage of the DUT respectively, which can be used to compare whether the two are the same. Similarly, the output num represents the number of data when the storage is full and the number of data when the storage is emptied by reading (deleting), which can also be used to compare whether the two are the same, so as to help determine the correctness of the DUT function. Among them, the two tasks, write and read, use get_response internally to obtain feedback from the driver. The response contains the data at the output end of the DUT, so that the operation result can be obtained, including whether the operation is successful and the read data.

[0048] Create a driver with feedback. By adding an id field to each sequence_item, the one-to-one correspondence problem between req requests and rsp feedback data is solved. That is, the id field is used to identify the sequence_item and the corresponding sequence. The key here is to set the set_id_info() function, which is used to copy the id field information of the req to the rsp, so as to inform the sequencer to return the response corresponding to the req to the corresponding sequence. When driving, (1) Call get_next_item() to initiate the acquisition of the sequence_item. Call the get_next_item method to obtain the sequence_item from the sequencer. (2) Drive the sequence_item to the DUT. Call the drive_item method to convert the transaction-level stimulus into a signal-level stimulus and drive it to the DUT. (3) Call put_response() or directly call item_done(rsp) to place the feedback while completing the driving of the current sequence_item. According to the need, return the response information to the sequence, and then the sequence can obtain the response information through get_response(). The sequence calls finish_item() to wait for the driver to call item_done (), and at this time, a handshake protocol like this completes the sending and driving of a sequence_item. Then loop like this until all the sequence_items generated in the sequence are transmitted and driven to the DUT.

[0049] Above, with reference to Figures 3 - 6 The above describes an excitation control method for the sequence feedback mechanism based on UVM according to an embodiment of the present invention. The state of the DUT is obtained by using sequence feedback to control the generation and sending of excitation, providing another technical route and thinking option for the generation and control of excitation. In actual chip verification work, different excitation control methods can be flexibly selected according to the situation of the DUT and the working habits of the verification personnel.

[0050] It should be noted that in this specification, the terms "including", "comprising" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "comprising..." do not exclude the existence of additional identical elements in the process, method, article or device including the elements.

[0051] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and alternatives to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. An excitation control method based on the sequence feedback mechanism of UVM, characterized in that It includes the following steps: Create the interfaces and transactions required for the device under test, where the transactions correspond to the interfaces; Create an excitation sequence and create a first feedback task within the excitation sequence; Create a driver and create a second feedback task in the driver; The excitation sequence generates transaction-level excitations corresponding to the transactions, and the transaction-level excitations are driven by the driver into signal-level excitations and transmitted to the device under test; The second feedback task obtains the feedback information of the device under test; While the driver drives the transaction-level excitations to the device under test, the feedback information is returned through the second feedback task; The first feedback task obtains the feedback information from the driver and feeds it back to the excitation sequence; The excitation sequence constrains, controls, and adjusts the transaction-level excitations according to the feedback information; 2. The excitation control method based on the UVM sequence feedback mechanism according to claim 1, wherein, The interface includes an input interface and an output interface, and each of the input interface and the output interface includes a clock control block; 3. The excitation control method based on the UVM sequence feedback mechanism according to claim 1, wherein The transaction-level excitations are constrained, controlled, and adjusted by random or directly setting values; 4. The excitation control method based on the UVM sequence feedback mechanism according to claim 1, characterized in that An id field is added to each of the transaction-level excitations to identify the transaction-level excitations and the excitation sequences corresponding to the transaction-level excitations.

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