A method for constructing a sub-circuit model of a lateral diffused metal oxide semiconductor

Abstract

The present invention discloses a method for constructing a sub-circuit model of a lateral diffused metal oxide semiconductor, comprising the following steps: Step S1, obtaining wafer acceptability test data; Step S2, constructing a sub-circuit model, selecting a mathematical model according to experience, selecting typical parameters that affect the linear threshold voltage (Vtlin) and the saturation threshold voltage (Vtsat), as well as the source-drain linear current (Idlin) and the source-drain saturation current (Idsat) for formulation, so that each typical parameter is converted into an expression containing the fork index (NF); Step S3, adjusting the secondary parameters in the expressions of the typical parameters in the sub-circuit model and other parameters in the compact model for the wafer acceptability test data, so that the sub-circuit model can fit the test data of the device varying with different fork indices.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and particularly to a method for constructing a sub-circuit model of a laterally diffused metal oxide semiconductor (LDMOS) field effect transistor. Background Art

[0002] The existing models of laterally diffused metal oxide semiconductor (LDMOS) field effect transistors have problems in accurately simulating the electrical characteristics of devices with different finger numbers for actual device electrical test data in some cases. For example, for some particularly irregular layout wirings, although the equations representing the metal wire resistance and contact hole resistance in the existing sub-circuit models contain the parameter of finger number NF, due to the form of the equations, they cannot accurately represent the metal wire resistance and contact hole resistance in some layouts, resulting in errors in calculating the overall resistance. Thus, in the final current simulation, the model cannot cover devices with different finger numbers.

[0003] The following is an example of the equation for calculating the metal wire resistance and contact hole resistance in the existing sub-circuit model. The specific values in the expression definition vary according to different processes and layouts:

[0004] +rc_nrsd = '110 / 18.7 / conum'

[0005] +conum =

[0006] 'max(1,int((wef / scale_mos - 2*0.03*1e - 6 - 0.04*1e - 6) / ((0.04 + 0.085)*1e - 6)+1))'

[0007] +rm_nrsd = '(wef / scale_mos*1e6) /

[0008] (0.0456*(wef / scale_mos*1e6)**2 + 3.5706*(wef / scale_mos*1e6) - 0.6022) / 18.7'

[0009] +wef = 'w / NF*scale_mos'

[0010] Among them, max(a,b) is the function to take the larger one of a and b, int(a) is the function to take the integer part of a, scale_mos is the MOS device size reduction factor, generally taking 1 or 0.9, and wef is the effective channel width of the MOS device.

[0011] As shown in Table 1 below, the fitting accuracy of the existing model for different finger number LDMOS field effect transistor devices is as follows:

[0012] Table 1

[0013]

[0014] In the above table, VtLIN1 is the linear threshold voltage, Vtsat1 is the saturation threshold voltage, IdLIN1 is the source-drain linear current, and Idsat1 is the source-drain saturation current.

[0015] As shown in Table 1, by comparing the fitting accuracy of the existing model for different finger number LDMOS field effect transistor devices, it can be seen that for the LDMOS field effect transistor device with finger number NF = 12, the fitting accuracy of its source-drain saturation current Idsat (Idsat1 in the table) is the worst (the width-to-length ratio W / L is 240 / 1) reaching more than 12%, and the fitting accuracy of the saturation threshold voltage Vtsat (Vtsat1 in the table) exceeds 10 mV, which is a very poor accuracy.

[0016] The solution of the existing technology generally uses post-layout simulation to extract parasitic resistances using the layout and the models of passive devices, and then combines the models of MOS devices to perform comprehensive simulation of the source-drain current to obtain simulation data. However, there is still a certain gap between the model values of the final source-drain linear current, source-drain saturation current, linear threshold voltage, saturation threshold voltage and other electrical parameters and the electrical test data of the actual test structure. Table 2 shows the fitting accuracy of the original model for different finger number LDMOS field effect transistor devices by the post-simulation method:

[0017] Table 2

[0018]

[0019] Among them, Wtotal(um) is the channel width value in micrometers (μm), NF is the finger number, WF(um) is the channel width value of a single finger in micrometers (μm), the WAT Median column is the median result of the Wafer Acceptable Test, the Mdl_post_simu column is the result of the model post-simulation, and the Mdl vs WAT column is the comparison result of the two.

[0020] As shown in Table 2, the existing model uses the post-simulation method to merge the existing MOS device models for comprehensive simulation. The accuracy of its source-drain saturation current Idsat reaches about 4% (the last column), and the fitting accuracy of the saturation threshold voltage Vtsat is still relatively large (exceeding 10 mV), and the post-simulation is time-consuming. Summary of the Invention

[0021] To overcome the deficiencies of the above-mentioned existing technologies, the purpose of the present invention is to provide a method for constructing a sub-circuit model of a laterally diffused metal oxide semiconductor to solve the problem that the existing LDMOS field effect transistor model cannot accurately simulate the electrical characteristics of devices with different finger numbers.

[0022] To achieve the above and other purposes, the present invention proposes a method for constructing a sub-circuit model of a laterally diffused metal oxide semiconductor, including the following steps:

[0023] Step S1, obtaining wafer acceptability test data;

[0024] Step S2, constructing a sub-circuit model, selecting a mathematical model according to experience, and formulating typical parameters that affect the linear threshold voltage (Vtlin), saturation threshold voltage (Vtsat), source-drain linear current (Idlin), and source-drain saturation current (Idsat), so that each typical parameter is converted into an expression containing the finger number (NF).

[0025] Step S3, adjusting the secondary parameters in the expressions of the typical parameters in the sub-circuit model and other parameters in the compact model according to the wafer acceptability test data, so that the sub-circuit model can fit the test data of the device changing with different finger numbers.

[0026] Preferably, step S3 further includes:

[0027] Step S300, adjusting the parameters in the compact model to accurately fit the device data with the smallest finger number NF and save the parameter values in the compact model;

[0028] Step S301, adjusting the secondary parameters in the expressions of the typical parameters in the sub-circuit model at different finger numbers NF to accurately fit the device data at different finger numbers NF.

[0029] Preferably, the typical parameters include the low-field mobility parameter (U0), the gate voltage-dependent parameter (UB) in the effective mobility model, and the long-channel device threshold voltage (VTH0).

[0030] Preferably, in step S2, the following mathematical model is used to formulate the typical parameters that affect the linear threshold voltage (Vtlin), the saturation threshold voltage (Vtsat), the source-drain linear current (Idlin), and the source-drain saturation current (Idsat):

[0031]

[0032] where P represents the corresponding typical parameter, P0 and P2 are secondary parameters, and P1 represents the fork exponent.

[0033] Preferably, in step S2, the expression of the threshold voltage (VTH0) of the long-channel device is:

[0034]

[0035] where VTH0_nf_0 and VTH0_wn correspond to the secondary parameters P0 and P2.

[0036] Preferably, in step S2, the expression of the low-field mobility parameter (U0) is:

[0037]

[0038] where U0_nf_0 and U0_wn correspond to the secondary parameters P0 and P2.

[0039] Preferably, in step S2, the expression of the gate voltage-dependent parameter (UB) in the effective mobility model is:

[0040]

[0041] where UB_nf_0 and UB_wn correspond to the secondary parameters P0 and P2.

[0042] Preferably, after fitting in step S3, the fitted values of the secondary parameters in the expression of the typical parameter VTH0 are determined as:

[0043] VTH0_nf_0 = -0.6245 VTH0_wn = -0.0075.

[0044] Preferably, after fitting in step S3, the fitted values of the secondary parameters in the expression of the typical parameter U0 are determined as:

[0045] U0_nf_0 = 0.0263 U0_wn = 0.035.

[0046] Preferably, the fitted values of the secondary parameters in the expression of the typical parameter UB are determined as:

[0047] UB_nf_0 = -1.0000e-018, UB_wn = 0.38.

[0048] Compared with the prior art, a method for constructing a sub-circuit model of a laterally diffused metal oxide semiconductor formulates and fits typical parameters that affect the linear threshold voltage (Vtlin), saturation threshold voltage (Vtsat), source-drain linear current (Idlin), and source-drain saturation current (Idsat), so that each typical parameter is converted into an expression with the fork index (NF) as a parameter. Then, a new sub-circuit model is constructed using the formulated and fitted typical parameters, thereby improving the fitting accuracy of the sub-circuit model by using the relationship between the formulated and fitted typical parameters and the fork index (NF), and solving the problem that the existing LDMOS field effect transistor model cannot accurately simulate the electrical characteristics of devices with different fork indices. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a flowchart of the steps of a method for constructing a sub-circuit model of a laterally diffused metal oxide semiconductor field effect transistor according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0050] The following describes the embodiments of the present invention through specific specific examples in combination with the drawings. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] Currently, the effective mobility μeff and the threshold voltage Vth are very critical electrical parameters of MOS devices, and these two parameters are required for integrated circuit model simulation. The formulas of the mobility model and the threshold voltage model in the compact model (such as the BSIM4 model) both contain parameters that affect the mobility and the threshold voltage, such as VTH0 (threshold voltage of long-channel devices), U0 (low-field mobility parameter), UB (gate voltage-dependent parameter in the effective mobility model), etc. The following are the formulas in the two BSIM4 models:

[0052]

[0053] Among them, μeff is the effective mobility, μ(T,L) is the low-field mobility parameter at the working temperature T, μ0 is the low-field mobility, which is an expression containing U0, temperature T, and channel length L. UA and UB are the gate voltage-dependent parameters in the effective mobility model, UC is the body bias-dependent parameter in the effective mobility model, UD is the Coulomb scattering-dependent parameter in the effective mobility model, V bseff is the effective source-substrate voltage parameter, E effis the effective average electric field, Vth is the threshold voltage, TOXE is the equivalent electrical gate oxide thickness parameter, V gsteff is the effective overdrive voltage parameter.

[0054]

[0055] Among them, VTH0 is the threshold voltage parameter of the long-channel device, K1 is the first-order body bias coefficient of the threshold voltage model, K2 is the second-order body bias coefficient of the threshold voltage model for the vertical doping non-uniformity effect, K1 ox is the first-order body bias coefficient of the threshold voltage model dependent on the gate oxide thickness, K2 ox is the second-order body bias coefficient of the threshold voltage model for the vertical doping non-uniformity effect dependent on the gate oxide thickness, LPE0 is the anti-short-channel effect parameter of the threshold voltage caused by pocket implantation, LPEB is the parameter of the anti-short-channel effect of the threshold voltage caused by pocket implantation affected by the body bias, is the surface potential, K3 is the narrow-channel effect parameter of the threshold voltage, K3B is the parameter of the narrow-channel effect of the threshold voltage affected by the body bias, V bseff is the effective source-substrate voltage parameter, DVT0W is the narrow-channel and short-channel effect parameter of the threshold voltage, DVT1W is the parameter dependent on the narrow-channel and short-channel effects of the threshold voltage, l C0 is the critical dimension of the drain-induced barrier lowering effect of the threshold voltage, l C1 is the critical dimension of the roll-off effect of the threshold voltage, l CW is the critical dimension of the narrow-channel effect of the threshold voltage, V bi is the built-in potential of the diode, DSUB is the channel length dependence parameter of the drain-induced barrier lowering effect of the threshold voltage, ETA0 is the source-drain voltage dependence parameter of the drain-induced barrier lowering effect of the threshold voltage, ETAB is the body bias dependence parameter of the drain-induced barrier lowering effect of the threshold voltage, n is the electron concentration, K B is the Boltzmann constant, T is the Kelvin temperature value of the operating temperature Temp, q is the electron charge, DVTP0 is the channel length dependence parameter of the drain-induced threshold voltage drift, DVTP1 is the source-drain voltage dependence parameter of the drain-induced threshold voltage drift, KT1 is the temperature dependence coefficient of the threshold voltage model, KT1L is the channel length dependence parameter of the threshold voltage dependence model, KT2 is the body bias dependence parameter of the threshold voltage temperature model, Temp is the operating temperature, TNOM is the standard temperature.

[0056] It can be seen that the low-field mobility parameter U0 and the gate voltage dependence parameter UB in the effective mobility model are parameters in the expression of the effective mobility μeff model, and the threshold voltage VTH0 of the long-channel device is a parameter in the expression of the threshold voltage Vth.

[0057] Figure 1This is the flowchart of the steps for constructing a sub - circuit model of a laterally diffused metal - oxide semiconductor according to the present invention. As Figure 1 shown, a method for constructing a sub - circuit model of a laterally diffused metal - oxide semiconductor according to the present invention includes the following steps:

[0058] Step S1, obtaining wafer acceptability test (WAT) data.

[0059] In the present invention, the wafer acceptability test (WAT) data refers to the data generated during the wafer acceptability test. Since the wafer acceptability test is an existing mature technology, the specific wafer acceptability test (WAT) data generated is also common knowledge for those skilled in the art and will not be elaborated here.

[0060] Step S2, constructing a sub - circuit model. Select a mathematical model according to experience, and select typical parameters that affect the linear threshold voltage (Vtlin), the saturation threshold voltage (Vtsat), the source - drain linear current (Idlin), and the source - drain saturation current (Idsat) for formulation, so that each typical parameter is converted into an expression containing the fork exponent (NF). The typical parameters include U0, UB, and VTH0.

[0061] In a specific embodiment of the present invention, to construct a sub - circuit model, select the following mathematical model according to experience:

[0062]

[0063] Among them, P0, P1, and P2 are secondary parameters of the above - mentioned mathematical model expression, and P0 is a linear fitting parameter.

[0064] For VTH0, U0, and UB, only need to replace P in the formula with the corresponding parameters to obtain the following expressions for each typical parameter:

[0065]

[0066] In the above formula, VTH0_nf_0 is equivalent to P0, VTH0_wn is equivalent to P2, and NF is P1

[0067]

[0068] In the above formula, U0_nf_0 is equivalent to P0, U0_wn is equivalent to P2, and NF is P1

[0069]

[0070] In the above formula, UB_nf_0 is equivalent to P0, UB_wn is equivalent to P2, and NF is P1

[0071] Step S3: For the wafer acceptability test data, adjust the secondary parameters in the expressions of the typical parameters in the sub-circuit model and other parameters in the compact model (such as the BSIM4 model) so that the sub-circuit model can fit the test data of the device varying with different finger numbers.

[0072] Specifically, step S3 further includes:

[0073] Step S300: Adjust the parameters in the compact model (such as the BSIM4 model) to accurately fit the device data with the minimum finger number NF and save the parameter values in the compact model (such as the BSIM4 model).

[0074] Step S301: Adjust the secondary parameters in the expressions of the typical parameters in the sub-circuit model at different finger numbers NF so that the device data at different finger numbers NF can be accurately fitted.

[0075] Specifically, adjust the secondary parameters in each typical parameter in the sub-circuit model at different finger numbers NF to obtain the corresponding typical parameter values. Substitute the obtained typical parameter values into formulas (1) and (2) of the compact model (such as the BSIM4 model) to obtain the effective mobility μeff and the threshold voltage Vth, and then calculate the parameters of WAT. Compare the calculation results with the test results in step S1, and perform iterative fitting according to the comparison results to finally determine the secondary parameters in the expressions of each typical parameter.

[0076] In a specific embodiment of the present invention, the fitting results of the secondary parameters in the expressions of each typical parameter are as follows:

[0077] VTH0_nf_0 = -0.6245 VTH0_wn = -0.0075;

[0078] U0_nf_0 = 0.0263 U0_wn = 0.035;

[0079] UB_nf_0 = -1.0000e-018 UB_wn = 0.38

[0080] The corresponding spice model construction syntax is as follows:

[0081] +VTH0_nf_0 = -0.6245 VTH0_wn = -0.0075

[0082] +VTH0_nf = VTH0_nf_0 / pwr(NF,VTH0_wn)

[0083] where VTH0_nf_0 is equivalent to P0, VTH0_wn is equivalent to P2, NF is P1, and pwr is the power exponent, that is, pwr(a, b) = a b

[0084] Accordingly,

[0085] +U0_nf_0 = 0.0263 U0_wn = 0.035

[0086] +U0_nf = U0_nf_0 / pwr(NF,U0_wn)

[0087] wherein, U0_nf_0 is equivalent to P0, U0_wn is equivalent to P2, and NF is P1

[0088] Accordingly,

[0089] +UB_nf_0 = -1.0000e-018 UB_wn = 0.38

[0090] +UB_nf = UB_nf_0 / pwr(NF,UB_wn)

[0091] wherein, UB_nf_0 is equivalent to P0, UB_wn is equivalent to P2, and NF is P1

[0092] Finally, the expressions of each typical parameter are as follows:

[0093]

[0094] wherein, for the secondary parameter P0, VTH0_nf_0 = -0.6245, for the secondary parameter P2, VTH0_wn = -0.0075, and for the secondary parameter P1, it is NF;

[0095]

[0096] wherein, for the secondary parameter P0, U0_nf_0 = 0.0263, for the secondary parameter P2, U0_wn = 0.035, and for the secondary parameter P1, it is NF;

[0097]

[0098] wherein, for the secondary parameter P0, UB_nf_0 = -1.0000e-018 = -1.0000×10 -18 , for the secondary parameter P2, UB_wn = 0.38, and for the secondary parameter P1, it is NF.

[0099] That is to say, VTH0, U0, and UB were originally all numerical parameters in the equation of drain current Id, but now they have become expressions with fork exponents as parameters.

[0100] The following is an exemplary Spice model library file for constructing the new sub-circuit model:

[0101] .option scale=0.9 gmin dc=1e-14 gmin=1e-14

[0102] **(Define the size reduction to 0.9 and the precision order of magnitude to 1e-14 in the simulation)

[0103] .subckt pld50g25_ckt d g s b

[0104] **(Subcircuit declaration of the model name and the four-port nodes of the MOS device)

[0105] +w=1e-6 l=1e-6 multi=1

[0106] **(Define parameters)

[0107] +NF=1 sa='saref' sb='sbref'

[0108] …

[0109] .param

[0110] +VTH0_nf_0=-0.6245 VTH0_wn=-0.0075

[0111] +VTH0_nf=VTH0_nf_0 / pwr(NF,VTH0_wn)

[0112] +U0_nf_0=0.0263 U0_wn=0.035

[0113] +U0_nf=U0_nf_0 / pwr(NF,U0_wn)

[0114] +UB_nf_0=-1.0000e-018 UB_wn=0.38

[0115] +UB_nf=UB_nf_0 / pwr(NF,UB_wn)

[0116] …

[0117] main d1 g s b pld50_ckt w=w l=lch m=multi NF=NF sa=sa sb=sb sd=sd as=as ad=ad ps=ps pd=pd nrs=nrs nrd=nrd sca=sca scb=scb scc=scc

[0118] **(Declare the BSIM4 compact model name and local parameters of the MOS device)

[0119] rd d d1 r = '(max(1e-3,(r0+r1*(tanh(r2*(v(d,s)+r3))))*wfac*dtemp_r_fac))' m ='multi*NF'

[0120] **(Define the drain resistance sub - circuit model)

[0121] .model pld50_ckt pmos

[0122] **(BSIM4 compact model name, the following is the parameter list)

[0123] +VTH0 = 'VTH0_nf' U0 = 'U0_nf' UB = 'UB_nf'

[0124] …

[0125] .ends pld50g25_ckt

[0126] **(End of the sub - circuit model)

[0127] As shown in Table 3 below, the fitting accuracy of the new sub - circuit model for different finger - number LDMOS field - effect transistor devices is as follows:

[0128] Table 3

[0129] <|> >|< VtLIN1 Vtsat1 IdLIN1 Idsat1 VtGM GMaX GmVtsat Rout W L NF Error Error Error (%) Error (%) Error Error (%) Error (%) Error (%) 20 1 2 3.56737 -5.23386 -0.228129 -0.444374 2.11878 0.662818 6.42474 7.09469 10 1 2 5.2327 -3.06984 -0.239888 -1.36856 3.00692 0.492226 6.16461 5.38525 40 1 2 4.29996 -4.60136 -0.600694 -0.455402 2.13922 0.0537847 5.74309 8.36629 20 1 4 4.98369 -3.94098 -1.78008 -2.94294 1.99595 -2.1092 4.71335 7.63943 40 1 4 3.11696 -6.00812 -1.70792 -2.08592 -0.0569529 -2.23575 4.49606 6.32735 60 1 4 2.9651 -6.26072 -1.49724 -1.46312 0.233833 -1.9732 4.6012 6.06648 80 1 4 2.34913 -6.77749 -1.31597 -0.804837 -0.606388 -1.8758 4.74529 6.54651 30 1 6 4.83622 -4.05385 -0.874388 -2.23073 1.65027 -2.2726 4.99036 7.28542 60 1 6 2.35684 -6.63795 -1.1836 -1.89668 -0.909278 -2.47616 4.45069 6.23186 90 1 6 2.09957 -6.89795 -0.51961 -0.553577 -0.600836 -2.03358 4.7221 5.75374 120 1 6 2.08069 -7.31881 -0.646438 -0.400791 -2.15976 -2.96541 4.52396 5.53295 60 1 12 7.02653 -1.82742 -0.195448 -3.28425 3.88352 -3.65541 2.83722 6.27349 120 1 12 5.49898 -3.91107 -0.0584059 -1.76341 1.23152 -4.14928 2.94152 8.31843 180 1 12 4.94235 -4.47179 0.313284 -0.686624 1.25028 -3.68958 2.70544 7.48288 240 1 12 5.22429 -4.39282 1.88055 1.3759 2.17316 -3.08176 3.28344 6.74969

[0130] Among them, Error represents the error between the simulation result of the invention model and WAT. For voltages such as VtLIN, Vtsat, and VtGM, the error unit is mV, and for linear source - drain current IdLIN, source - drain saturation current Idsat, maximum gain GMax, saturation gain GmVtsat, and output resistance Rout, it is a percentage (%). W is the device channel width in micrometers, L is the device channel length in micrometers, and NF is the finger - number.

[0131] As shown in Table 3, for the LDMOS field - effect transistor with NF = 12, the fitting accuracy of the new model's drain saturation current Idast (Idsat1 in the table) is the worst, only reaching 3.28%, which is a significant improvement compared with 12% of the existing technology and 4% of the post - simulation. For different finger - number LDMOS field - effect transistor devices, in most cases, it is less than 3%. The fitting accuracy of the saturation threshold voltage Vtsat (Vtsat1 in the table) is less than 7mV in most cases, and the worst is only 7.32mV. Compared with the existing technology (more than 10mV) and the post - simulation (more than 13mV), the present invention can be said to be very accurate.

[0132] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the protection of the present invention shall be as set forth in the claims.

Claims

1. A method for constructing a sub - circuit model of a laterally diffused metal - oxide semiconductor, which includes the following steps: Step S1, obtaining wafer acceptability test data; Step S2, constructing a sub - circuit model. Select a mathematical model according to experience, select typical parameters that affect the linear threshold voltage Vtlin, the saturation threshold voltage Vtsat, the source - drain linear current Idlin, and the source - drain saturation current Idsat for formulation, so that each typical parameter is converted into an expression containing the finger - exponent NF; the typical parameters include the low - field mobility parameter U0, the gate - voltage - dependent parameter UB in the effective mobility model, and the long - channel device threshold voltage VTH0; Step S3, adjusting the secondary parameters in the expressions of the typical parameters in the sub - circuit model and other parameters in the compact model for the wafer acceptability test data, so that the sub - circuit model can fit the test data of the device varying with different finger - exponents; Among them, In step S2, the following mathematical model is used to formulate the typical parameters that affect the linear threshold voltage Vtlin, the saturation threshold voltage Vtsat, the source - drain linear current Idlin, and the source - drain saturation current Idsat: Where P represents the corresponding typical parameter, P0 and P2 are secondary parameters, and P1 represents the finger - exponent.

2. The method for constructing a sub-circuit model of a lateral diffused metal oxide semiconductor according to claim 1, wherein Step S3 further includes: Step S300, adjusting the parameters in the compact model to accurately fit the device data with the smallest finger - exponent NF and save the parameter values in the compact model; Step S301, adjusting the secondary parameters in the expressions of each typical parameter in the sub - circuit model at different finger - exponents NF to accurately fit the device data at different finger - exponents NF.

3. The method for constructing a sub-circuit model of a lateral diffusion metal oxide semiconductor according to claim 2, wherein: In step S2, the expression of the long - channel device threshold voltage VTH0 is: Where VTH0_nf_0 and VTH0_wn correspond to the secondary parameters P0 and P2.

4. The method for constructing a sub-circuit model of a lateral diffusion metal oxide semiconductor according to claim 2, wherein: In step S2, the expression of the low - field mobility parameter U0 is: Where U0_nf_0 and U0_wn correspond to the secondary parameters P0 and P2.

5. The method for constructing a sub-circuit model of a lateral diffusion metal oxide semiconductor according to claim 2, characterized in that: In step S2, the expression of the gate - voltage - dependent parameter UB in the effective mobility model is: Where UB_nf_0 and UB_wn correspond to the secondary parameters P0 and P2.

6. The method for constructing a sub-circuit model of a lateral diffusion metal oxide semiconductor according to claim 2, characterized in that, After fitting in step S3, the fitted values of the secondary parameters in the expression of the typical parameter VTH0 are determined as: VTH0_nf_0 = - 0.6245 VTH0_wn = - 0.0075.

7. The method for constructing a sub-circuit model of a lateral diffusion metal oxide semiconductor according to claim 2, characterized in that, After fitting in step S3, the fitted values of the secondary parameters in the expression of the typical parameter U0 are determined as: U0_nf_0 = 0.0263 U0_wn = 0.

035.

8. The method for constructing a sub-circuit model of a lateral diffusion metal oxide semiconductor according to claim 2, wherein The fitted values of the secondary parameters in the expression of the typical parameter UB are determined as: UB_nf_0 = - 1.0000e - 018 UB_wn = 0.38.

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