Simulation method, storage medium and simulation device

Abstract

Provided are a simulation method, a storage medium, and a simulation device that achieve excellent accuracy even in a case of a low frequency. A C-V characteristic model using an interface between a semiconductor and an insulator includes a plurality of discrete interface states that trap and emit electrons in accordance with a change in voltage applied to a metal, the C-V characteristic model representing a third capacitance corresponding to the change in voltage, the third capacitance including a first capacitance corresponding to a depletion layer formed at the interface, a second capacitance corresponding to the plurality of discrete interface states, and a capacitance of the insulator. A first capacitance corresponding to a first voltage applied to the metal is calculated, and the second capacitance is calculated in accordance with an amount of electrons emitted by a first interface state of the plurality of discrete interface states corresponding to the first voltage, the first interface state being changed stage by stage by changing the first voltage stage by stage in calculating the second capacitance.

Description

Technical Field

[0001] This disclosure relates to simulation methods, storage media, and simulation devices. Background Technology

[0002] Interface states exist at the interface between the semiconductor and the insulating film in a semiconductor device, and these interface states influence the device's characteristics. For example, the current collapse of a high electron mobility transistor (HEMT) using GaN is deeply correlated with the density of interface states. Generally, the higher the density of interface states, the stronger the frequency dependence of the CV (Capacitance-Voltage) characteristic. Therefore, simulations are used to quantify interface states during the semiconductor device design phase through numerical calculation-based analysis of CV characteristics.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2003-092319

[0006] Non-patent literature

[0007] Non-patent literature 1: Japanese Journal of Appl. Phys. 63 (1988) 2120

[0008] Non-patent literature 2: Japanese Journal of Appl. Phys. 103 (2008) 104510

[0009] Non-patent literature 3: Japanese Journal of Appl. Phys. 57(2018)04FG04

[0010] In previous methods for simulating CV characteristics, the accuracy was low at frequencies as low as 1 Hz to 1 kHz. Summary of the Invention

[0011] The purpose of this disclosure is to provide a simulation method, program, and apparatus that achieves excellent accuracy even at low frequencies.

[0012] The simulation method disclosed herein is a method for simulating the CV characteristics of a stacked structure comprising a semiconductor, an insulator on the semiconductor, and a metal on the insulator. The simulation method uses a CV characteristic model of the stacked structure, wherein the interface between the semiconductor and the insulator includes multiple discrete interface states that capture and release electrons with a change in voltage applied to the metal. The CV characteristic model represents a third capacitance corresponding to the change in voltage. The third capacitance includes a first capacitance corresponding to a depletion layer formed at the interface, a second capacitance corresponding to the multiple discrete interface states, and a capacitance of the insulator. The first and second capacitances are connected in parallel, and the capacitance of the insulator is connected in series with the first and second capacitances connected in parallel. The simulation method includes the steps of: calculating the first capacitance corresponding to a first voltage applied to the metal; and calculating the second capacitance based on the amount of electrons released from the first interface state corresponding to the first voltage among the multiple discrete interface states. The step of calculating the second capacitance includes a step of changing the first interface state corresponding to the first voltage in stages by changing the first voltage in stages.

[0013] Invention Effects

[0014] According to this disclosure, excellent accuracy is achieved even at low frequencies. Attached Figure Description

[0015] Figure 1 It is a cross-sectional view of an object representing a simulation method of an implementation.

[0016] Figure 2 It means Figure 1 The energy band diagram of the ideal potential distribution in the object shown.

[0017] Figure 3 It means Figure 1 The energy band diagram shown considers the potential distribution of interface states in the object.

[0018] Figure 4 It means Figure 3 The diagram shows the equivalent circuit of the band structure.

[0019] Figure 5 It is an energy band diagram representing the potential distribution of the stacked structure used in the simulation method of the first embodiment.

[0020] Figure 6 It means Figure 5 The diagram shows the equivalent circuit of the band structure.

[0021] Figure 7It is an energy band diagram (1) showing the change in potential distribution associated with the change in voltage applied to the metal in the first embodiment.

[0022] Figure 8 It is an energy band diagram (2) showing the change in potential distribution associated with the change in voltage applied to the metal in the first embodiment.

[0023] Figure 9 It is an energy band diagram (3) showing the change in potential distribution associated with the change in voltage applied to the metal in the first embodiment.

[0024] Figure 10 It means Figure 9 The diagram shows the equivalent circuit of the band structure.

[0025] Figure 11 It is an energy band diagram (4) showing the change in potential distribution associated with the change in voltage applied to the metal in the first embodiment.

[0026] Figure 12 It means Figure 11 The diagram shows the equivalent circuit of the band structure.

[0027] Figure 13 It is a diagram showing the hardware structure of the simulation device.

[0028] Figure 14 It is a diagram showing the functional structure of the simulation device.

[0029] Figure 15 It is a flowchart illustrating the simulation method implemented by the simulation device.

[0030] Figure 16 It is a diagram showing the first potential distribution and the second potential distribution in the first embodiment side by side.

[0031] Figure 17 It is a cross-sectional view showing the stacked structure of the simulated objects in relation to the first embodiment.

[0032] Figure 18 It means about Figure 17 The figure shows the simulation results of the layered structure.

[0033] Figure 19 It means about Figure 17 The figure shows the measured results of the layered structure.

[0034] Figure 20 The diagram is an overlay representation of simulation results and measured results related to the first embodiment.

[0035] Figure 21 This is a cross-sectional view of the object representing the simulation method of the second embodiment.

[0036] Figure 22 It means Figure 21 The energy band diagram of the ideal potential distribution in the object shown.

[0037] Figure 23 This is an energy band diagram representing the potential distribution of the stacked structure used in the simulation method of the second embodiment.

[0038] Figure 24 It means Figure 23 The diagram shows the equivalent circuit of the band structure.

[0039] Figure 25 This is a diagram showing the first potential distribution and the second potential distribution in the second embodiment side by side.

[0040] Figure 26 This is a diagram showing the second and third potential distributions in the second embodiment side by side.

[0041] Figure 27 This is a cross-sectional view showing the stacked structure of the simulated objects in relation to the second embodiment.

[0042] Figure 28 It means about Figure 27 The figure shows the simulation results of the layered structure.

[0043] Figure 29 It means about Figure 27 The figure shows the measured results of the layered structure.

[0044] Figure 30 The diagram is an overlay representation of simulation results and measured results related to the second embodiment. Detailed Implementation

[0045] The following describes the implementation method.

[0046] [Description of embodiments of this disclosure]

[0047] First, embodiments of this disclosure are listed and described. In the following description, the same or corresponding elements are labeled with the same reference numerals, and the same descriptions are not repeated. At least some of the embodiments described below can be combined arbitrarily.

[0048] [1] A simulation method of the present disclosure is a method for simulating the CV characteristics of a stacked structure having a semiconductor, an insulator on the semiconductor, and a metal on the insulator. The simulation method uses a CV characteristic model of the stacked structure having multiple discrete interface states that capture and release electrons with a change in voltage applied to the metal at the interface between the semiconductor and the insulator. The CV characteristic model represents a third capacitance corresponding to the change in voltage. The third capacitance includes a first capacitance corresponding to a depletion layer formed at the interface, a second capacitance corresponding to the multiple discrete interface states, and a capacitance of the insulator. The first capacitance and the second capacitance are connected in parallel, and the capacitance of the insulator is connected in series with the first capacitance and the second capacitance connected in parallel. The simulation method includes the steps of: calculating the first capacitance corresponding to a first voltage applied to the metal; and calculating the second capacitance based on the amount of electrons released from the first interface state corresponding to the first voltage among the multiple discrete interface states. The step of calculating the second capacitance includes the step of changing the first interface state corresponding to the first voltage in stages by changing the first voltage in stages.

[0049] In a CV characteristic model where the interface between a semiconductor and an insulator comprises multiple discrete interface states, the second capacitances of the multiple discrete interface states are independently calculated based on the first capacitance of the semiconductor. The capacitance of the stacked structure is then calculated using the first capacitance and the second capacitances of the multiple discrete interface states. This method enables the high-precision acquisition of the CV characteristics of the stacked structure.

[0050] [2] In [1], it is possible to use the time constant of each of the plurality of interface states in the calculation of the third capacitor. In this case, a higher precision simulation is possible.

[0051] [3] In [1] or [2], the process of obtaining the first capacitor may include the following steps: calculating the first electron quantity in the semiconductor based on a first potential distribution when a second voltage higher than the first voltage is applied to the metal and electrons are trapped in the interface state; calculating the second electron quantity in the semiconductor based on a second potential distribution when a third voltage lower than the first voltage is applied to the metal while maintaining the state of electrons trapped in the interface state; and dividing the difference between the first electron quantity and the second electron quantity by the difference between the second voltage and the third voltage. In this case, the first capacitor can be obtained with higher accuracy by using the first potential distribution and the second potential distribution.

[0052] [4] In [3], the second capacitance can be calculated based on a third potential distribution when electrons are emitted from the interface state after a predetermined time elapsed from the moment the second potential distribution is obtained. In this case, the second capacitance can be obtained with higher accuracy by using the third potential distribution.

[0053] [5] In [3] or [4], it is permissible that the difference between the second voltage and the first voltage is equal to the difference between the first voltage and the third voltage. In this case, the first capacitor and the second capacitor can be easily calculated.

[0054] [6] In [1] to [5], the simulation method may include the following steps: setting multiple frequencies of AC signals applied to the metal; and calculating the CV characteristics of the stacked structure for each of the multiple frequencies based on the relationship between the first voltage and the third capacitor. In this case, the frequency dependence, i.e., frequency dispersion, of the CV characteristics can be analyzed.

[0055] [7] In [1] to [6], the semiconductor may have: a first semiconductor having a first bandgap; and a second semiconductor having a second bandgap smaller than the first bandgap on top of the first semiconductor, the insulator being disposed on top of the second semiconductor, and the CV characteristic model of the stacked structure including a quantum well of the second semiconductor between the first semiconductor and the insulator, the second capacitance being calculated based on the amount of electrons emitted from the first interface state corresponding to the first voltage in the plurality of discrete interface states to the quantum well. In this case, the frequency dependence of the CV characteristic in the HEMT is easily analyzed.

[0056] [8] Another aspect of this disclosure is a method for simulation using a computer program, which is a program that causes a computer to perform a simulation of the CV characteristics of a stacked structure having a semiconductor, an insulator on the semiconductor, and a metal on the insulator. The simulation uses a CV characteristic model of the stacked structure in which the interface between the semiconductor and the insulator includes multiple discrete interface states that capture and release electrons with a change in voltage applied to the metal. The CV characteristic model represents a third capacitance corresponding to the change in voltage. The third capacitance includes a first capacitance corresponding to a depletion layer formed at the interface, a second capacitance corresponding to the multiple discrete interface states, and a capacitance of the insulator. The first capacitance and the second capacitance are connected in parallel, and the capacitance of the insulator is connected in series with the first capacitance and the second capacitance connected in parallel. The computer program causes the computer to perform the following steps: calculate the first capacitance corresponding to a first voltage applied to the metal; calculate the second capacitance based on the amount of electrons released from the first interface state corresponding to the first voltage among the multiple discrete interface states; calculate the third capacitance; and change the first interface state corresponding to the first voltage in stages by changing the first voltage in stages.

[0057] (9) Another aspect of this disclosure is a storage medium in which the computer program described in (8) is stored in a computer-readable manner.

[0058]

[10] Another aspect of the present disclosure is a simulation apparatus for simulating the CV characteristics of a stacked structure comprising a semiconductor, an insulator on the semiconductor, and a metal on the insulator. The simulation uses a CV characteristic model of the stacked structure comprising multiple discrete interface states of the interface between the semiconductor and the insulator that capture and release electrons with a change in voltage applied to the metal. The CV characteristic model represents a third capacitance corresponding to the change in voltage. The third capacitance includes a first capacitance corresponding to a depletion layer formed at the interface, a second capacitance corresponding to the multiple discrete interface states, and a capacitance of the insulator. The first capacitance and the second capacitance are combined... The simulation device comprises: a first capacitance calculation unit that calculates the first capacitance corresponding to a first voltage applied to the metal; a second capacitance calculation unit that calculates the second capacitance based on the amount of electrons emitted from the first interface state corresponding to the first voltage in the plurality of discrete interface states; and a third capacitance calculation unit that calculates the third capacitance by causing the first interface state corresponding to the first voltage to change in stages by causing the first voltage to change in stages, the third capacitance calculation unit calculating a total capacitance value based on the first capacitance, the second capacitance calculated so far, and the capacitance of the insulator.

[0059] [First Implementation Method]

[0060] The first embodiment relates to a method for simulating the characteristics of a laminated structure having semiconductor, insulator and metal components. Figure 1 This is a cross-sectional view of an object representing the simulation method of the first embodiment. For example... Figure 1 As shown, the simulation method of the first embodiment targets a stacked structure 101 having a semiconductor 10, an insulator 20 on the semiconductor 10, and a metal 30 on the insulator 20. That is, the stacked structure 101 has a MIS (metal-insulator-semiconductor) structure. For example, the semiconductor 10 is an n-type GaN or AlGaN, and the insulator 20 is SiN or Al2O3.

[0061] Figure 2 This is an energy band diagram representing the ideal potential distribution in the object of the simulation method of the first embodiment. Figure 2 In the diagram, the vertical axis represents the magnitude of the electron's energy, and the horizontal axis represents the energy corresponding to... Figure 1 A cross-sectional view and perpendicular to the interface between insulator 20 and semiconductor 10, and the distance from insulator 20 toward semiconductor 10. E V E represents the vertex of the highest energy band (valence band) occupied by electrons in the band structure.C This indicates the bottom of the lowest empty energy band (conduction band) in the band structure. E F This represents the Fermi level. In Figure 2 In the example, semiconductor 10 is an n-type semiconductor, illustrating the process of... Figure 2 Metal 30 (not shown) Figure 1 A bias voltage V was applied. G The state.

[0062] In the stacked structure 101, a depletion layer 40 exists near the interface between the semiconductor 10 and the insulator 20, and the thickness of the depletion layer 40 varies in a direction perpendicular to the interface depending on the voltage applied to the metal 30. Figure 2 As shown, electrons e exist in the portion of semiconductor 10 that is further separated from insulator 20 than depletion layer 40. Furthermore, the capacitance and the amount of electrons between semiconductor 10 and metal 30 change with the change in the thickness of depletion layer 40.

[0063] And, in fact, although Figure 2 Although not shown, an interface state exists between the semiconductor 10 and the insulator 20. In this interface state, when a voltage is applied to the metal 30, electrons are captured and released according to the energy E of the interface state. For example, when a small AC bias voltage (a DC bias voltage superimposed with a small AC voltage) is applied to the metal 30, the amount of electrons in the semiconductor 10 changes, and the capture and release of electrons in the interface state occur.

[0064] Figure 3 This is an energy band diagram representing the potential distribution of interface states in the stacked structure 101. For example... Figure 3 As shown, the interface between the semiconductor 10 and the insulator 20 includes multiple interface states 50. Figure 3 In this paper, multiple interface states 50 are shown discretely for convenience, but in reality they exist continuously. Figure 3 The diagram shows the energy ratio from the Fermi level E. F The high interface state emits several electrons at the Fermi level E51. F Nearby or with energy greater than the Fermi level E F An example of electron 52 being trapped in a lower interface state.

[0065] Figure 4 It means Figure 3 The diagram shows the equivalent circuit of the band structure. Capacitor C ox This refers to the insulator capacitance C, which is constructed based on the thickness and dielectric constant of insulator 20. S This indicates that the impurity concentration of semiconductor 10 and the applied bias voltage V are used to determine the relationship between the impurity concentration and the applied bias voltage V. G The corresponding depletion layer thickness of 40 constitutes the depletion layer capacitance C.S Capacitor C ox and depletion layer capacitance C S In an equivalent circuit, it can be like this: Figure 4 As shown, they are structured as interconnected in series. Furthermore, the capacitor C... it The capacitance G represents the capacitance formed by the state in which electrons are captured or released based on interface state 50. it The time constant τ, used to represent the electrons captured or released by interface state 50, is related to the capacitance C. it Use τ=C together it / G it Let's define the time constant τ.

[0066] Capacitor C it and conductivity G it In an equivalent circuit, it can be like this: Figure 4 As shown, they are connected in series with each other and further connected with the depletion layer capacitance C. S A structure connected in parallel. The capacitor C of the stacked structure 101 as a whole. total The equivalent circuit can be represented as capacitor C ox Depletion layer capacitance C S Capacitor C it and conductivity G it like Figure 4 That kind of connection structure.

[0067] Indicates by Figure 4 The equivalent circuit derived from the stacked structure 101 has a capacitor C as a whole. total The formulas are expressed as shown in equations (1) to (5). In equation (5), f represents the applied bias voltage V. G The small amplitude variation frequency f. In previous simulation methods of CV characteristics, when the frequency f is as low as 1Hz to 1kHz, the capacitance C corresponding to the interface state is... it The reproducibility is insufficient, indicating that the capacitance C of the stacked structure 101 as a whole is not sufficient. total The accuracy is low.

[0068]

Mathematical Formula 1

[0069]

[0070]

Mathematical Formula 2

[0071]

[0072]

Mathematical Expression 3

[0073]

[0074]

Mathematical Expression 4

[0075]

[0076]

Mathematical Expression 5

[0077] ω=2πf (5)

[0078] In the first embodiment, a CV characteristic model (hereinafter referred to as the model) containing multiple discrete interface states is used relative to the stacked structure 101. Figure 5 This is an energy band diagram showing the potential distribution of the stacked structure 101 used in the simulation method of the first embodiment. Figure 6 It means Figure 5 The diagram shows the equivalent circuit of the band structure. Figure 5 band diagram and Figure 3 Compared to discrete band diagrams, it has multiple interface states. Figure 5 The example shown has five discrete interface states, E0, E1, E2, E3, and E4, starting from the higher energy.

[0079] Figure 6 The equivalent circuit shown is Figure 4 Compared to the equivalent circuit, it has multiple discrete interface states E k The corresponding parallel connection of multiple interface states of capacitance C it (E k and conductivity G it (E k k is an integer greater than or equal to 0. The larger the value of k, the higher the interface state E. k The deeper (the lower the energy of the electrons). Figure 6 The example has five discrete interface states E0, E1, E2, E3, and E4, and corresponds to the depletion layer capacitance C. S The capacitors C of the five interface states connected in parallel it (E0), C it (E1), C it (E2), C it (E3), C it (E4) and conductivity G it (E0), G it (E1), G it (E2), G it (E3), G it (E4). Various conductivities G it (E k ) represents the time constant τ(E) for the respective discrete interface states that capture or release electrons. k ), using τ(E) k ) = C it (E k ) / G it (Ek Defined by ). Indicates by Figure 6 The capacitor C of the cascaded structure 101 derived from the equivalent circuit shown is as a whole. total The formulas are expressed as shown in formulas (6) to (9).

[0080]

Mathematical Expression 6

[0081]

[0082]

Mathematical Expression 7

[0083]

[0084]

Mathematical Expression 8

[0085]

[0086]

Mathematical Expression 9

[0087] ω=2πf (9)

[0088] In the first embodiment, using Figure 5 and Figure 6 The model shown and the corresponding model formulas (6) to (9) are used to obtain the first voltage, such as the DC bias voltage V mentioned above, applied to the metal 30. G The capacitor C of semiconductor 10 at that time S For multiple discrete interface states E k Each interface state E k To calculate the capacitance C of the multiple discrete interface states when a first voltage is applied to metal 30. it (E k Capacitor C it (E k The capacitance C of the multiple discrete interface states varies when the voltage applied to the metal 30 changes. it (E k The calculation is based on the amount of electrons emitted.

[0089] Then, using capacitor C ox C S and multiple discrete interface states E k Each interface state E k Capacitor C it (E k To calculate the capacitance C of the stacked structure 101 when a first voltage is applied to the metal 30. total .

[0090] Thus, in this simulation method, based on the capacitance C S To independently compute multiple discrete interface states E kEach interface state E k Capacitor C it (E k Furthermore, based on this simulation method, the capacitance C of the stacked structure 101 under the first voltage can be calculated with high accuracy. total .

[0091] Furthermore, the first voltage is varied in stages, and for each varied first voltage, the interface state E corresponding to that first voltage is calculated. k Capacitor C it (E k This allows for the high-precision acquisition of CV characteristics.

[0092] Furthermore, by setting multiple frequencies of AC signals applied to the metal 30, and obtaining CV characteristics for each of these frequencies, it is possible to analyze the frequency dependence, i.e., frequency dispersion, of the CV characteristics.

[0093] Figures 7-12 This indicates that for each interface state E k To calculate the corresponding capacitance C it (E k A diagram of the action. Figure 7 and Figure 8 This illustrates the bias voltage V applied to the metal 30, which corresponds to the gate electrode of the transistor. G The case where the captured electrons are released from the corresponding interface state during the change. Figure 7 This indicates the bias voltage V applied to metal 30. G (V G =V0-dV) and thus elevate the initial discrete interface state E0 (k=0) to the Fermi level E F A band diagram showing the state up to a certain position. Figure 8 This indicates the bias voltage V applied to metal 30. G (V G =V1-dV) and thus elevate the next discrete interface state E1 (k=1) to the Fermi level E F A band diagram showing the state up to a certain position. Figure 8 It shows in Figure 7 The electrons trapped by the interface state between discrete interface state E1 and interface state E0 in the state shown are in Figure 8 The situation of being released from prison.

[0094] exist Figures 7-12 In both cases, t is defined as 1 / (2πf) using equation (9). Similar to equation (5), f in equation (9) represents the applied bias voltage V. G The small amplitude variation frequency f. As will be discussed later, in order to determine the depletion layer capacitance C. S and discrete interface states Ek Capacitor C it (E k A small bias voltage variation dV is applied to the DC voltage. The frequency of this small bias voltage variation dV is set as f. Due to the discrete interface state E... k The premise is that the release of captured electrons can keep up with the small change in bias voltage dV, so the period of frequency f is naturally suitable to be a larger value than the time constant defined by equation (8).

[0095] like Figure 7 and Figure 8 As shown, multiple interface states exist continuously, and many electrons are trapped in those multiple interface states. In contrast, in the model of this embodiment, the multiple interface states exist discretely. In other words, the multiple interface states use several discrete interface states E. k To represent, for example, through... Figure 7 and Figure 8 As clearly demonstrated by comparison, an electron trapped between discrete interface states E0 (k=0) and E1 (k=1) is represented as if it were trapped in discrete interface state E1 (k=1). This case is expressed by equation (10).

[0096]

Mathematical Formula 10

[0097]

[0098] Regarding equation (10), refer to Figure 7 and Figure 8 To elaborate, ΔV represents the difference between the two applied bias voltages, where ΔV = V1 - V2. Each applied bias voltage can be considered as a discrete interface state E relative to the desired value. k And in this discrete interface state E k The bias voltage required for the captured electrons to change from captured to emitted. Figure 7 and Figure 8 In the process, by applying a bias voltage with a difference of ΔV, a phenomenon occurs from... Figure 7 The state of the band diagram Figure 8 The energy band diagram shows a change in state. This change results in the release of electrons trapped between discrete interface states E1 and E0. The amount of electron released is defined as the increase in charge ΔQ. it (E k (Here, k = 1). Furthermore, the increase in charge ΔQ it (k)(k=1) Assume that it is stored in the discrete interface state E1 (k=1) as a representative, and define this as the capacitance C of the interface state. it(E1) (where k = 1). Equation (10) illustrates these relationships.

[0099] Figures 9-12 It will be with Figure 7 and Figure 8 The changes in the potential distribution of the energy band diagram are illustrated by the equivalent circuit diagrams, which are shown in a way that corresponds the discrete interface states of interest to the circuit diagrams.

[0100] Figure 9 This indicates the bias voltage V applied to the metal 30. G (V G =V1-dV) and thus elevate the discrete interface state E1 (k=1) to the Fermi level E F A band diagram showing the state up to a certain position. Figure 9 The text shows the relationship with... Figure 8 Same state. Figure 10 It means Figure 9 The diagram shows the equivalent circuit of the band structure. Figure 10 The capacitance C of the interface state is shown in the figure. it (E1) and conductivity G it (E1).

[0101] Figure 11 This indicates the bias voltage V applied to the metal 30. G (V G =V2-dV) and thus elevate the discrete interface state E2 (k=2) to the Fermi level E F A band structure diagram showing the state up to a certain position. Figure 11 In the middle, as with Figure 9 The result of applying a bias voltage following the state shows the state in which electrons trapped between discrete interface states E2 and E1 are released. Figure 12 It means Figure 11 The diagram shows the equivalent circuit of the band structure. Figure 12 In addition to Figure 10 The capacitor C in it (E1) and conductivity G it In addition to (E1), the capacitance C of the interface state is also shown. it (E2) and conductivity G it (E2).

[0102] Next, the preferred simulation apparatus for implementing the above simulation method will be described. Figure 13 This is a diagram showing the hardware structure of the simulation device. Figure 13In the analog device 100, the information processing device controlled by the computer has a CPU (central processing unit) 11, a main storage device 12, an auxiliary storage device 13, an input device 14, a display device 15, a communication interface (I / F) 17, and a drive device 18, and is connected to the bus B.

[0103] CPU 11 is equivalent to the processor of simulation device 100 that controls the program stored in main storage device 12. Main storage device 12 uses RAM (random access memory), ROM (read only memory), etc., to store or temporarily save the program executed by CPU 11, the data required for processing in CPU 11, and the data obtained by processing in CPU 11.

[0104] The auxiliary storage device 13 uses an HDD (hard disk drive) or similar device to store data such as programs used for performing various processes. A portion of the program stored in the auxiliary storage device 13 is loaded into the main storage device 12 and executed by the CPU 11, thereby performing various processes. The storage unit 130 includes the main storage device 12 and the auxiliary storage device 13.

[0105] Input device 14 includes a mouse, keyboard, etc., for users to input various information required for processing based on analog device 100. Display device 15 displays various information required under the control of CPU 11. Input device 14 and display device 15 may also be based on a user interface such as an integrated touch panel. Communication I / F 17 communicates via a network such as wired or wireless. Communication based on communication I / F 17 is not limited to wireless or wired.

[0106] The program that performs the processing via the analog device 100 is provided to the analog device 100 via a storage medium 19 such as a CD-ROM (compact disc read-only memory).

[0107] The drive unit 18 establishes a connection between the storage medium 19 (e.g., CD-ROM) of the drive unit 18 and the analog device 100.

[0108] Furthermore, the storage medium 19 stores programs that implement the various processes involved in this embodiment, which will be described later. These programs stored in the storage medium 19 are installed into the simulation device 100 via the drive device 18. The installed programs can be executed by the simulation device 100.

[0109] It should be noted that the storage medium 19 for storing the program is not limited to CD-ROM. In addition to CD-ROM, other storage media that can be read by a computer can include DVD (digital versatile disk), USB (universal serial bus) storage, and other removable recording media, as well as semiconductor storage such as flash memory.

[0110] Figure 14 This is a diagram illustrating the functional structure of the simulation device. Figure 14 In this simulation device 100, there are mainly an input data acquisition unit 41 and an simulation execution unit 42. The input data acquisition unit 41 and the simulation execution unit 42 are implemented by causing the CPU 11 of the simulation device 100 to execute the program installed in the simulation device 100. The storage unit 130 stores mathematical formulas, etc., used in the simulation to calculate the potential distribution.

[0111] The input data acquisition unit 41 acquires data input to the simulation execution unit 42. For example, the input data acquisition unit 41 acquires parameters related to the stacked structure 101 of the simulated object through input from the user.

[0112] The simulation execution unit 42 reads the data input to the input data acquisition unit 41 and performs the simulation. The simulation execution unit 42 includes a model acquisition unit 43 and a C... S Computing Department 44, C it (E k )Computing Unit 45 and C total Calculation Department 46.

[0113] Model acquisition unit 43 uses parameters related to the stacked structure 101 input to input data acquisition unit 41, according to... Figure 6 The equivalent circuit shown is used to fabricate and obtain multiple discrete interface states E at the interface between semiconductor 10 and insulator 20. k The model related to the model (Equations (6) to (9)).

[0114] C S The calculation unit 44 calculates the capacitance C of the semiconductor 10 when a first voltage is applied to the metal 30, based on the model formula created and obtained by the model formula acquisition unit 43. S C S The calculation unit 44 uses the parameters related to the stacked structure 101 input to the input data acquisition unit 41 to calculate the capacitance C. S C S The calculation unit 44 is an example of the first capacitor calculation unit.

[0115] C it (E kThe calculation unit 45, based on the model formula obtained by the model formula acquisition unit 43, calculates multiple discrete interface states E. k Each interface state E k And according to the discrete interface state E when the voltage applied to the metal 30 changes. k The discrete interface state E is calculated by the amount of electrons emitted when a first voltage is applied to metal 30. k Capacitor C it (E k C it (E k The calculation unit 45 is an example of a second capacitor calculation unit.

[0116] C total The calculation unit 46, based on the model formula created by the model formula acquisition unit 43, uses capacitor C S and multiple discrete interface states E k Each interface state E k Capacitor C it (E k To calculate the capacitance C of the stacked structure 101 when a first voltage is applied to the metal 30. total C total The calculation unit 46 is an example of the third capacitor calculation unit.

[0117] Next, the processing performed by the simulation device 100 will be explained. Figure 15 This is a flowchart illustrating the simulation method implemented by the simulation device. In this simulation method, the CV characteristics are simulated based on the change in the amount of electrons when a small AC bias voltage, which is superimposed on a DC bias voltage, is applied to the metal 30.

[0118] like Figure 15 As shown, the input data acquisition unit 41 first acquires parameters related to the stacked structure 101 (step S101). These parameters include, for example, the material, dielectric constant, thickness, and donor density of the semiconductor 10, and the material, dielectric constant, and thickness of the insulator 20. The parameters also include the frequency of the signal applied to the metal 30, the range of the simulated first voltage (DC bias), and the magnitude of the change in the first voltage (V). step The amplitude (dV) of the minute AC voltage. Here, the frequency of the signal and minute AC voltage applied to the metal 30 is f, the range of the first voltage is -10V to +10V, and it changes in stages of 0.1V. The amplitude of the minute AC voltage is 10mV.

[0119] Next, the model acquisition unit 43 uses information such as the materials of the semiconductor 10 and the insulator 20 to create and acquire the interface between the semiconductor 10 and the insulator 20, which includes multiple discrete interface states E. kThe model formula (step S102).

[0120] Next, the minimum value of the first voltage range (-10V) is set as the initial value V0 of the first voltage V (step S103), C S The calculation unit 44 calculates the voltage V of the metal 30. G A second voltage (V+dV) that is dV higher than the first voltage and exists in discrete interface state E k The first potential distribution when electrons are trapped is determined. Then, the amount of electrons Q1 in semiconductor 10 is calculated based on the first potential distribution (step S104).

[0121] Next, C S The computation unit 44 calculates the interface state E that is maintained in discreteness. k The voltage V of metal 30 that traps electrons G The second potential distribution is defined as a third voltage (V-dV) that is dV lower than the first voltage. Furthermore, the amount of electrons Q2 in the semiconductor 10 is calculated based on the second potential distribution (step S105).

[0122] Figure 16 This is an energy band diagram showing, side-by-side, the first potential distribution 191 when a second voltage is applied to the metal 30 and the second potential distribution 192 when a third voltage is applied to the metal 30. (As shown...) Figure 16 As shown, in the first embodiment, comparing the first potential distribution 191 and the second potential distribution 192, the electron energy of the third voltage applied to the metal 30 is higher than the electron energy of the second voltage. As a result, compared to the first potential distribution 191 (…), the electron energy of the third voltage applied to the metal 30 is higher. Figure 16 Compared to the left side, in the second potential distribution 192 ( Figure 16 In the right side (of the semiconductor 10), the thickness of the depletion layer 40 increases. Therefore, the capacitance C of the semiconductor 10... S As the value decreases, the amount of electrons Q2 in the semiconductor 10 in the second potential distribution becomes less than the amount of electrons Q1 in the semiconductor 10 in the first potential distribution.

[0123] C S After obtaining the model formula (step S102), the calculation unit 44 calculates the capacitance C of the insulator 20. OX (Step S120). Furthermore, C S After calculating the second potential distribution (step S105), the calculation unit 44 uses the difference in the amount of electrons in the semiconductor 10 between the first potential distribution 191 and the second potential distribution 192, ΔQ (=Q1-Q2), the difference in the second voltage and the third voltage, ΔV (=2dV), and the capacitance C of the insulator 20. OX To calculate the capacitance C of semiconductor 10 S(Step S106). Here, in this embodiment, it is assumed that time variation is not considered. That is, Figure 15 Steps S104 and S105 in the flowchart are performed, for example, at the instant t = 0. Specifically, at the instant t = 0, Figure 16 The application of the second voltage and the formation of the first potential distribution 191, as shown on the left, are completed instantaneously, or Figure 16 The application of the third voltage and the formation of the second potential distribution 192, as shown on the right side, are completed instantaneously.

[0124] As a result, in step S106, C S The calculation unit 44 does not consider the discreteness of electrons from the interface state E. k Calculate the capacitance C based on the discharge method. S That is, C S The computational unit 44 assumes that the interface state E is maintained in a discrete manner. k The state of the electron was captured and the capacitance C was calculated. S This is equivalent to assuming time t is the ratio time constant τ(E) in equations (6) to (8). k Small 0 and C it (E k ) = 0.

[0125] Next, C it (E k The calculation unit 45 calculates the voltage V of the metal 30. G The third potential distribution 193 is given at the third voltage (V-dV) and time t = 1 / (2πf). Furthermore, the amount of electrons Q3 in the semiconductor 10 is calculated based on the third potential distribution 193 (step S107). It should be noted that time t is the time when the times in steps S104 and S105, which obtain the first potential distribution 191 and the second potential distribution 192, are set to t = 0, for example, the specific time constant τ(E). k ) large 1 / (2πf). Figure 9 An example of the third potential distribution 193 is shown. Figure 9 The condition for the example of the third potential distribution 193 shown is "V G =V1-dV, t=1 / (2πf)". That is, Figure 9 The text shows the condition "V" G =V1-dV, t=0” Figure 16 The third potential distribution 193 is calculated in step S107, which follows step S105 shown on the right.

[0126] Next, C it (E kThe calculation unit 45 compares the second potential distribution 192 with the third potential distribution 193, and calculates the discrete interface states E within a time interval Δt. k The amount of electrons emitted ΔQ it (E k For each discrete interface state E k To calculate capacitance C it (E k (Step S108). For example, in Figure 9 and Figure 10 In the example shown, the capacitance C is calculated for the discrete interface state E1 corresponding to k=1. it (E1). As from Figure 7 Changes, such as Figure 8 As also shown, by applying a third voltage, the continuous interface states between the discrete interface states E0 and E1 are elevated to the level of the Fermi level E. F Equivalent energy or Fermi level E F Up to high energy, such as Figure 8 and Figure 9 As indicated by the arrows, electrons trapped in the continuous interface states between the discrete interface states E0 and E1 are released from the lower end of the conduction band. Furthermore, electrons trapped in interface states with energies lower than the discrete interface state E1 are released because their energies are lower than the Fermi level E1. F It remains in a low state while being captured in the interface state.

[0127] In each capacitor C it (E k In the calculation, the interface states E of each discrete element are used. k The amount of electrons emitted ΔQ it (E k The difference between the second and third voltages is ΔV (=2dV). In ΔQ it (E k ) and ΔV and C it (E k The relationship in equation (10) holds true between ). For example, ... Figure 10 As shown, find the capacitor C in the equivalent circuit diagram. it (E1) and conductivity G it (E1). Here, in this embodiment, when calculating the conductance G... it (E k When ), τ(E) is calculated by model equation (11) based on the SRH (Shockley-Read-Hall) model. k Substituting into equation (8), the conductance G can be easily calculated. it (E k ).

[0128]

Mathematical Expression 11

[0129]

[0130] In this embodiment, in equation (11), the discrete interface state E1 is substituted as the value of energy E to easily calculate τ(E1). Figure 9 As shown, there are multiple and continuous interface states in reality. However, in this embodiment, for example, electrons trapped in the continuous interface states between discrete interface states E0 and E1 can be considered to exist entirely in the discrete interface state E1, and the time constant for releasing these trapped electrons is uniquely defined as τ(E1). As a result, the value of model equation (11) can be substituted into equation (8).

[0131] Next, C total The computing unit 46 uses capacitor C S and multiple discrete interface states E k Each interface state E k Capacitor C it (E k To calculate the capacitance C of the stacked structure 101. total (Step S109). For example, as follows: Figure 11 and Figure 12 As shown, for the discrete interface state E2, V is set... G =V² - dV, find the capacitance C. it (E2), Conductivity G it (E2) After (step S108), the capacitance C relative to the discrete interface states E1 and E0 obtained so far is... it (E1), Conductivity G it (E1) and capacitor C it (E0), Conductivity G it A capacitor C is further added in parallel to (E0). it (E2), Conductivity G it (E2), set as the new total capacitance value C. total .

[0132] Then, if the first voltage V reaches a predetermined upper limit V end If the input range is capped at +10V (yes in step S110), then the process ends. If the first voltage V does not reach the upper limit V... end (If step S110 is negative), then the first voltage is increased by V. step Here, it is 0.1V (step S111). Accompanying the change in the first voltage, the value of k is increased by 1. That is, in the discrete multiple interface states E kIn this process, the interface state of interest for the next step is moved to a deeper interface state. Then, steps S104 to S111 are repeated until the first voltage V reaches its upper limit V. end until.

[0133] According to this simulation method, for a signal of a specific frequency f as a parameter input, the capacitance C between the signal and the stacked structure 101 is calculated every 0.1V within a first voltage range of -10V to +10V as a parameter input. total That is, it is possible to simulate the CV characteristics when a signal of frequency f is applied to metal 30. Furthermore, by changing the value of frequency f, CV characteristics can be obtained for multiple types of frequencies f, and the frequency dependence of the CV characteristics can be analyzed. This is achieved by adjusting the capacitance C. total The discrete interface state E is used in the calculation. k Each interface state E k The time constant τ(E) k It can perform simulations with higher precision.

[0134] Furthermore, by using the first potential distribution 191 and the second potential distribution 192, the capacitance C can be obtained with higher precision. S By using the third potential distribution 193, the capacitance C can be obtained with higher precision. it (E k ).

[0135] Furthermore, by using an AC voltage where the difference between the second and first voltages (dV) is equal to the difference between the first and third voltages (dV), the capacitance C can be easily calculated. S and capacitor C it (E k ).

[0136] Here, we will explain the results of the actual simulation. Figure 17 This is a cross-sectional view representing the stacked structure of the simulated objects. In this stacked structure, such as... Figure 17 As shown, a GaN layer 81A with a thickness of 900 nm is formed on a SiC substrate 80, and an n-type Al layer with a thickness of 20 nm is formed on the GaN layer 81A. 0.24 Ga 0.76 N layer 81B. In Al 0.24 Ga 0.76 An Al₂O₃ film 82 with a thickness of 30 nm is formed on top of the N layer 81B as a gate insulating film. A metal stack 83 consisting of a Ni film and an Au film as a gate electrode is formed on top of the Al₂O₃ film 82. Furthermore, on the Al₂O₃ film 82... 0.24 Ga 0.76Two layers 84, consisting of Ti, Al, and Ti and Au films serving as source and drain electrodes, are formed above the N-layer 81B. The diameter of the metal stack 83 in the top view is 200 μm. GaN layer 81A and Al... 0.24 Ga 0.76 The N-layer 81B corresponds to the semiconductor 10, the Al2O3 film 82 corresponds to the insulator 20, and the metal stack 83 corresponds to the metal 30. Here, the frequencies of the signals applied to the metal stack 83 are 1 kHz, 10 kHz, 100 kHz, and 1 MHz.

[0137] Figure 18 It means about Figure 17 The figure shows the simulation results of the layered structure. Figure 19 It means about Figure 17 The figure shows the measured results of the layered structure. Figure 20 This is a graph that overlaps simulation and measured results. Figure 20 Lieutenant General Figure 18 and Figure 19 A portion of it is enlarged and superimposed to show. Figures 18-20 The horizontal axis represents the voltage applied to the metal laminate 83, and the vertical axis represents the capacitance of the laminated structure. Figure 18 and Figure 19 In addition to CV characteristics, G is also shown. P / ω-V characteristics. In Figure 20 In the diagram, thin lines represent simulation results, and thick lines represent measured results. For example... Figures 18-20 As shown, in this embodiment, simulation results that are equivalent to the measured results were obtained.

[0138] The materials of semiconductor 10, insulator 20, and metal 30 are not limited. The amplitude of the small AC voltage, the range of the DC bias voltage, and the amount of change in the DC bias voltage are not limited. For example, the amplitude of the small AC voltage can be set to be above 10mV and below 15mV.

[0139] The first embodiment enables the simulation of a transistor comprising a semiconductor 10, an insulator 20, and a metal 30. Examples of such transistors include MIS field-effect transistors (FETs), MOS (metal-oxide-semiconductor) FETs, MIS-HEMTs, and MOS-HEMTs.

[0140] It should be noted that in the above embodiment, the conductivity type of semiconductor 10 is n-type, but the conductivity type of semiconductor 10 can also be p-type. When the conductivity type of semiconductor 10 is p-type, it is sufficient to simply reverse the polarity of the voltage.

[0141] [Second Implementation]

[0142] The second embodiment also relates to a method for simulating the characteristics of a stacked structure having semiconductor, insulator and metal components. Figure 21 This is a cross-sectional view of the object representing the simulation method of the second embodiment. For example... Figure 21 As shown, the simulation method of the second embodiment targets a stacked structure 201 comprising a first semiconductor 10A, a second semiconductor 10B above the first semiconductor 10A, an insulator 20 above the second semiconductor 10B, and a metal 30 above the insulator 20. The stacked structure 201 has a MIS structure. For example, the first semiconductor 10A includes GaN 10AA and an n-type AlGaN 10AB above the GaN 10AA, the second semiconductor 10B is GaN, and the insulator 20 is SiN or Al2O3. The thickness of the second semiconductor 10B is, for example, 1 nm or more and 5 nm or less, preferably 2 nm or more and 4 nm or less. The second band gap of the second semiconductor 10B is smaller than the first band gap of AlGaN 10AB.

[0143] Figure 22 This is an energy band diagram representing the ideal potential distribution in the object simulated by the second embodiment. Figure 22 In the diagram, the vertical axis represents the magnitude of the electron's energy, and the horizontal axis represents the energy corresponding to... Figure 21 The cross-sectional view and the distance from the insulator 20 toward the interface between the insulator 20 and the second semiconductor 10B and the first semiconductor 10A. E V E represents the vertex of the highest energy band (valence band) occupied by electrons in the band structure. C This indicates the bottom of the lowest empty energy band (conduction band) in the band structure. E F This represents the Fermi level. In Figure 22 In the example, AlGaN10AB is an n-type semiconductor, demonstrating the transformation to... Figure 22 Metal 30 (not shown) Figure 22 A bias voltage V was applied. G The state.

[0144] In the layered structure 201, although Figure 22 Although not shown in the diagram, an interface state exists at the interface between the second semiconductor 10B and the insulator 20. In this interface state, when a voltage is applied to the metal 30, electrons are captured and released depending on the energy of the interface state. For example, when a small AC bias voltage (a DC bias voltage superimposed on a small AC voltage) is applied to the metal 30, the electron density of the first semiconductor 10A and the second semiconductor 10B changes, and electrons are captured and released from the interface state.

[0145] In the second embodiment, the multiple interface states are also made to exist discretely, similar to the first embodiment. In other words, the multiple interface states are made to exist as several discrete interface states E. k It is used as a representative.

[0146] In the second embodiment, a quantum well model containing multiple discrete interface states and having a second semiconductor 10B between the first semiconductor 10A and the insulator 20 is used, relative to the stacked structure 201. Figure 23 This is an energy band diagram showing the potential distribution of the stacked structure 201 used in the simulation method of the second embodiment. Figure 24 It means Figure 23 The diagram shows the equivalent circuit of the band structure. Figure 23 band diagram and Figure 22 Compared to discrete band diagrams, it has multiple interface states. Figure 23 The example shown has five discrete interface states E0, E1, E2, E3, and E4, starting from higher energies. Furthermore, the quantum well of the second semiconductor 10B has a base energy level E. X .

[0147] Figure 24 The equivalent circuit shown is Figure 6 The equivalent circuit shown has the same discrete multiple interface states E as the one described above. k The corresponding parallel-connected multiple interface state capacitors C it (E k and conductivity G it (E k ). indicates by Figure 24 The equivalent circuit shown derives the stacked structure 201 as a whole, with capacitor C as the entirety. total The formula is expressed as shown in formulas (6) to (9) above.

[0148] In the second embodiment, using Figure 23 and Figure 24 The model shown and the corresponding model formulas (6) to (9) are used to obtain the first voltage, such as the DC bias voltage V mentioned above, applied to the metal 30. G The capacitor C of semiconductor 10 at that time S For multiple discrete interface states E k Each interface state E k To calculate the capacitance C of the multiple discrete interface states when a first voltage is applied to metal 30. it (E k Capacitor C it (E k The capacitance C of the multiple discrete interface states varies when the voltage applied to the metal 30 changes. it (E kThe amount of electrons emitted from the quantum well is calculated separately.

[0149] Then, using capacitor C S and multiple discrete interface states E k Each interface state E k Capacitor C it (E k To calculate the capacitance C of the stacked structure 201 when a first voltage is applied to the metal 30. total .

[0150] Thus, in this simulation method, based on the capacitance C S To independently compute multiple discrete interface states E k Each interface state E k Capacitor C it (E k Furthermore, based on this simulation method, the capacitance C of the stacked structure 201 under the first voltage can be calculated with high accuracy. total .

[0151] Furthermore, the first voltage is varied in stages, and the capacitance C is calculated for each varied first voltage. it (E k This allows for the high-precision acquisition of CV characteristics.

[0152] Furthermore, by setting multiple frequencies of AC signals applied to the metal 30, and obtaining CV characteristics for each of these frequencies, it is possible to analyze the frequency dependence, i.e., frequency dispersion, of the CV characteristics.

[0153] The simulation method described above can be used, for example, in the same way as the first embodiment. Figure 13 and Figure 14 The simulation device 100 shown is used for implementation. Furthermore, in the second embodiment, the simulation device 100 is also based on... Figure 15 The flowchart shown illustrates the implementation of the simulation method.

[0154] Here, based on the flowchart ( Figure 15 In the simulation method, the differences from the first embodiment will be mainly explained.

[0155] In the second embodiment, for example, the parameters obtained by the input data acquisition unit 41 in step S101 include the material, dielectric constant, thickness and donor density of the first semiconductor 10A, the material, dielectric constant, thickness and donor density of the second semiconductor 10B, and the material, dielectric constant and thickness of the insulator 20.

[0156] In step S102, the model acquisition unit 43 uses information such as the materials of the first semiconductor 10A, the second semiconductor 10B, and the insulator 20 to create and acquire the interface between the second semiconductor 10B and the insulator 20, which includes multiple discrete interface states E. k Furthermore, the model of a quantum well in which a second semiconductor 10B exists between the first semiconductor 10A and the insulator 20 is represented by the model formulas (Equations (6) to (9)).

[0157] Similar to the first embodiment, in step S104, C S The calculation unit 44 calculates the voltage V of the metal 30. G A second voltage (V+dV) that is dV higher than the first voltage and exists in discrete interface state E k The first potential distribution when electrons are captured. Similar to the first embodiment, in step S105, C S The computation unit 44 calculates the interface state E that is maintained in discreteness. k The voltage V of metal 30 in the state of electron capture G The second potential distribution is given when the third voltage (V-dV) is dV lower than the first voltage.

[0158] Figure 25 This is an energy band diagram showing, side-by-side, the first potential distribution 291 when a second voltage is applied to the metal 30 and the second potential distribution 292 when a third voltage is applied to the metal 30. (As shown...) Figure 25 As shown, in the second embodiment, when comparing the first potential distribution 291 and the second potential distribution 292, the energy of the first semiconductor 10A and the second semiconductor 10B is higher in the second potential distribution 292 than in the first potential distribution 291.

[0159] In step S106, C S The calculation unit 44 uses the difference ΔQ in the amount of electrons in the first semiconductor 10A and the second semiconductor 10B between the first potential distribution 291 and the second potential distribution 292, the difference ΔV (=2dV) between the second voltage and the third voltage, and the capacitance C of the insulator 20. OX To calculate the capacitance C of the first semiconductor 10A and the second semiconductor 10B. S .

[0160] In step S107, C it (E k The calculation unit 45 calculates the voltage V of the metal 30. GThe third potential distribution 293 is given by a third voltage (V-dV) at time t = 1 / (2πf). The energies of the first semiconductor 10A and the second semiconductor 10B are lower in the third potential distribution 293 compared to the second potential distribution 292. In this embodiment, this change in potential distribution does not occur at the discrete interface state E. k Electrons are trapped, which is considered an increase in the electron density in the quantum well. Figure 26 This is a diagram showing the second and third potential distributions.

[0161] In step S108, C it (E k The calculation unit 45 compares the second potential distribution 292 and the third potential distribution 293, and calculates the discrete interface states E within a time interval Δt. k The amount of electrons emitted ΔQ it (E k For each discrete interface state E k To calculate capacitance C it (E k ).

[0162] In step S109, C total The computing unit 46 uses capacitor C S and multiple discrete interface states E k Each interface state E k Capacitor C it (E k To calculate the capacitance C of the stacked structure 201. total .

[0163] The other processing is the same as in the first embodiment.

[0164] Here, we will explain the results of the actual simulation. Figure 27 This is a cross-sectional view representing the stacked structure of the simulated objects. In this stacked structure, such as... Figure 27 As shown, a GaN layer 81A with a thickness of 900 nm is formed on a SiC substrate 80, and an n-type Al layer with a thickness of 20 nm is formed on the GaN layer 81A. 0.24 Ga 0.76 N-layer 81B, in Al 0.24 Ga 0.76A GaN capping layer 81C is formed on top of the N layer 81B. An Al₂O₃ film 82 with a thickness of 30 nm is formed on the GaN capping layer 81C as a gate insulating film. A metal stack 83 consisting of a Ni film and an Au film as gate electrodes is formed on the Al₂O₃ film 82. Furthermore, a stack 84 consisting of a Ti film, an Al film, and a Ti film and an Au film as source and drain electrodes is formed at two locations on the GaN capping layer 81C. The diameter of the metal stack 83 in the top view is 200 μm. GaN layer 81A and Al… 0.24 Ga 0.76 The N-layer 81B corresponds to the first semiconductor 10A, the GaN capping layer 81C corresponds to the second semiconductor 10B, the Al2O3 film 82 corresponds to the insulator 20, and the metal stack 83 corresponds to the metal 30. Here, the frequencies of the signals applied to the metal stack 83 are 1 kHz, 10 kHz, 100 kHz, and 1 MHz.

[0165] Figure 28 It means about Figure 27 The figure shows the simulation results of the layered structure. Figure 29 It means about Figure 27 The figure shows the measured results of the layered structure. Figure 30 It is a graph that overlaps the simulation results and the measured results. Figures 28-30 The horizontal axis represents the voltage applied to the metal laminate 83, and the vertical axis represents the capacitance of the laminated structure. Figures 28-30 In addition to CV characteristics, G is also shown. P / ω-V characteristics. In Figure 30 In the diagram, thin lines represent simulation results, and thick lines represent measured results. For example... Figures 28-30 As shown, simulation results were obtained that are equivalent to the measured results.

[0166] The materials of the first semiconductor 10A, the second semiconductor 10B, the insulator 20, and the metal 30 are not limited. The amplitude of the minute AC voltage, the range of the DC bias voltage, and the amount of change in the DC bias voltage are not limited. For example, the amplitude of the minute AC voltage can be set to be 10mV or more but less than 15mV.

[0167] The second embodiment enables the simulation of a transistor comprising a first semiconductor 10A, a second semiconductor 10B, an insulator 20, and a metal 30. Examples of such transistors include MIS-HEMT and MOS (metal-oxide-semiconductor)-HEMT.

[0168] The above describes the embodiments in detail, but is not limited to specific embodiments. Various modifications and alterations can be made within the scope of the claims.

[0169] Explanation of reference numerals in the attached figures

[0170] 10: Semiconductors

[0171] 10A: First Semiconductor

[0172] 10AA: GaN

[0173] 10AB: AlGaN

[0174] 10B: Second Semiconductor

[0175] 12: Main storage device

[0176] 13: Auxiliary storage device

[0177] 14: Input device

[0178] 15: Display device

[0179] 17: Communication Interface (I / F)

[0180] 18: Drive unit

[0181] 19: Storage Media

[0182] 20: Insulator

[0183] 30: Metal

[0184] 40: Exhaustion Layer

[0185] 41: Input Data Acquisition Department

[0186] 42: Simulation Execution Unit

[0187] 43: Model-based acquisition department

[0188] 44:C S Computing Department

[0189] 45:C it (E k )Computing Department

[0190] 46: C total Computing Department

[0191] 50: Interface State

[0192] 51, 52: Electrons

[0193] 80: SiC substrate

[0194] 81A: GaN layer

[0195] 81B: Al 0.24 Ga 0.76 N layers

[0196] 81C: GaN capping layer

[0197] 82: Al2O3 membrane

[0198] 83: Metal laminate

[0199] 84: Layered bodies

[0200] 100: Simulation device

[0201] 101, 201: Layered structure

[0202] 130: Storage Department

[0203] 191, 291: First potential distribution

[0204] 192, 292: Second potential distribution

[0205] 193, 293: Third potential distribution

[0206] B: Bus.

Claims

1. A simulation method for simulating the CV characteristics of a stacked structure, the stacked structure comprising a semiconductor, an insulator on the semiconductor, and a metal on the insulator. The simulation method uses the stacked CV characteristic model, which includes multiple discrete interface states at the interface between the semiconductor and the insulator that capture and release electrons in response to changes in the voltage applied to the metal. The CV characteristic model represents the third capacitor corresponding to the change in voltage. The third capacitor includes a first capacitor corresponding to the depletion layer formed at the interface, a second capacitor corresponding to the plurality of discrete interface states, and the capacitance of the insulator. The first capacitor and the second capacitor are connected in parallel, and the capacitance of the insulator is connected in series with the first capacitor and the second capacitor connected in parallel. The simulation method comprises the following steps: Calculate the first capacitance corresponding to the first voltage applied to the metal; and The second capacitance is calculated based on the amount of electrons emitted from the first interface state corresponding to the first voltage among the plurality of discrete interface states. The process of calculating the second capacitor includes a step of causing the first interface state corresponding to the first voltage to change in stages by changing the first voltage in stages.

2. The simulation method according to claim 1, wherein, The calculation of the third capacitor uses the time constant of each of the multiple interface states.

3. The simulation method according to claim 1 or 2, wherein, The process of obtaining the first capacitor includes the following steps: The first electron quantity in the semiconductor is calculated based on the first potential distribution when a second voltage higher than the first voltage is applied to the metal and electrons are trapped in the first interface state; The second electron quantity in the semiconductor is calculated based on the second potential distribution when a third voltage lower than the first voltage is applied to the metal while the metal remains in the first interface state and electrons are trapped there. and Divide the difference between the first electron quantity and the second electron quantity by the difference between the second voltage and the third voltage.

4. The simulation method according to claim 3, wherein, The second capacitance is calculated based on the third potential distribution when electrons are emitted from the first interface state after a predetermined time elapsed from the moment the second potential distribution is obtained.

5. The simulation method according to claim 3, wherein, The difference between the second voltage and the first voltage is equal to the difference between the first voltage and the third voltage.

6. The simulation method according to claim 1 or 2, wherein, The simulation method comprises the following steps: Set the frequencies of multiple AC signals applied to the metal; and For each of the plurality of frequencies, the CV characteristics of the stacked structure are calculated based on the relationship between the first voltage and the third capacitor.

7. The simulation method according to claim 1 or 2, wherein, The semiconductor has: A first semiconductor having a first bandgap; and A second semiconductor having a second bandgap smaller than the first bandgap is placed on top of the first semiconductor. The insulator is disposed on the second semiconductor. The CV characteristic model of the stacked structure includes a quantum well of the second semiconductor between the first semiconductor and the insulator. The second capacitance is calculated based on the amount of electrons emitted into the quantum well from the first interface state corresponding to the first voltage among the plurality of discrete interface states.

8. A method for simulation using a computer program, the computer program causing a computer to perform a simulation of the CV characteristics of a stacked structure, the stacked structure comprising a semiconductor, an insulator above the semiconductor, and a metal above the insulator. The simulation uses the CV characteristic model of the stacked structure, which includes multiple discrete interface states at the interface between the semiconductor and the insulator that capture and release electrons in response to changes in the voltage applied to the metal. The CV characteristic model represents the third capacitor corresponding to the change in voltage. The third capacitor includes a first capacitor corresponding to the depletion layer formed at the interface, a second capacitor corresponding to the plurality of discrete interface states, and the capacitance of the insulator. The first capacitor and the second capacitor are connected in parallel, and the capacitance of the insulator is further connected in series with the first capacitor and the second capacitor connected in parallel. The computer program causes the computer to perform the following steps: Calculate the first capacitance corresponding to the first voltage applied to the metal; The second capacitance is calculated based on the amount of electrons emitted from the first interface state corresponding to the first voltage among the plurality of discrete interface states; Calculate the third capacitor; and The first interface state corresponding to the first voltage is changed in stages by changing the first voltage in stages.

9. A storage medium storing the computer program of claim 8 in a manner readable by a computer.

10. A simulation apparatus for simulating the CV characteristics of a stacked structure, the stacked structure comprising a semiconductor, an insulator above the semiconductor, and a metal above the insulator. The simulation uses the CV characteristic model of the stacked structure, which includes multiple discrete interface states at the interface between the semiconductor and the insulator that capture and release electrons in response to changes in the voltage applied to the metal. The CV characteristic model represents the third capacitor corresponding to the change in voltage. The third capacitor includes a first capacitor corresponding to the depletion layer formed at the interface, a second capacitor corresponding to the plurality of discrete interface states, and the capacitance of the insulator. The first capacitor and the second capacitor are connected in parallel, and the capacitance of the insulator is further connected in series with the first capacitor and the second capacitor connected in parallel. The simulation device has: The first capacitance calculation unit calculates the first capacitance corresponding to the first voltage applied to the metal; The second capacitance calculation unit calculates the second capacitance based on the amount of electrons emitted from the first interface state corresponding to the first voltage among the plurality of discrete interface states; and The third capacitor calculation unit calculates the third capacitor. By changing the first voltage in stages, the first interface state corresponding to the first voltage changes in stages. The third capacitance calculation unit calculates the total capacitance value based on the first capacitance, the second capacitance calculated so far, and the capacitance of the insulator.

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