Display device

Abstract

A display device is provided. The display device includes a substrate including a display area and a non-display area; a pixel connected to a first scan line, a second scan line, a third scan line, and an emission control line; a first scan driver supplying a first scan signal to the first scan line; a second scan driver supplying a second scan signal to some of a plurality of second scan lines and a third scan signal to the third scan line; an emission driver supplying an emission control signal to the emission control line; a first pad and a second pad provided in the non-display area; a first power supply line connected to the first pad, the first power supply line transmitting a first voltage to the first scan driver and the emission driver; and a second power supply line connected to the second pad, the second power supply line transmitting a second voltage to the second scan driver.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0066743, filed on June 2, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present invention generally relate to display devices, and more specifically, to display devices comprising a plurality of scan drivers. Background Technology

[0004] The display device includes a data driver, a gate driver, and pixels. The data driver provides data signals to the pixels via data lines. The gate driver generates gate signals using an externally supplied gate power supply voltage and clock signal, and provides the gate signals to the pixels via gate lines.

[0005] The gate driver may include multiple scan drivers that output different scan signals and a transmit driver that outputs transmit control signals according to the circuit structure of the pixel.

[0006] The information disclosed in this background section is only for understanding the background of the concept of the present invention, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0007] The display device constructed according to an embodiment of the present invention can reduce dead zones by integrating some of the scan drivers.

[0008] The embodiment also provides a display device in which the power lines connected to the second scan driver and the power lines connected to the first scan driver and the transmit driver are electrically and physically separated from each other.

[0009] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the inventive concept.

[0010] A display device according to embodiments includes a substrate including a display area and a non-display area; pixels arranged in the display area, the pixels connected to a first scan line, a second scan line, a third scan line, and an emission control line; a first scan driver arranged in the non-display area, the first scan driver supplying a first scan signal to the first scan line; a second scan driver arranged in the non-display area, the second scan driver supplying a second scan signal to some of the plurality of second scan lines and a third scan signal to the third scan line; an emission driver arranged in the non-display area, the emission driver supplying an emission control signal to the emission control line; a first pad and a second pad arranged in the non-display area with a space between each other; a first power supply line connected to the first pad, the first power supply line transmitting a first voltage to the first scan driver and the emission driver; and a second power supply line connected to the second pad, the second power supply line transmitting a second voltage to the second scan driver.

[0011] The first power supply line can be branched in the non-display area to be connected to the first scan driver and the emission driver.

[0012] The first voltage can be substantially the same as the second voltage.

[0013] In the non-display area, the second power supply line can not be electrically and physically connected with the first power supply line.

[0014] The display device can further include a third pad and a fourth pad, the third pad and the fourth pad arranged in the non-display area with a space between each other, a third power supply line connected to the third pad, the third power supply line transmitting a third voltage higher than the first voltage to the first scan driver and the emission driver, a fourth power supply line connected to the fourth pad, the fourth power supply line transmitting a fourth voltage higher than the second voltage to the second scan driver.

[0015] The third power supply line can be branched in the non-display area to be connected to the first scan driver and the emission driver.

[0016] The third voltage can be substantially the same as the fourth voltage.

[0017] In the non-display area, the fourth power supply line can not be electrically and physically connected with the third power supply line.

[0018] Each of the first scan driver, the second scan driver, and the emission driver can include a plurality of stages. Each of the plurality of stages can include a first power input terminal, a second power input terminal, and a third power input terminal.

[0019] The first power line can be branched into a first scan power line, a second scan power line, a first emission power line, and a second emission power line. The first scan power line and the second scan power line can be connected to a plurality of stages of the first scan driver, and the first emission power line and the second emission power line can be connected to a plurality of stages of the emission driver.

[0020] The first scan power line can be connected to a first power input terminal, the second scan power line can be connected to a second power input terminal, and the third power line can be connected to a third power input terminal.

[0021] The second power line can be branched into a third scan power line and a fourth scan power line. The third scan power line and the fourth scan power line can be connected to a plurality of stages of the second scan driver.

[0022] The display apparatus can further include a dummy scan driver disposed in the non-display area, the dummy scan driver supplying a second scan signal to other second scan lines among the second scan lines.

[0023] The dummy scan driver can include a plurality of dummy stages sequentially outputting the second scan signal.

[0024] An output of a last dummy stage of the dummy scan driver can be supplied as an input of a first stage of the second scan driver.

[0025] A third scan signal supplied to an i-th (i is a positive integer) pixel row can be the same as a signal offset by a predetermined k horizontal period (k is an integer of 8 or more) from a second scan signal. Widths of gate-on periods of a first scan signal, a second scan signal, and an emission control signal can be different from each other.

[0026] Each of the plurality of dummy stages can be connected to second scan lines of two or more consecutive pixel rows. The dummy scan driver can be connected to second scan lines of the first pixel row to the k-th pixel row.

[0027] The second scan driver can be connected to third scan lines of the first pixel row to the k-th pixel row, and connected to second scan lines and third scan lines of the k+1-th pixel row to an n-th (n is an integer greater than k+1) pixel row.

[0028] A first stage of the second scan driver can be connected to a third scan line of the first pixel row and a second scan line of the k+1-th pixel row.

[0029] A display device according to another embodiment includes: pixels connected to a first scan line, a second scan line, a third scan line, and an emission control line; a first scan driver configured to supply a first scan signal to the first scan line; a second scan driver configured to supply a second scan signal to some of the plurality of second scan lines and a third scan signal to the third scan line; an emission driver configured to supply an emission control signal to the emission control line; and a dummy scan driver including dummy stages that supply the second scan signal to other second scan lines of the second scan lines, wherein the dummy scan driver is connected to the second scan lines of a first pixel row to a k-th (k is an integer greater than 1) pixel row, and the second scan driver is connected to the third scan lines of the first pixel row to the k-th pixel row, and connected to the second scan lines and the third scan lines of a (k+1)th pixel row to an n-th (n is an integer greater than k+1) pixel row.

[0030] It will be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the concepts of the application.

[0032] Figure 1 is a diagram illustrating a display device according to an embodiment.

[0033] Figure 2 is an example of a circuit diagram of a pixel included in the display device shown in Figure 1 .

[0034] Figure 3 is an example of a timing chart of signals supplied to the pixel shown in Figure 2 .

[0035] Figure 4 is a schematic plan view illustrating a portion of the display device shown in Figure 1 according to an embodiment.

[0036] Figure 5 is a schematic plan view illustrating a portion of the display device shown in Figure 1 according to another embodiment.

[0037] Figure 6 is a schematic plan view illustrating a portion of the display device shown in Figure 1 according to still another embodiment.

[0038] Figure 7 is an example of a circuit diagram of a pixel included in the display device shown inFigure 1 An example of a block diagram of a gate driver in a display device is shown.

[0039] Figure 8 yes Figure 7 An example of a circuit diagram of a gate driver stage is shown.

[0040] Figure 9 This is an example showing that includes Figure 1 A schematic plan view of the gate driver in the display device shown.

[0041] Figure 10 From Figure 9 The example shown is a waveform diagram of the signal output by the gate driver.

[0042] Figure 11A and Figure 11B It is shown Figure 9 The diagram shows the connection between the gate driver and the pixel row.

[0043] Figure 12 It is shown Figure 9 Another example of a diagram showing the connection between the gate driver and the pixel row. Detailed Implementation

[0044] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, “implementation” and “method” are interchangeable terms and are non-limiting examples of apparatuses or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various embodiments may be practiced without specific details or in one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different, but are not necessarily exclusive. For example, a particular shape, configuration, and characteristic of an embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0045] Unless otherwise specified, the embodiments shown are to be understood as providing features of varying details that may be used to implement the inventive concept in practice. Therefore, unless otherwise specified, features, components, modules, layers, films, panels, areas and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0046] The use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries of regions or elements of the figures. As such, unless otherwise indicated, the presence of cross-hatching or shading in a figure shall not be construed as indicating a preference or requirement for a particular material, material property, dimension, ratio, commonality between elements shown in different figures, and / or any other characteristic, attribute, property, or the like of the elements being presented. Additionally, in the drawings, the size and relative sizes of elements can be exaggerated for clarity. Like reference numbers signify like elements in all examples and drawings unless otherwise noted.

[0047] When an element (such as a layer) is referred to as being "on" another element or layer, it can be directly on the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "directly on" another element or layer, then there are no intervening elements or layers present. In this context, the term "and / or" encompasses the association of either, both, or neither item linked by this term. In addition, the D1 axis, the D2 axis, and the D3 axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, the y-axis, and the z-axis), and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to include any one of X, Y, Z, or any combination of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the phrase "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] While the phrases "first," "second," etc. can be used herein to describe various types of elements, these elements should not be limited by these phrases. These phrases are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0049] Spatially relative terms such as "beneath", "below", "lower", "under", "above", "upper", "over", "higher", "side" (as in "sidewall") and the like can be used herein for descriptive purposes, and, thereby, to describe one element's relationship to another element(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including", "includes", "comprising", "comprise", "have", "has", "have", "having", or the like are used in this specification, such terms are intended to be inclusive in a manner similar to the term "comprising" as an open term (that is, meaning "including, but not limited to"). Also, as used in this specification, the terms "on", "under", "over", "above", "on top of", "positioned on" and the like can refer to direct or indirect positioning on in this specification. In addition, the term "substantially" as used herein is used to describe an arrangement that is not perfect, but is nonetheless sufficiently close to perfect to be considered perfect for the purposes of the disclosure. Thus, the term "substantially" is used to account for variations in measurement, calculation and / or provision of values that would be recognized by one of ordinary skill in the art.

[0051] Various embodiments are described herein with reference to cross-sectional and / or exploded illustrations that are schematic illustrations of idealized embodiments and / or intermediate structures of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for example, manufacturing. In this manner, regions illustrated in the figures can be schematic in nature and the shapes of the regions as illustrated in the figures can not reflect actual shapes of the regions and, as a result, are not intended to limit the scope of the present disclosure in any way.

[0052] As is conventional in the art, some of the embodiments are illustrated in and described with reference to functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are nothing more than a conceptualization of the physical hardware and / or software that is used to implement the embodiments. Those skilled in the art will appreciate that the blocks, units, and / or modules represent physical hardware and / or software that is used to implement the various functions discussed in this document. In the case of blocks, units, and / or modules implemented with microprocessors or other similar hardware, they can be programmed and controlled with software (e.g., microcode) to perform the various functions discussed in this document, and they can be selectively driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Moreover, each block, unit, and / or module of some embodiments can be physically separated into two or more interacting and discrete blocks, units, and / or modules without departing from the scope of the inventive concepts. Furthermore, blocks, units, and / or modules of some embodiments can be physically combined into more complex blocks, units, and / or modules without departing from the scope of the inventive concepts.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0054] Figure 1 FIG. 1 is a diagram of a display device 1000 according to an exemplary embodiment.

[0055] Referring to Figure 1 , the display device 1000 can include a pixel unit 100, a gate driver 200, a data driver 300, and a timing controller 400. The display device 1000 can further include a power supply 500.

[0056] The display device 1000 can display an image at various frame frequencies (e.g., refresh rates, driving frequencies, or screen refresh rates) according to a driving condition. The frame frequency is the frequency at which a data voltage is substantially written to a driving transistor of a pixel PXij during 1 second. For example, the frame frequency is referred to as a screen scanning rate or a screen refresh frequency, and represents the frequency at which a display screen is refreshed during 1 second.

[0057] In an embodiment, the display device 1000 can adjust the output frequency of the gate driver 200 and the output frequency of the corresponding data driver 300 according to a driving condition. For example, the display device 1000 can display an image according to various frame frequencies of 1 Hz to 120 Hz. However, the inventive concept is not limited thereto, and the display device 1000 can display an image at a frame frequency of 120 Hz or more (e.g., 240 Hz or 480 Hz).

[0058] The pixel unit 100 can include a plurality of scan lines S1_1 to S1_n, S2_1 to S2_n, S3_1 to S3_n, and S4_1 to S4_n, a plurality of emission control lines E1 to En, and a plurality of data lines D1 to Dm (m and n are integers greater than 1). Also, the pixel unit 100 can include a plurality of pixels PXij connected with the plurality of scan lines S1_1 to S1_n, S2_1 to S2_n, S3_1 to S3_n, and S4_1 to S4_n, the plurality of emission control lines E1 to En, and the plurality of data lines D1 to Dm. Each of the plurality of pixels PXij can include a driving transistor and a plurality of switching transistors. Also, the plurality of pixels PXij can constitute a plurality of pixel rows in units connected with the plurality of emission control lines E1 to En. For example, pixels PXij connected with the first emission control line E1 can be referred to as a first pixel row.

[0059] The timing controller 400 can receive an external input signal from a host system such as an application processor (AP) through a predetermined interface. The external input signal can include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, RGB data, and a clock signal.

[0060] The vertical synchronization signal can include a plurality of pulses. With respect to a time at which each of the plurality of pulses is generated, a previous frame period can end and a current frame period can begin. An interval between adjacent pulses among the plurality of pulses of the vertical synchronization signal can correspond to one frame period. The horizontal synchronization signal can include a plurality of pulses. With respect to a time at which each of the plurality of pulses is generated, a previous horizontal period can end and a new horizontal period can begin. An interval between adjacent pulses among the plurality of pulses of the horizontal synchronization signal can correspond to one horizontal period. The data enable signal can indicate that the RGB data is supplied in the horizontal period. For example, the RGB data can be supplied in the horizontal period in units of pixels (e.g., to pixels connected with the same first scan line) in correspondence with the data enable signal.

[0061] The timing controller 400 can generate control signals for the gate driver 200 and the data driver 300 based on the external input signal to correspond to a specification of the display device 1000.

[0062] The gate driver 200 can receive a control signal from the timing controller 400 and generate a gate signal based on the control signal. In an embodiment, the gate driver 200 can include a first scan driver connected with a plurality of first scan lines S1_1 to S1_n and a plurality of fourth scan lines S4_1 to S4_n, a second scan driver connected with a plurality of second scan lines S2_1 to S2_n and a plurality of third scan lines S3_1 to S3_n, and an emission driver connected with a plurality of emission control lines E1 to En.

[0063] The gate signal can include a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and an emission control signal. In some embodiments, the fourth scan signal can be the same as the first scan signal. Hereinafter, the first scan signal can include the fourth scan signal.

[0064] The gate driver 200 can generate the first scan signal, the second scan signal, the third scan signal, and the emission control signal having a gate-on voltage level based on a plurality of gate supply voltages VGL and VGH supplied from the power supply 500.

[0065] The gate driver 200 can include a first scan driver, a second scan driver, and an emission driver. The first scan driver can generate the first scan signal by using a plurality of gate supply voltages VGL and VGH, and the second scan driver can generate the second scan signal and the third scan signal by using a plurality of gate supply voltages VGL and VGH. The emission driver can generate the emission control signal by using a plurality of gate supply voltages VGL and VGH.

[0066] The first scan signal to the third scan signal can be set to a gate-on voltage corresponding to a type of a transistor to which a corresponding scan signal is supplied. The transistor receiving the scan signal can be set to be in an on state when the scan signal is supplied. For example, a gate-on voltage of a scan signal supplied to a P-channel Metal Oxide Semiconductor (PMOS) transistor can have a logic low level, and a gate-on voltage of a scan signal supplied to an N-channel Metal Oxide Semiconductor (NMOS) transistor can have a logic high level. Hereinafter, "a scan signal is supplied" can mean that the scan signal is supplied at a logic level in which a transistor controlled by the scan signal is turned on.

[0067] The emission control signal can be set to a gate-off voltage (e.g., a high voltage). The transistor receiving the emission control signal can be turned off when the emission control signal is supplied, and can be set to be in an on state in other cases. Hereinafter, "the emission control signal is supplied" can mean that the emission control signal is supplied at a logic level in which the transistor controlled by the emission control signal is turned off.

[0068] The power supply 500 can supply a plurality of gate power voltages VGL and VGH to the gate driver 200 through a power supply line. The first gate power voltage VGL can be a low voltage, and the second gate power voltage VGH can be a high voltage. A gate signal of a logic high level can be generated based on the second gate power voltage VGH, and a gate signal of a logic low level can be generated based on the first gate power voltage VGL.

[0069] In an embodiment, the power supply 500 can generate a first driving voltage VDD, a second driving voltage VSS, a first initialization voltage Vint1, and a second initialization voltage Vint2 for driving the pixel PXij, and supply the generated voltages to the pixel unit 100.

[0070] The data driver 300 can receive a control signal and image data supplied from the timing controller 400. The data driver 300 can convert image data RGB in a digital form into an analog data signal (a data voltage). The data driver 300 can supply the data signal to a plurality of data lines D1 to Dm. The data signal supplied to the plurality of data lines D1 to Dm can be supplied in synchronization with a first scan signal supplied to a plurality of first scan lines S1_1 to S1_n.

[0071] Each of the data driver 300, the timing controller 400, and the power supply 500 can be implemented as an independent integrated circuit, but the inventive concept is not limited thereto. For example, the data driver 300, the timing controller 400, and the power supply 500 can be implemented as a single integrated circuit. Alternatively, functions of at least some of the data driver 300, the timing controller 400, and the power supply 500 can be implemented with a single integrated circuit. For example, in some embodiments, a plurality of gate power voltages VGL and VGH can be supplied from the data driver 300 to the gate driver 200.

[0072] Figure 2 is an example of a circuit diagram of the pixel 10 included in the display apparatus 1000 shown in Figure 1

[0073] Figure 2 The pixel 10 located on an i-th horizontal line (or an i-th pixel row) and connected to a j-th data line Dj is shown, where i and j are natural numbers.

[0074] Referring to Figure 1 and​Figure 2 The pixel 10 can include a light emitting device LD, first to seventh transistors M1 to M7, and a storage capacitor Cst.

[0075] A first electrode (anode or cathode) of the light emitting device LD can be connected to the sixth transistor M6, and a second electrode (cathode or anode) of the light emitting device LD can be connected to the second driving voltage VSS. The light emitting device LD can generate light having a predetermined brightness according to an amount of current supplied from the first transistor M1.

[0076] In an embodiment, the light emitting device LD can be an organic light emitting diode including an organic light emitting layer. In another embodiment, the light emitting device LD can be an inorganic light emitting device formed of an inorganic material. In still another embodiment, the light emitting device LD can be a light emitting device configured in a complex of an inorganic material and an organic material. Alternatively, the light emitting device LD can have a form in which a plurality of inorganic light emitting devices are connected in parallel and / or in series between a line for transmitting the second driving voltage VSS and the sixth transistor M6.

[0077] A first electrode of the first transistor M1 (or a driving transistor) can be connected to a first pixel node PN1, and a second electrode of the first transistor M1 can be connected to a second pixel node PN2. A gate electrode of the first transistor M1 can be connected to a third pixel node PN3. The first transistor M1 can control an amount of current flowing through the light emitting device LD according to a voltage of the third pixel node PN3. To this end, the first driving voltage VDD can be set to a voltage higher than the second driving voltage VSS.

[0078] The second transistor M2 can be connected to a jth data line Dj (hereinafter referred to as a data line). A gate electrode of the second transistor M2 can be connected to an ith first scan line S1_i (hereinafter referred to as a first scan line). The second transistor M2 can be turned on to electrically connect the data line Dj and the first pixel node PN1 when a first scan signal is supplied to the first scan line S1_i.

[0079] The third transistor M3 can be connected between the third pixel node PN3 and a line for transmitting a first initialization voltage Vint1. A gate electrode of the third transistor M3 can be connected to an ith second scan line S2_i (hereinafter referred to as a second scan line). The third transistor M3 can be turned on to supply the first initialization voltage Vint1 to the third pixel node PN3 when a second scan signal is supplied to the second scan line S2_i. The first initialization voltage Vint1 can be set to a voltage lower than a voltage of a data signal supplied to the data line Dj. In an embodiment, the first initialization voltage Vint1 can be set to a value equal to or less than a value of a voltage of a white gray scale. For example, the first initialization voltage Vint1 can be about -2 V.

[0080] Accordingly, when the third transistor M3 is turned on, the gate voltage of the first transistor M1 can be initialized to the first initialization voltage Vint1.

[0081] The fourth transistor M4 can be connected between the second electrode of the first transistor M1 (i.e., the second pixel node PN2) and the third pixel node PN3. The gate electrode of the fourth transistor M4 can be connected to the ith third scan line S3_i (hereinafter referred to as the third scan line). The fourth transistor M4 can be turned on when a third scan signal is supplied to the third scan line S3_i to electrically connect the second electrode of the first transistor M1 and the third pixel node PN3. More specifically, the timing at which the second electrode of the first transistor M1 (e.g., the drain electrode) and the gate electrode of the first transistor M1 are connected to each other can be controlled by the third scan signal. When the fourth transistor M4 is turned on, the first transistor M1 can be connected in a diode form.

[0082] The fifth transistor M5 can be connected between a line for transmitting the first driving voltage VDD and the first pixel node PN1. The gate electrode of the fifth transistor M5 can be connected to the ith emission control line Ei (hereinafter referred to as the emission control line). The fifth transistor M5 can be turned off when an emission control signal is supplied to the emission control line Ei, and turned on in other cases.

[0083] The sixth transistor M6 can be connected between the second electrode of the first transistor M1 (i.e., the second pixel node PN2) and the first electrode of the light emitting device LD (i.e., the fourth pixel node PN4). The gate electrode of the sixth transistor M6 can be connected to the emission control line Ei. The sixth transistor M6 can be controlled substantially identically to the fifth transistor M5.

[0084] The seventh transistor M7 can be connected between the first electrode of the light emitting device LD (i.e., the fourth pixel node PN4) and a line for transmitting the second initialization voltage Vint2. The gate electrode of the seventh transistor M7 can be connected to the ith fourth scan line S4_i (hereinafter referred to as the fourth scan line). In an embodiment, the same first scan signal can be supplied to the fourth scan line S4_i and the first scan line S1_i. In this case, the gate electrode of the seventh transistor M7 can be regarded as being connected to the first scan line S1_i. The seventh transistor M7 can be turned on when the first scan signal is supplied to the first scan line S1_i to supply the second initialization voltage Vint2 to the first electrode of the light emitting device LD.

[0085] When the second initialization voltage Vint2 is supplied to the first electrode of the light emitting device LD, a parasitic capacitor of the light emitting device LD can be discharged. In this way, since a residual voltage charged in the parasitic capacitor is discharged (removed), unintended slight emission can be prevented. Thereby, the black performance of the pixel 10 can be improved.

[0086] The first initialization voltage Vint1 and the second initialization voltage Vint2 can be different from each other. More specifically, the voltage for initializing the third pixel node PN3 and the voltage for initializing the fourth pixel node PN4 can be set to be different from each other.

[0087] In low frequency driving in which the length of one frame period is extended, when the voltage of the first initialization voltage Vint1 supplied to the third pixel node PN3 is too low, the strong on bias is applied to the first transistor M1, which can shift the threshold voltage of the first transistor M1 in the corresponding frame period. This hysteresis characteristic can cause a flickering phenomenon in low frequency driving. Thus, the first initialization voltage Vint1 higher than the second driving voltage VSS can be required in the display device 1000 operating in low frequency driving.

[0088] However, when the second initialization voltage Vint2 supplied to the fourth pixel node PN4 is higher than a predetermined reference voltage, the voltage of the parasitic capacitor of the light emitting device LD is not discharged, but the parasitic capacitor can be charged. Thus, the second initialization voltage Vint2 can be required to be similar to or lower than the second driving voltage VSS. For example, the second initialization voltage Vint2 can be about -4 V. Also, the second initialization voltage Vint2 can be set to a voltage value lower than the voltage value of the first initialization voltage Vint1.

[0089] The storage capacitor Cst can be connected between the line for transmitting the first driving voltage VDD and the third pixel node PN3. The storage capacitor Cst can store the voltage applied to the third pixel node PN3.

[0090] According to an embodiment, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can be implemented with a polysilicon semiconductor transistor. For example, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can include a polysilicon semiconductor layer formed as an active channel through a Low Temperature Poly-Silicon (LTPS) process. Also, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can be implemented with P-type transistors (e.g., PMOS transistors). Thus, the gate on voltage at which the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned on can have a logic low level.

[0091] Since the polysilicon semiconductor transistor has a fast response speed, the polysilicon semiconductor transistor can be applied to a switching element requiring fast switching.

[0092] The third transistor M3 and the fourth transistor M4 can be implemented with oxide semiconductor transistors. For example, the third transistor M3 and the fourth transistor M4 can be implemented with N-type oxide semiconductor transistors (e.g., NMOS transistors) and include oxide semiconductor layers as active layers. Thus, the gate-on voltage at which the third transistor M3 and the fourth transistor M4 are turned on can have a logic high level.

[0093] An oxide semiconductor transistor can be formed by a low-temperature process and has a lower charge mobility than a polysilicon semiconductor transistor. That is, an oxide semiconductor transistor has excellent off-state current characteristics. Thus, when the third transistor M3 and the fourth transistor M4 are implemented with oxide semiconductor transistors, the leakage current from the second pixel node PN2 according to low-frequency driving can be minimized, and accordingly, display quality can be improved.

[0094] Figure 3 is supplied to Figure 2 An example of a timing chart of signals of the pixel 10 shown in FIG. 1 is shown in FIG. 2.

[0095] Referring to Figure 2 and Figure 3 In variable frequency driving for controlling a frame frequency, one frame period FP can include a first period P1 (e.g., a display scan period) and at least one second period P2 (e.g., a bias scan period).

[0096] The first scan signal can be supplied to the first scan line S1_i, the second scan signal can be supplied to the second scan line S2_i, the third scan signal can be supplied to the third scan line S3_i, and the emission control signal can be supplied to the emission control line Ei.

[0097] The first period P1 can include a first non-emission period NEP1 and a first emission period EP1. The second period P2 can include a second non-emission period NEP2 and a second emission period EP2.

[0098] The first period P1 includes a period in which a data signal actually corresponding to an output image is written to the gate electrode (or the storage capacitor Cst) of the first transistor M1. For example, when a still image is displayed by low-frequency driving, a data signal can be written to the gate electrode of the first transistor M1 in the first period P1.

[0099] The second period P2 can include a period in which a voltage (or a data signal) supplied through the data line Dj is supplied to the source electrode (i.e., the first pixel node PN1) of the first transistor M1. For example, when a predetermined voltage is supplied to the source electrode of the first transistor M1, the bias state of the first transistor M1 can be controlled.

[0100] As Figure 3As illustrated in FIG. 1, the emission control signal and the first scan signal can be supplied at a first frequency higher than the frame frequency. The second scan signal and the third scan signal can be supplied at a second frequency lower than the first frequency. For example, the first frequency can be 240 Hz, and the second frequency can be 60 Hz. The frequencies at which the second scan signal and the third scan signal are supplied can be substantially equal to the frame frequency.

[0101] However, the present inventive concept is not limited thereto. In some embodiments, the first frequency can be higher than 120 Hz, and the second frequency can be 60 Hz or less. The number of times the second period P2 repeats in the frame period FP (i.e., the number of bias scan periods) can increase as the second frequency becomes lower, or as the difference between the first frequency and the second frequency becomes larger. For example, the frame period FP can include one display scan period and a plurality of consecutive second periods P2 according to the frame frequency.

[0102] In embodiments, the second scan signal and the third scan signal can be supplied only in the first non-emission period NEP1.

[0103] In embodiments, the first scan signal can be supplied in the first non-emission period NEP1 and the second non-emission period NEP2. In the first non-emission period NEP1, the first scan signal can function to write the data signal to the pixel 10. In the second non-emission period NEP2, the first scan signal can function to control the bias state of the first transistor M1.

[0104] The period in which the emission control signal has a logic low level can correspond to the first emission period EP1 and the second emission period EP2, and the period other than the first emission period EP1 and the second emission period EP2 can correspond to the first non-emission period NEP1 and the second non-emission period NEP2.

[0105] The gate-on voltage of the second scan signal and the third scan signal supplied to the third transistor M3 and the fourth transistor M4, which are implemented as N-type transistors, respectively, has a logic high level. The gate-on voltage of the first scan signal supplied to each of the second transistor M2 and the seventh transistor M7, which are implemented as P-type transistors, has a logic low level.

[0106] Hereinafter, a description will be given of the operation of the pixel 10 and the scan signals supplied in the first period P1 and the second period P2 with reference to Figure 3 The scan signals supplied in the first period P1 and the second period P2 and the operation of the pixel 10 will be described in more detail.

[0107] The second scan signal can be supplied to the second scan line S2_i in the first non-emission period NEP1. When the third transistor M3 turns on in response to the second scan signal, the gate voltage of the first transistor M1 can be initialized.

[0108] Subsequently, a third scan signal can be supplied to the third scan line S3_i. The second scan signal and the third scan signal can not overlap each other. In an embodiment, the third scan signal can be a signal obtained by shifting the second scan signal by a predetermined horizontal period. In this manner, the second scan signal and the third scan signal can be output from one scan driver.

[0109] The fourth transistor M4 can be turned on in response to the third scan signal.

[0110] In a state in which the fourth transistor M4 is turned on, the first scan signal can be supplied to the first scan line S1_i. In response to the first scan signal, the second transistor M2 can be turned on, the first transistor M1 is connected in a diode form, and data signal writing and threshold voltage compensation can be performed. Since the supply of the third scan signal is maintained even after the supply of the first scan signal is suspended, the threshold voltage of the first transistor M1 can be compensated for a sufficient time.

[0111] Subsequently, the supply of the emission control signal is suspended, and the pixel 10 can emit light during the first emission period EP1.

[0112] The first scan signal can be supplied to the first scan line S1_i in the second non-emission period NEP2. Accordingly, the bias state of the first transistor M1 can be controlled in a periodical manner regardless of the frame frequency.

[0113] Meanwhile, the second scan signal and the third scan signal are not supplied in the second period P2. The number of times that the second period P2 of the frame period FP is repeated and the time in which the second scan signal and the third scan signal are not supplied can increase as the frame frequency becomes lower.

[0114] Figure 4 is a schematic plan view showing a portion of the display device 1000 shown in Figure 1 is a schematic plan view showing a portion of the display device 1000 shown in

[0115] Referring to Figures 1-4 , the gate driver 200 can include a first scan driver 220, a second scan driver 240, and an emission driver 260.

[0116] The display device 1000 can include a substrate 1. The substrate 1 can include a display area and a non-display area located near at least one side of the display area.

[0117] A pixel unit 100 including a pixel PXij can be provided in the display area of the substrate 1. In Figure 4 , the display area can correspond to the pixel unit 100.

[0118] A first scan driver 220, a second scan driver 240, and an emitter driver 260 may be provided in the non-display area of ​​substrate 1, and multiple pads PD1, PD2, PD3, and PD4 may be arranged in the non-display area of ​​substrate 1. The non-display area may correspond to the area of ​​substrate 1 excluding pixel units 100.

[0119] The first scan driver 220 can be connected to the first scan line S1_i to supply the first scan signal to the pixel PXij.

[0120] The second scan driver 240 can be connected to the second scan line S2_i and the third scan line S3_i to supply the second scan signal and the third scan signal to the pixel PXij. In this way, one of the multiple scan drivers that generate the second scan signal or the third scan signal in a conventional display device can be omitted.

[0121] The transmit driver 260 can be connected to the transmit control line Ei to supply the transmit control signal to the pixel PXij.

[0122] First pad PD1, second pad PD2, third pad PD3, and fourth pad PD4 can be connected to lines used for transmitting first voltage VGL1, second voltage VGL2, third voltage VGH1, and fourth voltage VGH2 supplied from power supply 500. Each of the first voltage VGL1, second voltage VGL2, third voltage VGH1, and fourth voltage VGH2 can be as described above. Figure 1 One of the multiple gate power supply voltages VGL and VGH described.

[0123] Figure 4 The arrangement of the gate driver 200 and the first pad PD1, second pad PD2, third pad PD3 and fourth pad PD4 shown are merely illustrative, and the concept of the invention is not limited to the specific positions of the components therein. For example, in some embodiments, the first scan driver 220 and the transmit driver 260 may be arranged in reverse.

[0124] A first voltage VGL1 (hereinafter referred to as the first low voltage) may be applied to the first pad PD1, and a second voltage VGL2 (hereinafter referred to as the second low voltage) may be applied to the second pad PD2. In some embodiments, the first low voltage VGL1 and the second low voltage VGL2 may have substantially the same voltage value. For example, the first low voltage VGL1 and the second low voltage VGL2 may have the same first gate power supply voltage VGL value. However, the concept of the invention is not limited thereto, and in other embodiments, the first low voltage VGL1 and the second low voltage VGL2 may be different from each other.

[0125] The logic low level of the scan signal and the emission control signal can be determined based on the first low voltage VGL1 and the second low voltage VGL2.

[0126] In an embodiment, the first pad PD1 and the second pad PD2 have no electrical connection and physical connection with each other. In addition, the line connected to the first pad PD1 and the line connected to the second pad PD2 have no electrical connection and physical connection with each other.

[0127] A third voltage VGH1 (hereinafter referred to as a first high voltage) can be transmitted to a third pad PD3, and a fourth voltage VGH2 (hereinafter referred to as a second high voltage) can be transmitted to a fourth pad PD4. In some embodiments, the first high voltage VGH1 and the second high voltage VGH2 can have the same value. For example, the first high voltage VGH1 and the second high voltage VGH2 can have the same second gate power voltage VGH value. However, the inventive concept is not limited thereto, and in other embodiments, the first high voltage VGH1 and the second high voltage VGH2 can be different from each other.

[0128] The logic high level of the scan signal and the emission control signal can be determined based on the first high voltage VGH1 and the second high voltage VGH2.

[0129] In an embodiment, the third pad PD3 and the fourth pad PD4 have no electrical connection and physical connection with each other. In addition, the line connected to the third pad PD3 and the line connected to the fourth pad PD4 have no electrical connection and physical connection with each other.

[0130] The first pad PD1 can be connected to a first power line PL1. The first power line PL1 can transmit the first low voltage VGL1 to the first scan driver 220 and the emission driver 260. In an embodiment, the first power line PL1 can be branched at a first line node LN1 of a non-display area to be connected to the first scan driver 220 and the emission driver 260.

[0131] The third pad PD3 can be connected to a third power line PL3. The third power line PL3 can transmit the first high voltage VGH1 to the first scan driver 220 and the emission driver 260. In an embodiment, the third power line PL3 can be branched at a second line node LN2 of a non-display area to be connected to the first scan driver 220 and the emission driver 260.

[0132] As described above with reference to FIGS. 1 to 3, Figure 3As described, the first scan driver 220 and the emission driver 260 can be driven in the first period P1 and the second period P2 of the frame period FP and output the first scan signal and the emission control signal in the first non-emission period NEP1 and the second non-emission period NEP2, respectively. That is, the first scan signal and the emission control signal can be output in fixed periods based on the first low voltage VGL1 and the first high voltage VGH1 regardless of a frame frequency. Accordingly, although the first scan driver 220 and the emission driver 260 share the first power line PL1 and the third power line PL3, variations in equivalent impedance for generating the first scan signal and the emission control signal are not large.

[0133] The second scan driver 240 can generate the second scan signal and the third scan signal by operating only in the first non-emission period NEP1 of the frame period FP.

[0134] When the first scan driver 220, the second scan driver 240, and the emission driver 260 share the first power line PL1, the voltage drop amount of the first low voltage VGL1 during the first period P1 (e.g., the first non-emission period NEP1) and the second period P2 (e.g., the second non-emission period NEP2) can be different from each other due to a difference between equivalent impedances in the first period P1 and the second period P2. Similarly, when the first scan driver 220, the second scan driver 240, and the emission driver 260 share the third power line PL3, the voltage drop amount of the first high voltage VGH1 during the first period P1 and the second period P2 can be different from each other due to a difference between equivalent impedances in the first period P1 and the second period P2.

[0135] The logic low level and the logic high level of the scan signal and the emission control signal can change due to a difference between voltage drop amounts of the gate power voltage (VGL and VGH shown in FIG. 1B) during the first period P1 and the second period P2. In addition, the voltage of the gate electrode of the transistor included in the pixel PXij and / or the voltage coupling amount of the gate electrode in a given period can change due to the capacitance of a parasitic capacitor connected to the gate electrode. Such unintended changes in the voltage of the gate electrode of the transistor can cause image flicker. Figure 1

[0136] To minimize unintended changes in the voltage of the gate electrode of the transistor, the first scan driver 220 and the emission driver 260 can be driven in the first period P1 and the second period P2 of the frame period FP and output the first scan signal and the emission control signal in the first non-emission period NEP1 and the second non-emission period NEP2, respectively. Figure 1 ​In order to minimize the difference between the voltage drop amounts of the plurality of gate power voltages VGL and VGH (e.g., VGL and VGH shown in FIG. 1), the second power line PL2 and the fourth power line PL4 connected to the second scan driver 240 can be separated from the first power line PL1 and the third power line PL3, respectively. Thus, the second scan driver 240 driven at a different timing from the first scan driver 220 and the emission driver 260 can apply the second low voltage VGL2 and the second high voltage VGH2 through power lines different from the power lines supplying the first low voltage VGL1 and the first high voltage VGH1.

[0137] The second pad PD2 can be connected to the second power line PL2. The second power line PL2 can transmit the second low voltage VGL2 to the second scan driver 240. In an embodiment, the second low voltage VGL2 can be equal to the first low voltage VGL1.

[0138] The fourth pad PD4 can be connected to the fourth power line PL4. The fourth power line PL4 can transmit the second high voltage VGH2 to the second scan driver 240. In an embodiment, the second high voltage VGH2 can be equal to the first high voltage VGH1.

[0139] As described above, the second scan driver 240 can supply the second scan signal and the third scan signal to the pixel PXij. Thus, the configuration of two scan drivers for generating the second scan signal and the third scan signal, respectively, is integrated into one, thereby reducing the area of a non-display region (dead zone).

[0140] The second power line PL2 and the fourth power line PL4 for transmitting the plurality of gate power voltages VGL and VGH to the second scan driver 240 can be electrically and physically separated from the first power line PL1 and the third power line PL3 for transmitting the plurality of gate power voltages VGL and VGH to the first scan driver 220 and the emission driver 260. Thus, in low-frequency driving including the first period P1 and at least one second period P2 in one frame period FP, image flicker that can occur due to the difference between the voltage drop amounts of the plurality of gate power voltages VGL and VGH during the first period P1 and the second period P2 can be minimized.

[0141] Figure 5 is a schematic plan view showing a portion of a display apparatus 1000 according to another embodiment. Figure 1 is a schematic plan view showing a portion of the display apparatus 1000 shown in FIG. 1.

[0142] In Figure 5 In the display apparatus 1000 shown in FIG. 1, the configuration of the power lines is the same as that of the display apparatus 1000 shown in FIG. 1 except that the first power line PL1 and the second power line PL2 are additionally branched. Thus, the display apparatus 1000 shown in FIG. 1 can minimize image flicker that can occur due to the difference between the voltage drop amounts of the plurality of gate power voltages VGL and VGH (e.g., VGL and VGH shown in FIG. 1) in low-frequency driving including the first period P1 and at least one second period P2 in one frame period FP. Figure 4 The configuration of the first power line PL1 to the fourth power line PL4 of the display apparatus 1000 shown in FIG. 1 is the same as that of the display apparatus 1000 shown in FIG. 1. Thus, the display apparatus 1000 shown in FIG. 1 can minimize image flicker that can occur due to the difference between the voltage drop amounts of the plurality of gate power voltages VGL and VGH (e.g., VGL and VGH shown in FIG. 1) in low-frequency driving including the first period P1 and at least one second period P2 in one frame period FP. Figure 4Components shown in the middle or corresponding components are designated by the same reference numerals, and repeated description thereof will be omitted.

[0143] Referring to Figure 1 and Figure 5 The display device 1000 can include a substrate 1. The substrate 1 can include a display area and a non-display area located near at least one side of the display area.

[0144] A gate driver 200 can be provided in the non-display area of the substrate 1, and a plurality of pads PD1, PD2, PD3, and PD4 can be arranged in the non-display area of the substrate 1. The gate driver 200 can include a first scan driver 220, a second scan driver 240, and an emission driver 260.

[0145] In an embodiment, the first power line PL1 can be branched into a first scan power line SPL1, a second scan power line SPL2, a first emission power line EPL1, and a second emission power line EPL2. The first scan power line SPL1 and the second scan power line SPL2 can be connected to stages of the first scan driver 220. The first scan power line SPL1 and the second scan power line SPL2 can transmit the first low voltage VGL1 to the first scan driver 220.

[0146] Each of the plurality of stages of the first scan driver 220 can include ten or more transistors, and have a complex circuit structure well known in the art. The first low voltage VGL1 can be supplied to the first scan driver 220 through the first scan power line SPL1 and the second scan power line SPL2 to prevent unintended voltage variation of the first low voltage VGL1 that can be caused by circuit size and circuit complexity, and short circuit between the first power line PL1 and other elements, etc. For the same reason, other power lines (e.g., the second power line PL2) can be branched into a plurality of branch power lines to be connected to the emission driver 260 and / or the second scan driver 240.

[0147] The first emission power line EPL1 and the second emission power line EPL2 can be connected to stages of the emission driver 260. The first emission power line EPL1 and the second emission power line EPL2 can transmit the first low voltage VGL1 to the emission driver 260. Each of the plurality of stages of the emission driver 260 can also include ten or more transistors, and include a complex circuit structure.

[0148] In an embodiment, the second power line PL2 can branch into a third scan power line SPL3 and a fourth scan power line SPL4. The third scan power line SPL3 and the fourth scan power line SPL4 can be connected to stages of the second scan driver 240. The third scan power line SPL3 and the fourth scan power line SPL4 can transmit the second low voltage VGL2 to the second scan driver 240.

[0149] Accordingly, the gate driver 200 according to the illustrated embodiment can improve output stability. It will be described in more detail with reference to Figure 7 and Figure 8 The configuration in which the power lines branch to be connected to the stages will be described in more detail.

[0150] Figure 5 The configuration of the power line branching illustrated in FIG. 1 is merely illustrative, and the inventive concept is not limited thereto. For example, the third power line PL3 and the fourth power line PL4 can also branch to be connected to stages corresponding thereto, respectively.

[0151] Figure 6 is a schematic plan view illustrating a portion of a display device 1000 according to still another embodiment. Figure 1

[0152] In the display device 1000 illustrated in FIG. 1, the configuration of the display device 1000 is substantially the same as that of the display device 1000 described with reference to Figure 6 and Figure 4 The configuration of the display device 1000 described with reference to Figure 5 and Figure 4 The same or corresponding components as those illustrated in FIG. 1 are designated by the same reference numerals, and a repeated description thereof will be omitted. Figure 5 With reference to

[0153] , the gate driver 200A can include a first scan driver 220, a second scan driver 240, an emission driver 260, a first auxiliary scan driver 222, a second auxiliary scan driver 242, and an auxiliary emission driver 262. Figure 6 In an embodiment, the first scan driver 220, the second scan driver 240, and the emission driver 260 can be arranged at one side (e.g., the left side) of the pixel unit 100, and the first auxiliary scan driver 222, the second auxiliary scan driver 242, and the auxiliary emission driver 262 can be arranged at the other side (e.g., the right side) of the pixel unit 100.

[0154]

[0155] ​​The first auxiliary scan driver 222 can be driven identically to the first scan driver 220. In an embodiment, the first scan line S1_i and the fourth scan line S4_i can be commonly connected to the first scan driver 220 and the first auxiliary scan driver 222.

[0156] The second auxiliary scan driver 242 can be driven identically to the second scan driver 240. In an embodiment, the second scan line S2_i and the third scan line S3_i can be commonly connected to the second scan driver 240 and the second auxiliary scan driver 242.

[0157] The auxiliary emission driver 262 can be driven identically to the emission driver 260. In an embodiment, the emission control line Ei can be commonly connected to the emission driver 260 and the auxiliary emission driver 262.

[0158] The first scan power line SPL1 and the second scan power line SPL2 connected to the first scan driver 220 can be electrically connected to the first auxiliary scan driver 222 through the first connection line CL1. The third power line PL3 can be electrically connected to the first auxiliary scan driver 222 and the auxiliary emission driver 262 through the second connection line CL2.

[0159] The third scan power line SPL3 and the fourth scan power line SPL4 can be electrically connected to the second auxiliary scan driver 242 through the third connection line CL3. The fourth power line PL4 can be electrically connected to the second auxiliary scan driver 242 through the fourth connection line CL4.

[0160] The first emission power line EPL1 and the second emission power line EPL2 can be electrically connected to the auxiliary emission driver 262 through the first connection line CL1.

[0161] In Figure 6 , although the first scan driver 220, the second scan driver 240, and the emission driver 260 are illustrated as being arranged at the left side of the pixel unit 100, and the first auxiliary scan driver 222, the second auxiliary scan driver 242, and the auxiliary emission driver 262 are illustrated as being arranged at the right side of the pixel unit 100, this is merely illustrative, and the arrangement of the drivers is not limited thereto. For example, in other embodiments, the first scan driver 220, the second scan driver 240, and the emission driver 260 at the left side of the pixel unit 100 and the first auxiliary scan driver 222, the second auxiliary scan driver 242, and the auxiliary emission driver 262 at the right side of the pixel unit 100 can be symmetrically arranged with respect to each other about the pixel unit 100.

[0162] Figure 7 is an example of a block diagram of the gate driver 200 included in the display device 1000 illustrated in Figure 1 .

[0163] Hereinafter, four stages and gate signals output therefrom will be exemplarily described with reference to Figure 7

[0164] Referring to Figure 1 , Figure 5 and Figure 7 , the gate driver 200 can include a plurality of stages ST1 to ST4. For example, the plurality of stages ST1 to ST4 can be connected to a predetermined plurality of gate lines G1 to G4, respectively, and output a plurality of gate signals GS1 to GS4 according to a plurality of clock signals CLK1 and CLK2. The plurality of stages ST1 to ST4 can be substantially implemented with the same circuit.

[0165] In an embodiment, the gate driver 200 can include a first scan driver 220, a second scan driver 240, and / or an emission driver 260. For example, the plurality of gate lines G1 to G4 can correspond to a plurality of first scan lines, a plurality of second scan lines, or a plurality of emission control lines, and the plurality of gate signals GS1 to GS4 can correspond to a plurality of first scan signals, a plurality of second scan signals, a plurality of third scan signals, or a plurality of emission control signals.

[0166] Each of the plurality of stages ST1 to ST4 can include a first input terminal 101, a second input terminal 102, a third input terminal 103, an output terminal 104, a first power input terminal 105, a second power input terminal 106, and a third power input terminal 107.

[0167] The first input terminal 101 can receive an output signal of a previous stage or a start pulse SSP. For example, the first input terminal 101 of the first stage ST1 can receive the start pulse SSP, and the first input terminal 101 of the second stage ST2 can receive a gate signal output from the first stage ST1.

[0168] In an embodiment, the second input terminal 102 of the k-th (k is a natural number) stage can receive the first clock signal CLK1, and the third input terminal 103 of the k-th stage can receive the second clock signal CLK2. On the other hand, the second input terminal 102 of the k+1-th stage can receive the second clock signal CLK2, and the third input terminal 103 of the k+1-th stage can receive the first clock signal CLK1.

[0169] The first clock signal CLK1 and the second clock signal CLK2 have the same period, and phases of the first clock signal CLK1 and the second clock signal CLK2 can not overlap each other. For example, the second clock signal CLK2 can be set as a signal that is offset by about half a period from the first clock signal CLK1.

[0170] ​Each output terminal 104 can be connected to a corresponding gate line among the plurality of gate lines G1 to G4. A corresponding gate signal among the plurality of gate signals GS1 to GS4 can be output through the output terminal 104.

[0171] The first power input terminal 105 can be connected to a first gate power line GPL1 for transmitting a first gate power voltage VGL. The first gate power line GPL1 can correspond to Figure 5 the first scan power line SPL1, the third scan power line SPL3, and the first emission power line EPL1 as illustrated in FIG. 1. For example, the first power input terminal 105 can be connected to the first scan power line SPL1 for transmitting the first low voltage VGL1.

[0172] The second power input terminal 106 can be connected to a second gate power line GPL2 for transmitting a first gate power voltage VGL. The second gate power line GPL2 can correspond to Figure 5 the second scan power line SPL2, the fourth scan power line SPL4, and the second emission power line EPL2 as illustrated in FIG. 1. For example, the second power input terminal 106 can be connected to the second scan power line SPL2 for transmitting the first low voltage VGL1.

[0173] As described above, the plurality of stages ST1 to ST4 can be connected to two gate power lines GPL1 and GPL2 for transmitting a first gate power voltage VGL.

[0174] The third power input terminal 107 can be connected to a third gate power line GPL3 for transmitting a second gate power voltage VGH. The third gate power line GPL3 can correspond to Figure 5 the third power line PL3 and the fourth power line PL4 as illustrated in FIG. 1. For example, the third power input terminal 107 can be connected to the third power line PL3 for transmitting the first high voltage VGH1.

[0175] Figure 8 is an exemplary circuit diagram illustrating Figure 7 a plurality of stages STi and STi+1 of the gate driver 200 as illustrated in FIG. 1.

[0176] Referring to Figure 5 , Figure 7 and Figure 8 , each of an i-th stage STi (i is a natural number) and an (i+1)-th stage STi+1 can include an input unit 11, an output unit 12, a first signal processor 13, a second signal processor 14, and a stabilizer 15.

[0177] As Figure 8As illustrated in FIG. 1, the first clock signal CLK1 is supplied to the second input terminal 102 and the second clock signal CLK2 is supplied to the third input terminal 103 in the i-th stage STi (e.g., an odd-numbered stage). In the i+1-th stage STi+1 (e.g., an even-numbered stage), the second clock signal CLK2 can be supplied to the second input terminal 102 and the first clock signal CLK1 can be supplied to the third input terminal 103. The i+1-th stage STi+1 can output a gate signal to the i+1-th gate line Gi+1.

[0178] In an embodiment, the start pulse SSP can be supplied to the first input terminal 101 of the first stage ST1 and a gate signal of a previous gate line can be supplied to the first input terminal 101 of each of the other stages.

[0179] Hereinafter, the i-th stage STi designated as a stage will be described in more detail.

[0180] The input unit 11 can control a voltage of the first node N1 and a voltage of the second node N2 in response to signals supplied to the first input terminal 101 and the second input terminal 102. In an embodiment, the input unit 11 can include a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0181] The fourth transistor T4 can be connected between the first input terminal 101 and the first node N1. The fourth transistor T4 can include a gate electrode connected to the second input terminal 102. The fourth transistor T4 can be turned on when the first clock signal CLK1 has a gate-on level (e.g., a low level) to electrically connect the first input terminal 101 and the first node N1.

[0182] The fifth transistor T5 can be connected between the second input terminal 102 and the second node N2. The fifth transistor T5 can include a gate electrode connected to the first node N1. The fifth transistor T5 can be turned on or turned off based on a voltage of the first node N1.

[0183] The sixth transistor T6 can be connected between the second power input terminal 106 supplied with the first gate power voltage VGL and the second node N2. A gate electrode of the sixth transistor T6 can be connected to the second input terminal 102. The sixth transistor T6 can be turned on when the first clock signal CLK1 is supplied to the second input terminal 102 to supply the first gate power voltage VGL to the second node N2.

[0184] The output unit 12 can supply the first gate power voltage VGL or the second gate power voltage VGH to the output terminal 104 based on a voltage of the third node N3 and a voltage of the fourth node N4. The gate signal can be determined as a first scan signal, a second scan signal, a third scan signal, or an emission control signal.

[0185] In an embodiment, the output unit 12 can include a seventh transistor T7 and an eighth transistor T8.

[0186] The seventh transistor T7 can be connected between the second power input terminal 106 and the output terminal 104. A gate electrode of the seventh transistor T7 can be connected to the third node N3. The seventh transistor T7 can be turned on or off in response to a voltage of the third node N3. When the seventh transistor T7 is turned on, a gate signal supplied to the output terminal 104 can have a low level (e.g., a gate off voltage of an N-type transistor).

[0187] The eighth transistor T8 can be connected between the third power input terminal 107 supplied with the second gate power voltage VGH and the output terminal 104. A gate electrode of the eighth transistor T8 can be connected to the fourth node N4. The eighth transistor T8 can be turned on or off in response to a voltage of the fourth node N4. When the eighth transistor T8 is turned on, a gate signal supplied to the output terminal 104 can have a high level (e.g., a gate on voltage of an N-type transistor).

[0188] The first signal processor 13 can control the voltage of the fourth node N4. For example, when the voltage of the second node N2 has a high level, the first signal processor 13 can make the voltage of the fourth node N4 stably have a gate off level (or a high level), thereby being able to completely turn off the eighth transistor T8. Also, the first signal processor 13 can control the voltage of the fourth node N4 to have a gate on level (or a low level) by using a low level of the second node N2.

[0189] In an embodiment, the first signal processor 13 can include a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a second capacitor C2, and a third capacitor C3.

[0190] A first terminal of the second capacitor C2 can be connected to the fifth node N5. A second terminal of the second capacitor C2 can be connected between the ninth transistor T9 and the tenth transistor T10.

[0191] The ninth transistor T9 can be connected between the second terminal of the second capacitor C2 and the fourth node N4. A gate electrode of the ninth transistor T9 can be connected to the third input terminal 103. The ninth transistor T9 can be turned on in response to a gate on level (e.g., a low level) of the second clock signal CLK2 supplied to the third input terminal 103.

[0192] The tenth transistor T10 can be connected between the second terminal of the second capacitor C2 and the third input terminal 103. A gate electrode of the tenth transistor T10 can be connected to the fifth node N5. The tenth transistor T10 can be turned on or off in response to a voltage of the fifth node N5.

[0193] The eleventh transistor T11 can be connected between the third power input terminal 107 and the fourth node N4. A gate electrode of the eleventh transistor T11 can be connected to the first node N1. The eleventh transistor T11 can be turned on or off in response to a voltage of the first node N1.

[0194] The third capacitor C3 can be connected between the third power input terminal 107 and the fourth node N4. The third capacitor C3 can charge a voltage applied to the fourth node N4 and stably maintain the voltage of the fourth node N4.

[0195] The stabilizer 15 can be electrically connected between the input unit 11 and the output unit 12. The stabilizer 15 can limit the amount of voltage drop in the first node N1 and the amount of voltage drop in the second node N2. Furthermore, the stabilizer 15 can function as a resistor when the voltage of the fifth node N5 is significantly lowered due to the coupling of the second capacitor C2. Accordingly, it is possible to protect the fifth transistor T5 and the sixth transistor T6 connected to the second node N2.

[0196] In an embodiment, the stabilizer 15 can include a twelfth transistor T12 and a thirteenth transistor T13.

[0197] The twelfth transistor T12 can be connected between the first node N1 and the third node N3. A gate electrode of the twelfth transistor T12 can be connected to the second power input terminal 106. Accordingly, the twelfth transistor T12 can have an on state.

[0198] The thirteenth transistor T13 can be connected between the second node N2 and the fifth node N5. A gate electrode of the thirteenth transistor T13 can be connected to the first power input terminal 105 to which the first gate power supply voltage VGL is supplied. Accordingly, the thirteenth transistor T13 can have an on state. Accordingly, it is possible to protect the fifth transistor T5 and the sixth transistor T6 from voltage variation in the fifth node N5.

[0199] In an embodiment, the second signal processor 14 can include a first transistor T1, a second transistor T2, a third transistor T3, a fourteenth transistor T14, and a first capacitor C1.

[0200] The first transistor T1 can be connected between the third node N3 and the sixth node N6. A gate electrode of the first transistor T1 can be connected to the sixth node N6. For example, the first transistor T1 can have a diode form in which the first transistor T1 is connected in a direction from the third node N3 to the sixth node N6.

[0201] In an embodiment, the second transistor T2 can be connected between the first input terminal 101 and the sixth node N6. A gate electrode of the second transistor T2 can be connected to the second input terminal 102. The second transistor T2 can be turned on to provide a signal supplied to the first input terminal 101 to the sixth node N6 when the first clock signal CLK1 is supplied to the second input terminal 102.

[0202] When a signal having a high level is supplied to the first input terminal 101, the first transistor T1 can function as a reverse diode, and thus, a voltage of the sixth node N6 can have no influence on the third node N3.

[0203] The third transistor T3 can be connected between the third input terminal 103 and an electrode of the first capacitor C1. For example, a first electrode of the third transistor T3 can be connected to the third input terminal 103, and a second electrode of the third transistor T3 can be connected to the first capacitor C1. The third transistor T3 can include a gate electrode connected to the sixth node N6. The third transistor T3 can be turned on or turned off in response to a voltage of the sixth node N6.

[0204] The first capacitor C1 can be connected between the sixth node N6 and the second electrode of the third transistor T3. According to a voltage change of the second electrode of the third transistor T3, a voltage level of the sixth node N6 can swing within a predetermined range due to the coupling of the first capacitor C1. That is, the voltage of the sixth node N6 can follow a change in the voltage level of the second clock signal CLK2.

[0205] The first transistor T1 diode-connected between the sixth node N6 and the third node N3 can operate as a charge pump. For example, a voltage of the sixth node N6 having a form similar to an AC voltage can be converted into a form such as a DC voltage at the third node N3 by the first transistor T1 functioning as a charge pump.

[0206] In this manner, although the voltage of the sixth node N6 can change, the voltage of the third node N3 can be maintained at a constant level by the first transistor T1 functioning as a charge pump.

[0207] The fourteenth transistor T14 can be connected between the second transistor T2 and the sixth node N6. A gate electrode of the fourteenth transistor T14 can be connected to the first power input terminal 105. Thus, the fourteenth transistor T14 can have a turned-on state. In this manner, a bias stress that can be applied to the second transistor T2 can be reduced.

[0208] In an embodiment, the first gate power line GPL1 and the second gate power line GPL2 can be disposed at both sides of the stage STi. Some transistors capable of being more easily connected to the first gate power line GPL1 can be connected to the first gate power line GPL1 to receive the first gate power voltage VGL, and other transistors can be connected to the second gate power line GPL2 to receive the first gate power voltage VGL. Accordingly, output stability of a gate signal can be improved.

[0209] Figure 9 is an exemplary plan view illustrating a gate driver 200B included in the display device 1000 shown in Figure 1 is a schematic plan view of the gate driver 200B shown in Figure 10 is a waveform diagram of signals output from the gate driver 200B shown in Figure 9

[0210] Referring to Figure 1 , Figure 2 , Figure 3 , Figure 9 , and Figure 10 , the gate driver 200B can include a first scan driver 220, a second scan driver 240, an emission driver 260, and a dummy scan driver 280.

[0211] The dummy scan driver 280 can be disposed in a non-display area of the substrate 1. The dummy scan driver 280 can supply a second scan signal to some of the plurality of second scan lines S2_1 to S2_i. In an embodiment, the dummy scan driver 280 can include a plurality of dummy stages sequentially outputting the second scan signal to some of the plurality of second scan lines S2_1 to S2_i.

[0212] As shown in Figure 9 , the pixel PXkj can connect the k-th (k is a natural number) first scan line S1_k, the k-th second scan line S2_k, the k-th third scan line S3_k, and the k-th emission control line E_k. The k-th second scan line S2_k can be connected to the dummy scan driver 280, and the k-th third scan line S3_k can be connected to the second scan driver 240.

[0213] The second scan driver 240 outputs both a second scan signal and a third scan signal offset from the second scan signal by a predetermined period, and thus the number of scan drivers can be reduced. However, since the second scan signal and the third scan signal are output from one second scan driver 240, some of the plurality of scan lines can not be supplied with a scan signal. Thereby, the dummy scan driver 280 can complement the lack of a scan signal.

[0214] Figure 10 ​Signals supplied to the scan lines and the emission control lines connected to the partial of the pixel unit 100 are exemplarily shown. For example, in Figure 10 Some of the scan signals and the emission control signals supplied to the first to twelfth pixel rows are shown in

[0215] The emission driver 260 can sequentially supply the emission control signals to the plurality of emission control lines E1 to E12. Two consecutive emission control lines can share one emission control signal. For example, an emission control signal having the same timing can be supplied to the first emission control line E1 and the second emission control line E2. The sharing structure of the emission control lines can improve the image quality of high frequency image driving of the high resolution display device.

[0216] The first scan driver 220 can sequentially supply the first scan signals to the plurality of first scan lines S1_1 to S1_12. The first scan driver 220 can supply the first scan signals at different timings for each pixel row so as to correspond to the supply of the data signals. In an embodiment, the pulse width of the first scan signal (width of the gate-on period) can correspond to about one horizontal period 1H.

[0217] The second scan driver 240 can supply the third scan signals to the plurality of third scan lines S3_1 to S3_12. Two consecutive third scan lines can share one third scan signal.

[0218] As described above with reference to Figure 3 , the third scan signal supplied to the pixel PXkj can be a signal offset by a predetermined horizontal period from the second scan signal. More specifically, after the gate voltage of the first transistor M1 is initialized by the second scan signal, data writing and threshold voltage compensation can be performed by the third scan signal.

[0219] In an embodiment, as shown in Figure 10 , the third scan signal supplied to the first pixel row can be the same as a signal offset by 10 horizontal periods 10H from the second scan signal supplied to the first pixel row. The third scan signals supplied to the plurality of third scan lines S3_1 and S3_2 corresponding to the first and second pixel rows can be supplied to the plurality of second scan lines S2_11 and S2_12 corresponding to the eleventh and twelfth pixel rows. In this case, the second scan driver 240 can not generate the second scan signals supplied to the plurality of second scan lines S2_1 to S2_10 of the first to tenth pixel rows.

[0220] According to an embodiment, the dummy scan driver 280 can generate second scan signals supplied to the plurality of second scan lines S2_1 to S2_10 of the first to tenth pixel rows. Specifically, the dummy scan driver 280 can supply the second scan signals to the plurality of second scan lines S2_1 to S2_10 of the initial pixel row corresponding to a time difference between the second scan signal and the third scan signal supplied to one pixel row.

[0221] Figure 11A and Figure 11B is a view illustrating a connection between the gate driver 200B shown in Figure 9 and the plurality of pixel rows.

[0222] Referring to Figure 9 , Figure 10 , Figure 11A and Figure 11B , the second scan driver 240 can be connected to some of the plurality of second scan lines S2_1 to S2_12 and the plurality of third scan lines S3_1 to S3_12, and the dummy scan driver 280 can be connected to the remaining second scan lines S2_1 to S2_12.

[0223] Figure 11A and Figure 11B illustrates an example of a connection between the gate driver 200B shown in Figure 10 and the plurality of pixel rows PXR1 to PXR12.

[0224] The first scan driver 220 can include a plurality of write stages WST1 to WST12 corresponding to the plurality of pixel rows PXR1 to PXR12, respectively. The plurality of write stages WST1 to WST12 can be connected to the plurality of first scan lines S1_1 to S1_12, respectively.

[0225] The emission driver 260 can include a plurality of emission stages EST1 to EST6. Each of the plurality of emission stages EST1 to EST6 can be connected to two consecutive emission control lines. For example, the first emission stage EST1 can be connected to an emission control line E1 of the first pixel row PXR1 and an emission control line E2 of the second pixel row PXR2. Accordingly, the number of the plurality of emission stages EST1 to EST6 can be half of the number of the plurality of pixel rows PXR1 to PXR12.

[0226] The second scan driver 240 can include a plurality of compensation stages CST1 to CST6. Each of the plurality of compensation stages CST1 to CST6 can be connected to two consecutive third scan lines. Accordingly, the number of the plurality of compensation stages CST1 to CST6 can be half of the number of the plurality of pixel rows PXR1 to PXR12.

[0227] For example, the first compensation stage CST1 can be connected to the third scan line S3_1 of the first pixel row PXR1, the third scan line S3_2 of the second pixel row PXR2, the second scan line S2_11 of the eleventh pixel row PXR11, and the second scan line S2_12 of the twelfth pixel row PXR12. The same scan signal can be supplied to the third scan line S3_1 of the first pixel row PXR1, the third scan line S3_2 of the second pixel row PXR2, the second scan line S2_11 of the eleventh pixel row PXR11, and the second scan line S2_12 of the twelfth pixel row PXR12. The third scan signal supplied to the third scan line S3_1 of the first pixel row PXR1 can be the same as a signal offset by 10 horizontal periods 10H from the second scan signal supplied to the second scan line S2_1 of the first pixel row PXR1.

[0228] The second scan driver 240 can not supply the second scan signal to the plurality of second scan lines S2_1 to S2_10 of the ten initial pixel rows. That is, when the pixel unit 100 includes n (n is a natural number greater than k+1) pixel rows, the second scan driver 240 can be connected to the third scan lines of the first to k-th pixel rows, and connected to the second and third scan lines of the k+1-th to n-th pixel rows.

[0229] The dummy scan driver 280 can include a plurality of dummy stages DST1, DST2,..., DSTn. The dummy scan driver 280 can supply the second scan signal to the plurality of second scan lines S2_1 to S2_10 of the ten initial pixel rows. In other words, the dummy scan driver 280 can be connected to the second scan lines of the initial pixel rows corresponding to the difference between the supply times of the second scan signal and the third scan signal. In an embodiment, the output of the last dummy stage of the dummy scan driver 280 can be supplied as the input of the first stage (i.e., the first compensation stage CST1) of the second scan driver 240.

[0230] Each of the plurality of dummy stages DST1, DST2,..., DSTn can be connected to two consecutive second scan lines. For example, the first dummy stage DST1 can be connected to the second scan line S2_1 of the first pixel row PXR1 and the second scan line S2_2 of the second pixel row PXR2. Accordingly, the number of the plurality of dummy stages DST1, DST2,..., DSTn can be half the number of the plurality of pixel rows PXR1 to PXR12. When the difference between the supply times of the second scan signal and the third scan signal to the same pixel row is 10 horizontal periods 10H, the dummy scan driver 280 can include five dummy stages DST1, DST2,..., DST5.

[0231] Accordingly, it is possible to reduce the number of stages of the gate driver 200B, and it is possible to reduce the dead space of the display device.

[0232] Figure 12 is an example of a diagram illustrating Figure 9 the connection between the gate driver 200B and the plurality of pixel rows shown in FIG. 10.

[0233] Except that the stages of the emission driver 260A and the second scan driver 240A are connected one-to-one to the pixel rows, Figure 12 the configuration shown in FIG. 11 is the same as the configuration described with reference to Figure 11A and Figure 11B Accordingly, the same or corresponding components as those shown in Figure 11A and Figure 11B are designated by the same reference numerals, and a repeated description thereof will be omitted.

[0234] With reference to Figure 9 and Figure 12 , the second scan driver 240A can be connected to some of the plurality of second scan lines S2_1 to S2_12 (e.g., S2_11 and S2_12) and the plurality of third scan lines S3_1 to S3_12, and the dummy scan driver 280A can be connected to the remaining second scan lines S2_1 to S2_12.

[0235] For example, the emission driver 260A can include a plurality of emission stages EST1 to EST12. The plurality of emission stages EST1 to EST12 can be connected one-to-one to the plurality of pixel rows PXR1 to PXR12. Accordingly, the number of the plurality of emission stages EST1 to EST12 can be equal to the number of the plurality of pixel rows PXR1 to PXR12.

[0236] The second scan driver 240A can include a plurality of compensation stages CST1 to CST12. Each of the plurality of compensation stages CST1 to CST12 can be connected to one third scan line. The plurality of compensation stages CST1 to CST12 can be connected one-to-one to the pixel rows PXR1 to PXR12. Accordingly, the number of the plurality of compensation stages CST1 to CST12 can be equal to the number of the plurality of pixel rows PXR1 to PXR12.

[0237] The dummy scan driver 280A can supply a second scan signal to the plurality of second scan lines S2_1 to S2_10 of the ten initial pixel rows. The plurality of dummy stages DST1, DST2,... can be connected one-to-one to some of the plurality of second scan lines. When the difference between the supply times of the second scan signal and the third scan signal to the same pixel row is 10 horizontal periods 10H, the dummy scan driver 280A can include ten dummy stages DST1, DST2,..., DST10.

[0238] However, this is merely illustrative, and the correspondence between the stages and the pixel rows is not limited thereto. For example, in some embodiments, each of the plurality of emission stages EST1 to EST12 can be connected to three or more emission control lines, according to the design of the display device.

[0239] As described above, the display device according to the embodiments includes a dummy scan driver having a small size that supplies a scan signal to some of the plurality of initial pixel rows, to enable the configuration of two scan drivers for respectively generating a second scan signal and a third scan signal to be integrated into one. In this manner, the area of a non-display region (dead space) can be reduced.

[0240] Further, the power supply line for transmitting the gate power supply voltage to the second scan driver can be electrically and physically separated from the power supply line for transmitting the gate power supply voltage to the first scan driver and the emission driver. Accordingly, in low frequency driving in which the first period (display scan period) and at least one second period (bias scan period) are included in one frame period, image flicker that can occur due to a difference between the amount of voltage drop of the gate power supply voltage during the first period and the second period can be prevented or minimized.

[0241] While certain embodiments and implementations have been described herein, other embodiments and modifications will occur to those skilled in the art. Accordingly, the present inventive concept is not limited to these embodiments, but is to be accorded the broadest scope in accordance with the principles and various features disclosed herein and as claimed below.

Claims

1. A display device, comprising: Substrate, the substrate including a display area and a non-display area; Pixels, which are arranged in the display area and connected to a first scan line, a second scan line, a third scan line and an emission control line; A first scan driver is disposed in the non-display area and configured to supply a first scan signal to the first scan line; A second scan driver is disposed in the non-display area and configured to supply a second scan signal to some of the plurality of second scan lines and to supply a third scan signal to the third scan line; A transmitter driver is disposed in the non-display area and configured to supply a transmitter control signal to the transmitter control line; A first pad and a second pad are arranged in the non-display area and spaced apart from each other; A first power line is connected to the first pad to transmit a first voltage to the first scan driver and the transmit driver; as well as A second power line, connected to the second pad, is used to transmit a second voltage to the second scan driver. The first power line branches off in the non-display area to connect to the first scan driver and the transmit driver.

2. The display device according to claim 1, wherein, The first voltage is the same as the second voltage.

3. The display device according to claim 2, wherein, In the non-display area, the second power line has no electrical or physical connection to the first power line.

4. The display device according to claim 1, further comprising: The third pad and the fourth pad are arranged in the non-display area and spaced apart from each other; A third power line is connected to the third pad to transmit a third voltage, which is higher than the first voltage, to the first scan driver and the transmit driver. as well as A fourth power line is connected to the fourth pad to transmit a fourth voltage, which is higher than the second voltage, to the second scan driver.

5. The display device according to claim 4, wherein, The third power line branches off in the non-display area to connect to the first scan driver and the transmit driver.

6. The display device according to claim 4, wherein, The third voltage is the same as the fourth voltage.

7. The display device according to claim 6, wherein, In the non-display area, the fourth power line has no electrical or physical connection with the third power line.

8. The display device according to claim 4, wherein, Each of the first scan driver, the second scan driver, and the transmit driver includes multiple stages; and Each of the plurality of stages includes a first power input terminal, a second power input terminal, and a third power input terminal.

9. The display device according to claim 8, wherein, The first power line branch is a first scan power line, a second scan power line, a first transmit power line, and a second transmit power line; The first scan power line and the second scan power line are connected to the plurality of stages of the first scan driver; and The first transmit power line and the second transmit power line are connected to the plurality of stages of the transmit driver.

10. The display device according to claim 9, wherein, The first scan power line is connected to the first power input terminal; The second scan power line is connected to the second power input terminal; and The third power line is connected to the third power input terminal.

11. The display device according to claim 8, wherein, The second power line branch is a third scan power line and a fourth scan power line; and The third and fourth scan power lines are connected to the plurality of stages of the second scan driver.

12. The display device according to claim 1, further comprising a dummy scan driver, wherein, The dummy scan driver is arranged in the non-display area and configured to supply the second scan signal to the remaining plurality of second scan lines.

13. The display device according to claim 12, wherein, The dummy scan driver includes multiple dummy stages configured to sequentially output the second scan signal.

14. The display device according to claim 13, wherein, The output of the last dummy stage of the dummy scan driver is supplied as the input of the first stage of the second scan driver.

15. The display device according to claim 13, wherein, The third scan signal supplied to the i-th pixel row is the same as the signal offset from the second scan signal by a predetermined k horizontal time intervals, where i is a positive integer and k is an integer of 8 or greater; and The widths of the gate conduction periods of the first scan signal, the second scan signal, and the transmit control signal are different from each other.

16. The display device according to claim 15, wherein, Each of the plurality of dummy levels is connected to the second scan line of two or more consecutive pixel rows; and The dummy scan driver is connected to the second scan line from the first pixel row to the k-th pixel row.

17. The display device according to claim 16, wherein, The second scan driver is connected to the third scan line from the first pixel row to the k-th pixel row, and is also connected to the second scan line and the third scan line from the (k+1)-th pixel row to the n-th pixel row, where n is an integer greater than k+1.

18. The display device according to claim 17, wherein, The first stage of the second scan driver is connected to the third scan line of the first pixel row and the second scan line of the (k+1)th pixel row.

19. A display device, comprising: A pixel, wherein the pixel is connected to a first scan line, a second scan line, a third scan line, and an emission control line; A first scan driver, configured to supply a first scan signal to the first scan line; A second scan driver is configured to supply a second scan signal to some of a plurality of second scan lines and to supply a third scan signal to the third scan line; A transmitter driver configured to supply a transmitter control signal to the transmitter control line; as well as A dummy scan driver, the dummy scan driver including multiple dummy stages configured to supply the second scan signal to the remaining multiple second scan lines, The dummy scan driver is connected to the second scan line located in the display area from the first pixel row to the k-th pixel row, where k is an integer greater than 1. The second scan driver is connected to the third scan line from the first pixel row to the k-th pixel row, and is also connected to the second scan line and the third scan line from the (k+1)-th pixel row to the n-th pixel row, where n is an integer greater than k+1.

Images