Delay Locked Loop Circuit

Abstract

The present invention discloses a delay locked loop circuit, which includes a delay circuit, a first phase detector, a second phase detector, and a counting control circuit. The delay circuit is used to delay a reference clock signal to output a delayed clock signal; the first phase detector is used to generate a phase difference signal; the second phase detector is used to generate a judgment signal; the counting control circuit generates a control delay signal according to the phase difference signal and the judgment signal, wherein the delay circuit outputs the delayed clock signal according to the control delay signal, and wherein the counting control circuit switches between a first mode with a first update frequency and a second mode with a second update frequency according to the phase difference signal and the judgment signal, and the first update frequency is lower than the second update frequency.

Description

Technical Field

[0001] The invention belongs to the field of delay-locked loop (DLL), and in particular relates to a delay-locked loop circuit with multiple modes. Background Art

[0002] According to the current specifications of Dynamic Random Access Memory (DRAM), DRAM products (especially the fourth generation double-data-rate (DDR4) memory) need better voltage and power stability. For faster and faster transmission speeds, even a slight power change will cause output data jitter and deteriorate the eye diagram of the output data. When the eye diagram of the output data is too poor, the system cannot read the correct data, causing the system to fail. Therefore, for the field of high transmission speed, the delay-locked loop (DLL) circuit needs to be improved to reduce jitter. To reduce jitter during data reading, different command sequences or different data reading modes actually lead to different internal voltage states. For example, the first instruction (bank active command) before reading consumes a lot of current, so a time signal (such as tAC signal) will generate a lot of delay at the beginning, and jitter will be generated when the delay is locked. Therefore, a novel method and related architecture are needed to achieve delay jitter reduction and fast delay lock without side effects or with less possibility of side effects and solve the problem. Summary of the invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides a delay locked loop circuit with multiple modes, which can effectively change the cycle and step size according to different reading states to solve the above problems.

[0004] An embodiment of the present invention discloses a delay locked loop circuit, comprising a delay circuit, a first phase detector, a second phase detector and a counting control circuit, wherein the delay circuit is used to receive a reference clock signal from an external source, and delay the reference clock signal to output a delayed clock signal, the first phase detector is used to receive the reference clock signal and the delayed clock signal, and detect a phase difference between the reference clock signal and the delayed clock signal to generate a phase difference signal, the second phase detector is used to receive the delayed clock signal delayed by a predetermined time, and detect the delayed clock signal delayed by the predetermined time to generate a judgment signal, and the counting control circuit is used to receive the delayed clock signal delayed by a predetermined time, and detect the delayed clock signal delayed by the predetermined time to generate a judgment signal, and the counting control circuit is used to receive the delayed clock signal delayed by a predetermined time, and detect the delayed clock signal delayed by the predetermined time to generate a judgment signal. A circuit is used to receive the phase difference signal and the judgment signal, and generate a control delay signal according to the phase difference signal and the judgment signal, wherein the delay circuit delays the reference clock signal according to the control delay signal to output the delayed clock signal, wherein the count control circuit has a first mode and a second mode, and the count control circuit switches the first mode and the second mode according to the phase difference signal and the judgment signal, and when the count control circuit is in the first mode, it has a first update frequency, and when the count control circuit is in the second mode, it has a second update frequency, and the first update frequency is lower than the second update frequency.

[0005] Compared with the prior art, the count control circuit of the delay locked loop circuit of the present invention has multiple modes (including a first mode and a second mode). When reading data starts and a large amount of delay is generated, the delay locked loop circuit can quickly lock the delay through the second mode, and after the delay is less than a predetermined time, the delay locked loop circuit can switch to the first mode to reduce the delay jitter that is not conducive to reading data. Furthermore, when the delay locked loop circuit is in the second mode, it can also be used to receive a time shift control signal to accelerate the locking delay through a delay clock signal shifting operation, and perform a compensation operation on the delay clock signal shifting operation when switching to the first mode. According to this configuration, the delay locked loop circuit of the present invention can achieve delay lock more quickly when reading data starts, so that the eye diagram of the output data becomes better and the delay jitter is effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a delay locked loop circuit according to an embodiment of the present invention.

[0007] Figure 2 FIG. 4 is a schematic diagram of a counting control circuit having multiple modes according to an embodiment of the present invention.

[0008] Figure 3FIG. 4 is a waveform diagram of a delayed clock signal output by a delay locked loop circuit in different modes according to an embodiment of the present invention.

[0009] Figure 4 FIG. 4 is a waveform diagram of a delayed clock signal output by a delay locked loop circuit in different modes and shifting operations according to an embodiment of the present invention.

[0010] The reference numerals are described as follows:

[0011] Delay locked loop circuit-10; delay circuit-12; first phase detector-14; counting control circuit-16; delay locked loop delay line-18; data output control circuit-20; second phase detector-22; delayer-24; read instruction detector-26. DETAILED DESCRIPTION

[0012] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a delay locked loop circuit 10 according to an embodiment of the present invention. Figure 1As shown, the delay locked loop circuit 10 includes a delay circuit 12, a first phase detector 14, a count control circuit 16, a second phase detector 22 and a delayer 24. The delay circuit 12 is used to receive a reference clock signal from the outside (for example, a reference clock signal of a dynamic random access memory (DRAM)), and delay the reference clock signal to output a delayed clock signal, and the delayed clock signal can be output to a clock signal tree (for example, a clock signal tree of a DRAM), and then output the delayed clock signal from the clock signal tree through an output driving circuit. The first phase detector 14 can be used to receive the reference clock signal and the delayed clock signal, and to detect a phase difference between the reference clock signal and the delayed clock signal to generate a phase difference signal. The delayer 24 can be used to delay the delayed clock signal by a predetermined time (for example, 30 picoseconds), and the second phase detector 22 can be used to receive the delayed clock signal delayed by the predetermined time, and detect the delayed clock signal delayed by the predetermined time to generate a determination signal. The counting control circuit 16 can be used to receive the phase difference signal and the judgment signal, and generate a control delay signal and a time shift control signal according to the phase difference signal and the judgment signal. The delay circuit delays the reference clock signal according to the control delay signal to output a delayed clock signal. For example, the delay circuit 12 includes a delay locked loop delay line 18 and a data output control circuit 20. The delay locked loop delay line 18 can receive the control delay signal and delay the reference clock signal according to the control delay signal. The data output control circuit 20 can receive the time shift control signal and output the delayed clock signal. The time shift control signal is used to control the data output control circuit to perform a translation operation on the delayed clock signal. The counting control circuit 16 has a first mode and a second mode, and the counting control circuit 16 can switch between the first mode and the second mode according to the instruction requirements of the external circuit and according to the phase difference signal and the judgment signal. The difference between the first mode and the second mode is that at least one of the update frequency and the delay step size of the two modes is different. For example, when the counting control circuit 16 is in the first mode, it has a first update frequency and a first delay step, and when the counting control circuit 16 is in the second mode, it has a second update frequency and a second delay step, and the first update frequency is lower than the second update frequency, and the first delay step is not greater than the second delay step.In addition, the DLL circuit 10 may further include a read command detector 26 connected to the count control circuit 16. The DLL circuit 10 detects an external circuit command through the read command detector 26. For example, the read command detector 26 may be implemented by a logic circuit.

[0013] The circuit connection of the delay locked loop circuit 10 is as follows: Figure 1 As shown: the reference clock signal is input to the first input end of the delay locked loop delay line 18, the output end of the delay locked loop delay line 18 is connected to the first input end of the data output control circuit 20, and the output end of the data output control circuit 20 outputs the delayed clock signal; the reference clock signal and the delayed clock signal are respectively input to the first input end and the second input end of the phase detector 14, the output end of the phase detector 14 is connected to the first input end of the counting control circuit 16, the first output end and the second output end of the counting control circuit 16 are respectively connected to the second input end of the delay locked loop delay line 18 and the second input end of the data output control circuit 20; the delayed clock signal is input to the input end of the delayer 24, the output end of the delayer 24 is connected to the input end of the second phase detector 22, and the output end of the second phase detector is connected to the second input end of the counting control circuit 16; the output end of the read instruction detector 26 is connected to the third input end of the counting control circuit 16. Among them, the delay locked loop delay line 18 and the data output control circuit 20 together constitute the delay circuit 12.

[0014] Please refer to Figure 2 , Figure 2 FIG. 1 is a schematic diagram showing that the counting control circuit 16 has multiple modes according to an embodiment of the present invention. Figure 2As shown, the count control circuit 16 receives the phase difference signal and the judgment signal, and generates the control delay signal according to the phase difference signal and the judgment signal, wherein the control delay signal can control the update frequency and delay step of the delay locked loop delay line 18, and further, the count control circuit 16 also generates the time shift control signal according to the phase difference signal and the judgment signal. In other words, the delay locked loop delay line 18 can adjust its update frequency and delay step according to the control delay signal and the judgment signal, and the data output control circuit 20 can perform a translation operation on the delayed clock signal according to the time shift control signal and the judgment signal. Furthermore, the count control circuit 16 is also used to receive an external circuit instruction through the read instruction detector 26, and switch the first mode and the second mode according to the external circuit instruction. For example, when the external circuit instruction received by the count control circuit 16 is a read start instruction, the count control circuit 16 is controlled to be in the second mode, and the count control circuit 16 has a second update frequency and a second delay step. The count control circuit 16 then controls the delay lock loop delay line 18 to use a second update frequency and a second delay step to perform delay locking through the control delay signal, wherein the second update frequency may be higher than the first update frequency, and the second delay step may be not less than the first delay step. For example, the second update frequency is to update the delay after 8 edges of the reference clock signal ( Figure 2 The second delay step is 20 picoseconds per update delay adjustment ( Figure 2 For simplicity, it is indicated as "20 picoseconds" in the figure). For another example, when the judgment signal indicates that the phase difference of the delayed clock signal is less than the predetermined time (for example, 30 picoseconds), the counting control circuit 16 is controlled to be in the first mode, and the counting control circuit 16 has a first update frequency and a first delay step. Similarly, the counting control circuit 16 controls the delay lock loop delay line 18 to use the first update frequency and the first delay step to perform delay locking through the control delay signal, wherein the first update frequency may be lower than the second update frequency, and the first delay step may be no greater than the second delay step, for example, the first update frequency is the update delay after 16 edges of the reference clock signal ( Figure 2 The first delay step is 10 picoseconds per update delay adjustment ( Figure 2 Furthermore, the count control circuit 16 sends the time shift control signal to the data output control circuit 20 to perform a shift operation, which can shift the output delayed clock signal 10 picoseconds earlier ( Figure 2denoted as -10 picoseconds for simplicity) and a translation of 0 picoseconds ( Figure 2 (denoted as “0 picoseconds” for simplicity)

[0015] According to the above configuration, the delay locked loop circuit 10 of the present invention can adjust different modes to have different update frequencies and delay steps according to the requirements of the external circuit instructions and the control delay signal and the judgment signal. Figure 3 , Figure 3 FIG. 1 is a waveform diagram of a delayed clock signal output by a delay locked loop circuit 10 in different modes according to an embodiment of the present invention. Figure 3 As shown, assuming that the external circuit starts to read data after reading the previous start command (bank active command), the delayed clock signal will be delayed by a longer time (for example, 80 picoseconds behind) than the reference clock signal. Figure 3 1 shows the difference between the delay locked loop circuit 10 using the first mode and the delay locked loop circuit 10 using the second mode. For example, when the delay locked loop circuit 10 receives a read start instruction, the count control circuit 16 is controlled to be in the second mode, so that the count control circuit 16 has the second update frequency (such as updating the delay after 8 edges of the reference clock signal) and the second delay step (such as adjusting the delay by 20 picoseconds each time), and the delay time of the delayed clock signal can be gradually locked with only a small number of reads. Compared with the first mode, the update frequency and delay step of the second mode use a shorter time to lock the delay of the delayed clock signal. It is worth noting that the delay lock in the second mode will generate jitter due to the higher update frequency and larger delay step. However, this jitter will only have a greater impact in the data reading state, and the impact of the delay jitter is smaller in the state where reading has just begun. In other words, the count control circuit 16 is controlled to be in the second mode, and compared with the first mode, the delay time can be reduced more quickly, so that the delay time after receiving the read start instruction is reduced. In this way, the improved delay time can make the eye diagram of the output data better, so that the entire circuit can face higher speed data reading and writing. In addition, when the delay time of the delayed clock signal is less than the predetermined time (for example, 30 picoseconds), the count control circuit 16 is controlled to be in the first mode, so that the count control circuit 16 has the first update frequency (such as 16 times the update delay after the edge of the reference clock signal) and the second delay step (such as 10 picoseconds for each update delay adjustment). By switching to the first mode, the delay lock of the delayed clock signal can be maintained without jitter, so as to facilitate the external circuit to read data.

[0016] The count control circuit 16 in the second mode can already achieve a rapid reduction in the delay time. The delay locked loop circuit 10 of the present invention can further perform a shift operation on the delayed clock signal according to the time shift control signal through the data output control circuit 20 to reduce the delay time more rapidly. Figure 4 , Figure 4 FIG. 1 is a waveform diagram of a delayed clock signal output by a delay locked loop circuit in different modes and shifting operations according to an embodiment of the present invention. Figure 4 Similarly, assuming that the external circuit starts to read data after reading the previous start instruction, the delayed clock signal will be delayed by a longer time (e.g., 80 picoseconds behind) than the reference clock signal. Figure 4 1 shows the difference between the delay locked loop circuit 10 using the first mode, the second mode, and the second mode and shifting 10 picoseconds earlier. For example, when the delay locked loop circuit 10 receives a read start instruction, the count control circuit 16 is controlled to be in the second mode, and performs a shift operation by sending the time shift control signal to the data output control circuit 20. In this embodiment, the data output control circuit 20 shifts the delayed clock signal 10 picoseconds earlier, but the present invention is not limited to this. The length of the shifting time can be determined according to the needs. Compared with using the second mode without shifting, using the second mode and shifting 10 picoseconds earlier can gradually lock the delay time of the delayed clock signal with only a small number of readings. In other words, when the count control circuit 16 is controlled to be in the second mode and the data output control circuit 20 shifts the delayed clock signal 10 picoseconds earlier, the delay time can be reduced more quickly, so that the delay time after receiving the read start instruction is reduced. In this way, the improved delay time can make the eye diagram of the output data better. In addition, when the delay time of the delayed clock signal is less than the predetermined time (for example, 30 picoseconds), the counting control circuit 16 is controlled to be in the first mode, and the counting control circuit 16 sends the time shift control signal to the data output control circuit 20 to shift the delayed clock signal by 10 picoseconds, so that the shift delay state of the delayed clock signal is switched to 0 picoseconds. In this way, the delay lock of the final delayed clock signal can be maintained without shifting.

[0017] Compared with the prior art, the counting control circuit of the delay locked loop circuit of the present invention has multiple modes (including a first mode and a second mode). When reading data starts and a large amount of delay is generated, the delay locked loop circuit can quickly lock the delay through the second mode, and after the delay is less than a predetermined time, the delay locked loop circuit can switch to the first mode to reduce the delay jitter that is not conducive to reading data. Furthermore, when the delay locked loop circuit is in the second mode, it can also be used to receive a time shift control signal to accelerate the locking delay through a delay signal shifting operation, and perform a compensation operation on the delay signal shifting operation when switching to the first mode. According to this configuration, after reading data starts, the delay locked loop circuit of the present invention can achieve delay lock more quickly, so that the eye diagram of the output data becomes better and the delay jitter is effectively reduced.

[0018] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A delay-locked loop circuit, characterized in that, the delay-locked loop circuit includes: a delay circuit for receiving a reference clock signal from the outside and delaying the reference clock signal to output a delayed clock signal; a first phase detector for receiving the reference clock signal and the delayed clock signal and detecting a phase difference between the reference clock signal and the delayed clock signal to generate a phase difference signal; a second phase detector for receiving the delayed clock signal delayed by a predetermined time and detecting the delayed clock signal delayed by the predetermined time to generate a judgment signal; and a count control circuit for receiving the phase difference signal and the judgment signal and generating a control delay signal based on the phase difference signal and the judgment signal, wherein the delay circuit delays the reference clock signal according to the control delay signal to output the delayed clock signal; wherein the count control circuit has a first mode and a second mode, and the count control circuit switches between the first mode and the second mode according to the phase difference signal and the judgment signal. When the count control circuit is in the first mode, it has a first update frequency. When the count control circuit is in the second mode, it has a second update frequency, and the first update frequency is lower than the second update frequency; when the phase difference is less than the predetermined time, the delay-locked loop circuit receives a continuous read instruction and the count control circuit is controlled to be in the first mode; when the delay-locked loop circuit receives a read start instruction, the count control circuit is controlled to be in the second mode.

2. The delay-locked loop circuit according to claim 1, characterized in that, the delay circuit includes: a delay-locked loop delay line for receiving the control delay signal and delaying the reference clock signal according to the control delay signal; and a data output control circuit for outputting the delayed clock signal.

3. The delay-locked loop circuit according to claim 2, characterized in that, the count control circuit sends a time shift control signal to the data output control circuit to control the data output control circuit to perform a translation operation on the delayed clock signal.

4. The delay-locked loop circuit according to claim 3, characterized in that, when the count control circuit is in the first mode, it does not send the time shift control signal. When the count control circuit is in the second mode, it sends the time shift control signal to control the data output control circuit to perform a translation operation on the delayed clock signal.

5. The delay-locked loop circuit according to claim 1, characterized in that, the second update frequency is 2 times the first update frequency.

6. The delay-locked loop circuit according to claim 1, characterized in that, the first update frequency is to update the delay after 16 edges of the reference clock signal.

7. The delay-locked loop circuit according to claim 1, characterized in that, The second update frequency updates the delay after 8 edges of the reference clock signal.

8. The delay locked loop circuit according to claim 1, wherein, when the counting control circuit is in the first mode, it has a first delay step, and when the counting control circuit is in the second mode, it has a second delay step, and the first delay step is not greater than the second delay step.

9. The delay locked loop circuit according to claim 8, wherein, the first delay step adjusts the delay by 10 picoseconds each time of update.

10. The delay locked loop circuit according to claim 8, wherein, the second delay step adjusts the delay by 20 picoseconds each time of update.

11. The delay locked loop circuit according to claim 1, wherein, the delay locked loop circuit further comprises: a read instruction detector electrically connected to the counting control circuit and used to detect a read start instruction from an external circuit; wherein when the read instruction detector detects the read start instruction, the counting control circuit is controlled to be in the second mode, so that the counting control circuit has the second update frequency.

12. The delay locked loop circuit according to claim 1, wherein, the delay locked loop circuit further comprises: a delay element to delay the delayed clock signal by the predetermined time.

Images