Rescuing bad blocks in a memory device

Abstract

This application relates to salvaging bad blocks in a memory device. Methods, systems, devices, memory devices, and machine-readable media for using non-defective portions of a memory block having defects on different portions are disclosed in some examples. Instead of disabling the entire block, the system can only disable a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Description

TECHNICAL FIELD

[0001] Embodiments relate to memory devices, such as NAND memory devices. Some embodiments relate to utilizing portions of memory blocks having defects by using good portions of blocks that are not affected by the defects. Some embodiments relate to combining good portions of defective blocks with other good portions of other defective blocks to form various virtual block structures. BACKGROUND

[0002] Memory devices for computers or other electronic devices can be classified as volatile and non-volatile memories. Volatile memories require power to maintain their data and include random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), among others. Non-volatile memories can retain stored data when not powered and include flash memory, read only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistance variable memory, phase change memory, storage class memory, resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically include one or more groups of transistors, such as floating gate or charge trap memory cells, that allow for high memory density, high reliability, and low power consumption. SUMMARY

[0004] One aspect of the disclosure provides a memory device comprising: a processor; a memory storing instructions that, when executed, cause the processor to perform operations comprising: receiving a request to perform an operation on a second portion of a block of memory cells, a first portion of the block of memory cells having a defect of a type from a first list of identified defect types and the second portion not having a defect of a type from a second list of identified defect types, a second set of identified defect types including a first set of identified defect types; identifying a bias voltage for the first portion of the block based on an operation type; performing the operation on the second portion, the performing the operation including disabling the first portion during the operation by applying a bias voltage to a word line of the first portion.

[0005] Another aspect of the disclosure provides a method for salvaging a portion of a defective block of a memory device, where the method includes receiving a request to perform an operation on a second portion of a block of memory cells, a first portion of the block of memory cells having a defect of a type from a first list of identified defect types and the second portion not having a defect of a type from a second list of identified defect types, the second set of identified defect types including the first set of identified defect types; identifying a bias voltage for the first portion of the block based on the type of operation; performing the operation on the second portion, the performing the operation including disabling the first portion during the operation by applying a bias voltage to word lines of the first portion.

[0006] Another aspect of the disclosure provides a machine-readable storage medium storing instructions that upon execution cause the machine to perform operations including receiving a request to perform an operation on a second portion of a block of memory cells, a first portion of the block of memory cells having a defect of a type from a first list of identified defect types and the second portion not having a defect of a type from a second list of identified defect types, the second set of identified defect types including the first set of identified defect types; identifying a bias voltage for the first portion of the block based on the type of operation; performing the operation on the second portion, the performing the operation including disabling the first portion during the operation by applying a bias voltage to word lines of the first portion. BRIEF DESCRIPTION OF DRAWINGS

[0007] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of similar components. The drawings illustrate generally, by way of example, various embodiments discussed in the present document.

[0008] Figure 1 A diagram showing a memory device, e.g., a storage device, in accordance with some examples of the disclosure.

[0009] Figure 2 An example schematic diagram showing a portion of a NAND architecture semiconductor memory array in accordance with some examples of the disclosure.

[0010] Figure 3 An example schematic diagram showing a 3D NAND architecture semiconductor memory in accordance with some examples of the disclosure.

[0011] Figure 4 An example block diagram showing a memory die in accordance with some examples of the disclosure.

[0012] Figure 5 A horizontal cross-section showing a memory block in accordance with some examples of the disclosure.

[0013] Figure 6 An example three-dimensional cross-section showing a 3D NAND architecture semiconductor memory device according to some examples of the present disclosure.

[0014] Figure 7 A diagram of a memory block showing an example defect in a top deck of a bottom deck that is still allowed to be used according to some examples of the present disclosure.

[0015] Figure 8 A diagram of a memory block showing an example defect in a top deck of a bottom deck that is not allowed to be salvaged according to some examples of the present disclosure.

[0016] Figure 9 A flowchart showing a method of identifying a salvageable portion of a memory block and utilizing the salvageable portion when a first portion is defective according to some examples of the present disclosure.

[0017] Figure 10 A flowchart showing a method of determining a salvageable block portion according to some examples of the present disclosure.

[0018] Figure 11 A composition of a virtual structure from a salvageable block portion according to some examples of the present disclosure.

[0019] Figure 12 A flowchart showing a method of forming a single planar virtual block from a plurality of salvageable block portions according to some examples of the present disclosure.

[0020] Figure 13 A flowchart showing a method of forming a multi-planar virtual block from a plurality of single planar virtual blocks according to some examples of the present disclosure.

[0021] Figure 14 A flowchart showing a method of forming a multi-planar multi-die virtual block from a plurality of multi-planar virtual blocks according to some examples of the present disclosure.

[0022] Figure 15 A block diagram illustrating an example machine upon which any one or more of the techniques (e.g., methodologies) discussed herein can perform. DETAILED DESCRIPTION

[0023] Modern flash memory devices can have millions of individual semiconductor memory cells, each of which stores one, two, three, or more bits of data. Among these millions of cells, due to imperfections in manufacturing, some cells will be defective, statistically. For some memory device architectures, such as NAND, a defect in a particular memory cell can affect not only the particular memory cell, due to each memory cell being connected to other memory cells in a block of memory cells via word lines and bit lines. These defects can affect the voltage placed on or read from other memory cells placed in the block. Example defects that would typically render the entire block unusable include a short between two word lines (word line to word line short), a word line that is not properly formed and thus does not pass electrical power (open word line), a slow programming to a word line, etc. Given the large number of memory cells in a typical memory device, statistically, several of these defects are expected. Due to these defects, a memory device is typically produced with more memory blocks than necessary to conform to a particular specified size of the capacity of the memory device. Additional blocks are also added for redundancy to compensate for failures of memory cells during operation and to allow various operations such as garbage collection.

[0024] Defects in memory cells can be determined through testing. For example, after manufacturing and throughout the lifetime of a memory device, various testing procedures can test each memory cell in a memory device to ensure that it performs as expected. Typically, when a defect is found in a memory cell, the block in which it is located is marked as bad, removed from a list of known good blocks, and no longer used to store data. Disabling an entire block for defects on a few memory cells wastes a large amount of memory cells that can still function.

[0025] Methods, systems, devices, memory devices, and machine-readable media for using a defect-free portion of a memory block having a defect on a different portion are disclosed in some examples. Instead of disabling an entire block, the system can only disable a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block). As used herein, a bad portion is a portion of a block that is not used due to a defect in the portion, and a salvageable portion is a portion of a block that does not have a defect that can be utilized by applying a compensation technique to one or more bad portions on the block. A salvageable portion can be utilized by applying one or more compensation techniques, such as applying one or more bias voltages to one or more bad portions when performing operations on the salvageable portion.

[0026] To address the salvageable block portions when reading from or writing to the salvageable block portions, one or more additional address bits can be used to indicate the salvageable portion of the block being addressed. For example, the portion can include one of two stacks in a block, and the address bits can indicate the upper or lower stack. In some examples, the recovery of the salvageable portion of a block can occur automatically, but in other examples, this can be a feature that can be enabled during device setup and / or initialization or during operation (e.g., in response to the number of defective blocks flagged as defective during operation exceeding a threshold).

[0027] Two or more salvageable block portions can be aggregated together to form a virtual block. In some examples, these virtual blocks can be organized to take advantage of the increased parallelism of a NAND memory device. For example, a NAND can be able to perform multiple operations (e.g., read, write, erase) on different planes of the memory device simultaneously. Thus, virtual blocks can be created such that a first salvageable block portion from a first plane can be paired in the virtual block with a second salvageable block portion from a second plane, etc. These virtual blocks can be composed of any number of different salvageable block portions, and can store user data, system data, system table information, etc.

[0028] As mentioned, a bad block portion can be a portion of a block that is unusable due to a defect, either a manufacturing defect or a defect from operation (e.g., cell wear-out). A salvageable block portion can be a portion of a block where there is a bad block portion, but the salvageable portion can still be usable by applying a compensation technique to one or more portions of the block, including the bad block portion and / or the salvageable block portion. Example compensation techniques include applying a particular bias voltage to the bad block portion during operation on the salvageable block portion.

[0029] Memory device overview

[0030] As mentioned previously, flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory typically includes one or more groups of transistors, such as floating gate or charge trap memory cells, that allow for high memory density, high reliability, and low power consumption. Two common types of flash memory array architecture include NAND and NOR architectures, named in the form of the logic in which the basic memory cells are arranged. The memory cells of a memory array are typically arranged in a matrix. In an example, the gates of each memory cell in a row of the array are coupled to an access line (e.g., a word line). In a NOR architecture, the drains of each memory cell in a column of the array are coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string of the array are coupled together in a source-to-drain fashion between a source line and a bit line.

[0031] NOR and NAND architecture semiconductor memory arrays are both accessed through decoders that activate a particular memory cell by selecting a word line coupled to the gate of the particular memory cell. In a NOR architecture semiconductor memory array, once activated, the selected memory cell places its data value on a bit line, causing a different current to flow depending on the programmed state of the particular cell. In a NAND architecture semiconductor memory array, a high bias voltage is applied to a drain side select gate (SGD) line. A word line coupled to the gates of unselected memory cells of each group is driven with a specified pass voltage (e.g., Vpass) to cause the unselected memory cells of each group to operate as pass transistors (e.g., to pass current without being limited by their stored data values). Current then flows from a source line through each serially coupled group to a bit line, limited only by the selected memory cell in each group, placing the current encoded data value of the selected memory cell on the bit line.

[0032] Flash memory cells in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively to one or several programmed states. For example, single level cells (SLCs) can represent one of two programmed states (e.g., 1 or 0), representing one bit of data. However, flash memory cells can also represent one of more than two programmed states, allowing for higher density memory to be manufactured without increasing the number of memory cells, as each cell can represent more than one binary digit (e.g., more than one bit). Such cells can be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In certain examples, MLCs can refer to memory cells that can store two bits of data per cell (e.g., one of four programmed states), triple level cells (TLCs) can refer to memory cells that can store three bits of data per cell (e.g., one of eight programmed states), and quad level cells (QLCs) can store four bits of data per cell. MLCs are used herein in their broader context, and can refer to any memory cell that can store more than one bit of data (i.e., can represent more than two programmed states).

[0033] Conventional memory arrays are two-dimensional (2D) structures arranged on the surface of a semiconductor substrate. To increase the memory capacity of a given area and reduce cost, the size of individual memory cells has been reduced. However, there are technical limitations to the reduction of individual memory cell size, and thus, there are technical limitations to the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures, such as 3D NAND architecture semiconductor memory devices, are used to further increase memory density and reduce memory cost.

[0034] These 3D NAND devices generally include strings of memory cells that are coupled in series (e.g., drain to source) between one or more source side select gates (SGS) proximate to a source and one or more drain side select gates (SGD) proximate to a bit line. In examples, the SGS or SGD can include one or more field effect transistors (FETs) or metal oxide semiconductor (MOS) structure devices, etc. In some examples, the string will extend vertically through a plurality of vertically spaced-apart levels containing respective word lines. A semiconductor structure (e.g., a polysilicon structure) can extend adjacent to the string of memory cells to form a channel for the memory cells of the string. In examples of vertical strings, the polysilicon structure can be in the form of a vertically extending pillar. In some examples, the string can be “folded” and thus arranged with respect to a U-shaped pillar. In other examples, a plurality of vertical structures can be stacked on one another to form a stacked array of memory cell strings.

[0035] Memory arrays or devices can be combined together to form a storage capacity of one of a memory system, such as a solid state drive (SSD), or various forms of managed memory devices. Memory devices can be configured and operated according to recognized industry standards. For example, a NAND device can be a Universal Flash Storage (UFS TM ) device or an Embedded MMC device (eMMC TM ), etc., as non-limiting examples. In the case of the above examples, for instance, a UFS device can be configured according to a Joint Electron Device Engineering Council (JEDEC) standard entitled “JEDEC UFS Flash Storage 3.0” (e.g., JEDEC standard JESD223D) and / or updates or subsequent versions to such standards. Similarly, the identified eMMC device can be configured according to a JEDEC standard entitled “JEDEC eMMC standard 5.1” (also) and / or updates or subsequent versions to such standards.

[0036] SSDs are particularly useful as primary storage devices for computers, having advantages over traditional hard disk drives with moving parts with respect to, for example, performance, size, weight, durability, operating temperature range, and power consumption. For example, SSDs can have reduced seek time, latency, or other delays associated with disk drives (e.g., electromechanical, etc.). SSDs use non-volatile memory cells, such as flash memory cells, to avoid the need for internal battery power, thus allowing the drive to be more versatile and compact.

[0037] SSDs can include a number of memory devices, including a number of dies or logical units (e.g., logical unit numbers or LUNs), and can include one or more processors or other controllers that perform logical functions required to operate the memory devices or interface with external systems. Such SSDs can include one or more flash memory dies that include a number of memory arrays and peripheral circuitry thereon. The flash memory arrays can include blocks of memory cells organized into a number of physical pages. In many instances, the SSDs will also include DRAM or SRAM (or other forms of memory dies or other memory structures). The SSDs can receive commands from a host in conjunction with memory operations such as read or write operations that transfer data (e.g., user data and associated integrity data such as error data and address data, etc.) between the memory devices and the host, or erase operations that erase data from the memory devices.

[0038] Memory devices include individual memory dies that may, for example, include a storage region comprising one or more arrays of memory cells, implementing a selected storage technology or technologies. Such memory dies will typically include support circuitry for operating the memory arrays. Other instances, sometimes referred to generally as “managed memory devices,” include an assembly of one or more memory dies in association with controller functionality configured to control operation of the one or more memory dies. Such controller functionality can facilitate interoperability with external devices such as “hosts,” as discussed later herein. In such managed memory devices, the controller functionality can be implemented on one or more dies that also incorporate the memory arrays, or on a separate die. In other instances, one or more memory dies can be combined with controller functionality to form a solid state drive (SSD) storage capacity. The term “memory device” is used herein to include one or more memory dies, as well as any controller functionality for such memory dies, when present; and thus, to include individual memory devices, managed memory devices, and SSDs.

[0039] For the presently described purposes, example embodiments include managed memory devices that implement NAND flash memory cells, referred to as “managed NAND” devices. Such managed NAND devices can be constructed and operated generally in accordance with the described JEDEC UFS Flash Memory 3.0 specification, modified as needed to incorporate the structures and functionality described herein. However, the described functionality can be implemented with other types of memory devices as described above, a number of non-limiting examples of which are discussed earlier herein; and can be configured for operation in accordance with other industry standards as discussed above; or according to non-industry standard protocols.

[0040] Electronic devices such as mobile electronic devices (e.g., smartphones, tablet computers, etc.), electronic devices for automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and Internet-connected appliance devices or devices (e.g., Internet of Things (IoT) devices, etc.) have varying storage needs depending on, among other things, the type of electronic device, the use environment, performance expectations, etc.

[0041] An electronic device can be decomposed into several major components: a processor (e.g., a central processing unit (CPU) or other main processor); a memory (e.g., one or more volatile or non-volatile random access memory (RAM) memory devices, such as dynamic RAM (DRAM), mobile or low power double data rate synchronous DRAM (DDR SDRAM), etc.); and a storage device (e.g., a non-volatile memory (NVM) device, such as a flash memory, read-only memory (ROM), an SSD, an MMC, or other memory card structure or assembly, etc.). In certain examples, an electronic device can include a user interface (e.g., a display, a touchscreen, a keyboard, one or more buttons, etc.), a graphics processing unit (GPU), a power management circuit, a baseband processor or one or more transceiver circuits, etc.

[0042] Figure 1 A diagram of a memory device 100, such as a storage device, is shown in accordance with some examples of the present disclosure. The memory device 100 can include one or more host interfaces 123 that can utilize one or more protocols, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC interface TM The host device 135 can send one or more commands, such as read commands, write commands, erase commands, etc., to the memory device 100 over the host interface 123. The host interface 123 can be part of the controller 105 or can be implemented by a separate circuit. The memory device 100 can send data, command responses, etc., to the host device 135 via the host bus 137 via the host interface.

[0043] The memory device 100 can include one or more memory controllers 105. The controller 105 can include processing circuitry 110, which can include one or more hardware processors 115. The processor 115 can be a general purpose hardware processor that executes firmware or other software instructions for performing operations of the memory device, including implementing a host interface 123 and a memory die interface 125. In other examples, the processor 115 can be a special purpose hardware processor that is specifically designed to perform operations of the memory device 100, either through hardware logic and / or through execution of software instructions. The processing circuitry 110 can also include logic circuitry and other circuit components configured to perform various control functionality and memory management operations, or portions thereof, examples of which are described below.

[0044] In the depicted example, the memory device 100 includes a host interface 123 that provides for communication over a host bus 137 to an external host device 135. The configuration of the host interface 123 can have various forms depending on the particular configuration of the memory device 100, which can also be referred to as a “memory system.” For example, in examples where the memory device 100 is a UFS device, the host interface will be in accordance with the applicable UFS standard.

[0045] The memory device 100 also incorporates one or more memory die interfaces 125 between the processing circuitry 110 of the controller 105 and at least some portion of the memory dies 130-A to 130N+1 within the memory device 100. The memory die interface 125 can be part of the controller 105 or can be implemented by separate circuitry. For example, in examples of a UFS device, one or more of the memory die interfaces 125 will be a suitable memory interface, such as, for example, an Open NAND Flash Interface (“ONFI”) as defined by the ONFI 4.0 specification or later versions or revisions thereof.

[0046] Components of the memory device 100, such as the controller 105, can include random access memory 120 for performing operations of the memory device 100. The random access memory 120 can be separate from the controller 105, or as shown, can be integrated in the controller 105.

[0047] The controller 105 can handle one or more functions of the memory by interacting with memory cells of the memory device that are part of the one or more memory dies 130-A to 130N+1. Figure 4An example implementation of a memory die 130 is shown in a schematic diagram. The controller 105 can communicate with these memory dies across the memory die bus 127 through the memory die interface 125. In some examples, the memory dies can have their own device controller to control operations on the respective memory die, including processing circuitry and a processor. Such a device controller can be formed on a die common with the device storage array, or can be on a separate die from the die containing the device storage array. Both configurations are encompassed by the identified "memory die" (130A to N+1) described herein. The memory die can be a NAND die, a three-dimensional NAND die, a phase change memory die, etc.

[0048] The host device 135 can be a personal computer, a smart phone, a tablet computer, part of an integrated circuit, an Internet of Things (IoT) device (e.g., a refrigerator or other appliance, a sensor, a motor or actuator, a mobile communication device, an automobile, a drone, etc.), etc.

[0049] For the presently described purposes, example memory operations and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory can have similar memory operations or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or recycling), error detection or correction, block retirement, or one or more other memory management functions.

[0050] The memory dies 130-A to 130-N+1 can include a number of memory cells arranged in, for example, a number of planes, sub-blocks, blocks, or pages. As one example, a 48 GB TLC NAND memory device can include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32 GB MLC memory device (storing two data bits per cell (i.e., 4 programmable states)) can include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but with half the write time and twice the program / erase (P / E) cycles required as compared to a corresponding TLC memory device. Other examples can include other numbers or arrangements. In some examples, a memory device or portions thereof can be selectively operated in SLC mode or in a required MLC mode (e.g., TLC, QLC, etc.).

[0051] In operation, data is typically written to or read from the memory device 100 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) can be performed on larger or smaller groups of memory cells as desired. The data transfer size for the memory device 100 is typically referred to as a page, while the data transfer size for the host is typically referred to as a sector.

[0052] While a page of data can include a number of bytes of user data (e.g., a data payload including a number of data sectors) and its corresponding metadata, the size of a page typically refers only to the number of bytes used to store user data. As an example, a page of data having a page size of 4KB can include 4KB of user data (e.g., 8 sectors assuming a sector size of 512B) and metadata, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data, corresponding to a number of bytes (e.g., 32B, 54B, 224B, etc.) of the user data.

[0053] Different types of memory cells can provide different page sizes, or can require different amounts of metadata associated therewith. For example, different memory device types can have different bit error rates, which can result in a need for different amounts of metadata to ensure the integrity of a page of data (e.g., a memory device having a higher bit error rate can require more bytes of error correction code data than a memory device having a lower bit error rate). As an example, a multi-level cell (MLC) NAND flash device can have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash device. As such, a MLC device can require more metadata bytes for error data than a corresponding SLC device.

[0054] Figure 2 An example diagram illustrating a portion of a NAND architecture semiconductor memory array 200 including a plurality of memory cells 202 arranged in a two-dimensional array of strings (e.g., strings 205-207) and tiers (e.g., shown as respective word lines (WL) WL0 210-WL7 217, source side gate (SGD) lines 225, source side gate (SGS) lines 230, etc.) and a sense amplifier or device 260 is shown in accordance with some examples of the present disclosure. For example, the memory array 200 can illustrate a portion of an example diagram of a physical page of memory cells from a memory die 130 of Figure 1

[0055] ​Each string of memory cells is coupled to a source line (SRC) 235 using a respective source-side select gate (SGS) (e.g., SGS 231-233) and to a respective data line (e.g., bit line (BL) BL0 220-BL2 222) using a respective drain-side select gate (SGD) (e.g., SGD 226-228). Although shown in the example of Figure 2 While shown in the example of FIG. 2 as having eight tiers (e.g., using word lines (WL) WL0 210-WL7 217) and three data lines (BL0 226-BL2 228), other examples can include strings of memory cells having more or fewer tiers or data lines as desired.

[0056] In a NAND architecture semiconductor memory array such as the example memory array 200, the state of a selected memory cell 202 can be accessed by sensing a current or voltage change associated with a particular data line containing the selected memory cell. The memory array 200 can be accessed using one or more drivers (e.g., by a control circuit, one or more processors, digital logic, etc.). In examples, the one or more drivers can activate a particular memory cell or set of memory cells by driving a particular potential to one or more data lines (e.g., bit lines BL0-BL2), access lines (e.g., word lines WL0-WL7), or select gates depending on the type of operation to be performed on the particular memory cell or set of memory cells.

[0057] To program or write data to a memory cell, a program voltage (Vpgm) (e.g., one or more program pulses, etc.) can be applied to a selected word line (e.g., WL4) and thus to the control gate of each memory cell coupled to the selected word line (e.g., control gates (CG) 241-243 of the memory cells coupled to WL4). For example, a program pulse can start at or near 15V, and in certain examples, the amplitude can be increased during each program pulse application. When a program voltage is applied to a selected word line, a potential such as a ground potential (e.g., Vss) can be applied to the data line (e.g., bit line) and substrate (and thus the channel between the source and drain) of the memory cell targeted for programming, causing a charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) of charge from the channel to a charge storage structure of the targeted memory cell. Such a charge storage structure can include, for example, a floating gate or a charge trap region of the respective memory cell. In a floating gate memory cell, charge is stored in an isolated polysilicon structure; while in a charge trap memory cell, charge is typically stored in a dielectric structure.

[0058] In contrast, a pass voltage (Vpass) can be applied to one or more word lines having memory cells that are not targeted for programming, or a inhibit voltage (e.g., Vcc) can be applied to a data line (e.g., bit line) having memory cells that are not targeted for programming, to, for example, inhibit the transfer of charge from the channel to the charge storage structure of such non-target memory cells. The pass voltage can vary depending on, for example, the proximity of the applied pass voltage to the word line that is targeted for programming. The inhibit voltage can include a power supply voltage (Vcc), such as a voltage from an external source or power supply (e.g., battery, AC-to-DC converter, etc.) relative to a ground potential (e.g., Vss).

[0059] As an example, if a program voltage (e.g., 15V or higher) is applied to a particular word line, such as WL4, a pass voltage of 10V can be applied to one or more other word lines, such as WL3, WL5, etc., to inhibit programming of non-target memory cells, or to preserve the value stored on such memory cells that are not targeted for programming. As the distance between the applied program voltage and the non-target memory cells increases, the pass voltage required to prevent programming of the non-target memory cells can decrease. For example, where a program voltage of 15V is applied to WL4, a pass voltage of 10V can be applied to WL3 and WL5, a pass voltage of 8V can be applied to WL2 and WL6, a pass voltage of 7V can be applied to WL1 and WL7, etc. In other examples, the pass voltage or number of word lines, etc., can be higher or lower, or more or less.

[0060] A sense amplifier 260 coupled to one or more of the data lines (e.g., first, second, or third bit lines (BL0-BL2) 220-222) can detect the state of each memory cell in the corresponding data line by sensing the voltage or current on the particular data line.

[0061] Between the application of one or more program pulses (e.g., Vpgm), a verify operation can be performed to determine whether the selected memory cell has reached its intended programmed state. If the selected memory cell has reached its intended programmed state, further programming thereof can be inhibited. If the selected memory cell has not reached its intended programmed state, an additional program pulse can be applied. If the selected memory cell has not reached its intended programmed state after a particular number of program pulses (e.g., a maximum number), the selected memory cell, or a string, block, or page associated with this selected memory cell, can be flagged as defective.

[0062] For single-level cells (SLC), there are two possible voltage levels programmed into a cell, one voltage level represents binary'1'and the other voltage level represents binary '0'. For multi-level cells (MLC), there are four possible voltage levels programmed into a cell. The four possible voltage levels represent '00', '01', '10', and '11'. To program a MLC cell, multiple programming pulses are applied. A first pulse programs a first page of data representing the most significant bit or the least significant bit of the cell. A second pulse programs a second page of data representing another bit of the cell that is not programmed by the first pulse. Similarly, a triple-level cell (TLC) stores eight possible voltage levels, and a quad-level cell (QLC) stores sixteen possible voltage levels.

[0063] To read a value stored in one or more memory cells, a read voltage is applied to the word line of the selected cell. If the voltage stored in the cell of the word line is greater than the read voltage, the cell passes the voltage to a sense amplifier. For SLC cells, the read voltage is selected to be between the two voltages representing'1'and '0'. For MLC, TLC, and QLC, multiple read operations are used to read each bit stored in the cell, each read operation utilizing a different read voltage.

[0064] To erase a memory cell or group of memory cells (e.g., erase is typically performed in blocks or sub-blocks), an erase voltage (Vers) can be applied (e.g., using one or more bit lines, select gates, etc.) to the substrate (and thus, the channel between the source and drain) of the memory cell that is the target of the erase while the word line of the target memory cell is held at a potential, such as ground potential (e.g., Vss), resulting in a charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the charge storage structure of the target memory cell to the channel.

[0065] Figure 3 An example schematic diagram of a 3D NAND architecture semiconductor memory array 300 including a number of strings of memory cells (e.g., A0 memory strings 305A0-307A0, A n Memory strings 305A n to 307A n , B0 memory strings 305B0-307B0, B n Memory strings 305B n to 307B n and sub-blocks (e.g., sub-block A0 301A0, sub-block A n 301A n , sub-block B0 301B0, sub-block Bn 301B n Memory array 300 represents a portion of a larger number of similar structures that would typically be found in a block, device, or other unit of a memory device.

[0066] Each string of memory cells includes several levels of charge storage transistors (e.g., floating gate transistors, charge-trapping structures, etc.) stacked in a source-to-drain manner in the Z-direction between a source line (SRC) 335 or source side select gate (SGS) (e.g., A0 SGS 331A0 to 333A0, A n SGS 331A n to 333A n , B0 SGS 331B0 to 333B0, B n SGS 331B n to 333B n , and a drain side select gate (SGD) (e.g., A0 SGD 326A0 to 328A0, A n SGD 326A n to 328A n , B0 SGD 326B0 to 328B0, B n SGD 326B n to 328B n , etc.). Each string of memory cells in a 3D memory array can be arranged along the X-direction as a data line (e.g., bit line (BL) BL0320 to BL2322) and along the Y-direction as a physical page.

[0067] Within a physical page, each level represents a row of memory cells, and each string of memory cells represents a column. A sub-block can include one or more physical pages. A block can include several sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although shown herein as having two blocks, each block having two sub-blocks, each sub-block having a single physical page, each physical page having three strings of memory cells, and each string having 8 levels of memory cells, in other examples, memory array 300 can include more or fewer blocks, sub-blocks, physical pages, strings of memory cells, memory cells, or levels. For example, each string of memory cells can include more or fewer levels (e.g., 16, 32, 64, 128, etc.) as desired, as well as one or more additional levels of semiconductor material above or below the charge storage transistors (e.g., select gates, data lines, etc.). As an example, a 48 Gb TLC NAND memory device can include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

[0068] Each memory cell in the memory array 300 includes a control gate (CG) coupled to (e.g., electrically or otherwise operatively connected to) an access line (e.g., word line (WL) WL00 310A to WL70 317A, WL01 310B to WL71 317B, etc.) that collectively couples the control gates (CGs) across a particular level or portion of levels as needed. A respective access line can be used to access or control a particular level in the 3D memory array, and thus a particular memory cell in a string. Various selection lines can be used to access groups of selection gates. For example, A0 SGD lines SGDA0 325A0 can be used to access A0 SGD 326A0 to 328A0, SGD lines SGDA n 325A n may be used to access A n SGD 326A n to 328A n , B0 SGD lines SGDB0 325B0 can be used to access B0 SGD 326B0 to 328B0, and B n SGD lines SGDB n 325B n may be used to access B n SGD 326B n to 328B n . Gate selection lines SGS0 330A can be used to access A0 SGS 331A0 to 333A0 and A n SGS 331A n to 333A n , and gate selection lines SGS1 330B can be used to access B0 SGS 331B0 to 333B0 and B n SGS 331B n to 333B n .

[0069] In an example, the memory array 300 can include a number of levels of semiconductor material (e.g., polysilicon, etc.) configured to couple the control gates (CGs) or selection gates (or portions of CGs or selection gates) of each memory cell of a respective level of the array. A combination of bit lines (BLs) and selection gates, etc. can be used to access, select, or control a particular string of memory cells in the array, and one or more access lines (e.g., word lines) can be used to access, select, or control a particular memory cell at one or more levels in the particular string.

[0070] Figure 4The diagram illustrates an example block diagram of a memory die 400 according to some embodiments of the present disclosure. The memory die 400 includes a memory array 402 having a plurality of memory cells 404, and one or more circuits or components for providing communication with the memory array 402 or performing one or more memory operations on the memory array 402. The memory die 400 may include a row decoder 412, a column decoder 414, a sense amplifier 420, a page buffer 422, a selector 424, input / output (I / O) circuitry 426, and a memory control unit 430.

[0071] The memory cells 404 of the memory array 402 can be arranged in blocks, such as a first block 402A and a second block 402B. Each block can contain sub-blocks. For example, the first block 402A can contain a first sub-block 402A0 and a second sub-block 402A0. n Furthermore, the second 402B block can include the first sub-block 402B0 and the second sub-block 402B. n In some instances, a sub-block may be referred to as a stack. Each sub-block may contain several physical pages, and each page may contain several memory cells 404. Although shown herein as having two blocks, each with two sub-blocks, and each sub-block having several memory cells 404, in other instances, the memory array 402 may contain more or fewer blocks, sub-blocks, memory cells, etc. In other instances, the memory cells 404 may be arranged in several rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, access lines 406, first data lines 410, or one or more select gate, source lines, etc.

[0072] The memory control unit 430 can utilize the memory controller at the memory interface (e.g., regarding...) Figure 1 The memory device 100 (as described in the controller 105 and host interface 123) receives one or more signals and / or instructions / commands on control line 432 to control the memory operation of the memory die 400. These signals and / or instructions may include, for example, one or more clock signals and / or control signals indicating the desired operation (e.g., write, read, erase, etc.), or address signals (A0 to AX) received on one or more address lines 416. One or more devices external to the memory die 400 may control the values ​​of the control signals on control line 432 or the address signals on address line 416. Examples of devices external to the memory die 400 may include, but are not limited to, a host, memory controller, processor, or... Figure 4 One or more circuits or components not shown in the diagram.

[0073] Memory die 400 can use access lines 406 and first data lines 410 to transfer data into (e.g., write or erase) or from (e.g., read) one or more of memory cells 404. Row decoder 412 and column decoder 414 can receive and decode address signals (A0 to AX) from address lines 416, can determine which memory cells 404 are to be accessed, and can provide signals to, for example, one or more of access lines 406 (e.g., one or more of a plurality of word lines (WL0 to WLm)) or first data lines 410 (e.g., one or more of a plurality of bit lines (BL0 to BLn)), as described above.

[0074] Memory die 400 can include sensing circuitry, such as sense amplifiers 420, configured to determine (e.g., read) values of data on memory cells 404 using first data lines 410, or to determine values of data to be written to memory cells 404. For example, in a selected string of memory cells 404, one or more of sense amplifiers 420 can read logic levels in selected memory cells 404 in response to a read current flowing through the selected string in memory array 402 to data lines 410.

[0075] One or more devices (e.g., controller 105) external to memory die 400 can communicate with memory die 400 using I / O lines (DQ0 to DQN) 408, address lines 416 (A0 to AX), or control lines 432. Input / output (I / O) circuitry 426 can transfer data values to or from memory die 400 using I / O lines 408 in accordance with, for example, control lines 432 and address lines 416, such as transferring data values to or from page buffer 422 or memory array 402. Page buffer 422 can store data received from one or more devices external to memory die 400 before the data is programmed into an associated portion of memory array 402, or can store data read from memory array 402 before the data is transferred to one or more devices external to memory die 400.

[0076] Column decoder 414 can receive and decode address signals (A0 to AX) into one or more column select signals (CSEL1 to CSELn). Selector 424 (e.g., a selection circuit) can receive column select signals (CSEL1 to CSELn) and select data in page buffer 422 that represents the value of the data to be read from or programmed into memory cells 404. The selected data can be transferred between page buffer 422 and I / O circuitry 426 using second data lines 418. In some examples, a flash translation layer (not shown) can map addresses provided by a host to physical memory addresses used by row decoder 412 and column decoder 414 to read data in memory array 402.

[0077] Memory control unit 430 can receive positive and negative power signals, such as power supply voltage (Vcc) 434 and negative supply (Vss) 436 (e.g., ground potential), from an external source or power supply (e.g., an internal or external battery, an AC-to-DC converter, etc.). In certain examples, memory control unit 430 can include regulator 428 to internally provide positive or negative power signals.

[0078] Rescuing portions of bad blocks

[0079] As mentioned previously, a number of blocks are allocated in each memory die for redundancy, yield, and over-provisioning. In the case of certain repair techniques, some defects can allow for partial use of a block. Example defects that can be rescued include word line to word line shorts that affect only data word lines; resistive word lines; slow programming to a word line; and word lines that do not pass the original bit error rate (RBER) requirement. In some examples, a rescuable portion of a block having one or more of the above defects can be isolated from a bad portion of the block by using one or more repair techniques. The rescuable portion can then be utilized, alone or in conjunction with other portions of the memory, to store data. Thus, where one portion of a block is defective and other portions of the block are not defective, the non-defective portion can be enabled for data storage. Example repair techniques include applying one or more bias voltages to the word lines of the bad portion.

[0080] Figure 5A horizontal cross-section of a memory block 500 is shown, in accordance with some examples of the present disclosure. The memory block 500 can comprise a 3D NAND flash memory array, where memory cells can be physically located in multiple levels, such that the memory cells can be stacked vertically. The memory cells of the memory block 500 can be formed around a shared common channel region, which can be formed, for example, as a region of respective pillars 515, 516, 520, 521, 525, 526, 530, and 531 of semiconductor material (e.g., polysilicon). Word lines (both data and dummy word lines) and select gates (including SGD and SGS) can be formed from alternating layers of polysilicon and dielectric material. In some examples, the layers of polysilicon and dielectric material can be formed over a substrate by a deposition process. Figure 6 The structure of the memory cells around the pillars is shown in more detail.

[0081] The memory block 500 can include two separate portions or "decks" 505 and 510. Each deck has one or more data word lines, one or more dummy word lines (DWLs), and one or more select gates formed around multiple pillars. Deck 1 505 is formed around pillars 515, 520, 525, and 530. Deck 2 510 is formed around pillars 516, 521, 526, and 531. The decks are separated from each other by one or more dummy word lines. In addition, the pillars of each deck can be electrically connected, for example, by polysilicon plugs or other connections. Thus, pillars 515 and 516 can be connected; pillars 520 and 521 can be connected; pillars 525 and 526 can be connected; and pillars 530 and 531, etc. As shown, the memory block 500 includes three word lines per deck, 4 pillars per deck, and two decks 505 and 510, but in other examples, more or fewer word lines, pillars, and decks can be utilized and more than two decks can be utilized. A deck can be defined as a set of alternating levels of conductive material and dielectric material that form one or more word lines, separated from another set of alternating levels of conductive material and dielectric material that form one or more other word lines by one or more dummy word lines, one or more other separate layers, etc. The pillars that extend to the decks can be formed individually to each deck and connected, or in some examples, can be continuous. In some examples, a dummy word line is a fully functional word line that has no memory cells used to store host data.

[0082] Figure 6 An example three-dimensional cross-section of a 3D NAND architecture semiconductor memory device 600 is shown, including: portions of two channels or pillars 616 and 626 (which can be, for example, adjacent two of the pillars 515, 516, 520, 521, 525, 526, 530, and 531 of FIG. 1, for example); a first access line 604, a second access line 606, and a third access line 608 (which can be from the set of access lines 104 of FIG. 1, for example); a first select gate 602 and a second select gate 603 (which can be from the set of select gates 106 of FIG. 1, for example); and a first dummy word line 607 and a second dummy word line 609 (which can be from the set of dummy word lines 108 of FIG. 1, for example). Figure 5 Figure 5 ​one or more word lines); and memory cells 628.

[0083] Each of the pillars 616, 626 includes a conductive structure 630, preferably a semiconductive material such as polysilicon. In many examples, the polysilicon will define a central void, which will typically be filled with a dielectric material. Figure 6 The portion of the second pillar 616 and the third pillar 626 shown in FIG. 6B includes three individual memory cells 628. Each 3D memory cell 628 includes a volume of semiconductive material, for example, a partial ring structure 632 (e.g., p+ type polysilicon, etc.) that acts as a floating gate in many examples, separated from the polysilicon of the second pillar 616 and the third pillar 626 by a tunnel dielectric 634, and separated from the respective first access line 604, second access line 606, third access line 608 by one or more intervening polysilicon dielectric layers, such as an oxide-nitride-oxide (ONO) structure, including, for example, a first silicon dioxide (Si02) layer 636, a silicon nitride (Si3N4) layer 638, and a second silicon dioxide layer 640. The respective memory cells 628 are separated from one another by additional levels of dielectric material 642. While the memory cells 628 in FIG. 6B include a floating gate storage structure, in other examples, other charge storage mechanisms can be utilized, such as charge trapping structures or other forms of storage structures. The spaces between the conductive levels 602 can include dielectric material, such as silicon dioxide (Si02), or one or more other dielectric materials. Figure 6

[0084] Figure 7 A diagram showing a memory block 700 according to some examples of the disclosure is shown, which shows still allowing for defects in a top deck 710 of a bottom deck of a deck according to some examples of the disclosure. A first defect 720 is a word line to word line short. For example, a defect in the dielectric material between word lines can allow for a short to occur between two word lines. A second defect is a resistive word line 730.

[0085] Typically, either of these defects would render the entire memory block 700 unusable. However, in some examples, where one deck has these defects and another deck does not have defects, the memory device can salvage the deck that does not have defects by applying one or more compensation techniques to the defective deck to use the salvageable deck.

[0086] In some examples, the memory device can apply a compensation technique to the defective deck to use the salvageable deck. Figure 7 ​In the case where the memory device can utilize the bottom stack 715 by applying a bias voltage to the top stack 710 during operations on the bottom stack, the bottom stack 715 can thus be a salvageable stack that can be used to store user data, system data, system over provisioning, etc. As mentioned previously, in some examples, a salvageable stack is a stack of memory cells that does not have defects from a first set of defect types, but is part of a block that has defects from a second set of defect types. In some examples, the second set of defect types can include word line to word line shorts, resistive word lines, slow programming to cells, and defects where the raw bit error rate (RBER) metric exceeds a threshold. In some examples, the first set of defect types includes the second set of defect types and additional defect types such as word line to pillar shorts, SGS and SGD shorts, dummy word line shorts, and other defects that would typically cause a block to be marked as bad. Thus, one of ordinary skill in the art will appreciate, given the benefit of this disclosure, that certain defects can allow for salvaging a portion of a block, while other defects do not allow for salvaging any portion of a block.

[0087] Figure 7 The top stack is shown as defective and the bottom stack is shown as not containing defects, but in other examples, the top stack can not contain defects (and thus can be salvageable), but the bottom stack can have one or more defects. In still other examples, where a block has more than two stacks, a stack that does not contain defects can be considered salvageable and can be utilized using one or more compensation techniques, such as applying one or more bias voltages to the bad stack, the salvageable stack, or both, as long as a single stack does not contain defects.

[0088] Despite these improvements, as mentioned, some defects do not allow for salvaging another stack. Figure 8 A diagram of a memory block 800 is shown that illustrates example defects in one portion (top stack 810) that does not allow for salvaging any other portion (in this case, bottom stack 815) in accordance with some examples of the disclosure. For example, a short between pillars 820, a short between a word line and a drain side select gate (SGD) 830, a word line to pillar short 840, or a short between a word line and a source side select gate (SGS) 845. Two stacks in a block having these defects would be marked as bad, even though the defects are only present in one stack.

[0089] Figure 9A flowchart showing a method 900 of identifying a salvageable portion of a memory block and utilizing the salvageable portion when a first portion is defective, according to some examples of the disclosure. The method 900 can be performed by a controller, such as the controller 105, or by either or both of a memory control unit, such as the memory control unit 430, on one or more memory dies, such as the memory dies 400, 130A-130N+1. At operation 910, a defect of a first portion of a block of memory cells that can allow utilization of the other portion can be identified, the defect being a type from a first identified list of defect types. The first identified list can include word line to word line shorts in data word lines, slow programming to a word line, a word line that does not meet RBFR requirements, and a resistive word line. As mentioned, the defects can be identified, for example, by one or more tests performed on the memory cells. Example tests can include a write test, an erase test, a read test, and the like. The tests at operation 910 can be performed after the memory device is manufactured and before the memory device is put into use. In other examples, the tests at operation 910 can be performed during or as a result of normal memory device operation. For example, defects can be identified by reading and / or writing particular memory cells and encountering errors during use of the device. The tests can be performed by the memory device, by a testing device, or by both the memory device and the testing device.

[0090] At operation 915, the system can identify that a second portion of the block identified at operation 910 does not have a defect from a second identified list of defect types. For example, the second list of defect types can include the first list of defect types and other defects, such as word line to pillar shorts, SG shorts, and dummy word line shorts. In some examples, the second list of defect types can be any defect. In some examples, the second list of defect types can be any defect that makes the second portion unusable, even if a compensation technique is applied to the first portion.

[0091] In response to identifying that there is a defect of the first portion at operation 910 and that the second portion does not have a defect at operation 915, the first portion can be marked as defective and the second portion can be marked as salvageable by the memory device. For example, the portions can be marked in a logical to physical (L2P) table in the controller, in the memory portion itself, in a table in the memory die that marks defective blocks and / or portions, in a one-time programmable area, and the like. In some examples, both portions can be first marked as “bad,” and after a particular feature is turned on to use the salvageable portion, if there is a salvageable portion, the memory device can update the designation of each portion of each block that is marked as bad. In some examples, before marking the portion as salvageable, the system can test the second portion, as shown in Figure 10

[0092] ​At operation 920, the memory die can receive a request to perform an operation on the second portion (the salvageable portion). For example, the controller can determine that an operation is to be performed on the second portion, and can request that the memory die perform the operation (e.g., by transmitting a request over the internal bus). Example operations can include an erase operation, a write operation, a read operation, etc. In some examples, the request can include additional address bits from the controller indicating which portion (e.g., stack) the operation is for. In other examples, such as each block having two portions, the memory die can infer which portion the operation is for based on which portion is marked as bad as indicated by one or more indicators stored within the memory die itself.

[0093] At operation 925, the memory die can select or identify a bias voltage applied to the word lines of the first portion while performing the operation on the second portion. For example, the memory die can identify or select the bias voltage, or the controller can select the bias voltage and deliver the appropriate bias voltage to the memory die. The selection of the bias voltage can depend on the type of operation being performed (e.g., whether the operation is a read, a write, or an erase). For example, for an erase operation, the erase pulse phase can typically operate at equal potential across all word lines of both good and bad portions. The erase verify phase can apply a uniform Vpass voltage to all word lines in the bad stack to bypass the defect site by normal verify bias (low voltage) to confirm pass or fail of the erase operation. The dummy word line and SGD or SGS remain the same as the normal block. For read and program operations, in addition to keeping the same dummy word line and SGD / SGS, all word line bias to unselected word line voltage in the bad stack. The selected bias voltage can be selected so as to prevent defects in the bad portion from interfering as current is passed to and from memory cells associated with the word lines of the salvageable portion.

[0094] At operation 930, the memory die can perform the requested operation on the second portion. For example, by applying one or more voltages to one or more word lines, SGS, SGD, etc. of the second portion, and applying the selected bias voltage to the first portion. For example, the memory die can read a value from the second portion, store a value in the second portion, erase the second portion, etc.

[0095] Figure 10A flowchart illustrating a method 1000 for determining salvageable block portions according to some embodiments of the present disclosure is shown. Method 1000 may be performed by a controller (e.g., controller 105) or by any one or both of a memory control unit (e.g., memory control unit 430) on one or more memory dies (e.g., memory dies 400, 130A to 130N+1). For example, and as shown in method 1000, the system may not only determine that the error exists in one portion but not in a second portion, but may also verify the suitability of the second portion to ensure that it can reliably store data. While the operation of method 1000 includes erasing, programming, and erasing and reading blank patterns, those skilled in the art will understand that, thanks to the present disclosure, more or fewer operations can be used to test the suitability of the second portion. For example, the system may perform only the erasure procedure and skip... Figure 10 The remaining operations. In other instances, the system is programmable and reads predetermined values, erases and reads blank patterns, and skips the erasure step at operation 1025. In still other instances, it can perform operations not in Figure 10 Additional suitability tests are shown in the diagram.

[0096] Execution can be performed on one or more blocks (e.g., all blocks) of one or more specific dies of a particular memory device. Figure 10 The operation involves screening memory cells for errors at operation 1010. In some instances, various tests can be performed after manufacturing to find errors, such as word line shorts, open word lines, etc. In other instances, various tests can be performed during the operation of the memory device. Tests can be performed by the memory device (e.g., by the memory device's controller), testing equipment, etc.

[0097] At operation 1015, the system can identify potentially salvageable portions of blocks from blocks having other portions (which have the error detected at operation 1010). These potentially salvageable block portions are called candidate salvageable portions. Blocks with certain types of specified errors can be identified on the first portion but not on the second portion.

[0098] Figure 10 The remaining operational procedures can be applied to one or more (or all) of the candidate recoverable portions identified in operation 1015. At operation 1020, the memory device can set erase trimming and erase verification trimming. For example, by setting erase trimming and erase verification trimming on the candidate recoverable portions and bias voltages (e.g., compensation techniques) on one or more other portions of the block. At operation 1025, the candidate recoverable portions can be erased.

[0099] At operation 1030, it can be determined whether the erase operation was successful. For example, the erase operation at operation 1025 can have a verification phase to verify that the erase was successful. For example, a threshold voltage read of the cells can be used to ensure that the desired erase value has been programmed into the cells. In some examples, verification is only performed for salvageable candidate portions. For any candidate salvageable portions where the erase was not successful, then at operation 1060, the entire block corresponding to the particular candidate salvageable portion that failed can be marked as bad.

[0100] If the erase was successful, then at operation 1035, the predetermined value can have been programmed into the candidate salvageable block portion, for example, by applying a compensation technique (e.g., a bias voltage) to one or more bad portions of the block. The candidate salvageable block portion is then read, and at operation 1040, if the number of errors determined during the verification step is greater than a raw bit error rate (RBER) threshold, then at operation 1060 the block is marked as bad. If the number of errors determined during the verification step is less than the RBER threshold, then at operation 1045, the candidate salvageable block portion can be erased and read for the blank pattern again by applying the appropriate compensation technique (e.g., bias voltage) to the bad portions of the block.

[0101] At operation 1047, the raw bit error rate (RBER) of the candidate salvageable portion for the read operation is determined, and if the RBER is less than a threshold (which can be the same threshold as at operation 1040, or a different threshold), then at operation 1050, the candidate salvageable block portion is marked as salvageable, in addition to the entire block being marked as bad at operation 1060.

[0102] Using salvageable portions

[0103] The salvageable portions can be used in various different ways depending on the system configuration and storage needs. The salvageable portions can be used in a physical mode. For example, data that fits within the salvageable portion can be written to the salvageable portion. For example, system reservation data, such as file system blocks. In some examples, the salvageable portions used in the physical mode to store system reservation data can be configured as SLC only.

[0104] In other examples, multiple salvageable portions can be used together to form a single virtual block on a single plane. For example, as shown in FIG. 5, a first salvageable portion 505 and a second salvageable portion 510 can be used together to form a single virtual block 515 on a single plane 520. The first salvageable portion 505 and the second salvageable portion 510 can be used together to form the single virtual block 515 in a physical mode. Figure 11As shown in FIG. 11, a single plane virtual block 1100 can include two salvagable block portions 1110 and 1120. These portions can be from the same die and the same plane. That is, a first portion of a first block in a first die and a first plane can be paired with a different portion from the first block in the first die and the first plane. Data can be stored on this structure in the same manner as data is stored on a regular block. The single plane virtual block 1100 can store system reserved data, system table blocks (e.g., L2P table blocks), user data blocks, etc. These portions can be configured as SLC, MLC, TLC, QLC, etc. The single plane virtual block can be two different salvagable portions from different blocks on the same plane.

[0105] In still other examples, multiple single plane virtual blocks can be combined to form a multi-plane virtual block. For example, multiple single plane virtual blocks 1100 can be paired together across multiple planes. For example, the single plane virtual block 1100 can be combined with single plane virtual blocks 1130, 1140, and 1150 each on a different plane from one another. This allows the memory device to store data in a parallel manner to take advantage of the memory device’s ability to write to multiple planes simultaneously. The multi-plane virtual block can be any virtual block formed by at least two single plane virtual blocks residing on different planes. These portions can be configured as SLC, MLC, TLC, QLC, etc. The multi-plane virtual block can store system reserved data, system table blocks (e.g., L2P table blocks), user data blocks, etc. While Figure 11 While four single plane virtual blocks from four different planes are shown in FIG. 11, one of ordinary skill in the art will appreciate that fewer or smaller single plane virtual blocks from fewer or smaller planes can be used. For example, five virtual blocks from five different planes. In other examples, multiple virtual blocks from the same plane can be included so long as at least one virtual block is from a different plane than at least one other virtual block.

[0106] Multiple multi-plane virtual blocks on different dies can also be combined to form a multi-plane multi-die virtual block (referred to as a virtual super block or VSB). For example, in Figure 11 In FIG. 11, the single plane virtual blocks 1100, 1130, 1140, and 1150 can be combined with virtual blocks 1160, 1165, 1170, and 1175. In these examples, data is stripped across dies and planes to take advantage of the memory device’s ability to write data to separate planes and dies in parallel and to protect data by writing portions of the same data segment across dies. Since data is written with error correction codes, a single failure of a single die is correctable and will not result in data loss.

[0107] Block portions that make up a multi-plane multi-die virtual block can be configured as SLC, MLC, TLC, QLC, etc. A multi-plane multi-die virtual block can store system reserved data, system table blocks (e.g., L2P table blocks), user data blocks, etc. Although Figure 11 two multi-plane virtual blocks from two different dies are shown in the middle, one of ordinary skill in the art will appreciate that fewer or smaller multi-plane virtual blocks from fewer or smaller dies can be used. For example, five multi-plane virtual blocks from five different dies can form a multi-plane multi-die virtual block. In other examples, multiple multi-plane virtual blocks from the same die can be included so long as at least one multi-plane virtual block is from a different die than at least one other multi-plane virtual block. Further, as mentioned above, the multi-plane virtual blocks that make up a multi-plane multi-die virtual block can have different configurations as discussed above.

[0108] Figure 12 A flowchart showing a method 1200 of forming a single plane virtual block from multiple salvageable block portions according to some examples of the disclosure is shown. The method 1200 can be performed by a controller (such as the controller 105) or by either or both of a memory control unit (such as the memory control unit 430) on one or more memory dies (such as the memory dies 400, 130A-130N+1). The method 1200 can be performed while the memory device is in use or can be performed dynamically at a later time. For example, if a block portion becomes bad during use and one or more block portions are salvageable, the salvageable portions can be combined with another salvageable portion during use.

[0109] At operation 1210, a first salvageable portion of a first block on a first plane is identified. For example, using the flowchart of FIG. 11, a memory controller can identify a first salvageable portion of a first block on a first plane. Figure 10 At operation 1215, a second salvageable portion of a second block on the first plane is identified. For example, using the flowchart of FIG. 11, a memory controller can identify a second salvageable portion of a second block on the first plane. Figure 10

[0110] At operation 1220, a virtual block can be created using the first and second salvageable portions. For example, a memory controller can store information about the composition of the virtual block in a data structure and insert the virtual block as a valid block. A logical to physical translation table that translates logical addresses to valid physical addresses can also be updated to reflect the availability of the virtual block and to indicate the appropriate addresses of the constituent portions of the virtual block.

[0111] ​At operation 1225, data can be stored in the virtual block by storing a first portion of the data in the first portion and storing a second portion of the data in the second portion. The data can include host data received from a host; system data (e.g., a portion of an L2P table); system reserved data; data generated when performing a garbage collection operation, etc. As previously described, data can be written to a salvageable portion, read from a salvageable portion, by applying an appropriate bias voltage to a bad portion on the same physical block as the salvageable portion, where the operation is being performed on the salvageable portion.

[0112] Reference is now made to Figure 13 , showing a flowchart of a method 1300 of forming a multi-plane virtual block from a plurality of single-plane virtual blocks, according to some examples of the present disclosure. The method 1300 can be performed by a controller (e.g., the controller 105) or by either or both of a memory control unit (e.g., the memory control unit 430) on one or more memory dies (e.g., the memory dies 400, 130A-130N+1). At operation 1310, a first single-plane virtual block on a first plane is identified. For example, the process of Figure 12 is used. At operation 1315, a second virtual block on a second plane is identified. For example, the process of Figure 12 is used. At operation 1320, a multi-plane virtual block can be generated from both the first and second virtual blocks identified in operations 1310 and 1315. For example, the memory controller can store information about the composition of the multi-plane virtual block in a data structure. For example, a logical-to-physical translation table can be used to translate logical addresses to valid physical addresses. At operation 1325, a first portion of data can be stored in the first virtual block and a second portion is stored in the second virtual block at the same time. That is, since the first virtual block is in the first plane and the second virtual block is in the second plane, a write or read operation on the first virtual block can be performed at the same time or nearly the same time as a write or read operation on the second virtual block.

[0113] Reference is now made to Figure 14 , showing a flowchart of a method 1400 of forming a multi-plane multi-die virtual block from a plurality of multi-plane virtual blocks, according to some examples of the present disclosure. The method 1400 can be performed by a controller (e.g., the controller 105) or by either or both of a memory control unit (e.g., the memory control unit 430) on one or more memory dies (e.g., the memory dies 400, 130A-130N+1). At operation 1410, a first multi-plane virtual block on a first die is identified. For example, the process of Figure 13 is used. At operation 1415, a second multi-plane virtual block on a second die is identified. For example, the process of Figure 13The process of operation 1410 can be performed in a similar manner as the process of operation 1405. At operation 1420, a multi-plane multi-die virtual block can be generated by both the first and second multi-plane virtual blocks identified in operations 1410 and 1415. For example, the memory controller can store information about the composition of the multi-plane multi-die virtual block in a data structure. For example, a logical to physical translation table can be used to translate logical addresses to effective physical addresses. At operation 1425, a first portion of data can be stored in the first virtual block and a second portion concurrently stored in the second virtual block. For example, the data can be striped across dies and across planes within each die.

[0114] As mentioned previously, the salvaging of portions of a memory block marked as defective occurs automatically, but in other examples, this can be a feature that can be enabled during device setup and / or initialization or during runtime. For example, the salvageable blocks can be marked as salvageable after manufacturing during initial testing rather than during enablement. Once a number of initial good blocks are marked as bad (e.g., they degrade in use and data on them fails to decode against an error correction code (ECC) a threshold number of times), the salvageable blocks can be enabled. This allows the memory device to continue storing the advertised capacity for a longer period of time and thus extends the useful life of the memory device. For example, the newly available salvageable blocks can be used to store user data, for over provisioning, for temporary storage (e.g., during garbage collection), for system data, etc. The use of the salvageable portions can be enabled by logic on the memory die itself, by a controller of the memory device, a host, etc. Once activated, the memory die or controller can add the previously identified salvageable portions as available blocks or block portions to the logical to physical mapping table. In some examples, as described previously, the controller can form virtual blocks with one or more multiple block portions, as described with respect to Figures 11 to 14 In still other examples, all portions are initially marked as bad and once the feature is enabled, the system can determine which portions are salvageable and enable them.

[0115] As described previously, while the figure has two portions (stacks) and one portion is salvageable, in other examples, the memory die can have more than two portions (e.g., three stacks) and more than one portion can be salvageable. In still other examples, the memory die can have only one stack, but the portion can be other portions of the stack, such as sub-blocks, etc.

[0116] Figure 9 、 10The methods illustrated in 12-14 can be implemented by special purpose hardware configured to perform the methods, by software stored on a general purpose processor configured such that the general purpose processor performs the methods, or by a combination of special purpose hardware and software. In software-based implementations, instructions can be stored on a computer- or machine-readable medium, which can be non-transitory. The instructions, when executed, cause a processor or other hardware to perform operations to carry out the methods.

[0117] Figure 15 A block diagram of an example machine 1500 is illustrated that can perform any one or more of the techniques (e.g., methods) discussed herein. The machine 1500, or one or more components of the machine 1500, can implement one or more of the memory devices or components of the memory devices described herein. For example, the machine 1500, or one or more components of the machine 1500, can implement the memory device 100. In some examples, the machine 1500 can be the host device 135. In some examples, the main memory 1504, the static memory 1506, and / or the mass storage device 1521 can be implemented by, e.g., the memory of the devices discussed herein with respect to Figures 1 to 12 the devices.

[0118] In alternative embodiments, the machine 1500 can operate as a standalone device or can be connected (e.g., networked) to other machines. In a networked deployment, the machine 1500 can operate in the capacity of a server machine, a host machine, a client machine, or some combination thereof, in a server-client network environment. In an example, the machine 1500 can act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine 1500 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, an IoT device, an automotive system, a host device, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.

[0119] Examples, as described herein, can include, or can operate on, logic or a number of components, modules, or mechanisms (hereinafter "modules"), or a combination thereof. Modules are tangible entities (e.g., hardware) capable of performing specified operations and can be configured or arranged in a certain manner. In an example, circuits can be arranged (e.g., internally or with respect to external entities such as other circuits) in a specified manner as a module. In an example, the whole or part of one or more computer systems (e.g., a standalone, client or server computer system) or one or more hardware processors can be configured by firmware or software (e.g., instructions, an application portion, or an application) as a module that operates to perform specified operations. In an example, the software can reside on a machine readable medium. In an example, the software, when executed by the underlying hardware of the module, causes the hardware to perform the specified operations.

[0120] Accordingly, the term "module" is understood to encompass a tangible entity, be that entity hardware, firmware, or software, that is specifically configured to perform portions or all of any operation described herein. In examples in which multiple so- called "modules" are described, each module can correspond to a separate entity. For example, in examples in which the module comprises the use of software, the software can be configured such that separate pieces of hardware are configured to perform the various portions of the software. Of course, software can be configured in any manner as would be known to one of ordinary skill in the art having the benefit of the present disclosure.

[0121] A machine (e.g., computer system) 1500 (e.g., host device 135, memory device 100, etc.) can include hardware processor 1502 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, etc.), main memory 1504, and static memory 1506, some or all of which can communicate with one another via an interlink (e.g., bus) 1508. The machine 1500 can further include a display unit 1510, an alphanumeric input device 1512 (e.g., a keyboard), and a user interface (UI) navigation device 1514 (e.g., a mouse). In an example, the display unit 1510, input device 1512 and UI navigation device 1514 can be a touch screen display. The machine 1500 can additionally include a storage device (e.g., a disk drive, memory device 1521), a signal generation device 1518 (e.g., a speaker), a network interface device 1520, and one or more sensors 1516, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine 1500 can include an output controller 1528, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

[0122] The storage device 1521 can include a machine readable medium 1522 on which is stored one or more sets of data structures or instructions 1524 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 1524 can also reside completely, or at least partially, within the main memory 1504, within static memory 1506, or within the hardware processor 1502 during execution thereof by the machine 1500. In an example, one or any combination of the hardware processor 1502, the main memory 1504, the static memory 1506, or the storage device 1521 can constitute machine readable media 1522.

[0123] While the machine readable medium 1522 is illustrated as a single medium, the term "machine readable medium" can include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store the one or more instructions 1524.

[0124] The term "machine-readable medium" can include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine 1500 and that cause the machine 1500 to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting machine-readable medium examples can include solid-state memories, and optical and magnetic media. In an example, a massed machine-readable medium comprises a machine-readable medium with a plurality of particles having invariant (e.g., rest) mass. Accordingly, massed machine-readable media are non-transitory. Particular examples of massed machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0125] Instructions 1524 (e.g., software, programs, an operating system (OS), etc.) or other data are stored on storage device(s) 1521, which are accessed by memory 1504 for use by the processor(s) 1502. Memory 1504 (e.g., DRAM) is typically fast, but volatile, and thus is a different type of storage than storage device(s) 1521 (e.g., SSD), which is suitable for long-term storage, including when in an "off' state. Instructions 1524 or data for use by a user or the machine 1500 are usually loaded in memory 1504 for use by the processor(s) 1502. When memory 1504 is full, virtual space from storage device(s) 1521 can be allocated to supplement memory 1504; however, because storage device(s) 1521 is typically slower than memory 1504 and write speeds are typically at least twice as slow as read speeds, the use of virtual memory can greatly degrade user experience due to storage device latency (compared to memory 1504, e.g., DRAM). Moreover, the use of storage device(s) 1521 for virtual memory can greatly reduce the usable lifespan of storage device(s) 1521.

[0126] In contrast to virtual memory, virtual memory compression (e.g., Kernel feature "ZRAM") uses a portion of memory as a compressed block store to avoid paging to storage device(s) 1521. Paging is done in the compressed block until it is necessary to write this data to storage device(s) 1521. Virtual memory compression increases the available size of memory 1504 while reducing wear on storage device(s) 1521.

[0127] Storage devices optimized for mobile electronic devices or mobile storage traditionally include MMC solid state storage devices (e.g., microSD TM(e.g., cards, etc.) MMC devices contain several parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are typically detachable and separable components from the host device. In contrast, eMMC... TM The device is attached to the circuit board and is considered a component of the host device; its read speed is comparable to that based on Serial ATA. TM SSD devices using Serial Advanced Technology (AT) Attached, or SATA, were previously used. However, the demand for mobile device performance continued to increase to fully enable virtual or augmented reality devices, take advantage of increased network speeds, and so on. In response to this demand, storage devices have transitioned from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices, which include the controller and firmware, communicate with host devices using a Low Voltage Differential Signaling (LVDS) serial interface with a dedicated read / write path, further advancing read / write speeds.

[0128] The system can further utilize any of several transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) to transmit or receive instructions 1524 on the communication network 1526 via the network interface device 1520 using the transport medium. Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series standards, referred to as… The IEEE 802.16 series of standards are called This includes standards such as IEEE 802.15.4 series and peer-to-peer (P2P) networks. In an example, network interface device 1520 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to communication network 1526. In an example, network interface device 1520 may include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered as including any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 1500, and including digital or analog communication signals or other intangible media used to facilitate communication of such software.

[0129] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the application can be practiced. These embodiments are also referred to as "examples." Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0130] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" can include "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0131] In various examples, components, controllers, processors, units, engines, or tables described herein can include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computational circuit, such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuit, including a processor or multi-core device group.

[0132] Various embodiments in accordance with the present disclosure and described herein include memories that utilize vertical structures of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives will be taken in a relative to the surface of the substrate on which the memory cells are formed (i.e., a vertical structure will be taken to extend away from the substrate surface, a bottom end of a vertical structure will be taken to be the end closest to the substrate surface, and a top end of a vertical structure will be taken to be the end farthest from the substrate surface).

[0133] As used herein, directional adjectives, such as horizontal, vertical, orthogonal, parallel, perpendicular, etc., can refer to relative orientations and are not intended to require strict adherence to a particular geometric property, unless otherwise indicated. For example, as used herein, a vertical structure need not be exactly perpendicular to a surface of a substrate, but can instead be generally perpendicular to a surface of a substrate, and can form an acute angle (e.g., between 60 and 120 degrees, etc.) with a surface of a substrate.

[0134] In some embodiments described herein, different doping configurations can be applied to the source side select gate (SGS), control gate (CG), and drain side select gate (SGD), each of which in this example can be formed of or at least include polysilicon, resulting in such tiers (e.g., polysilicon, etc.) can have different etch rates when exposed to an etching solution. For example, during the process of forming a single pillar in a 3D semiconductor device, the SGS and CG can form a recess, while the SGD can remain less recessed or even un-recessed. These doping configurations can thus enable selective etching into different tiers (e.g., SGS, CG, and SGD) in a 3D semiconductor device by using an etching solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0135] As used herein, operating a memory cell includes reading from, writing to, or erasing the memory cell. An operation that places a memory cell in an intended state is referred to herein as “programming,” and can include writing to or erasing from the memory cell (e.g., a memory cell can be programmed to an erased state).

[0136] According to one or more embodiments of the present disclosure, a memory controller (e.g., processor, controller, firmware, etc.) located internal or external to a memory device is capable of determining (e.g., selecting, setting, adjusting, calculating, changing, clearing, communicating, adapting, deriving, defining, utilizing, modifying, imposing, etc.) a number of wear cycles or a wear state (e.g., recording wear cycles, counting operations of the memory device as they occur, tracking operations of the memory device that initiate them, evaluating memory device characteristics corresponding to the wear state, etc.).

[0137] According to one or more embodiments of the present disclosure, a memory access device can be configured to provide wear cycle information to a memory device with each memory operation. Memory device control circuitry (e.g., control logic) can be programmable to compensate for memory device performance changes corresponding to the wear cycle information. The memory device can receive the wear cycle information and determine one or more operational parameters (e.g., values, characteristics) in response to the wear cycle information.

[0138] It will be understood that when an element is referred to as being "on" another element, "connected to" another element, or "coupled to" another element, it can be directly on, connected, or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers present. If two elements are shown to be connected by a line, then unless otherwise indicated, the two elements can be coupled or directly coupled.

[0139] Method examples described herein can be at least partially processor- or computer- implemented. Some examples can include a computer- or machine-readable medium encoded with instructions that, when executed, cause an electronic device to perform a method as described in the above examples. Implementations of such methods can include code, such as microcode, assembly language code, a higher-level languages code, or the like. Such code can include computer readable instructions for performing various methods. The code can form portions of computer program products. Further, the code can be tangibly embodied in one or more volatile or non-volatile tangible computer-readable media. Examples of these tangible computer-readable media can include, but are not limited to: hard disks, removable magnetic disks, removable magnetic disks, magnetic cassettes, memory cards or sticks, RAM, ROM, solid state drives (SSDs), universal serial bus (USB) flash drives, embedded MMC (eMMC) devices, etc.

[0140] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments will be apparent to those of ordinary skill in the art upon reviewing the above description. The scope of the application should, therefore, be determined not with reference to the above description, but instead with reference to the appended claims, along with their full scope of equivalents. Likewise, the features described above can be grouped together in any number of ways, as will occur to those of ordinary skill in the art. Nothing reported is intended to be required or essential in any claim. Rather, the inventive subject matter can reside in less than all features of a particular disclosed embodiment. Accordingly, the claims are hereby incorporated into the detailed description, where each claim stands as a separate embodiment, which can be combined with the features of any other claims in any number of ways. The scope of the application should be determined, therefore, with reference to the appended claims and aught equivalents thereof.

[0141] Other Notes and Examples

[0142] Example 1 is a method for salvaging a portion of a defective block of a memory device, the method comprising: receiving a request to perform an operation on a second portion of a block of memory cells, a first portion of the block of memory cells having a defect of a type from a first list of identified defect types and the second portion not having a defect of a type from a second list of identified defect types, the second set of identified defect types including the first set of identified defect types; identifying a bias voltage for the first portion of the block based on an operation type; performing the operation on the second portion, the performing the operation including disabling the first portion during the operation by applying a bias voltage to a word line of the first portion.

[0143] In Example 2, the subject matter described in Example 1 includes, wherein the first portion is a first deck of the block and the second portion is a second deck of the block.

[0144] In Example 3, the subject matter described in Examples 1-2 includes, wherein the defect comprises a short between two or more word lines.

[0145] In Example 4, the subject matter described in Examples 1-3 includes, wherein the defect comprises a resistive word line.

[0146] In Example 5, the subject matter described in Examples 1-4 includes, wherein the operation is one of: storing host data in the second portion, reading host data from the second portion, or erasing the second portion.

[0147] In Example 6, the subject matter described in Examples 1-5 includes, wherein identifying the defect of the first portion comprises determining that the defect is present based on an error rate of the first portion during an operation.

[0148] In Example 7, the subject matter described in Examples 1-6 includes, wherein performing the operation on the second portion comprises decoding address bits of a request message, the address bits specifying a portion of the block of memory cells to which the operation is to be applied.

[0149] Example 8 is a memory device comprising: a processor; a memory storing instructions that, when executed, cause the processor to perform operations comprising: receiving a request to perform an operation on a second portion of a block of memory cells, a first portion of the block of memory cells having a defect of a type from a first list of identified defect types and the second portion not having a defect of a type from a second list of identified defect types, a second set of identified defect types including a first set of identified defect types; identifying a bias voltage for the first portion of the block based on an operation type; performing the operation on the second portion, the performing the operation including disabling the first portion during the operation by applying a bias voltage to word lines of the first portion.

[0150] In Example 9, the subject matter from Example 8 includes, wherein the first portion is a first deck of the block and the second portion is a second deck of the block.

[0151] In Example 10, the subject matter from Examples 8-9 includes, wherein the defect comprises a short between two or more word lines.

[0152] In Example 11, the subject matter from Examples 8-10 includes, wherein the defect comprises a resistive word line.

[0153] In Example 12, the subject matter from Examples 8-11 includes, wherein the operation performed on the second portion is one of: storing host data in the second portion, reading host data from the second portion, or erasing the second portion.

[0154] In Example 13, the subject matter from Examples 8-12 includes, wherein the operation of identifying the defect of the first portion comprises determining that the defect is present based on an error rate of the first portion during an operation.

[0155] In Example 14, the subject matter from Examples 8-13 includes, wherein the operation of performing an operation on the second portion comprises decoding address bits of a request message, the address bits specifying a portion of the block of memory cells to which the operation is to be applied.

[0156] Example 15 is a machine-readable storage medium storing instructions that, when executed, cause the machine to perform operations comprising: receiving a request to perform an operation on a second portion of a block of memory cells, a first portion of the block of memory cells having a defect of a type from a first list of identified defect types and the second portion not having a defect of a type from a second list of identified defect types, the second set of identified defect types including the first set of identified defect types; identifying a bias voltage for the first portion of the block based on an operation type; performing the operation on the second portion, the performing the operation including disabling the first portion during the operation by applying a bias voltage to word lines of the first portion.

[0157] In Example 16, the subject matter from Example 15 includes, wherein the first portion is a first deck of the block and the second portion is a second deck of the block.

[0158] In Example 17, the subject matter from Examples 15-16 includes, wherein the defect comprises a short between two or more word lines.

[0159] In Example 18, the subject matter from Examples 15-17 includes, wherein the defect comprises a resistive word line.

[0160] In Example 19, the subject matter from Examples 15-18 includes, wherein the operation performed on the second portion is one of: storing host data in the second portion, reading host data from the second portion, or erasing the second portion.

[0161] In Example 20, the subject matter from Examples 15-19 includes, wherein the operation of identifying the defect of the first portion comprises determining that the defect is present based on an error rate of the first portion during an operation.

[0162] In Example 21, the subject matter from Examples 15-20 includes, wherein the operation of performing an operation on the second portion comprises decoding address bits of a request message, the address bits specifying a portion of the block of memory cells to which the operation is to be applied.

[0163] Example 22 is a memory device comprising: means for receiving a request to perform an operation on a second portion of a block of memory cells, a first portion of the block of memory cells having a defect of a type from a first list of identified defect types and the second portion not having a defect of a type from a second list of identified defect types, the second set of identified defect types including the first set of identified defect types; means for identifying a bias voltage for the first portion of the block based on a type of operation; means for performing the operation on the second portion, the performing the operation including disabling the first portion during the operation by applying a bias voltage to a word line of the first portion.

[0164] In Example 23, the subject matter from Examples 22 includes, wherein the first portion is a first deck of the block and the second portion is a second deck of the block.

[0165] In Example 24, the subject matter from Examples 22-23 includes, wherein the defect comprises a short between two or more word lines.

[0166] In Example 25, the subject matter from Examples 22-24 includes, wherein the defect comprises a resistive word line.

[0167] In Example 26, the subject matter from Examples 22-25 includes, wherein the operation is one of: storing host data in the second portion, reading host data from the second portion, or erasing the second portion.

[0168] In Example 27, the subject matter from Examples 22-26 includes, wherein the means for identifying the defect of the first portion comprises means for determining that the defect is present based on an error rate of the first portion during the operation.

[0169] In Example 28, the subject matter from Examples 22-27 includes, wherein the means for performing the operation on the second portion comprises means for decoding address bits of a request message, the address bits specifying a portion of the block of memory cells to which the operation is to be applied.

[0170] Example 29 is a method for salvaging portions of a block of memory cells of a memory device, the method comprising: identifying a first portion of a first NAND block in the memory device having defects in the first portion of a type in a first identified list of defect types and a second portion of the first NAND block not having defects from a second identified list of defect types; identifying a first portion of a second NAND block in the memory device having defects in the first portion of the type in the first identified list of defect types and a second portion of the second NAND block not having defects from the second identified list of defect types; forming a virtual block using the second portion of the first NAND block and the second portion of the second NAND block; and storing data in the virtual block by storing a first portion of the data in the second portion of the first NAND block and a second portion of the data in the second portion of the second NAND block.

[0171] In Example 30, the subject matter from Example 29 includes, wherein forming the virtual block comprises creating a table entry in an L2P table indicating that the first portion and the second portion form a virtual block.

[0172] In Example 31, the subject matter from Examples 29-30 includes grouping a second virtual block with the virtual block and storing a third portion of data in the second virtual block.

[0173] In Example 32, the subject matter from Example 31 includes selecting the second virtual block based on the second virtual block being on a different plane than the virtual block, and wherein storing the third portion of data is simultaneous with storing the first portion of data.

[0174] In Example 33, the subject matter from Example 32 includes grouping the first virtual block and the second virtual block with a third virtual block, the third virtual block being on a different die than the first virtual block and the second virtual block.

[0175] In Example 34, the subject matter from Examples 29-33 includes, wherein the data is host data received from a host.

[0176] In Example 35, the subject matter from Examples 29-34 includes, wherein the data is system data.

[0177] In Example 36, the subject matter from Examples 34-35 includes, wherein the system data is part of a logical to physical translation table.

[0178] Example 37 is a memory device comprising: a processor; a memory storing instructions that, when executed, cause the processor to perform operations comprising: identifying, in the memory device, a first portion of a first NAND block having defects of a type in a first identified list of defect types and a second portion of the first NAND block not having defects from a second identified list of defect types; identifying, in the memory device, a first portion of a second NAND block having defects of the type in the first identified list of defect types and a second portion of the second NAND block not having defects from the second identified list of defect types; forming a virtual block using the second portion of the first NAND block and the second portion of the second NAND block; and storing data in the virtual block by storing a first portion of the data in the second portion of the first NAND block and a second portion of the data in the second portion of the second NAND block.

[0179] In Example 38, the subject matter from Examples 37 comprises, wherein the operation of forming the virtual block comprises creating a table entry in an L2P table indicating that the first portion and the second portion form a virtual block.

[0180] In Example 39, the subject matter from Examples 37-38 comprises, wherein the operations further comprise grouping a second virtual block with the virtual block and storing a third portion of data in the second virtual block.

[0181] In Example 40, the subject matter from Example 39 comprises, wherein the operations further comprise selecting the second virtual block based on the second virtual block being on a different plane than the virtual block, and wherein the operation of storing the third portion of data is concurrent with the operation of storing the first portion of data.

[0182] In Example 41, the subject matter from Example 40 comprises, wherein the operations further comprise grouping the first virtual block and the second virtual block with a third virtual block, the third virtual block being on a different die than the first virtual block and the second virtual block.

[0183] In Example 42, the subject matter from Examples 37-41 comprises, wherein the data is host data received from a host.

[0184] In Example 43, the subject matter from Examples 37-42 comprises, wherein the data is system data.

[0185] In Example 44, the subject matter from Examples 42-43 comprises, wherein the system data is part of a logical to physical translation table.

[0186] Example 45 is a machine readable medium storing instructions which, when executed by a machine, cause the machine to perform operations comprising: identifying, in a memory device, a first portion of a first NAND block having defects of a type in a first identified list of defect types and a second portion of the first NAND block not having defects from a second identified list of defect types; identifying, in the memory device, a first portion of a second NAND block having defects of the type in the first identified list of defect types and a second portion of the second NAND block not having defects from the second identified list of defect types; forming a virtual block using the second portion of the first NAND block and the second portion of the second NAND block; and storing data in the virtual block by storing a first portion of the data in the second portion of the first NAND block and a second portion of the data in the second portion of the second NAND block.

[0187] In Example 46, the subject matter from Example 45 includes, wherein the operation of forming the virtual block comprises creating a table entry in an L2P table indicating that the first portion and the second portion form a virtual block.

[0188] In Example 47, the subject matter from Examples 45-46 includes, wherein the operations further comprise grouping a second virtual block with the virtual block and storing a third portion of data in the second virtual block.

[0189] In Example 48, the subject matter from Example 47 includes, wherein the operations further comprise selecting the second virtual block based on the second virtual block being on a different plane than the virtual block, and wherein the operation of storing the third portion of data is concurrent with the operation of storing the first portion of data.

[0190] In Example 49, the subject matter from Example 48 includes, wherein the operations further comprise grouping the first virtual block and the second virtual block with a third virtual block, the third virtual block being on a different die than the first virtual block and the second virtual block.

[0191] In Example 50, the subject matter from Examples 45-49 includes, wherein the data is host data received from a host.

[0192] In Example 51, the subject matter from Examples 45-50 includes, wherein the data is system data.

[0193] In Example 52, the subject matter from Examples 50-51 includes, wherein the system data is part of a logical to physical translation table.

[0194] Example 53 is a memory device comprising: means for identifying, in the memory device, a first portion of a first NAND block having defects in the first portion of a type in a first identified defect type list and a second portion of the first NAND block not having defects from a second identified defect type list; means for identifying, in the memory device, a first portion of a second NAND block having defects in the first portion of the type in the first identified defect type list and a second portion of the second NAND block not having defects from the second identified defect type list; means for forming a virtual block using the second portion of the first NAND block and the second portion of the second NAND block; and means for storing data in the virtual block by storing a first portion of the data in the second portion of the first NAND block and a second portion of the data in the second portion of the second NAND block.

[0195] In Example 54, the subject matter from Example 53 includes, wherein the means for forming the virtual block comprises means for creating an entry in an L2P table indicating that the first portion and the second portion form a virtual block.

[0196] In Example 55, the subject matter from Examples 53-54 includes means for grouping a second virtual block with the virtual block and storing a third portion of data in the second virtual block.

[0197] In Example 56, the subject matter from Example 55 includes means for selecting the second virtual block based on the second virtual block being on a different plane than the virtual block, and wherein storing the third portion of data is concurrent with storing the first portion of data.

[0198] In Example 57, the subject matter from Example 56 includes means for grouping the first virtual block and the second virtual block with a third virtual block, the third virtual block being on a different die than the first virtual block and the second virtual block.

[0199] In Example 58, the subject matter from Examples 53-57 includes, wherein the data is host data received from a host.

[0200] In Example 59, the subject matter from Examples 53-58 includes, wherein the data is system data.

[0201] In example 60, the subject matter of examples 58-59 includes, wherein the system data is part of a logical to physical translation table.

[0202] Example 61 is at least one machine readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of examples 1-60.

[0203] Example 62 is an apparatus comprising means for implementing any of examples 1-60.

[0204] Example 63 is a system for implementing any of examples 1-60.

[0205] Example 64 is a method for implementing any of examples 1-60.

Claims

1. A memory device comprising: processor; A memory that stores instructions, which, when executed, cause the processor to perform operations including: The first stack of blocks of the three-dimensional NAND is identified as having defects of the type from the first identified defect type list; The second stack of the identified block does not have defects from the first identified defect type list; The second stack is tested to determine whether it meets at least one quality criterion; In response to determining that the second stack does not have defects from the first identified defect type list and that the second stack meets at least one quality criterion, the second stack is marked as salvageable; Receive a request to perform an operation on the second stack group; The bias voltage of the first stack of the block is identified based on the operation type; as well as The operation is performed on the second stack group, the operation including deactivating the first stack group by applying a bias voltage to the word line of the first stack group during the operation.

2. The memory device of claim 1, wherein the defect includes a short circuit between two or more word lines.

3. The memory device of claim 1, wherein the defect includes resistive word lines.

4. The memory device of claim 1, wherein the operation performed on the second stack is one of: storing host data in the second stack, reading host data from the second stack, or erasing data on the second stack.

5. The memory device of claim 1, wherein the operation of identifying the defect of the first stack comprises determining the presence of the defect based on the error rate of the first stack during operation.

6. The memory device of claim 1, wherein the operation of performing the operation on the second stack includes decoding address bits of a request message, the address bits specifying the stack of memory cell blocks to which the operation is to be applied.

7. A method for rescuing a portion of a defective block in a memory device, the method comprising: The first stack of blocks of the three-dimensional NAND is identified as having defects of the type from the first identified defect type list; The second stack of the identified block does not have defects from the first identified defect type list; The second stack is tested to determine whether it meets at least one quality criterion; In response to determining that the second stack does not have defects from the first identified defect type list and that the second stack meets at least one quality criterion, the second stack is marked as salvageable; Receive a request to perform an operation on the second stack group; The bias voltage of the first stack of the block is identified based on the operation type; as well as The operation is performed on the second stack group, the operation including deactivating the first stack group by applying a bias voltage to the word line of the first stack group during the operation.

8. The method of claim 7, wherein the defect includes a short circuit between two or more word lines.

9. The method of claim 7, wherein the defect includes a resistive word line.

10. The method of claim 7, wherein the operation is one of: storing host data in the second stack, reading host data from the second stack, or erasing data on the second stack.

11. The method of claim 7, wherein identifying the defect of the first stack comprises determining the presence of the defect based on the error rate of the first stack during operation.

12. The method of claim 7, wherein performing the operation on the second stack includes decoding the address bits of a request message, the address bits specifying the stack of memory cell blocks to which the operation is to be applied.

13. A machine-readable storage medium storing instructions that, when executed, cause the machine to perform operations including: The first stack of blocks of the three-dimensional NAND is identified as having defects of the type from the first identified defect type list; The second stack of the identified block does not have defects from the first identified defect type list; The second stack is tested to determine whether it meets at least one quality criterion; In response to determining that the second stack does not have defects from the first identified defect type list and that the second stack meets at least one quality criterion, the second stack is marked as salvageable; Receive a request to perform an operation on the second stack group; The bias voltage of the first stack of the block is identified based on the operation type; as well as The operation is performed on the second stack group, the operation including deactivating the first stack group by applying a bias voltage to the word line of the first stack group during the operation.

14. The machine-readable storage medium of claim 13, wherein the defect includes a short circuit between two or more word lines.

15. The machine-readable storage medium of claim 13, wherein the defect includes resistive word lines.

16. The machine-readable storage medium of claim 13, wherein the operation performed on the second stack is one of: storing host data in the second stack, reading host data from the second stack, or erasing data on the second stack.

17. The machine-readable storage medium of claim 13, wherein the operation of identifying the defect in the first stack comprises determining the presence of the defect based on the error rate of the first stack during operation.

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