Memory device and method of operation thereof

Abstract

A memory device capable of reducing peak current includes a plurality of strings of memory cells each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating a memory device includes pre-charging channel regions of the plurality of strings of memory cells through the common source line and setting a bit line voltage applied to the bit line while the channel regions of the plurality of strings of memory cells are being pre-charged after starting pre-charging the channel regions of the plurality of strings of memory cells.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0109111, filed on August 28, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to an electronic device, and more specifically, to a memory device and a method of operating the same. Background Technology

[0004] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device can include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are memory devices that store data only when power is supplied and lose the stored data when power is interrupted. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices are memory devices in which data is retained even when power is interrupted. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the Invention

[0007] The embodiments provide a memory device capable of reducing peak current and a method of operating the memory device.

[0008] According to one aspect of this disclosure, a method for operating a memory device is provided, the memory device including a plurality of memory cell strings, each of the plurality of memory cell strings including: a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells, the method including: pre-charging a channel region of the plurality of memory cell strings through the common source line; and setting a bit line voltage applied to the bit line while the channel regions of the plurality of memory cell strings are being pre-charged after the pre-charging of the channel regions of the plurality of memory cell strings has begun.

[0009] According to another aspect of this disclosure, a memory device is provided, the memory device including a plurality of memory blocks, peripheral circuitry, and a programming operation controller; each of the plurality of memory blocks includes a plurality of memory cell strings, each of the plurality of memory cell strings including: a plurality of memory cells connected in series between a common source line and a bit line, a plurality of source select lines connected in series between the common source line and the plurality of memory cells, and a plurality of drain select lines connected in series between the bit line and the plurality of memory cells; the peripheral circuitry is configured to execute a plurality of programming cycles, each of the plurality of programming cycles including: a programming voltage application step of providing a programming voltage to a selected memory block among the plurality of memory blocks, and a verification step of verifying the programming state of the selected memory block; the programming operation controller is configured to: control the peripheral circuitry to precharge the channel regions of the plurality of memory cell strings through the common source line, and in the programming voltage application step, set the bit line voltage applied to the bit line at a predetermined time relative to the start of precharging the channel regions of the plurality of memory cell strings.

[0010] According to another aspect of this disclosure, a method for operating a memory device is provided, the memory device including a plurality of memory cell strings, each of the plurality of memory cell strings including: a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells, the method including: increasing the voltage of the common source line; increasing the voltage of the source select line of each of the plurality of memory cell strings applied to the common source line through the common source line; and, while the voltage of the source select line of each of the plurality of memory cell strings applied to the source line is increased, setting the bit line voltage applied to the bit line after a predetermined elapsed time after the voltage of the source select line of each of the plurality of memory cell strings is increased.

[0011] According to one aspect of this disclosure, a memory device is provided, including a plurality of memory blocks, peripheral circuitry, and a programming operation controller; each of the plurality of memory blocks includes a plurality of memory cell strings, each of the plurality of memory cell strings including: a plurality of memory cells connected in series between a common source line and a bit line, wherein at least one memory cell is a dummy memory cell; a plurality of source select lines connected in series between the common source line and the plurality of memory cells; and a plurality of drain select lines connected in series between the bit line and the plurality of memory cells; the peripheral circuitry is configured to execute a plurality of programming cycles, each of the plurality of programming cycles including: a programming voltage application step of providing a programming voltage to a selected memory block among the plurality of memory blocks, and a verification step of verifying the programming state of the selected memory block; the programming operation controller is configured to: control the peripheral circuitry to precharge the channel regions of the plurality of memory cell strings through the common source line, and in the programming voltage application step, set the bit line voltage applied to the bit line at a predetermined time relative to the start of precharging the channel regions of the plurality of memory cell strings.

[0012] At least one dummy memory cell can reduce the electric field between a predetermined source selection transistor and a predetermined first portion of a plurality of memory cells.

[0013] At least one dummy memory cell can reduce the electric field between a predetermined drain-select transistor and a predetermined second part of the memory cell. Attached Figure Description

[0014] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0015] In the accompanying drawings, dimensions may be enlarged for clarity. It should be understood that when an element is referred to as "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements. Throughout the text, similar reference numerals refer to similar elements.

[0016] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0017] Figure 2 It is a diagram. Figure 1 A diagram of the memory device shown.

[0018] Figure 3 It is a diagram. Figure 2 A diagram of an embodiment of the memory cell array shown.

[0019] Figure 4 It is a diagram. Figure 3 The circuit diagram of any one of the memory blocks shown.

[0020] Figure 5 It is a diagram. Figure 3 A circuit diagram of another embodiment of one of the memory blocks shown.

[0021] Figure 6 It is a diagram. Figure 3 A circuit diagram of yet another embodiment of one of the memory blocks shown.

[0022] Figure 7 It is a diagram. Figure 2 The diagram shows the programming operations of the memory device.

[0023] Figure 8 It is a diagram. Figure 2 The diagram shows the memory cells included in the memory device in the order in which they are programmed.

[0024] Figure 9 This is a waveform diagram illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0025] Figure 10 This is a waveform diagram illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0026] Figure 11 yes Figure 2 The diagram shows the configuration of the programmable controller included in the control logic.

[0027] Figure 12 It is a diagram. Figure 1 The diagram shows the memory controller.

[0028] Figure 13 This is a block diagram illustrating a memory card system of a storage device according to an embodiment of the present disclosure.

[0029] Figure 14 This is an exemplary block diagram illustrating a solid-state drive (SSD) system that applies a storage device according to an embodiment of the present disclosure.

[0030] Figure 15 This is a block diagram illustrating a user system using a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0031] The specific structural or functional descriptions disclosed herein are illustrative only and are intended to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0032] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0033] refer to Figure 1 Storage device 50 may include memory device 100 and memory controller 200 for controlling the operation of memory device 100. Storage device 50 may be a device for storing data under the control of host 300, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0034] Depending on the host interface arranged with the host 300 in a communication scheme, the storage device 50 can be manufactured as any of various types of storage devices. For example, the storage device 50 can be implemented using any of various types of storage devices, such as solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), small form factor MMCs (RS-MMCs), micro MMCs (micro-MMCs), secure digital cards (SDs), mini SD cards, micro SD cards, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media cards (SMCs), memory sticks, etc.

[0035] Storage device 50 can be manufactured in any of a variety of package types. For example, storage device 50 can be manufactured in any of a variety of package types, such as stacked package (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0036] The memory device 100 can store data. The memory device 100 can operate under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) that includes a plurality of memory cells for storing data.

[0037] Each memory cell in the memory unit can operate as any of the following: a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, and a four-level cell (QLC) storing four data bits.

[0038] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In one embodiment, a page may be a unit for storing data in or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0039] In one embodiment, the memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Transfer Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, the case where the memory device 100 is NAND flash memory is assumed and described.

[0040] Memory device 100 can receive commands CMD and addresses ADDR from memory controller 200 and access the region selected by address ADDR in the memory cell array. Memory device 100 can perform operations indicated by command CMD on the region selected by address ADDR. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. In a programming operation, memory device 100 can program the data in the region selected by address ADDR. In a read operation, memory device 100 can read data from the region selected by address ADDR. In an erase operation, memory device 100 can erase the data stored in the region selected by address ADDR.

[0041] In one embodiment, the memory device 100 may include a programming operation controller 131.

[0042] The programming operation controller 131 can perform programming operations that store data in multiple memory cells included in the memory device 100.

[0043] In one embodiment, the programming operation controller 131 can control the memory device to precharge a channel region of a plurality of memory cell strings comprising a plurality of memory cells and set a voltage applied to bit lines connected to the plurality of memory cells, wherein precharging of the channel can be initiated and then, during at least a predetermined portion of the precharging, a bit line voltage that can be applied to the bit lines can be followed.

[0044] In one embodiment, the memory device 100 can precharge the channel regions of a plurality of memory cell strings via a common source line.

[0045] Furthermore, in one embodiment, after precharging of the channel regions of the plurality of memory cell strings begins, while the channel regions of the plurality of memory cell strings are being precharged, the memory device 100 may set a bit line voltage to be applied to the bit lines.

[0046] The memory controller 200 can control the overall operation of the storage device 50.

[0047] When power is applied to storage device 50, memory controller 200 can execute firmware (FW). When storage device 100 is a flash memory device, FW may include: a host interface layer (HIL) for controlling communication with host 300, a flash translation layer (FTL) for controlling communication between host and storage device 100, and a flash interface layer (FIL) for controlling communication with storage device 100.

[0048] In one embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300 and translate the LBA into a physical block address (PBA), which represents the address of a memory cell included in the memory device 100 where data is to be stored. In this specification, LBA and "logical address" or "logical address" may be used with the same meaning. In this specification, PBA and "physical address" may be used with the same meaning.

[0049] In response to a request from host 300, memory controller 200 can control memory device 100 to perform programming operations, read operations, erase operations, etc. During a programming operation, memory controller 200 can provide programming commands, PBAs, and data to memory device 100. During a read operation, memory controller 200 can provide read commands and PBAs to memory device 100. During an erase operation, memory controller 200 can provide erase commands and PBAs to memory device 100.

[0050] In one embodiment, the memory controller 200 can autonomously generate commands, addresses, and data regardless of any requests from the host 300, and transmit these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 for performing read operations and programming operations that accompany wear leveling, read recycling, garbage collection, etc.

[0051] In one embodiment, the memory controller 200 can control at least two memory devices 100. The memory controller 200 can control the memory devices according to an interleaving technique to improve operational performance. The interleaving technique can be a method for controlling the operation of at least two memory devices 100 to overlap with each other.

[0052] The host 300 can communicate with the storage device 50 using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0053] Figure 2 It is a diagram. Figure 1 A diagram of the memory device 100 shown.

[0054] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0055] Memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz can be connected to row decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz can be connected to page buffer group 123 via bit lines BL1 to BLm. Each memory block in the multiple memory blocks BLK1 to BLKz may include multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block may include multiple pages.

[0056] A row line RL may include at least one source select line, multiple word lines, and at least one drain select line.

[0057] Each memory cell included in the memory cell array 110 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0058] The peripheral circuit 120 can perform programming, reading, or erasing operations on selected regions of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 can drive the memory cell array 110. For example, the peripheral circuit 120 can apply various operating voltages to the row lines RL and bit lines BL1 to BLm or discharge the applied voltages under the control of the control logic 130.

[0059] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0060] The row decoder 121 can be connected to the memory cell array 110 via row lines RL. The row line RL may include at least one source select line, multiple word lines, and at least one drain select line. In one embodiment, the word lines may include ordinary word lines and dummy word lines. In another embodiment, the row line RL may further include pipe select lines.

[0061] The line decoder 121 can operate under the control of the control logic. The line decoder 121 can receive the line address RADD from the control logic 130.

[0062] The row decoder 121 can decode the row address RADD. The row decoder 121 can select at least one memory block from memory blocks BLK1 to BLKz based on the decoded address. In addition, the row decoder 121 can select at least one word line of the selected memory block to apply the voltage generated by the voltage generator 122 to at least one word line WL according to the decoded address.

[0063] For example, in a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and can apply a programming pass voltage with a level lower than the programming voltage to the unselected word line. In a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and can apply a verification pass voltage with a level higher than the verification voltage to the unselected word line.

[0064] During a read operation, the line decoder 121 can apply a read voltage to the selected word line and can apply a read voltage with a level higher than the read voltage to the unselected word line.

[0065] In one embodiment, the erase operation of memory device 100 can be performed on a block-by-block basis. During the erase operation, row decoder 121 can select a memory block based on the decoded address. During the erase operation, row decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0066] Voltage generator 122 can operate under the control of control logic 130. Voltage generator 122 can generate multiple voltages using the external power supply voltage provided to memory device 100. Specifically, in response to the operation signal OPSIG, the voltage generator can generate various operating voltages Vop used in programming, reading, and erasing operations. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., under the control of control logic 130.

[0067] In one embodiment, voltage generator 122 can generate an internal supply voltage by adjusting an external supply voltage. The internal supply voltage generated by voltage generator 122 can be used as the operating voltage of memory device 100.

[0068] In one embodiment, voltage generator 122 can generate multiple voltages by using an external supply voltage or an internal supply voltage.

[0069] For example, voltage generator 122 may include a plurality of pump capacitors for receiving an internal supply voltage, and voltage generator 122 may generate a plurality of voltages by selectively activating the plurality of pump capacitors under the control of control logic 130.

[0070] Multiple generated voltages can be provided to the memory cell array 110 via the row decoder 121.

[0071] Page buffer group 123 may include first page buffers to m-th page buffers PB1 to PBm. First page buffers to m-th page buffers PB1 to PBm may be connected to memory cell array 110 via first bit lines to m-th bit lines BL1 to BLm, respectively. First bit lines to m-th bit lines BL1 to BLm may operate under the control of control logic 130. Specifically, first bit lines to m-th bit lines BL1 to BLm may operate in response to page buffer control signal PBSIGNALS. For example, first page buffers to m-th page buffers PB1 to PBm may temporarily store data received via first bit lines to m-th bit lines BL1 to BLm, or sense the voltage or current of bit lines BL1 to BLm during read or verification operations.

[0072] Specifically, during programming operations, when a programming voltage is applied to the selected word line, the first page buffer to the m-th page buffers PB1 to PBm can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first bit line to the m-th bit line BL1 to BLm. The memory cell of the selected page can be programmed based on the transmitted data DATA. Memory cells connected to the bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to the bit lines to which a programming disable voltage (e.g., supply voltage) is applied can be maintained. During programming verification operations, the first page buffer to the m-th page buffers PB1 to PBm can read page data from the selected memory cell via the first bit line to the m-th bit line BL1 to BLm.

[0073] During the read operation, the first page buffer to the m-th page buffers PB1 to PBm can read data DATA from the memory cell of the selected page through the first bit line to the m-th bit line BL1 to BLm, and under the control of the column decoder 124, the read data DATA can be output to the input / output circuit 125.

[0074] During the erase operation, the first page buffer to the m-th page buffer PB1 to PBm can float the first bit line to the m-th bit line BL1 to BLm.

[0075] In response to the column address CADD, the column decoder 124 can communicate data between the input / output circuitry 125 and the page buffer group 123. For example, the column decoder 124 can communicate data with the first page buffer to the m-th page buffers PB1 to PBm via the data line DL, or it can communicate data with the input / output circuitry 125 via the column line CL.

[0076] The input / output circuit 125 can be obtained from the reference. Figure 1 The memory controller 200 described herein receives commands CMD and addresses ADDR and passes them to control logic 130, or may exchange data DATA with column decoder 124.

[0077] During a read or verification operation, the sensing circuit 126 can generate a reference current in response to the enable bit VRYBIT signal, and can output a pass signal PASS or a failure signal FAIL by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current.

[0078] In response to the command CMD and address ADDR, control logic 130 can control peripheral circuitry 120 by outputting the operation signal OPSIG, the row address RADD, the page buffer control signal PBSIGNALS, and the enable bit VRYBIT. Furthermore, in response to the pass signal PASS or the failure signal FAIL, control logic 130 can determine whether the verification operation has passed or failed.

[0079] In one embodiment, control logic 130 may include a programmable operation controller 131.

[0080] The programming operation controller 131 can perform programming operations that store data in multiple memory cells included in the memory device 100.

[0081] In one embodiment, the programming operation controller 131 can control the memory device to precharge a channel region of a plurality of memory cell strings comprising a plurality of memory cells and set a voltage applied to bit lines connected to the plurality of memory cells, wherein precharging of the channel region can be initiated and then setting of the voltage applied to the bit lines can be initiated.

[0082] Reference Figure 11 Detailed description of the programmable controller 131.

[0083] Figure 3 It is a diagram. Figure 2 A diagram of an embodiment of the memory cell array shown.

[0084] refer to Figure 3 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate (not shown). The multiple memory cells may be arranged along the +X, +Y, and +Z directions. (Refer to...) Figure 4 and Figure 5 The structure of each memory block is described in more detail.

[0085] Figure 4 It is a diagram. Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz shown.

[0086] refer to Figure 4 The memory block BLKa may include multiple memory cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the multiple memory cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m memory cell strings may be arranged in the row direction (i.e., the +X direction). Figure 4 The illustration shows two strings of memory cells arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it should be understood that three strings of memory cells can be arranged in the column direction.

[0087] Each of the multiple memory cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell to an nth memory cell MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0088] The selector transistors SST and DST, and the memory cells MC1 to MCn, can have structures similar to each other. In one embodiment, each of the selector transistors SST and DST, and the memory cells MC1 to MCn, may include a channel layer, a tunnel insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, pillars for providing the channel layer may be provided in each memory cell string. In one embodiment, pillars for providing at least one of the channel layer, tunnel insulating layer, charge storage layer, and barrier insulating layer may be provided in each memory cell string.

[0089] The source selection transistor SST of each memory cell string can be connected between the common source line CSL and memory cells MC1 to MCp.

[0090] In one embodiment, the source select transistors of memory cell strings arranged in the same row can be connected to source select lines extending in the row direction, and the source select transistors of memory cell strings arranged in different rows can be connected to different source select lines. Figure 4 In the first row, the source select transistors of memory cell strings CS11 to CS1m can be connected to the first source select line SSL1. The source select transistors of memory cell strings CS21 to CS2m in the second row can be connected to the second source select line SSL2.

[0091] In another embodiment, the source select transistors of memory cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source select line.

[0092] The first memory cell to the nth memory cell MC1 to MCn of each memory cell string can be connected between the source selection transistor SST and the drain selection transistor DST.

[0093] The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp can be arranged sequentially in opposite directions in the +Z direction and can be connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th to nth memory cells MCp+1 to MCn can be arranged sequentially in the +Z direction and can be connected in series between the channel transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn can be connected via the channel transistor PT. The gate electrodes of the first to nth memory cells MC1 to MCn in each memory cell string can be connected to the first word line to the nth word line WL1 to WLn, respectively.

[0094] The gate of the pipe transistor PT in each memory cell string can be connected to the pipe line PL.

[0095] The drain select transistor (DST) of each memory cell string can be connected between the corresponding bit line and memory cells MCp+1 to MCn. Memory cell strings arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors of memory cell strings CS11 to CS1m in the first row can be connected to the first drain select line DSL1. The drain select transistors of memory cell strings CS21 to CS2m in the second row can be connected to the second drain select line DSL2.

[0096] A string of memory cells arranged in the column direction can be connected to bit lines extending in the column direction. Figure 4 In the diagram, memory cell strings CS11 and CS21 in the first column can be connected to the first bit line BL1. Memory cell strings CS1m and CS2m in the m-th column can be connected to the m-th bit line BLm.

[0097] In a row-oriented memory cell string, memory cells connected to the same word line can form a page. For example, memory cells in the memory cell strings CS11 to CS1m in the first row connected to the first word line WL1 can form a page. Memory cells in the memory cell strings CS21 to CS2m in the second row connected to the first word line WL1 can form another page. When either drain select line DSL1 or DSL2 is selected, a memory cell string arranged in a row direction can be selected. When any word line WL1 to WLn is selected, a page can be selected from the selected memory cell string.

[0098] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit lines to the m-th bit lines BL1 to BLm. Furthermore, memory cell strings with even-numbered addresses in the row-direction memory cell strings CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and memory cell strings with odd-numbered addresses in the row-direction memory cell strings CS11 to CS1m or CS21m to CS2m can be connected to the odd-numbered bit lines.

[0099] In one embodiment, at least one of the memory cells MC1 to MCn from the first memory cell to the nth memory cell can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. Increasing the number of dummy memory cells can improve the operational reliability of the memory block BLKa. On the other hand, the size of the memory block BLKa can be increased. When the number of dummy memory cells decreases, the size of the memory block BLKa can be decreased. On the other hand, the operational reliability of the memory block BLKa may decrease.

[0100] To effectively control at least one dummy memory cell, the dummy memory cell can have a desired threshold voltage. Before or after an erase operation on memory block BLKa, a programming operation can be performed on all or some of the dummy memory cells. When an erase operation is performed after a programming operation, the threshold voltage of the dummy memory cell can control the voltage applied to the dummy word line connected to the corresponding dummy memory cell, ensuring that the dummy memory cell has the desired threshold voltage.

[0101] Figure 5 It is a diagram. Figure 3 The circuit diagram shows another embodiment of memory block BLKb, one of the memory blocks BLK1 to BLKz shown.

[0102] refer to Figure 5The memory block BLKb may include multiple memory cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple memory cell strings CS11' to CS1m' and CS21' to CS2m' may extend along the +Z direction. Each of the multiple memory cell strings CS11' to CS1m' and CS21' to CS2m' may include at least one source selection transistor SST, first memory cells to nth memory cells MC1 to MCn, and at least one drain selection transistor DST, which may be stacked on a substrate (not shown) beneath the memory block BLKb.

[0103] The source select transistor SST of each memory cell string can be connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of memory cell strings arranged in the same row can be connected to the same source select line. The source select transistors of memory cell strings CS11' to CS1m' arranged in the first row can be connected to the first source select line SSL1. The source select transistors of memory cell strings CS21' to CS2m' arranged in the second row can be connected to the second source select line SSL2. In another embodiment, the source select transistors of memory cell strings CS11' to CS1m' and CS21' to CS2m' can be connected to a common source select line.

[0104] The first memory cell to the nth memory cell MC1 to MCn in each memory cell string can be connected in series between the source selection transistor SST and the drain selection transistor DST. The gate electrodes of the first memory cell to the nth memory cell MC1 to MCn can be connected to the first word line to the nth word line WL1 to WLn, respectively.

[0105] The drain select transistor (DST) of each memory cell string can be connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of memory cell strings arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors of memory cell strings CS11' to CS1m' in the first row can be connected to the first drain select line DSL1. The drain select transistors of memory cell strings CS21' to CS2m' in the second row can be connected to the second drain select line DSL2.

[0106] Therefore, in addition to from Figure 5 Each memory cell string in the array excludes the pipe transistor PT. Figure 5 The memory block BLKb has the same Figure 4 The circuitry is similar to that of the memory block BLKa.

[0107] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit lines to the m-th bit lines BL1 to BLm. Furthermore, memory cell strings with even-numbered addresses in the row-direction memory cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the even-numbered bit lines, and memory cell strings with odd-numbered addresses in the row-direction memory cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the odd-numbered bit lines.

[0108] In one embodiment, at least one of the memory cells MC1 to MCn from the first memory cell to the nth memory cell can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. Increasing the number of dummy memory cells can improve the operational reliability of the memory block BLKb. On the other hand, the size of the memory block BLKb can be increased. When the number of dummy memory cells decreases, the size of the memory block BLKb can be decreased. On the other hand, the operational reliability of the memory block BLKb may decrease.

[0109] To effectively control at least one dummy memory cell, the dummy memory cell can have a desired threshold voltage. Before or after an erase operation on memory block BLKb, a programming operation can be performed on all or some of the dummy memory cells. When an erase operation is performed after a programming operation, the threshold voltage of the dummy memory cell can control the voltage applied to the dummy word line connected to the corresponding dummy memory cell, ensuring that the dummy memory cell has the desired threshold voltage.

[0110] Figure 6 It is a diagram. Figure 3 The circuit diagram shows another embodiment of the memory block BLKi, one of the memory blocks BLK1 to BLKz shown.

[0111] refer to Figure 6In a memory block BLKi, multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, the memory block BLKi can include multiple memory cell strings ST connected between bit lines BL1 to BLm and a common source line (CSL). Bit lines BL1 to BLm can be individually connected to memory cell strings ST, and the common source line (CSL) can be collectively connected to memory cell strings ST. Memory cell strings ST can be configured identically to each other, and therefore, as an example, the memory cell string ST connected to the first bit line BL1 will be described in detail.

[0112] A memory cell string ST may include a source select transistor (SST), multiple memory cells MC1 to MC16, and a drain select transistor (DST), which may be connected in series between a common source line CSL and a first bit line BL1. A memory cell string ST may include at least one drain select transistor (DST), and a memory cell string ST may include source select transistors and memory cells. The number of source select transistors is greater than the number of source select transistors (SST) shown in the figure, and the number of memory cells is greater than the number of memory cells MC1 to MC16 shown in the figure.

[0113] The source of the source select transistor SST can be connected to the common source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different memory cell strings ST can be connected to the source select line SSL, and the gate of the drain select transistor DST included in different memory cell strings ST can be connected to the drain select line DSL. The gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word lines among the memory cells included in different memory cell strings ST can be called a physical page PG. Therefore, a physical page PG corresponding to the number of word lines WL1 to WL16 can be included in the memory block BLKi.

[0114] A memory cell can store one bit of data. This memory cell is often referred to as a single-level cell (SLC). A physical page (PG) can store one logical page (LPG) of data. An LPG of data can include data bits corresponding to the number of cells included in a physical page (PG).

[0115] A memory cell can store two or more bits of data. A physical page (PG) can store two or more physical pages (LPGs).

[0116] Figure 7 It is a diagram. Figure 2 The diagram shows the programming operations of the memory device.

[0117] exist Figure 7 For ease of description, it is assumed that each of the plurality of memory cells can be a multi-level cell (MLC) storing 2 bits of data. However, the scope of this disclosure is not limited thereto, and each of the plurality of memory cells can be a three-level cell (TLC) storing 3 bits of data or a four-level cell (QLC) storing 4 bits of data.

[0118] The programming operation of memory device 100 may include multiple programming cycles PL1 to PLm. That is, by executing multiple programming cycles PL1 to PLm, memory device 100 can program selected memory cells to have a threshold voltage corresponding to any one of the multiple programming states.

[0119] Each of the multiple programming cycles PL1 to PLm may include: a programming voltage application step PGM Step that provides the programming voltage, and a verification step Verify Step that determines whether the memory cell has been programmed by applying a verification voltage.

[0120] The programming voltage application step (PGM Step) included in each programming cycle may include a precharge period, a programming period, and a discharge period.

[0121] During the precharge period, precharge operations can be performed on multiple strings of memory cells. This precharge operation on multiple strings of memory cells can be referred to as a "string precharge operation."

[0122] Furthermore, during the precharge period, operations can be performed to set the bit line voltages to the voltages applied to multiple bit lines. This operation of setting the bit line voltages can be referred to as a "bit line setting operation."

[0123] Bit line setup operations may include setting the bit line voltage to a programming enable voltage or a programming disable voltage. When a programming pulse is applied to the selected word line during a subsequent programming session, the memory cell connected to the bit line whose bit line voltage is set to the programming enable voltage may have an increased threshold voltage. Furthermore, during subsequent programming sessions, the threshold voltage of the memory cell connected to the bit line whose bit line voltage is set to the programming disable voltage can be maintained.

[0124] In one embodiment, the programming enable voltage can be the ground voltage. Conversely, the programming disable voltage can be the supply voltage. Specifically, the bit line voltage can be set by increasing the page buffer control signal applied to the page buffer from the off voltage to the on voltage.

[0125] String precharge operations may include the transfer of voltage applied from the common source line to unselected memory cell strings. For example, because different memory cell strings share the same word line, during programming operations on selected memory cell strings, memory cells included in unselected memory cell strings may be affected by programming pulses applied to the word line.

[0126] Therefore, the voltage of the channel region of the unselected memory cell string can be increased sufficiently in advance, so as to prevent the threshold voltage of the memory cells included in the unselected memory cell string from being accidentally moved.

[0127] In one embodiment, the memory device 100 may perform both a serial precharge operation and a bit line setup operation simultaneously during the precharge period.

[0128] The programming period (Program) can be a time period in which selected memory cells are programmed to have a threshold voltage corresponding to the programming state. For example, memory device 100 can apply a programming voltage to the selected word line and can apply a programming voltage with a level lower than the programming voltage to an unselected word line. Furthermore, memory device 100 can apply a ground voltage corresponding to 0V to the selected bit line and can apply a supply voltage to the unselected bit line. Therefore, memory device 100 can program selected memory cells to have a threshold voltage corresponding to the programming state.

[0129] The discharge period can be a time interval during which the voltage applied to the word lines and select lines is discharged. The memory device 100 can discharge the voltage applied to the word lines and select lines by applying a ground voltage corresponding to 0V to the word lines and select lines.

[0130] Figure 8 It's a diagram. Figure 2 The memory cells included in the memory device shown can be represented by a diagram of the order in which they are programmed.

[0131] exist Figure 8 The diagram illustrates a memory cell string. A memory cell string can include multiple memory cells connected in series between the bit line BL and the common source line CSL. Each memory cell can be connected to a word line. A drain-select transistor can be connected between the memory cell and the bit line, and a source-select transistor can be connected between the memory cell and the common source line. The drain-select transistor can be controlled via the drain-select line DSL, and the source-select transistor can be controlled via the source-select line SSL.

[0132] For ease of description, assume that the memory cells are connected in a string to eight word lines WL1 to WL8. Furthermore, assume that the memory cells connected to the fifth to eighth word lines WL5 to WL8 are the programmed memory cells, and that the memory cells connected to the first to fourth word lines WL1 to WL4 are the memory cells before they were programmed.

[0133] In one embodiment, programming operations can be performed sequentially from the eighth word line WL8 adjacent to the drain select line DSL to the first word line WL1 adjacent to the source select line SSL. This is called the reverse sequence.

[0134] Reference Figure 7 During the described precharge period, memory device 100 can precharge the channel of the memory cell string via the common source line CSL. For example, with the source select transistor on, memory device 100 can precharge the channel via the common source line CSL and the source select line SSL. The drain select transistor can be in the drain select transistor off state. That is, memory device 100 can precharge the unselected memory cell string before applying the programming voltage to reduce interference during programming operations. The reduction in interference becomes greater as the level of the precharge voltage in the common source line CSL becomes higher.

[0135] Figure 9 This is a waveform diagram illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0136] Figure 9 The operation method shown can be, for example, by Figure 2 The memory device 100 shown is executed.

[0137] exist Figure 9In this context, T0 to T4 represent the programming voltage application step (PGM Step) included in the programming operation, and T4 to T5 represent the verification step (Verify Step). The memory device 100 may perform the verification step (Verify Step) before T0.

[0138] The Programming Voltage Application Step (PGM Step) can include a Precharge period, a Program period, and a Discharge period.

[0139] T0 to T2 can be the precharge period, T2 to T3 can be the program period, and T3 to T4 can be the discharge period.

[0140] Memory cells can be programmed sequentially according to word line order. Therefore, memory cells connected to word lines in the Unselected WL that were programmed earlier than the Selected WL can be in a programmed state, and memory cells connected to word lines that are programmed later than the Selected WL can have a threshold voltage corresponding to the erase state.

[0141] exist Figure 9 In this context, it is assumed that the memory device 100 can perform programming operations sequentially from the word line WL adjacent to the drain select line DSL to the word line WL adjacent to the source select line SSL. Therefore, a memory cell connected to an unselected word line Unselected WL located between the selected word line Selected WL and the source select line SSL can be a memory cell that has not undergone programming operations. Furthermore, a memory cell connected to an unselected word line Unselected WL located between the selected word line Selected WL and the drain select line DSL can be a memory cell that has already undergone programming operations.

[0142] exist Figure 9 In this context, the first unselected word line group (GROUP 1 Unselected WL) can correspond to the unselected word line (Unselected WL) located between the selected word line (Selected WL) and the source select line (SSL). The second unselected word line group (GROUP 2 Unselected WL) can correspond to the unselected word line (Unselected WL) located between the selected word line (Selected WL) and the drain select line (DSL).

[0143] Since the first unselected word line group (GROUP 1 Unselected WL) is programmed later than the selected word line group (Selected WL), the memory cell connected to the first unselected word line group (GROUP 1 Unselected WL) can be a memory cell in an erased state. Since the second unselected word line group (GROUP 2 Unselected WL) is programmed earlier than the selected word line group (Selected WL), the memory cell connected to the second unselected word line group (GROUP 2 Unselected WL) can be in a state where the memory cell is programmed to a threshold voltage corresponding to the stored data.

[0144] At T0, memory device 100 can precharge the selected word line Selected WL. For example, memory device 100 can apply a precharge voltage Vpre to the selected word line Selected WL. Therefore, the voltage of the selected word line Selected WL can be increased. Furthermore, memory device 100 can apply the precharge voltage Vpre to the first unselected word line group GROUP 1 Unselected WL. Therefore, the voltage of the first unselected word line group GROUP 1 Unselected WL can be increased. Memory device 100 can apply a ground voltage GND to the second unselected word line group GROUP 2 Unselected WL.

[0145] Furthermore, the memory device 100 can precharge the common source line CSL. For example, the memory device 100 can apply a precharge voltage to the common source line CSL. Therefore, the voltage of the common source line CSL can be increased. The voltage applied to the common source line CSL can be a voltage used to precharge an unselected string of memory cells.

[0146] The memory device 100 can precharge the channel regions of multiple memory cell strings via the common source line CSL. Specifically, the memory device 100 can perform a string precharge operation.

[0147] In one embodiment, memory device 100 may apply a precharge voltage Vpre, which is applied to a common source line CSL, to the source selection line of each of a plurality of memory cell strings.

[0148] For example, memory device 100 can apply a precharge voltage Vpre to the selected source select line (Selected SSL), which is a source select line of a selected memory cell string. Furthermore, memory device 100 can apply the precharge voltage Vpre to the unselected source select line (Unselected SSL), which is a source select line of an unselected memory cell string. Therefore, the voltage of both the selected and unselected source select lines can be increased.

[0149] Furthermore, the memory device 100 can apply a ground voltage GND to the selected drain selection line (Selected DSL), which is a drain selection line of the selected memory cell string, at which the drain selection transistor is turned off. Conversely, the memory device 100 can apply a ground voltage GND to the unselected drain selection line (Unselected DSL), which is a drain selection line of the unselected memory cell string, at which the drain selection transistor is turned off. Therefore, the voltage of both the selected drain selection line (Selected DSL) and the unselected drain selection line (Unselected DSL) can be reduced.

[0150] While the channel regions of multiple memory cell strings are being precharged, the memory device 100 can set the bit line voltage applied to the bit lines. Specifically, the memory device 100 can perform a string precharge operation and a bit line setting operation simultaneously, wherein the precharge of the memory cell strings begins before the bit line voltage is applied to the bit lines.

[0151] In one embodiment, the memory device 100 can set the bit line voltage according to the data to be stored in memory cells connected to a selected word line (Selected WL) among a plurality of memory cells.

[0152] In one embodiment, the memory device 100 may set the bit line voltage to one of a programming enable voltage or a programming disable voltage.

[0153] For example, memory device 100 can apply a programming enable voltage or programming disable voltage to a bit line by increasing the page buffer control signal PBSENSE to the on-state voltage Vpbs.

[0154] At T1, memory device 100 can apply ground voltage GND to the selected word line Selected WL and the first unselected word line group GROUP 1 Unselected WL. Therefore, the voltage of the selected word line Selected WL and the voltage of the first unselected word line group GROUP 1 Unselected WL can be reduced.

[0155] At T2, the string precharge operation and bit line setup operation can be terminated.

[0156] At T2, memory device 100 can apply ground voltage GND to the selected source line (Selected SSL) and the unselected source line (Unselected SSL). Therefore, the voltage of the selected source line (Selected SSL) and the unselected source line (Unselected SSL) can be reduced.

[0157] In addition, the memory device 100 can reduce the page buffer control signal PBSENSE to ground voltage GND.

[0158] At T2, memory device 100 can provide the programming voltage VPGM to the selected word line Selected WL.

[0159] For example, memory device 100 can apply a voltage Vpass to word lines Selected WL, GROUP1Unselected WL, and GROUP2Unselected WL. Subsequently, memory device 100 can apply a programming voltage VPGM to the selected word line Selected WL. The voltages of the other unselected word lines GROUP1Unselected WL and GROUP2Unselected WL are maintained through voltage Vpass.

[0160] In addition, the memory device 100 can apply a drain selection voltage VDSL to the selected drain selection line Selected DSL, at which the drain selection transistor can be turned on.

[0161] At T3, memory device 100 can discharge the selected word line Selected WL.

[0162] For example, memory device 100 can apply ground voltage GND to word lines Selected WL, GROUP1Unselected WL, and GROUP2Unselected WL.

[0163] In addition, the memory device 100 can apply a ground voltage GND to the selected drain select line SelectedDSL, at which the drain select transistor can be turned off.

[0164] At T4, the memory device can apply a verification voltage Vpv to the selected word line Selected WL and a verification pass voltage Vpass to the unselected word lines GROUP 1Unselected WL and GROUP 2Unselected WL. The verification voltage Vpv can be a voltage used to determine the programming state of the selected memory cell. The verification pass voltage Vpass can be a voltage at which the memory cells connected to the unselected word lines GROUP 1Unselected WL and GROUP 2Unselected WL are turned on without affecting the bit line voltage.

[0165] Furthermore, the memory device 100 can apply a drain selection voltage VDSL to the selected drain selection line Selected DSL, at which the drain selection transistor can be turned on. Additionally, the memory device 100 can apply a drain selection voltage VDSL to the unselected drain selection line Unselected DSL, at which the drain selection transistor can be turned on. This is to prevent the channel potential of the unselected memory cell string from being excessively increased by the high verification pass voltage Vpass applied to the unselected word lines GROUP 1Unselected WL and GROUP 2Unselected WL.

[0166] Furthermore, the memory device 100 can apply a source select voltage VSSL to the selected source select line Selected SSL, at which the source select transistor is turned on. Additionally, the memory device 100 can apply a source select voltage VSSL to the unselected source select line Unselected SSL, at which the source select transistor is turned on. This is to prevent the channel potential of the unselected memory cell string from being excessively increased by the high verification pass voltage Vpass applied to the unselected word lines GROUP 1Unselected WL and GROUP 2Unselected WL.

[0167] The ground voltage GND can be applied to the common source line CSL.

[0168] Then, at T5, the Verify Step can be completed.

[0169] refer to Figure 9 It can perform string precharge and bit line setup operations simultaneously. The current required for string precharge and bit line setup can be consumed simultaneously. Therefore, the current consumed in memory device 100 can increase rapidly and instantaneously.

[0170] According to embodiments of this disclosure, the string precharge operation and the bit line setup operation can be performed simultaneously, but can be controlled to start at different times. Therefore, the current consumed in the memory device 100 can be distributed over time, thereby reducing the peak current generated during the string precharge operation and the bit line setup operation. (Refer to...) Figure 10 This will be described in detail.

[0171] Figure 10 This is a waveform diagram illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0172] Figure 10 The operation method shown can be, for example, by Figure 2 The memory device 100 shown is executed.

[0173] exist Figure 10 In this context, T0' to T5' represent the programming voltage application step (PGM Step) included in the programming operation, and T5' to T6' represent the verification step. The memory device 100 may perform the verification step before T0'.

[0174] T0' to T3' can be the precharge period, T3' to T4' can be the program period, and T4' to T5 can be the discharge period.

[0175] The operations during the time period T2' to T6' can be referenced. Figure 9 The described memory devices operate identically during time periods T1 to T5.

[0176] Figure 10 The embodiments shown may differ from those shown. Figure 9 The embodiment shown differs in that, between T0' and T2', the string precharge operation and the bit line setup operation can be performed simultaneously, but can start at different times.

[0177] In one embodiment, after precharging of the channel regions of the plurality of memory cell strings begins, while the channel regions of the plurality of memory cell strings are being precharged, the memory device 100 may set the bit line voltage applied to the bit lines. For example, a voltage may be applied to increase the voltage of the source select line of each of the plurality of memory cell strings, and after a predetermined time has elapsed from the time when the voltage applied to the source select line of each of the plurality of memory cell strings increases, the memory device 100 may set the bit line voltage applied to the bit lines.

[0178] Specifically, at T0', memory device 100 can begin serial precharge operation.

[0179] For example, memory device 100 can apply a precharge voltage Vpre to the common source line CSL. Furthermore, memory device 100 can apply the precharge voltage Vpre to the selected source select line Selected SSL and the unselected source select line Unselected SSL. Additionally, memory device 100 can apply a ground voltage GND to the selected drain select line DSL and the unselected drain select line Unselected DSL. Furthermore, memory device 100 can apply the precharge voltage Vpre to the selected word line Selected WL and the first unselected word line group GROUP 1 Unselected WL. Furthermore, memory device 100 can apply a ground voltage GND to the second unselected word line group GROUP2 Unselected WL.

[0180] Subsequently, at T1', the memory device 100 can begin a bit line setting operation during the execution of a string precharge operation. For example, after a predetermined time period has elapsed following the application of a precharge voltage Vpre to the selected source select line (Selected SSL) and the unselected source select line (Unselected SSL), the memory device 100 can increase the level of the page buffer control signal PBSENSE to the on-state voltage Vpbs. The memory device 100 can apply a programming enable voltage or a programming disable voltage to the bit lines based on the page buffer control signal PBSENSE. That is, the memory device 100 can set the bit line voltage after a predetermined time period has elapsed following the application of a precharge voltage to the source select line of each of the multiple memory cell strings.

[0181] Therefore, the current consumed in the memory device 100 can be allocated over time, thereby reducing the peak current generated during string precharge operations and bit line setup operations.

[0182] Figure 11 yes Figure 2The diagram shows the configuration of the programmable controller included in the control logic.

[0183] exist Figure 11 In this configuration, the memory cell array 110, the row decoder 121, the voltage generator 122, and the page buffer group 123 can be respectively connected to a reference. Figure 2 The described memory cell array 110, row decoder 121, voltage generator 122, and page buffer group 123 are configured and operated in the same manner. The programming operation controller 1100 can represent... Figure 2 The programmable operation controller 131 shown is shown.

[0184] refer to Figure 11 The programmable operation controller 1100 may include a programmable voltage control signal generator 1110, a source selection line controller 1120, a source line controller 1130, and a bit line controller 1140.

[0185] The programming voltage control signal generator 1110 can generate programming voltage control signals that indicate the multiple voltages to be generated in the programming voltage application step.

[0186] In one embodiment, the programmable voltage control signal generator 1110 can generate a precharge voltage control signal that indicates the generation of precharge-associated voltages, which are voltages having various levels, to be used during the precharge period. Furthermore, the programmable voltage control signal generator 1110 can provide the precharge voltage control signal to a voltage generator 122. The voltage generator 122 can generate various precharge-associated voltages to be used during the precharge period based on the precharge voltage control signal. Subsequently, the voltage generator 122 can provide the precharge-associated voltages to the line decoder 121.

[0187] The source select line controller 1120 can control the voltage applied to the source select line. For example, the source select line controller 1120 can provide a source select line control signal to the row decoder 121 to allow a precharge voltage to be applied to the source select line. The row decoder 121 can then provide the precharge voltage to the memory cell array 110 according to the source select line control signal.

[0188] The source line controller 1130 can control the pre-charge voltage applied to the common source line. For example, the source line controller 1130 can apply a pre-charge voltage to the common source line of the memory cell array 110.

[0189] Bit line controller 1140 can control the bit line voltage applied to the bit line. For example, bit line controller 1140 can generate a page buffer control signal for controlling the bit line voltage. Subsequently, bit line controller 1140 can pass the page buffer control signal to page buffer group 123. Page buffer group 123 can set the bit line voltage to a programming enable voltage or a programming disable voltage according to the page buffer control signal.

[0190] Figure 12 It is a diagram. Figure 1 The diagram shows the memory controller.

[0191] refer to Figure 1 and Figure 12 The memory controller 200 may include a processor 220, RAM 230, error correction circuitry 240, ROM 250, host interface 270, and flash memory interface 280.

[0192] The processor 220 can control the overall operation of the memory controller 200. The RAM 230 can be used as a buffer memory, high-speed cache memory, working memory, etc. of the memory controller 200.

[0193] Error correction circuit 240 can perform error correction. Error correction circuit 240 can perform error correction code (ECC) encoding on data to be written to the memory device via flash interface 280. ECC-decoded data can be transmitted to the memory device via flash interface 280. Error correction circuit 240 can perform ECC decoding on data received from the memory device via flash interface 280. Exemplarily, error correction circuit 240 can be included as a component of flash interface 280.

[0194] ROM 260 can store various information required for the operation of memory controller 200 in the form of firmware.

[0195] The memory controller 200 can communicate with external devices (e.g., host 300, application processor, etc.) via host interface 270.

[0196] The memory controller 200 can communicate with the memory device 100 via the flash interface 280. The memory controller 200 can transmit commands (CMD), addresses (ADDR), control signals (CTRL), etc., to the memory device 100 via the flash interface 280, and receive data (DATA). For example, the flash interface 280 may include a NAND interface.

[0197] Figure 13 This is a block diagram illustrating a memory card system for use with a storage device according to an embodiment of the present disclosure.

[0198] refer to Figure 13The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0199] Memory controller 2100 can be connected to memory device 2200. Memory controller 2100 can access memory device 2200. For example, memory controller 2100 can control read operations, write operations, erase operations, and background operations of memory device 2200. Memory controller 2100 can provide an interface between memory device 2200 and host computer. Memory controller 2100 can drive firmware used to control memory device 2200. Memory controller 2100 can be referenced... Figure 1 The memory controller 200 described is implemented in the same manner as in the reference. Figure 2 The memory device 2200 is implemented in the same manner as the memory device 100 described.

[0200] For example, the memory controller 2100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and ECC circuitry.

[0201] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to a specific communication protocol. Exemplarily, the memory controller 2100 can communicate with external devices via at least one of a variety of communication protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. Exemplarily, connector 2300 can be defined by at least one of the aforementioned communication protocols.

[0202] For example, the memory device 2200 can be implemented using various non-volatile memory devices, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0203] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 can form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash memory (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro and eMMC), an SD card (SD, miniSD, microSD and SDHC), and a universal flash memory (UFS).

[0204] Figure 14 This is an exemplary block diagram illustrating a solid-state drive (SSD) system for use with a storage device according to an embodiment of the present disclosure.

[0205] refer to Figure 14 The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals SIG with the host 3100 through a signal connector 3001 and receive power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0206] In one embodiment, the SSD controller 3210 can be used as a reference. Figure 1 The memory controller 200 is described.

[0207] In response to a signal SIG received from host 3100, SSD controller 3210 can control multiple flash memory modules 3221 to 322n. Exemplarily, the signal SIG can be a signal based on the interface between host 3100 and SSD 3200. For example, the signal SIG can be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0208] Auxiliary power supply 3230 can be connected to host 3100 via power connector 3002. When the power supply from host 3100 is unstable, auxiliary power supply 3230 can provide power to SSD 3200. Exemplarily, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be located on the motherboard and can provide auxiliary power to SSD 3200.

[0209] Buffer memory 3240 can operate as a buffer memory for SSD 3200. For example, buffer memory 3240 can temporarily store data received from host 3100 or data received from multiple flash memory modules 3221 to 322n, or temporarily store metadata (e.g., mapping tables) of flash memory modules 3221 to 322n. Buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0210] Figure 15 This is a block diagram illustrating a user system that can be applied to a storage device according to an embodiment of the present disclosure.

[0211] refer to Figure 15 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0212] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include a controller for controlling components, interfaces, graphics engines, etc., included in user system 4000. Application processor 4100 may be provided as a system-on-chip (SoC).

[0213] Memory module 4200 can operate as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory (RAM) or non-volatile RAM. Volatile RAM includes types such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM. Non-volatile RAM includes types such as PRAM, ReRAM, MRAM, and FRAM. Exemplarily, application processor 4100 and memory module 4200 can be provided as a single semiconductor package by packaging application processor 4100 and memory module 4200 in a stacked package (PoP).

[0214] Network module 4300 can communicate with external devices. Exemplarily, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. Exemplarily, network module 4300 can be included in application processor 4100.

[0215] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. Exemplarily, storage module 4400 can be implemented using a non-volatile semiconductor memory device, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional structure. Exemplarily, storage module 4400 can be provided as a removable drive, such as a memory card of user system 4000 or an external drive.

[0216] For example, the storage module 4400 may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may be configured with reference to a reference. Figure 1 The memory device 100 described operates in the same manner. The memory module 4400 can operate in the same manner as the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0217] User interface 4500 may include interfaces for inputting data or commands to application processor 4100 or outputting data to external devices. Exemplarily, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0218] According to this disclosure, the memory device and the method of operating the memory device may be able to reduce peak current.

Claims

1. A method for operating a memory device, the memory device comprising a plurality of memory cell strings, each of the plurality of memory cell strings comprising: The method comprises: a plurality of memory cells connected between a common source line and a bit line; a source select line connected between the common source line and the plurality of memory cells; and a drain select line connected between the bit line and the plurality of memory cells. The channel regions of the plurality of memory cell strings are pre-charged through the common source line; and After the pre-charging of the channel regions of the plurality of memory cell strings begins, while the channel regions of the plurality of memory cell strings are being pre-charged, a bit line voltage is set to be applied to the bit lines.

2. The method of claim 1, further comprising applying a pre-charge voltage to the common source line.

3. The method of claim 2, wherein the pre-charging of the channel region comprises: The precharge voltage applied to the common source line is applied to the source selection line of each of the plurality of memory cell strings.

4. The method of claim 3, wherein setting the bit line voltage comprises: The bit line voltage is set after a predetermined time period elapsed from the time when the precharge voltage is applied to the source select line of each of the plurality of memory cell strings.

5. The method of claim 1, wherein in setting the bit line voltage, the bit line voltage is set according to data to be stored in a memory cell, the memory cell being connected to a selected word line among word lines connected to the plurality of memory cells.

6. The method of claim 5, wherein in the setting of the bit line voltage, the bit line voltage is set to one of a programming enable voltage or a programming disable voltage.

7. The method according to claim 1, further comprising: When the channel region of the plurality of memory cell strings is precharged, the drain selection transistor connected to the drain selection line is turned off.

8. The method according to claim 1, further comprising: A precharge voltage is applied to a selected word line among the word lines connected to the plurality of memory cells.

9. The method according to claim 1, further comprising: After the channel regions of the plurality of memory cell strings are precharged, a programming voltage is provided to a selected word line among the word lines connected to the plurality of memory cells.

10. The method of claim 9, further comprising: After the programming voltage is supplied to the selected word line, the selected word line is discharged.

11. A memory device, comprising: Multiple memory blocks, each of the multiple memory blocks including multiple memory cell strings, each of the multiple memory cell strings including: multiple memory cells connected in series between a common source line and a bit line, multiple source select lines connected in series between the common source line and the multiple memory cells, and multiple drain select lines connected in series between the bit line and the multiple memory cells; The peripheral circuitry is configured to execute multiple programming cycles, each of which includes: a programming voltage application step of providing a programming voltage to a selected memory block among the multiple memory blocks, and a verification step of verifying the programming state of the selected memory block; and The programming operation controller is configured to: control the peripheral circuitry to precharge the channel regions of the plurality of memory cell strings through the common source line, and, in the programming voltage application step, set the bit line voltage applied to the bit line at a predetermined time relative to the start of precharging the channel regions of the plurality of memory cell strings.

12. The memory device of claim 11, wherein the programming operation controller includes a programming voltage control signal generator configured to generate a programming voltage control signal indicating a plurality of voltages to be generated for use in the programming voltage application step.

13. The memory device of claim 12, wherein the programming operation controller further comprises a source line controller configured to control the voltage applied to the common source line.

14. The memory device of claim 13, wherein the programming operation controller further comprises a source select line controller configured to control voltages applied to the plurality of source select lines.

15. The memory device of claim 14, wherein the programming operation controller further comprises a bit line controller configured to control the bit line voltage.

16. A method for operating a memory device, the memory device comprising a plurality of memory cell strings, each of the plurality of memory cell strings comprising: The method comprises: a plurality of memory cells connected between a common source line and a bit line; a source select line connected between the common source line and the plurality of memory cells; and a drain select line connected between the bit line and the plurality of memory cells. Increase the voltage of the common source line; Through the common source line, the voltage of the source selection line applied to each of the plurality of memory cell strings is increased; and When the voltage applied to the source select line of each of the plurality of memory cell strings is increased, after the voltage applied to the source select line of each of the plurality of memory cell strings is increased, the bit line voltage applied to the bit line is set after a predetermined elapsed time.

17. The method of claim 16, wherein in setting the bit line voltage, the bit line voltage is set according to data to be stored in a memory cell, the memory cell being connected to a selected word line among word lines connected to the plurality of memory cells.

18. The method of claim 17, wherein in the setting of the bit line voltage, the bit line voltage is set to one of a programming enable voltage or a programming disable voltage.

19. The method of claim 16, further comprising: When the voltage applied to the source select line of each of the plurality of memory cell strings is increased, the drain select transistor connected to the drain select line is turned off.

20. The method of claim 16, further comprising increasing the voltage of a selected word line among the word lines connected to the plurality of memory cells.

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