Defect analysis system for semiconductor device, defect analysis method for semiconductor device, and program

Abstract

The present invention relates to a defective analysis system for semiconductor devices, a defective analysis method for semiconductor devices, and a program. A defective analysis system for semiconductor devices is provided, which can perform integrated analysis across multiple inspection steps for good / bad information in block units and column units, improving the analysis efficiency. The defective analysis system for semiconductor devices includes a memory (13), a defective information management table (19), and an analysis unit (18). The memory (13) stores good / bad information collected in block units and column units within a chip in multiple inspection steps of a semiconductor memory. The defective information management table (19) adds product information common to multiple inspection steps, manufacturing information including batch number, wafer number, and chip address, step information, and test information to the good / bad information in block units and column units stored in the memory (13), and stores them. The analysis unit (18) analyzes the good / bad information in block units and column units across multiple inspection steps based on the information stored in the defective information management table (19).

Description

[0001] [Related Application]

[0002] This application claims priority based on Japanese Patent Application No. 2020-143635 (filing date: August 27, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a defective analysis system for a semiconductor device, a defective analysis method for a semiconductor device, and a program. Background Art

[0004] In a semiconductor memory, electrical evaluation is performed on a wafer-by-wafer basis using a tester in a pre-manufacturing process step, and after the wafer is divided into multiple chips in a post-process step, electrical evaluation is performed on a chip-by-chip basis using a tester. Based on the evaluation results for the wafer-by-wafer in the pre-process step and the evaluation results for the chip-by-chip in the post-process step, a wafer defect distribution is generated that has defect information for chip positions within the wafer plane configured in chip units.

[0005] A NAND (Not And) type flash memory has spare blocks and spare columns in addition to normal blocks and normal columns, and when a defect occurs in a normal block or normal column, the spare blocks and spare columns are allocated as a replacement. Summary of the Invention

[0006] The problem to be solved by the embodiments is to provide a defective analysis system for a semiconductor device, a defective analysis method for a semiconductor device, and a program that can perform integrated analysis across multiple inspection steps for good / bad information in block units and column units, thereby improving the analysis efficiency.

[0007] The defective analysis system for a semiconductor device according to the present embodiment includes a memory, a defect information management table, and an analysis unit. The memory stores good / bad information collected in block units and column units within a chip in multiple inspection steps of a semiconductor memory. The defect information management table adds product information common to the multiple inspection steps, manufacturing information including a lot number, a wafer number, and a chip address as manufacturing units, process step information, and test information to the good / bad information in block units and column units stored in the memory, and stores the same. The analysis unit analyzes the good / bad information in block units and column units across multiple inspection steps based on the information stored in the defect information management table. Description of the Drawings

[0008] Figure 1 is a configuration diagram of a defective analysis system for a semiconductor device according to an embodiment.

[0009] Figure 2 is a flowchart of a defective analysis method for a semiconductor device according to an embodiment.

[0010] Figure 3A This is a diagram showing an example of a wafer map of a semiconductor memory in a defect analysis system of a semiconductor device according to an embodiment.

[0011] Figure 3B This is a diagram showing an example of the chip configuration of a semiconductor memory in a defect analysis system of a semiconductor device according to an embodiment.

[0012] Figure 4 This is a diagram showing an example of pre - manufacturing process inspection in a defect analysis system of a semiconductor device according to an embodiment.

[0013] Figure 5A This is a diagram showing defective column addresses for power test PT1 in a defect analysis system of a semiconductor device according to an embodiment.

[0014] Figure 5B This is a diagram showing all defective column addresses after power test PT2 in a defect analysis system of a semiconductor device according to an embodiment.

[0015] Figure 5C This is a diagram showing defective column addresses for power test PT2 in a defect analysis system of a semiconductor device according to an embodiment.

[0016] Figure 6 This is a diagram showing an example of a tester - collected information file in block units and column units in a defect analysis system of a semiconductor device according to an embodiment.

[0017] Figure 7A This is a diagram showing an example of a summary table of a defective information management table in block units and column units collected by a tester in a defect analysis system of a semiconductor device according to an embodiment.

[0018] Figure 7B This is a diagram showing an example of a block table in a defect analysis system of a semiconductor device according to an embodiment.

[0019] Figure 7C This is a diagram showing an example of a list table in a defect analysis system of a semiconductor device according to an embodiment.

[0020] Figure 8 This is a diagram showing an example of a total defective information chart in a defect analysis system of a semiconductor device according to an embodiment.

[0021] Figure 9 This is a diagram showing an example of the block configuration within a chip in a defect analysis system of a semiconductor device according to an embodiment.

[0022] Figure 10This is a diagram showing an example of a block logical-physical address table that correlates the logical block address and physical block address for each product and each plane in a defective analysis system for a semiconductor device according to an embodiment.

[0023] Figure 11 This is a diagram showing an example of the column configuration within a chip in a defective analysis system for a semiconductor device according to an embodiment.

[0024] Figure 12 This is a diagram showing an example of a column logical-physical address conversion table that correlates the logical column address and physical column address for each product and each plane in a defective analysis system for a semiconductor device according to an embodiment.

[0025] Figure 13A This is a diagram showing a defective block diagram of plane P0 in a defective analysis system for a semiconductor device according to an embodiment.

[0026] Figure 13B This is a diagram showing a block diagram of 4-block cycle defects in a defective analysis system for a semiconductor device according to an embodiment.

[0027] Figure 14A This is a diagram showing a column diagram of plane-end defects in a defective analysis system for a semiconductor device according to an embodiment.

[0028] Figure 14B This is a diagram showing a defective column diagram for every other column on the left side of a plane in a defective analysis system for a semiconductor device according to an embodiment.

[0029] Figure 15A This is a diagram showing a block diagram of the previous-step test BA in a defective analysis system for a semiconductor device according to an embodiment.

[0030] Figure 15B This is a diagram showing a block diagram of the post-step test ba in a defective analysis system for a semiconductor device according to an embodiment.

[0031] Figure 15C This is a diagram showing an overlap of the block diagram of the previous-step test BA and the block diagram of the post-step test ba in a defective analysis system for a semiconductor device according to an embodiment.

[0032] Figure 16A This is a diagram showing an example of a wafer map of defective blocks in a monitoring test during the pre-manufacturing step of a defective analysis system for a semiconductor device according to an embodiment.

[0033] Figure 16B This is a diagram showing an example of a wafer map of defective columns in a defective analysis system for a semiconductor device according to an embodiment.

[0034] Figure 16CThis is a diagram showing an example of a wafer map that overlays defective blocks and defective columns in a defective analysis system for a semiconductor device according to an embodiment.

[0035] Figure 16D (a) of this is a diagram showing a wafer map of defective blocks in the monitoring test BB in the pre-manufacturing process of a defective analysis system for a semiconductor device according to an embodiment. Figure 16D (b) of this is a diagram showing a wafer map of defective blocks in the normal test ba in the post-manufacturing process of a defective analysis system for a semiconductor device according to an embodiment.

[0036] Figure 17 This is a diagram showing an example of a summary table including an inspection device in a defective analysis system for a semiconductor device according to an embodiment.

[0037] Figure 18 This is a diagram showing an example of a summary table including process conditions, manufacturing devices, and manufacturing date information in a defective analysis system for a semiconductor device according to an embodiment. Detailed Embodiments

[0038] Hereinafter, while referring to the attached Figure One a defective analysis system for a semiconductor device according to an embodiment, a method for analyzing defects in a semiconductor device, and a program for analyzing defects in a semiconductor device will be described in detail.

[0039] The accompanying drawings referred to are schematic diagrams. In the following description, elements having the same function and configuration are denoted by common reference numerals.

[0040] Figure 1 This is a configuration diagram of a defective analysis system for a semiconductor device according to an embodiment. Figure 2 This is a flowchart of a method for analyzing defects in a semiconductor device according to an embodiment. While referring to Figure 1 and Figure 2 a defective analysis system for a semiconductor device and a method for analyzing defects in a semiconductor device will be described.

[0041] In a defective analysis system for a semiconductor device, to the good / bad information collected in block units and column units within a chip in a plurality of inspection steps of a semiconductor memory, product information common to the plurality of inspection steps, manufacturing information including a lot number, a wafer number, and a chip address as manufacturing units, step information, and test information are added. The plurality of inspection steps are a pre-semiconductor manufacturing inspection step, a post-inspection step, and a final inspection step before shipment.

[0042] Based on the good / bad information in block units and column units, product information, manufacturing information, step information, and test information, the defective analysis system for a semiconductor device analyzes the good / bad information in block units and column units that spans multiple inspection steps.

[0043] (Wafer Map of Semiconductor Memory)

[0044] Figure 3A This is an example of a wafer map of a semiconductor memory in a defective analysis system of a semiconductor device according to an embodiment. The semiconductor memory is, for example, a NAND type flash memory, but may also be other memories as long as blocks and columns are set in the memory chip. For the chips 2 arranged on the wafer 1, coordinates in the horizontal (X) direction and the vertical (Y) direction (chip addresses) are set for management.

[0045] (Chip Configuration)

[0046] Figure 3B This is an example of the chip configuration of a semiconductor memory in a defective analysis system of a semiconductor device according to an embodiment. The outermost frame represents the chip 2, and the large partition that divides the chip 2 is the plane 3. In the example, the chip 2 is composed of two planes 3. The small partitions arranged horizontally in the plane 3 are the blocks 4.

[0047] In addition, columns 5 are arranged vertically in the plane 3. On the chip 2, in addition to the general blocks 4 and general columns 5, there are also remaining blocks 4a and remaining columns 5b, which are allocated as substitutes when defects occur in the general blocks 4 and general columns 5.

[0048] Figure 3B In, the small area arranged horizontally in the plane 3 is an example of the remaining block 4a, and the area vertically in the plane 3 is an example of the remaining column 5a. The remaining blocks 4a and remaining columns 5a are arranged and configured in the same way as the general blocks 4 and general columns 5, and are managed and inspected by allocating addresses in the same way as the general blocks 4 and general columns 5. In addition, when defects occur in the general blocks 4 and general columns 5, normal remaining blocks 4a and remaining columns 5a are allocated as substitutes to remedy the defects in block units and column units.

[0049] (Configuration of Defective Analysis System of Semiconductor Device)

[0050] As Figure 1 shown, the defective analysis system of the semiconductor device includes a data management server 10, a semiconductor defective analysis user interface 32, and a user PC (personal computer) 31. The data management server 10 is connected to a tester collection information file 8 that stores the information collected by the tester 7.

[0051] The user PC 31 gives an instruction for defective analysis of the semiconductor device to the data management server 10 via the semiconductor defective analysis user interface 32. The semiconductor defective analysis user interface 32 undertakes the communication between the user PC 31 and the data management server 10.

[0052] The data management server 10 uses the good / bad information, product information, manufacturing information, step sequence information, and test information in block units and column units from the tester-collected information file 8 to analyze the good / bad information in block units and column units across multiple inspection steps.

[0053] (Configuration of the data management server 10)

[0054] The data management server 10 includes: a tester output information receiving unit 12, a tester output information memory 13, a good / bad information reading unit 14, a memory configuration information 15, an information attachment unit 16, a production management database 17, an information registration and analysis unit 18, a bad information management table 19, a logical-physical address conversion table 20, a logical-physical address conversion unit 21, a graph information creation unit 22, a graph information unit 23, and an information display unit 24.

[0055] In addition, the data management server 10 has a ROM (Read Only Memory) 25 and a control unit 26. The ROM 25 is a dedicated memory for data reading. The ROM 25 stores a bad analysis program (corresponding to a computer program). The ROM 25 can also be, for example, a computer-readable non-transitory recording medium that stores a computer program for analyzing the good / bad of a semiconductor memory. The control unit 26 executes each process of the Figure 2 shown flowchart by executing the bad analysis program stored in the ROM 25.

[0056] (Configuration of the tester 7)

[0057] The tester 7 performs various tests in the pre-manufacturing step inspection, post-step inspection, and final step inspection of the semiconductor memory. In each step inspection, multiple test contents and the order of executing the tests are defined in the test program. Then, the test program is activated to perform a series of tests. The tester 7 performs a good / bad determination test for blocks or a good / bad determination test for each column.

[0058] Figure 4 is a diagram showing an example of the pre-manufacturing step inspection of the bad analysis system of the semiconductor device according to the embodiment. The test names consist of 16, namely, power test PT1, PT2, data transfer test DT1, DT2, leakage test LT1 - LT6, non-interrupt test OT1, OT2, erase test ET1, ET2, program test PRT1, PRT2.

[0059] As test types, there are column tests for determining good / bad for each column and block tests for determining good / bad for each block. In addition to the test types, there is also a test distinction between normal tests and monitoring tests. A normal test is a test for determining good / bad in the manufacturing process. A monitoring test is a test in which conditions are accelerated in order to grasp the true capabilities of the memory, etc.

[0060] Figures 5A - 5C This is an example of a method for calculating bad addresses in each test of the bad analysis system of the semiconductor device of the embodiment. Figure 5A This is a diagram showing the occurrence status of column defects in the power supply test PT1 of sequence 1 of a certain chip and its addresses. The numbers at the top of the diagram represent column addresses. In the power supply test PT1, columns C0, C1, C38, and C39 at both ends of the chip are defective.

[0061] Figure 5B This is a diagram showing all the defective columns and their addresses after the power supply test PT2 of sequence 2 of the same chip. In addition to the 4 columns C0, C1, C38, and C39 at both ends of the chip that are defective in the power supply test PT1, the 4 columns C18, C19, C20, and C21 in the center of the chip are also defective.

[0062] Figure 5C This is a diagram showing the occurrence status of column defects in the power supply test PT2 and its addresses. From Figure 5B all the defective column addresses that occur after the column defects in the power supply test PT2, excluding the column addresses of the column defects in the previous test, i.e., Figure 5A the power supply test PT1, the column addresses of the defective columns in the power supply test PT2 of Figure 5B are obtained. The 4 columns C18, C19, C20, and C21 in the center of the chip can be specified as the newly defective columns.

[0063] In this way, the tester 7 obtains the difference from the bad address information in the previous test by outputting all the addresses of the bad blocks or bad columns, and specifies the bad blocks or columns in the said test. The tester 7 collects the good / bad information of blocks and the good / bad information of columns for multiple step inspections covering the pre-step inspection, post-step inspection, and final step inspection before shipment of semiconductor manufacturing, and outputs the collected bad information to the tester collection information file 8 (step S11).

[0064] In addition, in addition to performing a series of normal tests for determining good / bad in the manufacturing process, the tester 7 also intersperses monitoring tests between the series of normal tests, collects good / bad information for reference, and the monitoring test is a test in which conditions are accelerated, for example, in order to grasp the true capabilities of the memory, etc.

[0065] The tester collection information file 8 stores defect information in block units or column units that span multiple step inspections collected by the tester 7, and transmits the information to the data management server 10 (step S12).

[0066] (Composition of the tester collection information file 8)

[0067] Figure 6 It is a diagram showing an example of the tester collection information file 8 in block units and column units that span multiple step inspections collected by the tester 7 of the defect analysis system for semiconductor devices according to the embodiment. The tester collection information file 8 is, for example, set on a disk, and outputs the product name A, the lot number L1 and the wafer number W1 as manufacturing unit information, and the inspection step name in the first line. The inspection device name (tester name) can also be additionally output. Below it, the test names BA, BB, CA..., the number of defects and the defective block address Bad or defective column address Cad of the inspection start date, the chip address (chip X, chip Y), and the plane information P0, P1 are output.

[0068] Among the test names BA, BB, CA..., any one or a combination of the inspection part, purpose, data input terminal, test command, command input order (e.g., write → erase → read), the waiting time between commands, conditions such as temperature during testing, voltage applied during testing, stress acceleration, and the criteria for determining good / defective are different.

[0069] The tester output information receiving unit 12 receives defect information in block units or column units that span multiple step inspections stored in the tester collection information file 8. The tester output information memory 13 is, for example, a disk, and stores good / defect information collected in block units and / or column units that span multiple step inspections received by the tester output information receiving unit 12 (step S13).

[0070] The good / defect information reading unit 14 reads the good / defect information in block and column units from the tester output information memory 13, and outputs the good / defect information in block and column units to the information adding unit 16.

[0071] The information adding unit 16 adds product information common to multiple inspection steps as the memory configuration information 15, manufacturing information including the lot number, wafer number, and chip address as the manufacturing unit, step information, and test information to the good / defect information collected in block units and column units within the chip.

[0072] Next, the information adding unit 16 determines whether the manufacturing information registered in the defect information management table 19 is insufficient (step S14). If the manufacturing information is insufficient, the information adding unit 16 inquires of the production management database 17 and adds the manufacturing information (step S15).

[0073] The information registration and analysis unit 18 registers the good / bad information in units of blocks and columns obtained in the information addition unit 16, the product information common to the inspection steps, the manufacturing information including the lot number, wafer number, and chip address as the manufacturing unit, the step information, and the test information used in the inspection in the bad information management table 19 (step S16). The bad information management table 19 for blocks and columns includes a summary table 19a, a block table 19b, and a list table 19c.

[0074] (Composition of the bad information management table 19)

[0075] The bad information management table 19 attaches the product information common to the inspection steps, the manufacturing information including the lot number, wafer number, and chip address as the manufacturing unit, the step information, and the test information used in the inspection to the good / bad information in units of blocks and columns, and stores them.

[0076] (Composition of the summary table 19a)

[0077] Figure 7A It is a diagram showing an example of the summary table 19a of the bad information management table 19 for units of blocks and columns collected by the tester 7 of the bad analysis system of the semiconductor device according to the embodiment. The summary table 19a sets a total of 11 items to manage information, and these 11 items are product name, lot number L1 as manufacturing unit information, wafer number W1, chip CX, chip CY, plane P0, P1, inspection steps (previous step, subsequent step), test type (block / column) for distinguishing block information blk or column information col, test names BA, BB…, test classification (normal, monitoring), and the number of bads among the 10 items.

[0078] The information registration and analysis unit 18 registers the information of normal (Pass) chips and planes without bad blocks or bad columns in the summary table 19a in the form of the number of bads "0", thereby managing the chip address, the number of chips, and the Pass information of the inspection object. When a part of the manufacturing unit information is unclear during data registration in subsequent step inspections, etc., the production management database 17 is queried, additional information is added and registered.

[0079] When the test type (block / column) in the summary table 19a is block (blk), Figure 7B the block table 19b shown manages the bad block logical address. When the test type (block / column) is column (col), Figure 7C the list table 19c shown manages the bad column logical address.

[0080] (Composition of the block table 19b)

[0081] Figure 7BIt is a diagram showing an example of a block table 19b of a defective analysis system for a semiconductor device according to an embodiment. The block table 19b manages information on a total of 10 items, which are obtained by adding a defective block (logic) address to 9 items of the same product name, lot number L1, wafer number W1, chip CX, chip CY, planes P0, P1, inspection step (previous step, subsequent step), test name, and test classification (normal, monitoring) as those in the summary table 19a. In the block table 19b, the product name A, lot number L1, wafer number W1, chip CX, chip CY, step, and defective block address for each test are confirmed.

[0082] Figure 7A The second row of the summary table 19a of ,

[0082] , Figure 7A is "Product A, Lot L1, Wafer W1, Chip X = 5, Chip Y = 5, Plane = P0, Previous step, blk, Tests BA, BB…, Number of defects = 4". Since the test type (block / column) is block (blk), the block table 19b manages the defective block address. The 4 address information with the number of defects = 4 is managed by Figure 7B rows 2 to 5 of Figure 7B .

[0083] (Composition of the list table 19c)

[0084] Figure 7C It is a diagram showing an example of a list table 19c of a defective analysis system for a semiconductor device according to an embodiment. The list table 19c manages information on a total of 10 items, which are obtained by adding a defective column (logic) address to 9 items of the same product name, lot number L1, wafer number W1, chip CX, chip XY, planes P0, P1, inspection step, test name, and test classification (normal, monitoring) as those in the summary table 19a. In the block table 19b, the product name, lot number L1, wafer number W1, chip CX, chip CY, step, and defective column address for each test are confirmed.

[0085] The information registration and analysis unit 18 corresponds to the analysis unit of the present invention, and uses the information in the summary table 19a to sum up the number of defects for the wafer number W1, inspection step, and each test name of a certain product name A and a certain lot number L1, and analyzes which wafer number has more defects or which step has more defects.

[0086] Figure 8 It is a diagram showing an example of a defective data total chart of a defective analysis system for a semiconductor device according to an embodiment. The defective data total chart is a chart made by using the information in the summary table 19a and summing up the number of defects for the wafer number W1, inspection step, and each test name of a certain product name A or lot number L1 by the information registration and analysis unit 18. In the defective data total chart, it is found that the number of defects of the wafer number w2 is relatively large, and there is a tendency that the number of defects in the previous step test BA is relatively large.

[0087] Similarly, the information registration and analysis unit 18 can perform various aggregations, such as aggregating the number of defects for each inspection start date, or aggregating the defect rate for each test name. In addition, it is possible to arrange and aggregate the data of multiple inspection steps and perform comparisons.

[0088] In this way, using the summary table 19a, it is possible to output the defect aggregations and defect distributions in block units and column units across multiple inspection steps. Therefore, for the good / defect information in block units and column units, it is possible to perform integrated analysis across multiple inspection steps.

[0089] In addition, as Figure 1 shown, the defect analysis system of the semiconductor device includes a logical-physical address conversion table 20, a logical-physical address conversion unit 21, a graph information creation unit 22, a graph information unit 23, and an information display unit 24.

[0090] (Configuration of the logical-physical address conversion table 20)

[0091] The logical-physical address conversion table 20 stores the logical block address and the physical block address in correspondence. The logical-physical address conversion unit 21 refers to the logical-physical address conversion table 20 and converts the logical block address into a physical block address.

[0092] Figure 9 is a diagram showing an example of the block configuration within a chip of the defect analysis system of the semiconductor device according to the embodiment. The planes P0 and P1 are arranged on the left and right within the chip, and the physical block addresses Pb0 to Pb999 are sequentially arranged from the top in each plane. The logical block addresses Vb402 to Vb0 to Vb404 corresponding to the physical block addresses Pb0 to Pb201 to Pb999 are described in parentheses ().

[0093] Figure 10 is a diagram showing an example of the logical-physical address conversion table that correlates the logical block addresses Vb0 to Vb5... for each product A, each plane P0, P1 of the defect analysis system of the semiconductor device according to the embodiment with the physical block addresses Pb201 to Pb199...

[0094] Figure 11 is a diagram showing an example of the column configuration within a chip of the defect analysis system of the semiconductor device according to the embodiment. The planes P0 and P1 are arranged on the left and right within the chip, and the physical column addresses pc0 to Pc99 are sequentially arranged from the left in each of the planes P0 and P1. The logical column addresses Vc0 to Vc99 corresponding to the physical block addresses Pc0 to Pc99 are described in parentheses ().

[0095] Figure 12It is a diagram showing an example of a column logical-physical address conversion table that associates logical column addresses Vc0, Vc1, Vc2 to Vc5... with physical column addresses Pc0, Pc2, Pc4 to Pc10... for each product A, each plane P0, P1 of the defective analysis system for the semiconductor device according to the embodiment.

[0096] The logical-physical address conversion unit 21 refers to Figure 10 the logical-physical address conversion table 20 shown, and Figure 7B converts the logical block address in the block table 19b of

[0097] (Display of block diagram and column diagram)

[0098] The diagram information creation unit 22 uses the converted physical block address to create a block diagram as shown in Figure 13A and Figure 13B (step S18). The information display unit 24 displays the block diagram created by the diagram information creation unit 22. Figure 13A A diagram showing all blocks Pb0 to Pb999 in plane P0 to be defective. Figure 13B A diagram showing periodic defects in 4 blocks Pb0, Pb4, Pb8...

[0099] In addition, the diagram information creation unit 22 refers to Figure 7C the logical column address in the list table 19c of Figure 11 the column logical-physical address conversion table 20 shown, and uses the physical column address information to create a column diagram as shown in Figure 14A and Figure 14B (step S18). Figure 14A A diagram showing defects in multiple columns Pc0, Pc1, Pc2... at the left and right ends of planes P0 and P1. Figure 14B A diagram showing defects in every other column Pc0, Pc2, Pc4... on the left side of planes P0 and P1.

[0100] Figures 15A - 15C It is an example of overlapping multiple block diagrams at the chip level of the defective analysis system for the semiconductor device according to the embodiment. The multiple defective diagrams can be diagrams obtained from different multiple tests in the same sequence, or diagrams obtained from multiple tests in different multiple sequences.

[0101] Figure 15A It is a block diagram obtained from the test BA in the previous step of the defective analysis system for the semiconductor device according to the embodiment. Figure 15B It represents a block diagram obtained from the test ba in the subsequent step of the defective analysis system for the semiconductor device according to the embodiment. As shown in Figure 15C , the information display unit 24 overlaps the two block diagrams and displays a diagram in which the defects of both are color-coded (step S19).

[0102] In the test BA of the previous step, a diagram showing defective blocks Pb3 and Pb4 is presented on plane P0, and in the test ba of the subsequent step, a diagram showing defective blocks Pb3 and Pb4 is presented on plane P1. If the two diagrams are overlapped, it becomes clear that the good / bad situation spanning planes P0 and P1 is located at the same physical block address. By performing defective analysis by overlapping the test results of multiple steps in this way, high-precision defective analysis can be achieved.

[0103] (Display of wafer diagram)

[0104] Figures 16A - 16D This is an example of a wafer diagram of the defective analysis system of the semiconductor device according to the embodiment. Figure 16A This is an example of a wafer diagram of defective blocks in the monitoring test BA of the pre-manufacturing step of the defective analysis system of the semiconductor device according to the embodiment. Defective blocks exist in the X direction. Each chip is represented as CPXY according to the chip XY coordinates (diagram address). For example, if X = 5 and Y = 8, then the chip XY coordinates (chip address) of the chip can be represented as CP58. The diagram information creation unit 22 arranges the defective block diagrams of each chip according to the chip XY coordinates (chip address) within the wafer surface, thereby creating a wafer diagram (step S20). The information display unit 24 displays the wafer diagram created by the diagram information creation unit 22 (step S21).

[0105] Figure 16B This is an example of a wafer diagram of defective columns of the defective analysis system of the semiconductor device according to the embodiment. Defective columns exist in the Y direction. The diagram information creation unit 22 arranges the defective column diagrams of each chip according to the chip XY coordinates within the wafer surface, thereby creating a wafer diagram. The information display unit 24 displays the wafer diagram created by the diagram information creation unit 22.

[0106] Figure 16C This is an example of a wafer diagram in which the defective blocks and defective columns of the defective analysis system of the semiconductor device according to the embodiment are overlapped and displayed. The diagram information creation unit 22 arranges the defective block diagrams and column diagrams of each chip according to the chip XY coordinates within the wafer surface, thereby creating a wafer diagram (step S20). The information display unit 24 displays the wafer diagram created by the diagram information creation unit 22 (step S21).

[0107] For the wafer diagram, it is also possible to overlap the diagrams of multiple tests of multiple steps. There is an example where defects caused by exposure, immersion, etc. in semiconductor manufacturing do not occur in chip units but occur over a wide range on the wafer. In this case, it is effective to use the wafer diagram for defective analysis.

[0108] Figure 16D (a) of this is an example of a wafer diagram of defective blocks in the monitoring test BB of the pre-manufacturing step of the defective analysis system of the semiconductor device according to the embodiment. Figure 16DExample of a wafer map of defective blocks in the normal test ba of the post-manufacturing process of the defective analysis system for the semiconductor device of the embodiment. In both wafer maps, defects tend to occur more frequently near the lower outer periphery of the wafer, and the tendency is very similar. In this example, by examining the monitoring test BB in the previous process and changing the monitoring test BB to the normal test as needed.

[0109] Thus, blocks initially determined to be defective in the normal test ba of the subsequent process can be determined to be defective in the previous process. If defective determination can be made in the previous process, it is easier to analyze the yield in the wafer state. In addition, the assembly cost and test cost in the subsequent process can be reduced.

[0110] (Summary table including inspection device information)

[0111] Figure 17 is a diagram showing an example of a summary table including inspection device information of the defective analysis system for the semiconductor device of the embodiment. In Figure 7A the items of the summary table 19a, inspection device information is added. The inspection device information pre-exports the inspection device name to Figure 6 the test collection information file 8 and registers it in the summary table 19a. By using the inspection device information and the inspection start date as search keywords to confirm the information in the summary table 19a, defects caused by the inspection device can be analyzed.

[0112] (Summary table including manufacturing device information and manufacturing date information)

[0113] Figure 18 is a diagram showing a summary table including process conditions, manufacturing device information, and manufacturing date information of the defective analysis system for the semiconductor device of the embodiment. In Figure 7A the items of the summary table 19a, information on process conditions, manufacturing devices, and manufacturing dates is added.

[0114] The information addition unit 16 uses product information such as product name A, lot number L1, and wafer number W1 as search keywords to retrieve the production management database 17 and obtain information on process conditions, manufacturing devices, and manufacturing dates. The information registration and analysis unit 18 registers the obtained information on process conditions, manufacturing devices, and manufacturing dates in the summary table 19a. By using the process conditions, manufacturing devices, and manufacturing dates as search keywords to confirm the information in the summary table 19a, defects caused by the process can be analyzed.

[0115] (Effect of the defective analysis system for semiconductor devices)

[0116] Thus, according to the semiconductor device failure analysis system of the embodiment, the tester output information memory 13 stores good / bad information collected in units of blocks and columns in the chip during pre-manufacturing step inspection, post-step inspection, and final step inspection before shipment.

[0117] The defect information management table 19 adds product information, manufacturing information, step information and test information to the good / bad information of the block unit and the column unit and stores it. The information registration and analysis unit 18 analyzes the good / bad information of the block unit and the column unit across multiple inspection steps based on the information stored in the defect information management table 19.

[0118] As a result, it is possible to perform integrated analysis across a plurality of inspection steps for good / bad information in block units and column units, which are remediation units, thereby improving analysis efficiency.

[0119] In addition, the logical-physical address conversion unit 21 refers to the logical-physical address conversion table 20 that associates the logical addresses of blocks and columns with the physical addresses of blocks and columns, and converts the logical address information of bad blocks and columns into physical address information, thereby understanding the physical positions of bad blocks and columns.

[0120] In addition, the map information generating unit 22 generates a bad block map and a bad column map showing the physical configuration in the bad chip based on the physical address information of the bad blocks and bad columns converted by the logical-physical position converting unit 21. Since the information displaying unit 24 displays the bad block map and the bad column map generated by the map information generating unit 22 in an overlapping manner, it is possible to analyze whether the blocks and columns are good or bad.

[0121] In addition, the map information production unit 22 produces a wafer map, which is obtained by configuring the bad block map and bad column map of each chip on the wafer surface based on the chip address information on the wafer surface. Therefore, the bad block map and bad column map of each chip can be grasped on the wafer map.

[0122] In addition, the defect information management table 19 stores information on manufacturing steps including inspection devices, manufacturing devices, and process information. The information registration and analysis unit 18 can count and analyze the number of defects in block units and column units based on the information stored in the defect information management table 19 .

[0123] As described above, several embodiments of the present invention are described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The embodiments or their variations are included in the scope or spirit of the invention, and are included in the invention described in the claims and their equivalents.

[0124] [Explanation of Symbols]

[0125] 1 Wafer

[0126] 2 Chips

[0127] 3 Planes

[0128] 4 Blocks

[0129] 4a Remaining Blocks

[0130] 5 Columns

[0131] 5a Remaining Columns

[0132] 7 Testers

[0133] 8 Tester Information Collection File

[0134] 10 Data Management Servers

[0135] 12 Tester Output Information Receiver

[0136] 13 Tester Output Information Memory

[0137] 14 Good / Bad Information Reader

[0138] 15 Memory Configuration Information

[0139] 16 Information Attachment Unit

[0140] 17 Production Management Database

[0141] 18 Information Registration and Analysis Unit

[0142] 19 Bad Information Management Table

[0143] 19a Summary Table

[0144] 19b Block Table

[0145] 19c List Table

[0146] 20 Logical-Physical Address Conversion Table

[0147] 21 Logical-Physical Address Conversion Unit

[0148] 22 Graph Information Creation Unit

[0149] 23 Graph Information Unit

[0150] 24 Information Display Unit

[0151] 25 ROM

[0152] 26 Control Unit

[0153] 31 User PC

[0154] 32 Semiconductor Defect Analysis User Interface

Claims

1. A defective analysis system for a semiconductor device, comprising: A tester configured to: In each of a plurality of inspection steps including inspection in a previous step including an undivided wafer, inspection in a subsequent step after dividing the wafer into a plurality of chips, and inspection in a final step of semiconductor manufacturing before shipping the manufactured semiconductor product, Performing a test of the semiconductor device, including: Perform power supply testing, data transfer testing including transferring data to a chip of the semiconductor device, leakage testing, non-interruption testing, erasure testing including erasing data from the chip, and programming testing including programming the chip; After any one of the tests for determining good / bad of a block unit or column unit in the chip is performed, output all addresses of defective blocks or columns; and Based on the difference between the defective address information at the end of the test and the defective address information at the end of the previous test of the test, identify defective blocks or columns generated in the test; and A data management server connected to a tester collection information file storing information output by the tester, and including: A receiving unit that receives good / bad information collected in block units and column units within a chip in each of the plurality of inspection steps of the semiconductor memory from the tester collection information file, and stores the received good / bad information in a memory; An information addition unit that adds product information common to the plurality of inspection steps, manufacturing information including a lot number, a wafer number, and a chip address, step information, and test information to the good / bad information in block units and column units stored in the memory, and stores the information in a defective information management table; and An analysis unit that comprehensively analyzes good / bad information in block units and column units across the plurality of inspection steps based on the information stored in the defective information management table; and The tester identifies defective blocks or columns newly generated in the test by removing all the defective address information at the end of the previous test from all the defective address information at the end of the test, thereby collecting good / bad information of the blocks and good / bad information of the columns in each of the plurality of inspection steps, and outputs the collected good / bad information of the blocks and good / bad information of the columns to the tester collection information file; The test information at least includes information for distinguishing between a normal test and a monitoring test. The normal test is a test for determining good / bad in a manufacturing step, and the monitoring test is a test in which conditions are accelerated to grasp the true strength of the semiconductor device. The analysis unit is configured to comprehensively analyze the good / bad information of the block units by determining that a block unit initially determined to be defective in a normal test in a subsequent step inspection will also be automatically determined to be defective in a previous step.

2. The defective analysis system for a semiconductor device according to claim 1, wherein The data management server further includes a logical-physical address conversion table that establishes correspondence between the logical addresses of blocks and columns of each product and the physical addresses of blocks and columns representing the configuration on the chip, The analysis unit stores logical address information of defective blocks and columns, and The data management server further includes a logical-physical address conversion unit that, with reference to the logical-physical address conversion table, converts the logical address information of the defective blocks and defective columns stored in the defective information management table into physical address information.

3. The defective analysis system for a semiconductor device according to claim 2, further comprising: a diagram production unit that produces a defective block diagram and a defective column diagram showing the physical configuration within a defective chip based on the physical address information of the defective blocks and defective columns of each inspection step and each test converted by the logical-physical address conversion unit; and a diagram display unit that overlays and displays the defective block diagram and the defective column diagram produced by the diagram production unit.

4. The defective analysis system for a semiconductor device according to claim 3, wherein the diagram production unit produces a wafer diagram, which is formed by arranging the defective block diagrams and defective column diagrams of each chip within the wafer plane based on the chip address information within the wafer plane.

5. The defective analysis system for a semiconductor device according to claim 1, wherein the defective information management table stores information on the manufacturing steps including inspection devices, manufacturing devices, and process information, and the analysis unit totals and analyzes the number of defective units in blocks and columns based on the information stored in the defective information management table.

6. A method for analyzing defects of a semiconductor device, characterized in that including the following steps: In each of a plurality of inspection steps including inspection in a previous step including an undivided wafer, inspection in a subsequent step after dividing the wafer into a plurality of chips, and inspection in a final step of semiconductor manufacturing before shipping the manufactured semiconductor product, performing a test of the semiconductor device by a tester, including: a power supply test, a data transfer test for transferring data to a chip of the semiconductor device, a leakage test, a non-interruption test, an erasure test for erasing data from the chip, and a programming test for programming the chip; after performing one of the tests for determining good / bad in units of blocks or columns within the chip, outputting all addresses of defective blocks or defective columns by the tester; identifying defective blocks or defective columns generated in one of the tests by the tester based on the difference between the defective address information at the end of one of the tests and the defective address information at the end of the previous test; receiving good / bad information collected in units of blocks and columns within the chip in the plurality of inspection steps of the semiconductor memory from an information file collected by the tester; storing the received good / bad information in a memory; producing a defective information management table, attaching product information common to the plurality of inspection steps, manufacturing information including a lot number, a wafer number, and a chip address, step information, and test information to the good / bad information in units of blocks and columns stored in the memory, and storing the same; integrating and analyzing the good / bad information in units of blocks and columns across the plurality of inspection steps based on the information stored in the defective information management table; The tester identifies the newly generated defective blocks or defective columns in the test by removing all the defective address information at the end of the previous test from all the defective address information at the end of the test, thereby collecting the good / bad information of the blocks and the good / bad information of the columns in each of the multiple inspection steps, and outputting the collected good / bad information of the blocks and the good / bad information of the columns to the tester collection information file; The test information at least includes information for distinguishing between a normal test and a monitoring test. The normal test is a test for determining good / bad in the manufacturing process, and the monitoring test is a test in which the conditions are accelerated to grasp the true strength of the semiconductor device. By determining that the blocks initially determined to be defective in the normal test in the subsequent step inspection will also be automatically determined to be defective in the previous step, the good / bad information of the block unit is comprehensively analyzed.

7. A defective analysis system for a semiconductor device, comprising: A tester configured to: In each of multiple inspection steps including inspection in a previous step including an uncut wafer, inspection in a subsequent step after dividing the wafer into multiple chips, and inspection in a final step of semiconductor manufacturing before shipping the manufactured semiconductor product, Performing a test of the semiconductor device, including: Perform a power supply test, a data transfer test for transferring data to the chips of the semiconductor device, a leakage test, a non-interruption test, an erase test for erasing data from the chips, and a programming test for programming the chips; After performing one of the tests for determining good / bad of the block unit or column unit in the chip, output all the addresses of the defective blocks or defective columns; and Based on the difference between the defective address information at the end of one of the tests and the defective address information at the end of the previous test, identify the defective blocks or defective columns generated in one of the tests; and A computer-readable non-transitory recording medium storing a computer program executed by a computer, the computer program causing the computer to perform processing: Receive the good / bad information collected in units of blocks and columns within the chip in the multiple inspection steps of the semiconductor memory from the tester collection information file; Store the received good / bad information in a memory; Create a defective information management table, attach product information common to the multiple inspection steps, manufacturing information including batch number, wafer number, chip address, step information, and test information to the good / bad information of the block unit and column unit stored in the memory, and store them; Based on the information stored in the defective information management table, comprehensively analyze the good / bad information of the block unit and column unit across the multiple inspection steps; and The tester identifies the newly generated defective blocks or defective columns in the test by removing all the defective address information at the end of the previous test from all the defective address information at the end of the test, thereby collecting the good / bad information of the blocks and the good / bad information of the columns in each of the multiple inspection steps, and outputs the collected good / bad information of the blocks and the good / bad information of the columns to the tester collection information file; The test information at least includes information for distinguishing between a normal test and a monitoring test. The normal test is a test for determining good / bad in the manufacturing process, and the monitoring test is a test in which conditions are accelerated to grasp the true strength of the semiconductor device. By determining that the blocks initially determined to be defective in the normal test inspected in the subsequent process will also be automatically determined to be defective in the previous process, the good / bad information of the blocks is comprehensively analyzed.

8. The defective analysis system for a semiconductor device according to claim 7, wherein The test information at least includes information for distinguishing between a normal test and a monitoring test. The normal test is a test for judging good / bad in the manufacturing process, and the monitoring test is a test in which conditions are accelerated to grasp the true strength of the memory.

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