A method for preparing a silicon-based patterned substrate

Abstract

The present invention provides a method for preparing a silicon-based patterned substrate, comprising the following steps: S1. growing a first extension layer on a Si substrate; S2. etching the first extension layer until the Si substrate is exposed; S3. growing a dielectric layer on the exposed Si substrate; S4. etching the dielectric layer within the width range of the first strip-shaped trench until the Si substrate is exposed; S5. growing a second extension layer on the Si substrate exposed by the second strip-shaped trench; S6. etching a strip-shaped window in the second extension layer above the dielectric layer; S7. removing the dielectric layer under the strip-shaped window, thereby forming a Si-based patterned substrate in a shape of a Chinese character 'hui'. By epitaxially growing group III-V semiconductor materials such as GaAs, InP, GaN, etc. on the prepared Si-based patterned substrate in the shape of a Chinese character 'hui', most of the threading dislocations can be confined within the patterned substrate, realizing the epitaxy of low-defect-density Si-based GaAs, InP, GaN, etc. materials.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing, and particularly relates to a method for preparing a silicon-based patterned substrate. Background Art

[0002] As the integrated circuit technology develops to below the 10nm technology node, the silicon-based integrated circuit technology is restricted by a series of basic physical problems and technical process problems in terms of speed, power consumption, integration degree, etc. Implementing high-performance compound heterogeneous integrated devices can effectively solve these problems. On the one hand, this technology can greatly reduce the cost of compound devices. On the other hand, it can make full use of the combination of silicon-based materials and compound materials to realize the integration of multifunctional devices and circuits, such as optoelectronic integration, high-voltage and low-voltage integration, digital microwave integration, etc., which will bring huge changes to future system design.

[0003] Epitaxially growing high-quality group III-V semiconductor materials on a Si substrate is a prerequisite for preparing silicon-based heterogeneous integrated devices. However, group III-V semiconductor materials, such as GaAs, InP, GaN, etc., have large lattice mismatch and thermal mismatch with Si, and a large number of dislocations will be generated during the heteroepitaxial process. These dislocations will extend to the surface of the epitaxial layer during the epitaxy process, seriously affecting the performance of the device. Suppressing the extension of dislocations is a problem that must be solved. Summary of the Invention

[0004] To solve the above technical problem that when using group III-V semiconductor materials on a Si substrate, due to the large lattice mismatch and thermal mismatch between such materials and Si, a large number of dislocations will be generated during the heteroepitaxial process, affecting the device performance, the present invention provides a method for preparing a silicon-based patterned substrate.

[0005] The present invention adopts the following technical solutions:

[0006] A method for preparing a silicon-based patterned substrate, comprising the following steps:

[0007] S1. Growing a first extension layer on a Si substrate;

[0008] S2. Etching the first extension layer until the Si substrate is exposed, and the etched area forms a first strip-shaped trench, and the unetched area is a first strip-shaped platform;

[0009] S3. Growing a dielectric layer on the Si substrate exposed in the first strip-shaped trench, and covering the first strip-shaped platform with the dielectric layer;

[0010] S4. Etching the dielectric layer within the width range of the first strip-shaped trench until the Si substrate is exposed, and the etched area forms a second strip-shaped trench, and the unetched area is a second strip-shaped platform. During etching, avoid exposing the first strip-shaped platform so that the second strip-shaped platform contains the first strip-shaped platform;

[0011] S5. Grow a second extension layer on the Si substrate exposed in the second strip-shaped groove, and make the second extension layer cover the second strip-shaped platform;

[0012] S6. Etch a strip-shaped window on the second extension layer above the dielectric layer until the dielectric layer is exposed;

[0013] S7. Remove the dielectric layer under the strip-shaped window, namely a Si-based patterned substrate is formed.

[0014] Furthermore, the Si substrate in step S1 is a p-type high-resistance (001) Si.

[0015] Furthermore, the first extension layer in step S1 is a SiO2 or SiN X material; the thickness of the first extension layer is 500 - 1000 nm.

[0016] Furthermore, the width of the first strip-shaped groove in step S2 is 1000 - 5000 nm; the width of the first strip-shaped platform is 500 - 3000 nm.

[0017] Furthermore, the dielectric layer in step S3 is a GaAs or AlAs material.

[0018] Furthermore, in step S3, the dielectric layer is grown by MOCVD or MBE process; the growth thickness of the dielectric layer is 700 - 1500 nm, the growth temperature is 350 - 550 °C, and the growth rate is 0.15 - 0.5 nm / s.

[0019] Furthermore, the width of the second strip-shaped groove in step S4 is 600 - 3000 nm; the width of the second strip-shaped platform is 700 - 4000 nm.

[0020] Furthermore, the second extension layer in step S5 is a SiO2 or SiN X layer.

[0021] Furthermore, the thickness of the second extension layer in step S5 is 800 - 1200 nm.

[0022] Furthermore, the width of the strip-shaped window etched in step S6 is 200 - 2000 nm.

[0023] Advantages of the present invention:

[0024] For the substrate structure obtained by the method provided by the present invention, more threading dislocation defects can be restricted in the patterned substrate, preventing them from extending onto the epitaxial layer, thereby realizing the epitaxy of low-defect-density Si-based III-V materials. Description of the drawings

[0025] Figure 1 It is a schematic structural diagram after growing a first extended layer on a Si substrate according to the method of the present invention;

[0026] Figure 2 It is a schematic structural diagram of forming a first strip-shaped groove after photolithography and etching according to the method of the present invention;

[0027] Figure 3 It is a schematic structural diagram after growing a dielectric layer on the groove according to the method of the present invention;

[0028] Figure 4 It is a schematic structural diagram of forming a second strip-shaped groove after photolithography and etching according to the method of the present invention;

[0029] Figure 5 It is a schematic structural diagram after growing a second extension on the groove according to the method of the present invention;

[0030] Figure 6 It is a schematic structural diagram after preparing a strip-shaped window on the second extended layer according to the method of the present invention;

[0031] Figure 7 It is a schematic structural diagram after etching away the dielectric layer under the window according to the method of the present invention;

[0032] Explanation of reference numerals: 1. Si substrate; 2. First extended layer; 21. First strip-shaped platform; 22. First strip-shaped groove; 3. Dielectric layer; 31. Second strip-shaped platform; 32. Second strip-shaped groove; 4. Second extended layer. Detailed implementation manners

[0033] The following further describes the present invention in conjunction with embodiments. The embodiments are only used to illustrate the present invention and do not constitute a limitation on the scope of the claims. Other alternative means that those skilled in the art can think of are all within the scope of the claims of the present invention.

[0034] In addition, in the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "central", "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. Embodiment 1

[0035] Figures 1 to 7Shows the steps of the method for preparing a silicon-based patterned substrate according to an embodiment of the present invention. Please refer to Figures 1 to 7 , a method for preparing a silicon-based patterned substrate, comprising the following steps:

[0036] Step S1: As Figure 1 shown, grow a first extension layer 2 on the Si substrate 1, where the Si substrate 1 can be a p-type high-resistance (001) Si, and the first extension layer 2 can be SiO2 or SiN X material, and the thickness of the first extension layer 2 is 500 - 1000 nm.

[0037] Step S2: As Figure 2 shown, etch the first extension layer 2 by photolithography and plasma etching until the Si substrate 1 is exposed, and the etched area forms a first strip-shaped trench 22, and the unetched area is a first strip-shaped platform 21; wherein the width of the first strip-shaped trench 22 is 1000 - 5000 nm, and the width of the first strip-shaped platform 21 is 500 - 3000 nm.

[0038] Step S3: As Figure 3 shown, place the substrate in a reaction chamber, first remove the oxide film on the substrate surface at high temperature, and then epitaxially grow a dielectric layer 3 with a thickness of 700 - 1500 nm on the Si substrate 1 exposed in the first strip-shaped trench 22 by MOCVD or MBE process, and make the dielectric layer 3 cover the first strip-shaped platform 21, where the dielectric layer 3 can be GaAs or AlAs material, the growth temperature of the dielectric layer 3 is 350 - 550 °C, and the growth rate is 0.15 - 0.5 nm / s.

[0039] Step S4: As Figure 4 shown, etch the dielectric layer 3 within the width range of the first strip-shaped trench 22 by photolithography and plasma etching until the Si substrate 1 is exposed, and the etched area forms a second strip-shaped trench 32, and the unetched area is a second strip-shaped platform 31. Avoid exposing the first strip-shaped platform 21 during etching so that the second strip-shaped platform 32 contains the first strip-shaped platform 21; wherein the width of the second strip-shaped trench 32 is 600 - 3000 nm, and the width of the second strip-shaped platform 31 is 700 - 4000 nm.

[0040] Step S5: As Figure 5 shown, grow a second extension layer 4 on the Si substrate 1 exposed in the second strip-shaped trench 32, and make the second extension layer 4 cover the second strip-shaped platform 31; where the material of the second extension layer 4 can be SiO2 or SiN X , and the thickness of the second extension layer 4 is 800 - 1200 nm.

[0041] Step S6: As Figure 6As shown, a strip-shaped window is etched on the second extension layer 4 above the dielectric layer 3 by means of photolithography and plasma etching until the dielectric layer is exposed, wherein the width of the strip-shaped window is 200-2000 nm.

[0042] Step S7: As Figure 7 shown, the dielectric layer 3 under the strip-shaped window is removed by wet etching to form a Si-based patterned substrate; for GaAs materials, it is removed by a mixed solution of ammonia water, hydrogen peroxide and water; for AlAs materials, it is removed by a dilute hydrochloric acid solution.

[0043] Epitaxy of Group III-V semiconductor materials such as GaAs, InP, GaN, etc. is carried out on the prepared Si-based patterned substrate, and most of the threading dislocation defects can be confined in the patterned substrate, realizing epitaxy of low-defect-density Si-based GaAs, InP, GaN and other materials.

[0044] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A method for preparing a silicon-based patterned substrate, characterized in that, Including the following steps: S1. Growing a first extended layer on the Si substrate; S2. Etching the first extended layer until the Si substrate is exposed, and the etched area forms a first strip-shaped groove, and the unetched area is a first strip-shaped platform; S3. Growing a dielectric layer on the Si substrate exposed in the first strip-shaped groove, and covering the first strip-shaped platform with the dielectric layer; S4. Etching the dielectric layer within the width range of the first strip-shaped groove until the Si substrate is exposed, and the etched area forms a second strip-shaped groove, and the unetched area is a second strip-shaped platform. Avoid exposing the first strip-shaped platform during etching so that the second strip-shaped platform contains the first strip-shaped platform; S5. Growing a second extended layer on the Si substrate exposed in the second strip-shaped groove, and covering the second strip-shaped platform with the second extended layer; S6. Etching a strip-shaped window on the second extended layer above the dielectric layer until the dielectric layer is exposed; S7. Removing the dielectric layer under the strip-shaped window, thereby forming a Si-based patterned substrate.

2. The method for preparing a silicon-based patterned substrate according to claim 1, wherein, The Si substrate in step S1 is a p-type high-resistance (001) Si.

3. The method for preparing a silicon-based patterned substrate according to claim 1, wherein, The first extension layer described in step S1 is SiO2 or SiN X material; the thickness of the first extension layer is 500-1000 nm.

4. The manufacturing method of the silicon-based patterned substrate according to claim 1 or 3, characterized in that, In step S2, the width of the first strip-shaped groove is 1000 - 5000 nm; the width of the first strip-shaped platform is 500 - 3000 nm.

5. The manufacturing method of the silicon-based patterned substrate according to claim 1, wherein, The dielectric layer in step S3 is made of GaAs or AlAs material.

6. The method for preparing a silicon-based patterned substrate according to claim 1 or 5, characterized in that In step S3, the dielectric layer is grown by MOCVD or MBE process; the growth thickness of the dielectric layer is 700 - 1500 nm, the growth temperature is 350 - 550 °C, and the growth rate is 0.15 - 0.5 nm / s.

7. The method for preparing a silicon-based patterned substrate according to claim 1, wherein, In step S4, the width of the second strip-shaped groove is 600 - 3000 nm; the width of the second strip-shaped platform is 700 - 4000 nm.

8. The preparation method of the silicon-based patterned substrate according to claim 1, characterized in that The second extension layer described in step S5 is SiO2 or SiN X layer.

9. The method for preparing a silicon-based patterned substrate according to claim 1 or 8, characterized in that, In step S5, the thickness of the second extended layer is 800 - 1200 nm.

10. The method for preparing a silicon-based patterned substrate according to claim 1, wherein, In step S6, the width of the etched strip-shaped window is 200 - 2000 nm.

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