Method for manufacturing semiconductor device including deep trench structure

Abstract

The present application discloses a method for manufacturing a semiconductor device including a deep trench structure, comprising: providing a substrate, a first epitaxial layer is formed on the substrate, a liner oxide layer is formed on the first epitaxial layer, a hard mask layer is formed on the liner oxide layer, a first oxide layer is formed on the hard mask layer, the region on the substrate comprises a first region and a second region, the first region is used to form an alignment mark, and the second region is used to form a semiconductor device; performing a first etching process by a photolithography process, forming a first trench in the first region, forming a second trench in the second region, the first trench and the second trench have the same depth, and the first epitaxial layer at the bottom of the first trench and the second trench is exposed; performing a second etching process on the second region by a photolithography process, making the depth of the second trench reach a predetermined region in the first epitaxial layer, and forming a deep trench; forming an alignment mark in the first trench, and forming a deep trench structure in the deep trench.

Description

Technical Field

[0001] The present application relates to the technical field, and in particular to a method for manufacturing a semiconductor device including a deep trench (DT) structure. Background Art

[0002] Deep trench structures (whose height-to-width ratio is usually greater than 4) are widely used in the field of semiconductor integrated circuits, for example, in the manufacturing processes of Bi-CMOS devices (complementary metal oxide semiconductor (CMOS) devices and bipolar junction transistor (BJT) devices integrated on the same chip), high voltage (HV) devices, and image sensors (CMOS contact image sensor, CIS) devices.

[0003] In the manufacturing process of semiconductor devices with deep groove structures, deep grooves are usually etched on the flat substrate surface, and then a series of complex process flows are carried out. In this process, clear alignment marks are required to provide a basis for subsequent processes. However, in the related art, the alignment marks formed in the manufacturing process of semiconductor devices with deep groove structures have many shortcomings, for example, the alignment marks are not clear, the alignment accuracy is not high, and there is a problem that the alignment marks are not flat on the substrate surface, which will cause uneven photoresist coating or glue throwing in the subsequent process, thereby reducing the yield of the product. Summary of the invention

[0004] The present application provides a method for manufacturing a semiconductor device including a deep trench structure, which can solve the problem that the alignment mark formed in the method for manufacturing a semiconductor device including a deep trench structure provided in the related art is unclear and the substrate surface is uneven. The method comprises:

[0005] A substrate is provided, wherein a first epitaxial layer is formed on the substrate, a pad oxide layer is formed on the first epitaxial layer, a hard mask layer is formed on the pad oxide layer, a first oxide layer is formed on the hard mask layer, and a region on the substrate includes a first region and a second region, the first region is used to form an alignment mark, and the second region is used to form the semiconductor device;

[0006] Performing a first etching process by a photolithography process to form a first trench in the first region and a second trench in the second region, wherein the first trench and the second trench have the same depth, and the first epitaxial layer at the bottom of the first trench and the second trench is exposed;

[0007] Performing a second etching process on the second region by a photolithography process, so that the depth of the second trench reaches a predetermined depth in the first epitaxial layer, thereby forming a deep trench;

[0008] An alignment mark is formed in the first trench, and a deep trench structure is formed in the deep trench.

[0009] In some embodiments, forming an alignment mark in the first trench and forming a deep trench structure in the deep trench includes:

[0010] A second epitaxial layer and a second oxide layer are sequentially formed at the bottom of the first trench and at the sidewall and bottom of the deep trench below the first oxide layer;

[0011] forming a third oxide layer, wherein the third oxide layer fills the first trench and the deep trench;

[0012] Performing a planarization process until the hard mask layer is exposed;

[0013] Performing a third etching process to remove the second oxide layer and the third oxide layer in the deep trench at a predetermined depth, wherein the predetermined depth is lower than the liner oxide layer;

[0014] The liner oxide layer and the hard mask layer are removed, the remaining second epitaxial layer, the second oxide layer and the third oxide layer in the first region constitute the alignment mark, and the second epitaxial layer, the second oxide layer and the third oxide layer in the deep trench of the second region constitute the deep trench structure;

[0015] forming a third epitaxial layer, wherein the third epitaxial layer covers the alignment mark and fills the exposed area in the third trench;

[0016] A planarization process is performed until the alignment mark is exposed.

[0017] In some embodiments, the first epitaxial layer and the second epitaxial layer have different impurity types, and the second epitaxial layer and the third epitaxial layer have the same impurity type.

[0018] In some embodiments, the impurity types in the substrate and the first epitaxial layer are different.

[0019] In some embodiments, the hard mask layer includes a silicon nitride layer.

[0020] In some embodiments, the performing the third etching process includes:

[0021] The third etching process is performed by a wet etching process.

[0022] In some embodiments, the semiconductor device includes an image sensor device.

[0023] The technical solution of this application has at least the following advantages:

[0024] During the manufacturing process of the semiconductor device, a first groove is formed in a first area for forming an alignment mark through a first etching process, a second groove is formed in a second area for forming the semiconductor device, and then a second etching process is performed in the second area to further etch the second groove downward to form a deep groove, thereby forming an alignment mark in the first groove and a deep groove structure in the deep groove. Since the deep groove and the first groove are formed separately, the problem of unclear alignment mark caused by forming the grooves of the alignment mark and the deep groove structure at the same time is solved, thereby improving the yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 is a flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application;

[0027] Figures 2 to 13 is a schematic diagram of a manufacturing process of a semiconductor device provided by an exemplary embodiment of the present application;

[0028] Fig.14 It is a flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0030] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0031] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0032] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0033] refer to Figure 1 , which shows a flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application, wherein the semiconductor device includes a deep trench structure, and the semiconductor device includes at least one of a Bi-CMOS device, a high voltage device, and a graphic sensor device, such as Figure 1 As shown, the method includes:

[0034] Step S1, providing a substrate, a first epitaxial layer is formed on the substrate, a pad oxide layer is formed on the first epitaxial layer, a hard mask layer is formed on the pad oxide layer, a first oxide layer is formed on the hard mask layer, the area on the substrate includes a first area and a second area, the first area is used to form an alignment mark, and the second area is used to form a semiconductor device.

[0035] refer to Figure 2 , which shows a cross-sectional schematic diagram of a substrate having multiple thin film layers provided by an exemplary embodiment of the present application. Figure 2 As shown, a first epitaxial layer 221 is formed on the substrate 210 , a pad oxide layer 230 is formed on the first epitaxial layer 221 , a hard mask layer 240 is formed on the pad oxide layer 230 , and a first oxide layer 251 is formed on the hard mask layer 240 .

[0036] The pad oxide layer 230 may be silicon oxide (e.g., silicon dioxide (SiO2 )) layer, the first oxide layer 251 may be a silicon oxide (eg, silicon dioxide) layer, and the constituent material of the hard mask layer 240 does not include silicon oxide, for example, it may be a silicon nitride (eg, silicon nitride (SiN)) layer.

[0037] Among them, the first epitaxial layer 221 can be formed on the substrate 210 through an epitaxial process, the pad oxide layer 230 can be formed on the epitaxial layer 230 through a thermal oxidation process, the hard mask layer 240 can be formed by depositing silicon nitride on the pad oxide layer 230 through a chemical vapor deposition (CVD) process, and the first oxide layer 251 can be formed by depositing silicon nitride on the hard mask layer 240 through a CVD process.

[0038] The surface of the substrate 210 is distributed with a first area 201 and a second area 202. The first area 201 is used to form an alignment mark, and the second area 202 is used to form a semiconductor device. If the semiconductor device used for integration on the substrate 210 is an image sensor device, the second area 202 can be a pixel area of ​​the image sensor device.

[0039] Step S2, performing a first etching process by a photolithography process to form a first trench in the first area and a second trench in the second area, wherein the first trench and the second trench have the same depth, and the first epitaxial layer at the bottom of the first trench and the second trench is exposed.

[0040] refer to Figure 3 , which shows a cross-sectional schematic diagram of covering the photoresist on the first oxide layer by a photolithography process; Figure 4 , which shows a cross-sectional schematic diagram of etching to form a first groove and a second groove. Figure 3 and Figure 4 As shown, step S2 includes but is not limited to: covering the first oxide layer 251 with a photoresist 300 through a photolithography process to expose the target area (the target area in the first area 201 is 3001, and the target area in the second area 202 is 3002); performing dry etching until the first epitaxial layer 221 of the target area is exposed, forming a first groove 301 in the first area 201, and forming a second groove 302 in the second area 202. Since the first groove 301 and the second groove 302 are formed in the same etching step, their depths are the same; removing the photoresist 300.

[0041] Step S3, performing a second etching process on the second region by a photolithography process, so that the depth of the second trench reaches a predetermined depth in the first epitaxial layer, thereby forming a deep trench.

[0042] refer to Figure 5, which shows a cross-sectional schematic diagram of covering the photoresist in the first area by a photolithography process; Figure 6 , which shows a cross-sectional schematic diagram of etching to form deep trenches. Figure 5 and Figure 6 As shown, step S3 includes but is not limited to: covering the photoresist 300 in the first region 201 through a photolithography process to expose the second region 202; performing etching (for example, through a dry etching process) to make the depth of the second groove 302 reach a predetermined depth in the first epitaxial layer 221 to form a deep groove 303, and at the same time the first oxide layer 251 of the second region 202 is thinned; removing the photoresist 300.

[0043] Step S4, forming an alignment mark in the first trench and forming a deep trench structure in the deep trench.

[0044] refer to Fig.11 , which shows a cross-sectional schematic diagram of the formed alignment mark and deep trench structure. Fig.11 As shown, in the first region 201, the thin film layer filled in the first trench 301 forms an alignment mark 410, and the thin film layer filled in the first trench 301 includes the second epitaxial layer 222, the second oxide layer 252 and the third oxide layer 253 from bottom to top; in the second region 202, the thin film layer filled in the deep trench 303 forms a deep trench structure 420, and the thin film layer filled in the deep trench 303 includes a lower part and an upper part, and the thin film layer in the lower part includes the second epitaxial layer 222, the second oxide layer 252 and the third oxide layer 253 from outside to inside, and the thin film layer in the upper part includes the second epitaxial layer 222. Among them, the second oxide layer 252 and the third oxide layer 253 include silicon oxide (e.g., silicon dioxide) layers.

[0045] In the embodiment of the present application, the impurity types in the substrate 210 and the first epitaxial layer 221 are different, and the impurity types in the first epitaxial layer 221 and the second epitaxial layer 222 are different. If the impurity type in the substrate 210 is P (positive) type, the impurity type in the first epitaxial layer 221 is N (negative) type, and the impurity type in the second epitaxial layer 222 is P type.

[0046] To summarize, in an embodiment of the present application, during the manufacturing process of a semiconductor device, a first groove is formed in a first area for forming an alignment mark through a first etching treatment, a second groove is formed in a second area for forming a semiconductor device, and then a second etching treatment is performed in the second area to further etch the second groove downward to form a deep groove, thereby forming an alignment mark in the first groove, and a deep groove structure is formed in the deep groove. Since the deep groove and the first groove are formed separately, the problem of unclear alignment mark caused by forming the grooves of the alignment mark and the deep groove structure at the same time is solved, thereby improving the yield of the product.

[0047] refer to Fig.14 , which shows a flowchart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application, the method can be Figure 1 In an optional implementation of step S4 in the embodiment, the method includes:

[0048] Step S4.1, forming a second epitaxial layer and a second oxide layer in sequence at the bottom of the first trench and at the sidewall and bottom of the deep trench below the liner oxide layer.

[0049] refer to Figure 7 , which shows a cross-sectional schematic diagram of forming a second epitaxial layer and a second oxide layer. Figure 7 As shown, the second epitaxial layer 222 can be formed by an epitaxial process, and silicon oxide can be deposited on the second epitaxial layer 222 by a CVD process to form a second oxide layer 252, and etching (for example, by a dry etching process) is performed to remove the second epitaxial layer 222 and the second oxide layer 252 on the side walls of the first trench 301, and to remove the second epitaxial layer 222 and the second oxide layer 252 above the first epitaxial layer 221 in the deep trench 303 (since the depth-to-width ratio of the deep trench 303 is relatively large, this can be achieved by adjusting the angle of the dry etching process).

[0050] Step S4.2, forming a third oxide layer, wherein the third oxide layer fills the first trench and the deep trench.

[0051] refer to Figure 8 , which shows a cross-sectional schematic diagram of forming a third oxide layer. Figure 8 As shown, silicon oxide may be deposited by a CVD process to form a third oxide layer 253 , and the third oxide layer 253 fills the unfilled areas in the first trench 301 and the deep trench 303 .

[0052] Step S4.3, performing a planarization process until the hard mask layer is exposed.

[0053] refer to Fig. 9 , which shows a cross-sectional schematic diagram of removing the first oxide layer and the third oxide layer above the hard mask layer after the planarization process. Exemplarily, the planarization process can be performed by a chemical mechanical polishing (CMP) process, with the hard mask layer 240 as a stop layer.

[0054] Step S4.4, performing a third etching process to remove the second oxide layer and the third oxide layer to a predetermined depth in the deep trench, where the predetermined depth is lower than the pad oxide layer.

[0055] refer to Fig.10 , which shows a cross-sectional schematic diagram after the third etching process. Fig.10 As shown, since the hard mask layer 240 does not contain silicon oxide, a third etching process can be performed through a wet etching process to remove the second oxide layer 252 and the third oxide layer 253 at a predetermined depth in the deep trench 303, and the predetermined depth is lower than the pad oxide layer 230. At the same time, the third oxide layer 252 in the first trench 301 is thinned.

[0056] Step S4.5, removing the pad oxide layer and the hard mask layer, the remaining second epitaxial layer, the second oxide layer and the third oxide layer in the first area constitute an alignment mark, and the second epitaxial layer, the first oxide layer and the third oxide layer in the deep trench of the second area constitute a deep trench structure.

[0057] refer to Fig.11 , which shows a cross-sectional schematic diagram after removing the liner oxide layer and the hard mask layer. Fig.11 As shown, the pad oxide layer 230 and the hard mask layer 240 can be removed by a dry etching process. The remaining second epitaxial layer 222, the second oxide layer 252 and the third oxide layer 253 in the first region 201 form an alignment mark 410, and the second epitaxial layer 222, the second oxide layer 252 and the third oxide layer 253 in the deep trench 303 of the second region 202 form a deep trench structure 420.

[0058] Step S4.6, forming a third epitaxial layer, wherein the third epitaxial layer covers the alignment mark and fills the exposed area in the third trench.

[0059] refer to Fig.12 , which shows a cross-sectional schematic diagram of forming a third epitaxial layer. Fig.12 As shown, the third epitaxial layer 223 may be formed by an epitaxial process, wherein the third epitaxial layer 223 and the substrate 210 have the same impurity type.

[0060] Step S4.7, performing a planarization process until the alignment mark is exposed.

[0061] For example, Fig.13 As shown, a planarization process may be performed by a CMP process, with the third oxide layer 253 in the first region 101 being used as a stop layer.

[0062] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing a semiconductor device comprising a deep trench structure, It is characterized in that include: A substrate is provided, wherein a first epitaxial layer is formed on the substrate, a pad oxide layer is formed on the first epitaxial layer, a hard mask layer is formed on the pad oxide layer, a first oxide layer is formed on the hard mask layer, and a region on the substrate includes a first region and a second region, the first region is used to form an alignment mark, and the second region is used to form the semiconductor device; Performing a first etching process by a photolithography process to form a first trench in the first region and a second trench in the second region, wherein the first trench and the second trench have the same depth, and the first epitaxial layer at the bottom of the first trench and the second trench is exposed; Performing a second etching process on the second region by a photolithography process, so that the depth of the second trench reaches a predetermined depth in the first epitaxial layer, thereby forming a deep trench; A second epitaxial layer and a second oxide layer are sequentially formed at the bottom of the first trench and at the sidewall and bottom of the deep trench below the first oxide layer; forming a third oxide layer, wherein the third oxide layer fills the first trench and the deep trench; Performing a planarization process until the hard mask layer is exposed; Performing a third etching process to remove the second oxide layer and the third oxide layer in the deep trench at a predetermined depth, wherein the predetermined depth is lower than the liner oxide layer; The liner oxide layer and the hard mask layer are removed, the remaining second epitaxial layer, the second oxide layer and the third oxide layer in the first region constitute an alignment mark, and the second epitaxial layer, the second oxide layer and the third oxide layer in the deep trench of the second region constitute a deep trench structure; forming a third epitaxial layer, wherein the third epitaxial layer covers the alignment mark and fills the exposed area in the deep trench; A planarization process is performed until the alignment mark is exposed.

2. The method according to claim 1, It is characterized in that The first epitaxial layer and the second epitaxial layer have different impurity types, and the second epitaxial layer and the third epitaxial layer have the same impurity type.

3. The method according to claim 2, It is characterized in that The substrate and the first epitaxial layer have different impurity types.

4. The method according to any one of claims 1 to 3, It is characterized in that The hard mask layer includes a silicon nitride layer.

5. The method according to claim 4, It is characterized in that The third etching process comprises: The third etching process is performed by a wet etching process.

6. The method according to claim 5, It is characterized in that The semiconductor device includes an image sensor device.

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