Organic interposer and method of manufacturing the same

Abstract

An organic interposer and a method of manufacturing the same, the organic interposer including a dielectric material layer that internally embeds a redistribution interconnect structure, a package side bump structure located at a first side of the dielectric material layer, and a die side bump structure located at a second side of the dielectric material layer. There is a gap region between a first region including a first die side bump structure and a second region including a second die side bump structure. A stress mitigation line structure is located on or within the dielectric material layer in a plan view within a range of the gap region. Each stress mitigation line structure includes a plurality of straight segment portions extending laterally along a respective horizontal direction, and is not electrically connected to the redistribution interconnect structure. The stress mitigation line structure can include a same or different material as a metal material of the redistribution interconnect structure or the bump structure located at a same horizontal level.

Description

Technical Field

[0001] This invention relates to a semiconductor manufacturing technology, and more particularly to an organic interposer for semiconductor packaging and a method for manufacturing the same. Background Technology

[0002] Fan-out wafer-level package (FOWLP) uses an interposer between the semiconductor die and the package substrate. An acceptable interposer has sufficient mechanical strength to withstand the bonding process used to connect the semiconductor die and the package substrate. Summary of the Invention

[0003] This disclosure provides an organic interposer in several embodiments. The organic interposer includes multiple dielectric material layers, multiple package-side bump structures, multiple die-side bump structures, and multiple stress-relief wiring structures. Multiple redistribution interconnect structures are embedded within the dielectric material layers. The package-side bump structures are located on a first side of the dielectric material layers and connected to a package-side subset of the redistribution interconnect structures. The die-side bump structures are located on a second side of the dielectric material layers and connected to a die-side subset of the redistribution interconnect structures. The die-side bump structures include multiple first die-side bump structures located in a first region and multiple second die-side bump structures located in a second region. In a plan view, the second region is laterally separated from the first region by a gap region, in which no die-side bump structures are present. The stress-relief wiring structures are located on or within the dielectric material layers within the gap region in the plan view. The stress-relief circuit structure and one of the package-side bump structure, the redistributed interconnect structure and the die-side bump structure are made of the same material and are located at the same horizontal level.

[0004] Other embodiments of this disclosure provide an organic interposer layer. The organic interposer layer includes multiple dielectric material layers, multiple package-side bump structures, multiple die-side bump structures, and multiple stress-reducing circuit structures. Multiple redistributed interconnect structures are embedded within the dielectric material layers. The package-side bump structures are located on a first side of the dielectric material layers and connected to a package-side subset of the redistributed interconnect structures. The die-side bump structures are located on a second side of the dielectric material layers and connected to a die-side subset of the redistributed interconnect structures. The die-side bump structures include multiple first die-side bump structures located in a first region and multiple second die-side bump structures located in a second region. In a plan view, the second region is laterally spaced from the first region by a gap region, in which no die-side bump structures are present. The stress-reducing circuit structures are located above or within the dielectric material layers within the gap region in the plan view. The stress-reducing circuit structures are at the same horizontal height as a metal component selected from the package-side bump structures, the redistributed interconnect structures, and the die-side bump structures. The stress-relief circuit structure comprises materials different from those used in metal components.

[0005] This disclosure further provides a method for forming an organic interposer layer in some embodiments. The method includes forming a plurality of package-side bump structures embedded within a package-side dielectric material layer over a carrier substrate. The method also includes forming a plurality of interconnect-level dielectric material layers and a plurality of redistributed interconnect structures over the package-side bump structures. The method further includes forming a die-side dielectric material layer over the interconnect-level dielectric material layer. The method also includes forming a plurality of die-side bump structures over the die-side dielectric material layer. The die-side bump structures include a plurality of first die-side bump structures located in a first region and a plurality of second die-side bump structures located in a second region. In a plan view, the second region is laterally spaced from the first region by a gap region, in which no die-side bump structures are present. Furthermore, the method includes forming a plurality of stress-reducing circuit structures within or above one of the package-side dielectric material layer, the interconnect-level dielectric material layer, or the die-side dielectric material layer within the gap region in a plan view. Each of the stress-relief circuit structures includes a plurality of straight segments extending laterally along their respective horizontal directions, and the stress-relief circuit structure has at least one of the following features: the stress-relief circuit structure is not electrically connected to the redistributed interconnect structure; and the stress-relief circuit structure is located at the same horizontal height as the package-side bump structure or the die-side bump structure. Attached Figure Description

[0006] Figure 1AThis is a vertical cross-sectional view of an exemplary structure including an organic interposer layer formed above a carrier substrate, according to some embodiments of the present disclosure.

[0007] Figure 1B It is located in Figure 1A An enlarged view of the first structure of the stress-relief line structure in region B.

[0008] Figure 1C It is located in Figure 1A An enlarged view of the second structure of the stress-relief line structure in region B.

[0009] Figure 1D It is located in Figure 1A An enlarged view of the third structure of the stress-relief line structure in region B.

[0010] Figure 1E It is located in Figure 1A An enlarged view of the fourth structure of the stress-relief line structure in region B.

[0011] Figure 1F It is located in Figure 1A An enlarged view of the fifth structure of the stress-relief line structure in region B.

[0012] Figure 1G It is located in Figure 1A An enlarged view of the sixth structure of the stress-relief line structure in region B.

[0013] Figure 1H It is located in Figure 1A An enlarged view of the seventh structure of the stress-relief line structure in region B.

[0014] Figure 1I yes Figure 1A A plan view of an exemplary structure.

[0015] Figure 2 This is a vertical cross-sectional view of an exemplary structure after a semiconductor die has been attached to an organic interposer, according to some embodiments of the present disclosure.

[0016] Figure 3 This is a vertical cross-sectional view of an exemplary structure after fan-out wafer-level packaging has been formed, according to some embodiments of the present disclosure.

[0017] Figure 4 This is a vertical cross-sectional view of an exemplary structure after dicing a fan-out wafer-level package according to some embodiments of the present disclosure.

[0018] Figure 5 This is a vertical cross-sectional view of an exemplary structure after a packaging substrate has been attached to a fan-out wafer-level package, according to some embodiments of the present disclosure.

[0019] Figure 6 This is a vertical cross-sectional view of an exemplary structure after the packaging substrate has been attached to a printed circuit board (PCB) according to some embodiments of the present disclosure.

[0020] Figure 7A This is a first flowchart illustrating the sequence of first processing steps for forming an organic intermediary layer according to some embodiments of the present disclosure.

[0021] Figure 7B This is a second flowchart illustrating the sequence of second processing steps for forming an organic intermediary layer according to some embodiments of the present disclosure.

[0022] Figure 7C This is a third flowchart illustrating the sequence of third processing steps for forming an organic intermediary layer according to some embodiments of the present disclosure.

[0023] The reference numerals in the attached figures are explained as follows:

[0024] 12: (Encapsulation side) Dielectric material layer

[0025] 18: Encapsulation side bump structure

[0026] 20: (Interconnection level) Dielectric material layer

[0027] 22: (First) Dielectric material layer

[0028] 24: (Second) Dielectric material layer

[0029] 26: (Third) Dielectric material layer

[0030] 28: (Fourth) Dielectric material layer

[0031] 40: Redistributed interconnect structure

[0032] 42: First redistributed interconnect structure

[0033] 44: Second redistributed interconnect structure

[0034] 46: Third redistributed interconnect structure / metal substrate

[0035] 48: Metal pad structure

[0036] 60: (Grain side) Dielectric material layer

[0037] 80: Grain side bump structure

[0038] 80A: First grain side bump structure

[0039] 80B: Second grain side bump structure

[0040] 100: Printed Circuit Board

[0041] 110: PCB substrate

[0042] 118: (Packaging side) Stress-reducing circuit structure

[0043] 140: (Interconnection level) Stress-reducing circuit structure

[0044] 180: (Grain-side) Stress-reducing circuit structure

[0045] 188: PCB bonding pad

[0046] 190: Solder joint

[0047] 192: Bottom filling material section

[0048] 200: Packaging substrate

[0049] 210: Core substrate

[0050] 212: Dielectric sheath

[0051] 214: Through-core guide hole structure

[0052] 240: Surface Add-on Circuit

[0053] 242: Side insulation layer

[0054] 244: Embedded board side wiring interconnection

[0055] 248: Side joint solder pads

[0056] 260: Wafer-side surface-addition circuit

[0057] 262: Wafer-side insulating layer

[0058] 264: Embedded chip-side wiring interconnect

[0059] 268: Wafer-side bonding pad

[0060] 292, 780: Bottom filling material section

[0061] 294: Stable Structure

[0062] 300: Carrier substrate

[0063] 301: Adhesive layer

[0064] 400: Organic Intermediate Layer

[0065] 450, 788: Solder section

[0066] 701: (First) Semiconductor die

[0067] 702: (Second) Semiconductor die

[0068] 708: Grain bump structure

[0069] 790: EMC grain framework

[0070] 710, 712, 720, 722, 730, 740, 742: Steps

[0071] B: Region

[0072] DA1: First Region

[0073] DA2: Second Region

[0074] GR: Gap region

[0075] UIA: Unit Intermediate Layer Region

[0076] α: First angle

[0077] β: Second angle

[0078] ls1: First straight segment

[0079] ls2: Second straight segment

[0080] hd1: First horizontal direction

[0081] hd2: Second horizontal direction Detailed Implementation

[0082] The following disclosure provides many different embodiments or examples to implement different features of this application. Specific examples of components and their arrangements are described below to illustrate this disclosure. Of course, these embodiments are merely examples and should not be construed as limiting the scope of this disclosure. For example, the specification may describe a first feature formed on or above a second feature, which may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, repeated reference numerals and / or designations may be used in different examples of this disclosure; this repetition is for simplification and clarity and is not intended to limit any specific relationship between the various embodiments and / or structures discussed.

[0083] Furthermore, spatial terms such as "below," "below," "lower," "above," "higher," and similar terms are used to facilitate the description of the relationship between one element or feature and another element(s) in the illustration. In addition to the orientation shown in the diagram, these spatial terms are intended to encompass different orientations of the device in use or operation. The device may be rotated to different orientations (90 degrees or other orientations), and the spatial terms used herein may be interpreted in the same way. Unless otherwise explicitly stated, it is assumed that each element with the same reference numeral has the same material composition and a thickness within the same thickness range.

[0084] This disclosure relates to semiconductor devices, and more particularly to wafer package structures including organic interposers and methods for forming the same, wherein the organic interposers include stress-resistant bonding structures, various aspects of which will be described in detail below.

[0085] In general, the methods and structures of the embodiments of this disclosure can be used to provide an organic interposer that is resistant to structural damage caused by stress that may occur during the attachment of at least one semiconductor die. Specifically, applying an underfill material portion between the organic interposer and the semiconductor die typically induces mechanical stress on the organic interposer. Such applied and induced stress may cause deformation or breakage of the redistributed interconnect structure in the organic interposer. According to some embodiments of this disclosure, stress-relief line structures can be formed in gap regions between adjacent regions of the organic interposer for attaching the semiconductor die. The stress-relief line structures may include the same material as the redistributed interconnect structure or bump structure, or may include a different material. The mechanical strength of the stress-relief line structure may be less than that of the redistributed interconnect structure, such that deformation of the stress-relief line structure occurs before deformation of the redistributed interconnect structure. In other words, the stress-relief line structure is deformable under mechanical stress, thereby protecting the redistributed interconnect structure from deformation and preventing harmful deformation of the redistributed interconnect structure.

[0086] In embodiments where the stress-reducing circuit structure comprises the same material as the redistributed interconnect structure, the size (e.g., width) of the stress-reducing circuit structure can be selected (for example, by using a width smaller than the average width of the redistributed interconnect structure) such that the stress-reducing circuit structure deforms before the redistributed interconnect structure deforms. In embodiments where the stress-reducing circuit structure comprises a different material than the redistributed interconnect structure, the material of the stress-reducing circuit structure can have a smaller Young's modules, thus allowing it to deform and absorb external stresses while preventing deformation of the redistributed interconnect structure.

[0087] The stress-relief circuit structure can be conductive and electrically connected to a redistributed interconnect structure located in a region overlapping with the die-side bump structure. Alternatively, the stress-relief circuit structure can be electrically isolated from the redistributed interconnect structure and the bump structure located in a region overlapping with the die-side bump structure. The stress-relief circuit structure can be configured in many different patterns. The stress-relief circuit structure can have a zigzag circuit structure including multiple straight segments, can include multiple straight segments connected by curved segments, or can have a mesh structure. Various aspects of the methods and structures of embodiments of this disclosure are described below with reference to the accompanying drawings.

[0088] Figure 1A This is a vertical cross-sectional view of an exemplary structure including an organic interposer layer formed above a carrier substrate, according to some embodiments of the present disclosure. Figure 1B It is located in Figure 1A An enlarged view of the first structure of the stress-relief line structure in region B. Figure 1C It is located in Figure 1A An enlarged view of the second structure of the stress-relief line structure in region B. Figure 1D It is located in Figure 1A An enlarged view of the third structure of the stress-relief line structure in region B. Figure 1E It is located in Figure 1A An enlarged view of the fourth structure of the stress-relief line structure in region B. Figure 1F It is located in Figure 1A An enlarged view of the fifth structure of the stress-relief line structure in region B. Figure 1G It is located in Figure 1A An enlarged view of the sixth structure of the stress-relief line structure in region B. Figure 1H It is located in Figure 1A An enlarged view of the seventh structure of the stress-relief line structure in region B. Figure 1I yes Figure 1A A plan view of an exemplary structure.

[0089] Reference Figure 1AExemplary structures according to some embodiments of this disclosure may include a plurality of organic interposer layers 400 formed over a carrier substrate 300. An organic interposer layer refers to an interposer layer comprising at least one organic insulating material (e.g., an organic polymer matrix material). Each organic interposer layer 400 may be formed within a separate unit interposer area (UIA). A two-dimensional array of organic interposer layers 400 may be formed on the carrier substrate 300. The carrier substrate 300 may be a circular wafer or a rectangular wafer. The lateral dimensions of the carrier substrate 300 (e.g., the diameter of a circular wafer or the side length of a rectangular wafer) may range from 100 millimeters (mm) to 500 millimeters (e.g., 200 millimeters to 400 millimeters), although smaller or larger lateral dimensions may also be used. The carrier substrate 300 may include a semiconductor substrate, an insulating substrate, or a conductive substrate. The carrier substrate 300 may be transparent or opaque. The thickness of the carrier substrate 300 may be sufficient to provide mechanical support for the array of organic interposer layers 400 subsequently formed thereon. For example, the thickness of the carrier substrate 300 can range from 60 microns to 1 millimeter, although smaller or larger thicknesses can also be used.

[0090] The adhesive layer 301 can be applied to the top surface of the carrier substrate 300. In some embodiments, the carrier substrate 300 may comprise a light-transparent material such as glass or sapphire. In this embodiment, the adhesive layer 301 may comprise a light-to-heat-conversion (LTHC) layer. The LTHC layer is a solvent-based coating applied using a spin coating method. The LTHC layer can form a layer that converts ultraviolet light into heat, thereby causing the LTHC layer to lose its adhesiveness. Alternatively, the adhesive layer 301 may comprise a thermally decomposable adhesive material. For example, the adhesive layer 301 may comprise an acrylic pressure-sensitive adhesive that decomposes at high temperatures. The debonding temperature of the thermally decomposable adhesive material can be in the range of 150 degrees to 400 degrees. Other suitable thermally decomposable adhesive materials that decompose at other temperatures are also within the scope of this disclosure.

[0091] Bump structures can then be formed over the adhesive layer 301. These bump structures are subsequently used to provide bonding with the package substrate and are therefore referred to herein as package-side bump structures 18. Package-side bump structures 18 can include any metallic material that can be bonded to solder. For example, an underbump metallurgy (UBM) layer stack can be deposited over the adhesive layer 301. The order of the material layers within the UBM layer stack can be selected so that solder portions can be subsequently bonded to portions of the bottom surface of the UBM layer stack. Layer stacks that can be used for UBM layer stacks include, but are not limited to, stacks of Cr / Cr-Cu / Cu / Au, Cr / Cr-Cu / Cu, TiW / Cr / Cu, Ti / Ni / Au, and Cr / Cu / Au. Other suitable materials are also within the scope of this disclosure. The thickness of the UBM layer stack can range from 5 micrometers to 60 micrometers (e.g., 10 micrometers to 30 micrometers), although smaller or larger thicknesses can also be used.

[0092] A photoresist layer can be applied over the UBM layer stack, and the photoresist layer can be photolithographically patterned to form an array of discrete patterned photoresist material portions. An etching process can be performed to remove the unmasked portions of the UBM layer stack. The etching process can be an isotropic etching process or anisotropic etching process. The remaining portions of the UBM layer stack include package-side bump structures 18. In some embodiments, the package-side bump structures 18 can be arranged as a two-dimensional array, which can be a two-dimensional periodic array, such as a rectangular periodic array. In some embodiments, the package-side bump structures 18 can be formed as controlled collapse chip connection (C4) bump structures.

[0093] According to some embodiments of this disclosure, a stress-reducing circuit structure can be formed at the horizontal height of the package-side bump structure 18. In embodiments where the stress-reducing circuit structure is formed at the same horizontal height as the package-side bump structure 18, such a stress-reducing circuit structure is referred to as a package-side stress-reducing circuit structure 118. As used herein, a circuit structure refers to a structure that extends laterally with a uniform or substantially uniform width (i.e., a width that varies less than 50% relative to the average width of the structure). The circuit structure may have a uniform height and may be straight, curved, or may have multiple adjacent circuit segments, each of which is straight or curved. As used herein, a circuit structure refers to a circuit structure used for the purpose of reducing stress on an assembly including a stress-reducing circuit structure, such that another structure within the assembly does not deform under external mechanical stress, while the stress-reducing circuit structure deforms in response to external mechanical stress.

[0094] In some embodiments, each organic interposer 400 may be formed within a unit interposer region UIA. Each unit interposer region UIA may include a first region DA1 (also referred to as a first die region), wherein a first semiconductor die will be attached to the organic interposer 400, and a second region DA2 (also referred to as a second die region), wherein a second semiconductor die will be attached to the organic interposer 400. A gap region GR is located between the first region DA1 and the second region DA2. Typically, multiple non-overlapping regions may be provided in each unit interposer region UIA, such that a semiconductor die can subsequently be attached to the organic interposer 400 within each non-overlapping region. A gap region GR may be provided between each adjacent pair of multiple non-overlapping regions within each unit interposer region UIA. Although a unit interposer region UIA including a first region DA1 and a second region DA2 is used in the various embodiments described herein, the scope of the invention explicitly covers embodiments in which a unit interposer region UIA may include three or more regions for bonding semiconductor dies and embodiments in which two or more gap regions GR are provided within the unit interposer region UIA.

[0095] Package-side stress-reducing line structures 118 may be formed in one or more and / or each gap region GR. In some embodiments, at least one metal material used to form the package-side bump structure 18 (e.g., a UBM layer stack) may be patterned such that the package-side stress-reducing line structure 118 can be formed simultaneously with the formation of the package-side bump structure 18. In other words, the patterned portion of the at least one metal material may include the package-side bump structure 18 and the package-side stress-reducing line structure 118. In some embodiments, a blank material layer comprising at least one metal material (e.g., a UBM layer stack) may be deposited over the carrier substrate 300, and a photoresist layer may be applied over the blank material layer and patterned. The pattern in the photoresist layer may be transferred to the blank material layer by an etching process, such as an anisotropic etching process. The patterned portion of the blank material layer may include the package-side stress-reducing line structure 118 and the package-side bump structure 18. In this embodiment, the package-side stress-reducing circuit structure 118 may include the same material as the package-side bump structure 18 and may have the same thickness as the package-side bump structure 18. The pattern and size of the package-side stress-reducing circuit structure 118 may be selected such that the package-side stress-reducing circuit structure 118 may deform before the deformation of the package-side bump structure 18 or the redistribution circuit structure to be formed subsequently.

[0096] In other embodiments, the package-side stress-reducing circuit structure 118 can be formed before or after the formation of the package-side bump structure 18 by depositing a preform material layer comprising a material different from that of the package-side bump structure 18. The preform material layer may comprise a metallic, semiconductor, or dielectric material. The preform material layer may comprise a material having a Young's modulus lower than that of the material of the redistribution circuit structure to be formed subsequently. For example, if the redistribution circuit structure to be formed subsequently comprises copper (Young's modulus approximately 128 GPa), the preform material layer may comprise a material with a Young's modulus in the range of 1 GPa to 120 GPa (e.g., 5 GPa to 100 GPa). Exemplary materials that can be used for the preform material layer include, but are not limited to, aluminum, silver, gold, gallium, indium, lead, and silicon oxide. A photoresist layer may be applied over the preform material layer and patterned. The pattern in the photoresist layer can be transferred to the preform material layer by an etching process, such as an anisotropic etching process. The patterned portion of the preform material layer may include the package-side stress-reducing circuit structure 118. In this embodiment, the package-side stress-reducing circuit structure 118 may include a different material from the package-side bump structure 18 and may have a different thickness than the package-side bump structure 18. In some embodiments, the pattern and size of the package-side stress-reducing circuit structure 118 may be selected such that the package-side stress-reducing circuit structure 118 can be easily deformed before the deformation of the package-side bump structure 18 or the redistribution circuit structure to be formed subsequently.

[0097] A dielectric material layer, referred to herein as package-side dielectric layer 12, may be deposited over the package-side bump structure 18. Package-side dielectric layer 12 may comprise a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable materials are also within the scope of this disclosure. The thickness of package-side dielectric layer 12 may range from 4 micrometers to 60 micrometers, although smaller or larger thicknesses may also be used. The package-side dielectric layer 12 is embedded within the package-side bump structure 18 above the carrier substrate 300.

[0098] Subsequently, multiple redistributed interconnect structures 40 and multiple additional dielectric layers can be formed over the package-side bump structure 18 and the package-side dielectric layer 12. These additional dielectric layers are collectively referred to herein as interconnect-level dielectric layers 20. The interconnect-level dielectric layer 20 may include multiple dielectric layers (22, 24, 26, 28), such as a first dielectric layer 22, a second dielectric layer 24, a third dielectric layer 26, and a fourth dielectric layer 28. Although the various embodiments described herein use four dielectric layers (22, 24, 26, 28) within which the redistributed interconnect structures 40 are embedded, the scope of this disclosure explicitly covers embodiments where the interconnect-level dielectric layer 20 may include two, four, five, or more dielectric layers.

[0099] Typically, at least one of the dielectric material layers (22, 24, 26, 28) may include an organic polymer matrix layer, that is, a continuous material layer comprising and / or substantially composed of an organic polymer. In some embodiments, each of the dielectric material layers (22, 24, 26, 28) may include an organic polymer matrix layer. Therefore, the organic interposer to be formed subsequently includes at least one organic polymer matrix layer.

[0100] The redistributed interconnect structure 40 includes multiple redistributed interconnect structures 40, each formed through a corresponding one of the dielectric material layers (22, 24, 26, 28). The redistributed interconnect structure 40 may include metal via structures, metal circuit structures, and / or integrated circuit and via structures. Each integrated circuit and via structure includes a unitary structure comprising a metal circuit structure and at least one metal via structure. A unitary structure refers to a single continuous structure in which each point within the structure can be connected by a continuous line (which may or may not be a straight line) extending only within the structure.

[0101] In one illustrative example, the redistributed interconnect structure 40 may include a first redistributed interconnect structure 42 formed through and / or on the top surface of the first dielectric layer 22; a second redistributed interconnect structure 44 formed through and / or on the top surface of the second dielectric layer 24; and a third redistributed interconnect structure 46 formed through and / or on the top surface of the third dielectric layer 26. Although the redistributed interconnect structure 40 is embedded within three dielectric layers (22, 24, 26) in the various embodiments described herein, the scope of this disclosure explicitly covers embodiments in which the redistributed interconnect structure 40 is embedded within one, two, four, or more dielectric layers.

[0102] Each of the interconnect-level dielectric material layers 20 may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable materials are also within the scope of this disclosure. The thickness of each interconnect-level polymer matrix layer 20 may range from 4 micrometers to 20 micrometers, although smaller or larger thicknesses may also be used. Each of the redistributed interconnect structures 40 includes at least one metallic material, such as Cu, Mo, Co, Ru, W, TiN, TaN, WN, or combinations or stacks thereof. Other suitable materials are also within the scope of this disclosure. For example, each of the redistributed interconnect structures 40 may include a stack of TiN and Cu layers. In embodiments where the redistributed interconnect structure 40 includes a metallic circuit structure, the thickness of the metallic circuit structure may range from 2 micrometers to 20 micrometers, although smaller or larger thicknesses may also be used.

[0103] The redistributed interconnect structure 40 at the topmost metal interconnect level may include metal pad structures 48. The metal pad structures 48 may be formed in the region where the grain-side bump structure 80 will subsequently be formed. In some embodiments, the metal pad structures 48 may be formed as a two-dimensional array.

[0104] In some embodiments, the metal pad structure 48 may be formed as a pad portion of an individual integral structure comprising a metal pad structure 48 and a metal via structure. For example, the metal pad structure 48 may be located on the top surface of the third dielectric layer 26, and the metal via structure may extend vertically through the third dielectric layer 26. Each metal via structure connected to the upper metal pad structure 48 may contact the top surface of a corresponding lower redistributed interconnect structure (which may be one of the second redistributed interconnect structures 44).

[0105] According to some embodiments of this disclosure, stress-reducing line structures can be formed at the horizontal height (one or more levels) of one or more of the redistributed interconnect structures 40. In embodiments where the stress-reducing line structure is formed at the same horizontal height as any of the redistributed interconnect structures 40 (any level), such a stress-reducing line structure is referred to as an interconnect-level stress-reducing line structure 140. In some embodiments, each organic interposer layer 400 can be formed within a unit interposer layer region UIA. Each unit interposer layer region UIA may include a first region DA1 (also referred to as a first die region), wherein a first semiconductor die will be attached to the organic interposer layer 400, and a second region DA2 (also referred to as a second die region), wherein a second semiconductor die will be attached to the organic interposer layer 400. Gap regions GR are located between the first region DA1 and the second region DA2 and / or between each adjacent region subsequently used for attaching semiconductor dies.

[0106] Interconnect-level stress-reducing line structures 140 may be formed in one or more and / or each gap region GR. In some embodiments, at least one metal material used to form the redistributed interconnect structure 40 may be patterned such that the interconnect-level stress-reducing line structure 140 may be formed simultaneously with the formation of the redistributed interconnect structure 40. In other words, the patterned portion of the at least one metal material may include the redistributed interconnect structure 40 and the interconnect-level stress-reducing line structure 140. In some embodiments, a preform material layer comprising at least one metal material (e.g., a stack of metal barrier layers and copper layers) may be deposited over one of the package-side dielectric material layer 12 or the interconnect-level dielectric material layer 20, and a photoresist layer may be applied over the preform material layer and the photoresist layer may be patterned. The pattern in the photoresist layer may be transferred to the preform material layer by an etching process, such as an anisotropic etching process. The patterned portion of the preform material layer may include the interconnect-level stress-reducing line structure 140 and the redistributed interconnect structure 40. In this embodiment, the interconnect-level stress-reducing line structure 140 may include the same material as the redistributed interconnect structure 40 and may have the same thickness as the redistributed interconnect structure 40. The pattern and size of the interconnect-level stress-reducing line structure 140 may be selected such that the interconnect-level stress-reducing line structure 140 can be deformed before the deformation of the package-side bump structure 18 or the redistributed interconnect structure 40.

[0107] In other embodiments, the interconnect stage stress-reducing line structure 140 can be formed before or after the formation of that stage in the redistributed interconnect structure 40 by depositing a preform material layer comprising a material different from that of the stage in the redistributed interconnect structure 40. The preform material layer can include a metallic, semiconductor, or dielectric material. The preform material layer can include a material having a Young's modulus lower than that of the material in the redistributed interconnect structure 40. For example, if the redistributed interconnect structure 40 comprises copper (Young's modulus approximately 128 GPa), the preform material layer can include a material with a Young's modulus in the range of 1 GPa to 120 GPa (e.g., 5 GPa to 100 GPa). Exemplary materials that can be used for the preform material layer include, but are not limited to, aluminum, silver, gold, gallium, indium, lead, and silicon oxide. A photoresist layer can be applied over the preform material layer and patterned. The pattern in the photoresist layer can be transferred to the preform material layer by an etching process, such as an anisotropic etching process. The patterned portion of the preform material layer may include interconnect-level stress-reducing circuitry 140. In this embodiment, interconnect-level stress-reducing circuitry 140 may include a different material than the redistributed interconnect structure 40 and may have a different thickness than the redistributed interconnect structure 40. In some embodiments, the pattern and size of interconnect-level stress-reducing circuitry 140 may be selected such that, under the action of mechanical stress (which may occur, for example, during the bonding process), interconnect-level stress-reducing circuitry 140 is easily deformed before the deformation of the package-side bump structure 18 or the redistributed interconnect structure 40.

[0108] An additional dielectric material layer may be deposited over the metal pad structure 48 of each organic interposer layer 400 and at least one metal substrate 46. This additional dielectric material layer is referred to herein as a grain-side dielectric material layer 60. The grain-side dielectric material layer 60 comprises a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable materials are also within the scope of this disclosure. The thickness of the grain-side dielectric material layer 60 may range from 4 micrometers to 60 micrometers (e.g., 8 micrometers to 30 micrometers), although smaller or larger thicknesses may also be used. In this document, the package-side dielectric material layer 12, the interconnect-level dielectric material layer 20, and the grain-side dielectric material layer 60 are collectively referred to as dielectric material layers (12, 20, 60).

[0109] A photoresist layer can be applied over the grain-side dielectric layer 60, and the photoresist layer can be photolithographically patterned to form discrete openings therethrough. The openings in the photoresist layer include a first opening overlying a corresponding metal pad structure 48 and a second opening overlying the at least one metal substrate 46. Anisotropic etching can be performed to transfer the pattern of the openings in the photoresist layer to the grain-side dielectric layer 60. This forms a first via cavity and a second via cavity through the grain-side dielectric layer 60. The first via cavity extends to the top surface of a corresponding metal pad structure 48, while the second via cavity extends to the top surface of the at least one metal substrate 46.

[0110] At least one metallic material can be deposited in the bump via cavity and above the top surface of the grain-side dielectric material layer 60. The at least one metallic material may include a metal substrate and a copper layer. The metal substrate may include materials such as Ti, Ta, W, TiN, TaN, WN, or combinations thereof, and may have a thickness ranging from 30 nanometers (nm) to 300 nanometers. The copper layer may have a thickness ranging from 10 micrometers (µm) to 60 micrometers, although smaller or larger thicknesses may also be used.

[0111] A photoresist layer can be applied over the at least one metallic material and can be photolithographically patterned to cover discrete regions. An etching process can be performed to remove unmasked portions of the at least one metallic material. Each patterned portion of the at least one metallic material includes a bump structure, referred to herein as a grain-side bump structure 80. The grain-side bump structure 80 may include a first grain-side bump structure 80A formed in a first region DA1 and a second grain-side bump structure 80B formed in a second region DA2. In some embodiments, each grain-side bump structure 80 may include a metal substrate and a copper portion. Structurally, each grain-side bump structure 80 may include a bump via portion extending through the grain-side dielectric material layer 60 and contacting a metal pad structure, and a bonding bump portion overlying the grain-side dielectric material layer 60. In some embodiments, each bonding bump portion may have a cylindrical shape, i.e., a cylindrical shape with a circular horizontal cross-section. Each bonding bump portion may have sidewalls having a cylindrical surface shape.

[0112] According to some embodiments of this disclosure, stress-reducing circuit structures can be formed at the horizontal height of the grain-side bump structure 80. In embodiments where the stress-reducing circuit structure is formed at the same horizontal height as the grain-side bump structure 80, such a stress-reducing circuit structure is referred to as a grain-side stress-reducing circuit structure 180. In some embodiments, each organic interposer layer 400 can be formed within a unit interposer layer region UIA. Each unit interposer layer region UIA may include a first region DA1 (also referred to as a first grain region), wherein a first semiconductor grain will be attached to the organic interposer layer 400, and a second region DA2 (also referred to as a second grain region), wherein a second semiconductor grain will be attached to the organic interposer layer 400. Gap regions GR are located between the first region DA1 and the second region DA2 and / or between each adjacent region subsequently used for attaching semiconductor grains.

[0113] The grain-side stress-reducing circuit structure 180 can be formed in one or more and / or each gap region GR. In some embodiments, at least one metal material used to form the grain-side bump structure 80 can be patterned such that the grain-side stress-reducing circuit structure 180 can be formed simultaneously with the formation of the grain-side bump structure 80. In other words, the patterned portion of the at least one metal material can include the grain-side bump structure 80 and the grain-side stress-reducing circuit structure 180. In some embodiments, a preform material layer including at least one metal material (e.g., a stack of metal barrier layers and copper layers) can be deposited over the grain-side dielectric material layer 60, and a photoresist layer can be applied over the preform material layer and patterned. The pattern in the photoresist layer can be transferred to the preform material layer by an etching process, such as an anisotropic etching process. The patterned portion of the preform material layer can include the grain-side bump structure 80 and the grain-side stress-reducing circuit structure 180. In this embodiment, the grain-side stress-reducing circuit structure 180 may include the same material as the grain-side bump structure 80 and may have the same thickness as the grain-side bump structure 80. The pattern and size of the grain-side stress-reducing circuit structure 180 may be selected such that the grain-side stress-reducing circuit structure 180 can be deformed before the deformation of the package-side bump structure 18, the redistribution interconnect structure 40, or the grain-side bump structure 80.

[0114] In other embodiments, the grain-side stress-reducing circuit structure 180 can be formed before or after the formation of the grain-side bump structure 80 by depositing a preform material layer comprising a material different from that of the grain-side bump structure 80. The preform material layer may comprise a metallic, semiconductor, or dielectric material. The preform material layer may comprise a material having a Young's modulus lower than that of the material of the redistribution interconnect structure 40. For example, if the redistribution interconnect structure 40 comprises copper (Young's modulus approximately 128 GPa), the preform material layer may comprise a material with a Young's modulus in the range of 1 GPa to 120 GPa (e.g., 5 GPa to 100 GPa). Exemplary materials that can be used for the preform material layer include, but are not limited to, aluminum, silver, gold, gallium, indium, lead, and silicon oxide. A photoresist layer may be applied over the preform material layer and patterned. The pattern in the photoresist layer can be transferred to the preform material layer by an etching process, such as an anisotropic etching process. The patterned portion of the preform material layer may include a grain-side stress-reducing circuit structure 180. In this embodiment, the grain-side stress-reducing circuit structure 180 may include a different material than the grain-side bump structure 80 and may have a different thickness than the grain-side bump structure 80. In some embodiments, the pattern and size of the grain-side stress-reducing circuit structure 180 may be selected such that, under the action of mechanical stress (which may occur, for example, during the bonding process), the grain-side stress-reducing circuit structure 180 is easily deformable before the deformation of the package-side bump structure 18, the redistributed interconnect structure 40, or the grain-side bump structure 80.

[0115] Exemplary patterns that can be used in stress-relief circuit structures (118, 140, and / or 180) are as follows: Figures 1B to 1H As shown. (Refer to...) Figures 1B to 1H Each of the stress-reducing circuit structures (118, 140, and / or 180) may include a plurality of straight segments (ls1, ls2) that extend laterally in their respective horizontal directions. In some embodiments, each of the stress-reducing circuit structures (118, 140, and / or 180) includes a set of straight segments (ls1, ls2) that are parallel to each other.

[0116] In some embodiments, the stress-relief line structure (118, 140, and / or 180) may extend laterally beyond the range of the gap region GR and into the first region DA1 and the second region DA2, as shown. Figures 1B to 1DAs shown. In this embodiment, the stress-relief circuit structure 118 may extend through the gap region GR and may laterally protrude into the first region DA1 and / or the second region DA2. In some embodiments, the stress-relief circuit structures (118, 140 and / or 180) may include a metallic material and may be used as a conductive path as a signal path between the first region DA1 and the second region DA2.

[0117] In some embodiments, the stress-relief line structures (118, 140, and / or 180) may be entirely located within the gap region GR, and therefore do not extend laterally into the first region DA1 or the second region DA2, such as Figures 1E to 1H As shown. In this embodiment, the stress-relief circuitry (118, 140 and / or 180) is not electrically connected to the redistributed interconnect structure to be formed subsequently.

[0118] In some embodiments, each of the stress-relief line structures (118, 140, and / or 180) may include a plurality of first straight segments ls1 extending laterally along a first horizontal direction hd1, and a plurality of second straight segments ls2 extending laterally along a second horizontal direction hd2 different from the first horizontal direction hd1, such as Figure 1B , Figure 1C as well as Figures 1E to 1H As shown. The angle between the first horizontal direction hd1 and the second horizontal direction hd2 can be in the range of 10 degrees to 145 degrees.

[0119] exist Figure 1B , Figure 1C , Figure 1F as well as Figure 1G In the illustrated embodiment, the sidewalls of the first straight segment ls1 and the second straight segment ls2 of each of the stress-reducing circuit structures are abutted against each other by vertical edges. The sidewall of the first straight segment ls1 may abut against the sidewall of the second straight segment ls2 at a first angle α less than 180 degrees and a second angle β greater than 180 degrees.

[0120] Figure 1D and Figure 1H In the embodiments shown, the straight sections of the stress-relief line structures (118, 140 and / or 180) can be interconnected by curved sections with curved sidewalls.

[0121] exist Figure 1EIn the illustrated embodiment, the stress-reducing circuit structure (118, 140, and / or 180) may include a plurality of first stress-reducing circuit structures extending laterally along a first horizontal direction hd1 (therefore including a plurality of first straight segments ls1 extending laterally along the first horizontal direction hd1), and a plurality of second stress-reducing circuit structures extending laterally along a second horizontal direction hd2 (therefore including a plurality of second straight segments ls2 extending laterally along the second horizontal direction hd2). The stress-reducing circuit structures (118, 140, and / or 180) may be arranged as an interconnected mesh, wherein the first stress-reducing circuit structures and the second stress-reducing circuit structures are adjacent to each other in a mesh pattern.

[0122] Common Reference Figures 1A to 1I And according to various embodiments of the present disclosure, an organic interposer 400 is provided, comprising: a dielectric material layer (12, 20, 60) with an embedded redistribution interconnect structure 40; a package-side bump structure 18 located on a first side of the dielectric material layer (12, 20, 60) and connected to a package-side subset of the redistribution interconnect structure 40; and a die-side bump structure 80 located on a second side of the dielectric material layer (12, 20, 60) and connected to a die-side subset of the redistribution interconnect structure 40. The subset includes a first grain-side bump structure 80 located in a first region DA1 and a second grain-side bump structure 80B located in a second region DA2. In a plan view (i.e., a view along the vertical direction perpendicular to the horizontal plane of the dielectric material layers (12, 20, 60), the second region DA2 is laterally separated from the first region DA1 by a gap region GR, in which there are no grain-side bump structures 80; and stress-reducing line structures (118, 140, and / or 180) located above or within the dielectric material layers (12, 20, 60) within the gap region GR in the plan view. The stress-reducing line structures (118, 140, and / or 180) are made of the same material and located at the same horizontal height as one of the package-side bump structure 18, the redistributed interconnect structure 40, and the grain-side bump structure 80.

[0123] In some embodiments, each of the stress-relief line structures (118, 140 and / or 180) includes a plurality of straight segments extending laterally in their respective horizontal directions and is not electrically connected to the redistribution interconnect structure 40.

[0124] In some embodiments, each of the stress-relief circuit structures (118, 140, and / or 180) includes: a plurality of first straight segments ls1 extending laterally along a first horizontal direction hd1; and a plurality of second straight segments ls2 extending laterally along a second horizontal direction hd2 different from the first horizontal direction hd1. In some embodiments, the sidewalls of the first straight segments and the sidewalls of the second straight segments in each of the stress-relief circuit structures are abutted against each other by vertical edges. In some embodiments, the straight segments are connected to each other by curved segments having curved sidewalls.

[0125] In some embodiments, the stress-reducing circuit structure (118, 140, and / or 180) includes a plurality of first stress-reducing circuit structures extending laterally along a first horizontal direction, and a plurality of second stress-reducing circuit structures extending laterally along a second horizontal direction. Furthermore, the stress-reducing circuit structures are arranged as an interconnect, wherein the first and second stress-reducing circuit structures are adjacent to each other in a grid pattern, such as... Figure 1E As shown.

[0126] In some embodiments, the dielectric material layers (12, 20, 60) include a grain-side dielectric material layer 60. Each of the grain-side bump structures 80 includes a horizontal surface in contact with the horizontal surface of the grain-side dielectric material layer 60. A stress-reducing circuit structure (in embodiments where the stress-reducing circuit structure includes a grain-side stress-reducing circuit structure 180) is in contact with the horizontal surface of the grain-side dielectric material layer 60. Furthermore, the stress-reducing circuit structure has the same material composition and the same thickness as the grain-side bump structure 80.

[0127] In some embodiments, the dielectric material layers (12, 20, 60) include a package-side dielectric material layer 12, within which a package-side bump structure 18 and a stress-reducing circuit structure (in embodiments where the stress-reducing circuit structure includes a package-side stress-reducing circuit structure 180) are embedded. Furthermore, the horizontal plane of the package-side bump structure 18 and the horizontal plane of the stress-reducing circuit structure, which does not contact the dielectric material layers (12, 20, 60) or the redistributed interconnect structure 40, lie in the same horizontal plane (e.g., the horizontal plane including the bottommost surface of the organic interposer layer 400). In some embodiments, the stress-reducing circuit structure has the same material composition and the same thickness as the package-side bump structure 18.

[0128] In some embodiments, the stress-reducing circuitry (in embodiments where the stress-reducing circuitry includes an interconnect-level stress-reducing circuitry 140) is embedded within dielectric material layers (12, 20, 60) and located between a first horizontal plane and a second horizontal plane. The first horizontal plane includes the interface between the package-side bump structure 18 and a first subset of the redistributed interconnect structure 40, and the second horizontal plane includes the interface between the die-side bump structure 80 and a second subset of the redistributed interconnect structure 40. In some embodiments, the stress-reducing circuitry has the same material composition and the same thickness as a subset of the redistributed interconnect structure 40, wherein the subset is different from or the same as one of the first and second subsets.

[0129] According to other embodiments of this disclosure, an organic interposer 400 is provided, comprising: a dielectric material layer (12, 20, 60) with an embedded redistribution interconnect structure 40; an encapsulation-side bump structure 18 located on a first side of the dielectric material layer (12, 20, 60) and connected to an encapsulation-side subset of the redistribution interconnect structure 40; and a die-side bump structure 80 located on a second side of the dielectric material layer (12, 20, 60) and connected to a die-side subset of the redistribution interconnect structure 40, wherein the die-side bump structure 80 encapsulates... The system includes a first grain-side bump structure 80A located in a first region DA1 and a second grain-side bump structure 80B located in a second region DA2. In a plan view, the second region DA2 is laterally separated from the first region DA1 by a gap region GR, in which there are no grain-side bump structures 80; and stress-reducing circuit structures (118, 140, and / or 180) located above or within dielectric material layers (12, 20, 60) within the gap region GR in the plan view. The stress-reducing circuit structures (118, 140, and / or 180) are located at the same horizontal level as a metal component selected from the package-side bump structure 18, the redistributed interconnect structure 40, and the grain-side bump structure 80. The stress-reducing circuit structures (118, 140, and / or 180) are made of different materials than the metal component.

[0130] In some embodiments, the dielectric material layers (12, 20, 60) include a grain-side dielectric material layer 60. Each of the grain-side bump structures 80 includes a horizontal surface in contact with the horizontal surface of the grain-side dielectric material layer 60. A stress-reducing circuit structure (in embodiments where the stress-reducing circuit structure includes a grain-side stress-reducing circuit structure 180) is in contact with the horizontal surface of the grain-side dielectric material layer 60. Furthermore, the stress-reducing circuit structure has a different material composition or a different thickness than the grain-side bump structure 80.

[0131] In some embodiments, the dielectric material layers (12, 20, 60) include a package-side dielectric material layer 12, within which a package-side bump structure 18 and a stress-reducing circuit structure (in embodiments where the stress-reducing circuit structure includes a package-side stress-reducing circuit structure 180) are embedded. The horizontal plane of the package-side bump structure 18 and the horizontal plane of the stress-reducing circuit structure, which does not contact the dielectric material layers (12, 20, 60) or the redistributed interconnect structure 40, lie in the same horizontal plane (e.g., the horizontal plane including the bottommost surface of the package-side dielectric material layer 12). Furthermore, the stress-reducing circuit structure has a different material composition or a different thickness than the package-side bump structure 18.

[0132] In some embodiments, the stress-reducing circuit structure (in embodiments where the stress-reducing circuit structure includes an interconnect-level stress-reducing circuit structure 140) is embedded within dielectric material layers (12, 20, 60) and located between a first horizontal plane and a second horizontal plane. The first horizontal plane includes the interface between the package-side bump structure 18 and a first subset of the redistributed interconnect structure 40, and the second horizontal plane includes the interface between the die-side bump structure 80 and a second subset of the redistributed interconnect structure 40. Furthermore, the stress-reducing circuit structure has a different material composition than the redistributed interconnect structure.

[0133] In some embodiments, each of the grain-side bump structures 80 includes a horizontal surface that contacts the horizontal surface of the grain-side dielectric material layer 60, and the stress-relief circuit structure (e.g., the grain-side stress-relief circuit structure 180) contacts the horizontal surface of the grain-side dielectric material layer 60.

[0134] Figure 2 This is a vertical cross-sectional view of an exemplary structure after a semiconductor die has been attached to an organic interposer, according to some embodiments of the present disclosure. At least one semiconductor die (701, 702) may be attached to a respective organic interposer 400. Each semiconductor die (701, 702) may be bonded via solder portions 788 to a corresponding subset of a die-side bump structure 80 within a separate unit interposer region (UIA). Each semiconductor die (701, 702) may include a die bump structure 708. In some embodiments, the die bump structure 708 may include a two-dimensional array of microbump structures, and each semiconductor die (701, 702) may be attached to the die-side bump structure 80 via C2 bonding (i.e., solder bonding between a pair of microbumps). After the die bump structures 708 of the semiconductor dies (701, 702) are disposed over the array of solder portions 788, a C2 bonding process may be performed to reflow the solder portions 788.

[0135] The at least one semiconductor die (701, 702) may include any semiconductor die known in the art. In some embodiments, the at least one semiconductor die (701, 702) may include a system-on-chip (SoC) die, such as an application processor die. In some embodiments, the at least one semiconductor die (701, 702) may include multiple semiconductor dies (701, 702). In some embodiments, the multiple semiconductor dies (701, 702) may include a first semiconductor die 701 and at least one second semiconductor die 702. In some embodiments, the first semiconductor die 701 may be a central processing unit die, while the at least one second semiconductor die 702 may include a graphics processing unit die. In other embodiments, the first semiconductor die 701 may include a system-on-a-chip (SoC) die, while the at least one second semiconductor die 702 may include at least one high bandwidth memory (HBM) die, each HBM die comprising a vertically stacked plurality of static random access memory (SRAM) dies and providing high bandwidth as defined by JEDEC standards (i.e., standards defined by the JEDEC Solid State Technology Association). The top surfaces of the semiconductor dies (701, 702) attached to the same organic interposer 400 may lie in the same horizontal plane. Typically, at least one semiconductor die (701, 702) may be attached to the die-side bump structure 80 via at least one set of solder portions 788.

[0136] Figure 3 This is a vertical cross-sectional view of an exemplary structure after forming a fan-out wafer-level package according to some embodiments of the present disclosure. At least one underfill material portion 780 may be formed around each set of bonded solder portions 788. After reflowing the solder portions 788, each underfill material portion 780 may be formed by injecting underfill material around the array of solder portions 788. Any known underfill material application method may be used, such as a capillary underfill method, a molded underfill method, or a printed underfill method. In some embodiments, a plurality of semiconductor dies (701, 702) may be attached to an organic interposer layer 400 within each unit interposer region UIA, and a single underfill material portion 780 may extend continuously beneath the plurality of semiconductor dies (701, 702).

[0137] According to some embodiments of this disclosure, the stress-reducing circuit structures (118, 140, 180) can absorb mechanical stress from the organic interposer layer 400 during the application and curing of the underfill material. Specifically, the underfill material application process can apply pressure to the grain-side dielectric material layer 60. The stress-reducing circuit structures (118, 140, 180) can deform in response to mechanical stress, such that portions of the organic interposer layer 400 located in the first region DA1 and the second region DA2 deform less during the underfill material application process or subsequently during processes that may generate mechanical stress.

[0138] Epoxy molding compound (EMC) is applied to the gap between the organic interposer 400 and the semiconductor grains (701, 702). EMC comprises curable (i.e., hardenable) epoxy-containing compounds to provide a dielectric material portion with sufficient rigidity and mechanical strength. EMC may include epoxy resin, hardener, silica (as a filler), and other additives. EMC can be provided in liquid or solid form, depending on its viscosity and flowability. Liquid EMC provides better workability, good flowability, fewer voids, better filling effect, and fewer flow marks. Solid EMC can reduce curing shrinkage, increase support strength, and reduce grain drift. Higher filler content within the EMC (e.g., 85% by weight) can shorten molding time, reduce mold shrinkage, and reduce mold warpage. Uniform distribution of filler size in the EMC can reduce flow marks and improve flowability. The curing temperature of the EMC can be lower than the release (debonding) temperature of the adhesive layer 301. For example, the curing temperature of EMC can be in the range of 125°C to 150°C.

[0139] The EMC can be cured at a curing temperature to form an EMC matrix that laterally surrounds each semiconductor die (701, 702). The EMC matrix comprises a plurality of EMC die frames 790 laterally adjacent to each other. Each EMC die frame 790 is located within an individual unit interposer region (UIA) and laterally surrounds and embeds a corresponding set (which may be multiple semiconductor dies (701, 702)) of at least one semiconductor die (701, 702). Excess EMC can be removed from a horizontal plane including the top surface of the semiconductor dies (701, 702) by a planarization process (using a chemical mechanical planarization method).

[0140] Figure 4This is a vertical cross-sectional view of an exemplary structure after dicing a fan-out wafer-level package according to some embodiments of the present disclosure. The carrier substrate 300 can be separated from the components of the organic interposer 400, semiconductor dies (701, 702), and EMC die frame 790. The adhesive layer 301 can be deactivated, for example, by thermal annealing at a high temperature. Embodiments may include an adhesive layer 301 having a thermally deactivated adhesive material. In other embodiments where the adhesive layer 301 can be transparent, the adhesive layer 301 may have an ultraviolet-deactivated adhesive material.

[0141] An assembly of an organic interposer 400, semiconductor dies (701, 702), and an EMC die frame 790 can be diced along a dicing channel located at the boundary of the unit interposer region UIA. Each diced portion of the organic interposer 400, semiconductor dies (701, 702), and EMC die frame 790 includes a fan-out wafer-level package (FOWLP), comprising at least one semiconductor die (701, 702) (which may be multiple semiconductor dies), an organic interposer 400, an underfill portion 780, and an EMC frame 790. The EMC die frame 790 and the organic interposer 400 may have vertically overlapping sidewalls, i.e., their sidewalls lie in the same vertical plane. In embodiments where the fan-out wafer-level package includes multiple semiconductor dies (701, 702), the underfill portion 780 may contact the sidewalls of the multiple semiconductor dies (701, 702). The EMC die frame 790 extends continuously around the at least one semiconductor die (701, 702) within the fan-out wafer-level package and laterally surrounds the semiconductor die (701, 702).

[0142] Figure 5 This is a vertical cross-sectional view of an exemplary structure after attaching a packaging substrate to a fan-out wafer-level package, according to some embodiments of the present disclosure. (Refer to...) Figure 5A packaging substrate 200 is provided. The packaging substrate 200 may be a cored packaging substrate including a core substrate 210, or a coreless packaging substrate excluding a packaging core. Alternatively, the packaging substrate 200 may include a system-integrated package substrate (SoIS) comprising a redistribution layer and / or a dielectric interlayer, and at least one embedded interposer layer (e.g., a silicon interposer). Such a system-integrated package substrate may include layer-to-layer interconnections using solder portions, microbumps, underfill material portions (e.g., molded underfill material portions), and / or adhesive films. Although an exemplary packaging substrate is used herein to describe embodiments of the present disclosure, it should be understood that the scope of the invention is not limited to any particular type of packaging substrate and may include system-integrated package substrates (SoIS).

[0143] The core substrate 210 may include a glass epoxy plate comprising an array of through-plate holes. Through-core via structures 214, comprising a metallic material, may be provided within the through-plate holes. Each through-core via structure 214 may or may not include a cylindrical hollow interior. Optionally, a dielectric liner 212 may be used to electrically isolate the through-core via structures 214 from the core substrate 210.

[0144] The packaging substrate 200 may include a board-side surface augmentation circuit (SLC) 240 and a wafer-side surface augmentation circuit (SLC) 260. The board-side SLC 240 may include a board-side insulating layer 242 for embedded board-side wiring interconnects 244. The wafer-side SLC 260 may include a wafer-side insulating layer 262 for embedded wafer-side wiring interconnects 264. The board-side and wafer-side insulating layers 242 may include a photosensitive epoxy resin material that can be photolithographically patterned and subsequently cured. The embedded board-side and wafer-side wiring interconnects 244 and 264 may include copper, which can be deposited within patterns in the board-side or wafer-side insulating layers 242 by electroplating. An array of board-side bonding pads 248 may be electrically connected to the embedded board-side wiring interconnects 244 and may be configured to allow bonding via solder balls. An array of wafer-side bonding pads 268 can be electrically connected to wafer-side wiring interconnects 264 and can be configured to allow bonding via C4 solder balls.

[0145] Solder portions 450 of the package-side bump structure 18, which are components attached to the organic interposer 400, at least one semiconductor die (701, 702), and the EMC die frame 790, can be disposed on an array of wafer-side bonding pads 268 of the package substrate 200. A reflow process can be performed to reflow the solder portions 450, thereby inducing bonding between the organic interposer 400 and the package substrate 200. In some embodiments, the solder portions 450 may include C4 solder balls, and the components of the organic interposer 400, the at least one semiconductor die (701, 702), and the EMC die frame 790 can be attached to the package substrate 200 using an array of C4 solder balls. An underfill portion 292 can be formed around the solder portion 450 by applying and shaping an underfill material. Optionally, a stabilizing structure 294, such as a cap structure or a ring structure, can be attached to the organic interposer 400, the at least one semiconductor die (701, 702), the EMC die frame 790, and the package substrate 200 to reduce deformation of the components during subsequent processing steps and / or during use.

[0146] Figure 6 This is a vertical cross-sectional view of an exemplary structure after the packaging substrate has been attached to a printed circuit board (PCB) according to some embodiments of this disclosure. (Refer to...) Figure 6 A printed circuit board (PCB) 100 is provided, which includes a PCB substrate 110 and PCB bonding pads 188. The PCB substrate 110 includes printed circuitry (not shown) on at least one side. An array of solder contacts 190 can be formed to bond an array of board-side bonding pads 248 to an array of PCB bonding pads 188. The solder contacts 190 can be formed by distributing an array of solder balls between the array of board-side bonding pads 248 and the array of PCB bonding pads 188, and by reflowing the array of solder balls. Underfill material portions 192 can be formed around the solder contacts 190 by applying and shaping an underfill material. A package substrate 200 is attached to the PCB substrate 110 via the array of solder contacts 190.

[0147] Figure 7A This is a first flowchart illustrating the sequence of first processing steps for forming an organic interposer layer according to some embodiments of the present disclosure. Referring to step 710 and... Figures 1A to 1I A package-side bump structure 18 is formed above the carrier substrate 300, embedded in the package-side dielectric material layer 12. Refer to steps 712 and... Figures 1A to 1IA stress-reducing circuit structure (e.g., a package-side stress-reducing circuit structure 118) is formed within and / or on the package-side dielectric material layer 12 within the gap region GR in the plan view. Each stress-reducing circuit structure includes a plurality of straight segments extending laterally in its respective horizontal direction. The stress-reducing circuit structure may be located at the same horizontal height as the package-side bump structure 18. Refer to step 720 and... Figures 1A to 1H An interconnect-level dielectric material layer 20 and a redistributed interconnect structure 40 are formed above the package-side bump structure 18. In some embodiments, the stress-relief line structure (e.g., package-side stress-relief line structure 118) is not electrically connected to the redistributed interconnect structure 40. Referring to step 730 and... Figures 1A to 1I A grain-side dielectric material layer 60 is formed above the interconnect-level dielectric material layer 20. Refer to step 740 and... Figures 1A to 1I A grain-side bump structure 80 is formed above the grain-side dielectric material layer 60. The grain-side bump structure 80 includes a first grain-side bump structure 80A located in a first region DA1 and a second grain-side bump structure 80B located in a second region DA2. In a plan view, the second region DA2 is laterally separated from the first region DA1 by a gap region GR, and there is no grain-side bump structure 80 in the gap region GR.

[0148] Figure 7B This is a second flowchart illustrating a second sequence of processing steps for forming an organic interposer layer according to some embodiments of the present disclosure. Referring to step 710 and... Figures 1A to 1I A package-side bump structure 18 is formed above the carrier substrate 300, embedded in the package-side dielectric material layer 12. Refer to steps 720 and... Figures 1A to 1H An interconnect-level dielectric material layer 20 and a redistributed interconnect structure 40 are formed above the package-side bump structure 18. Refer to steps 722 and... Figures 1A to 1I A stress-reducing circuit structure (e.g., interconnect-level stress-reducing circuit structure 140) is formed within and / or on top of the interconnect-level dielectric material layer 20 within the gap region GR in the plan view. Each stress-reducing circuit structure includes a plurality of straight segments extending laterally in its respective horizontal direction. The stress-reducing circuit structure may be located at the same horizontal height as the redistributed interconnect structure 40. In some embodiments, the stress-reducing circuit structure (e.g., interconnect-level stress-reducing circuit structure 140) is not electrically connected to the redistributed interconnect structure 40. Referring to step 730 and... Figures 1A to 1I A grain-side dielectric material layer 60 is formed above the interconnect-level dielectric material layer 20. Refer to step 740 and... Figures 1A to 1IA grain-side bump structure 80 is formed above the grain-side dielectric material layer 60. The grain-side bump structure 80 includes a first grain-side bump structure 80A located in a first region DA1 and a second grain-side bump structure 80B located in a second region DA2. In a plan view, the second region DA2 is laterally separated from the first region DA1 by a gap region GR, and there is no grain-side bump structure 80 in the gap region GR.

[0149] Figure 7C This is a third flowchart illustrating a third sequence of processing steps for forming an organic interposer layer according to some embodiments of the present disclosure. Referring to step 710 and... Figures 1A to 1I A package-side bump structure 18 is formed above the carrier substrate 300, embedded in the package-side dielectric material layer 12. Refer to steps 720 and... Figures 1A to 1H An interconnect-level dielectric material layer 20 and a redistributed interconnect structure 40 are formed above the package-side bump structure 18. Refer to step 730 and... Figures 1A to 1I A grain-side dielectric material layer 60 is formed above the interconnect-level dielectric material layer 20. Refer to step 740 and... Figures 1A to 1I A grain-side bump structure 80 is formed above the grain-side dielectric material layer 60. The grain-side bump structure 80 includes a first grain-side bump structure 80A located in a first region DA1 and a second grain-side bump structure 80B located in a second region DA2. In a plan view, the second region DA2 is laterally separated from the first region DA1 by a gap region GR, in which there are no grain-side bump structures 80. Refer to steps 742 and... Figures 1A to 1I A stress-reducing circuit structure (e.g., a grain-side stress-reducing circuit structure 180) is formed within and / or on the grain-side dielectric material layer 60 within the gap region GR in the planar view. Each stress-reducing circuit structure includes a plurality of straight segments extending laterally along their respective horizontal direction. The stress-reducing circuit structure may be located at the same horizontal height as the grain-side bump structure 80. In some embodiments, the stress-reducing circuit structure (e.g., the grain-side stress-reducing circuit structure 180) is not electrically connected to the redistributed interconnect structure 40.

[0150] Various embodiments of this disclosure can be used to provide an organic interposer 400 and a semiconductor structure including the organic interposer 400, semiconductor dies (701, 702), and a package substrate 200. The organic interposer 400 includes stress-reducing line structures (118, 140, 180), which can advantageously induce deformation in areas where the semiconductor dies (701, 702) are absent (i.e., in the gap region GR), rather than in areas of the organic interposer 400 that overlap with the semiconductor dies (701, 702) in a planar view. Therefore, the yield of fan-out wafer-level packages (FOWLP) including the organic interposer 400 and multiple semiconductor dies (701, 702) can be improved.

[0151] According to some embodiments of this disclosure, an organic interposer layer is provided. The organic interposer layer includes multiple dielectric material layers, multiple package-side bump structures, multiple die-side bump structures, and multiple stress-reducing circuit structures. Multiple redistributed interconnect structures are embedded within the dielectric material layers. The package-side bump structures are located on a first side of the dielectric material layers and connected to a package-side subset of the redistributed interconnect structures. The die-side bump structures are located on a second side of the dielectric material layers and connected to a die-side subset of the redistributed interconnect structures. The die-side bump structures include multiple first die-side bump structures located in a first region and multiple second die-side bump structures located in a second region. In a plan view, the second region is laterally separated from the first region by a gap region, in which no die-side bump structures are present. The stress-reducing circuit structures are located above or within the dielectric material layers within the gap region in the plan view. The stress-reducing circuit structures and one of the package-side bump structures, the redistributed interconnect structures, and the die-side bump structures comprise the same material and are located at the same horizontal height.

[0152] In some embodiments, each of the stress-reducing circuit structures includes a plurality of straight segments extending laterally along a respective horizontal direction and is not electrically connected to a redistributed interconnect structure. In some embodiments, each of the stress-reducing circuit structures includes: a plurality of first straight segments extending laterally along a first horizontal direction; and a plurality of second straight segments extending laterally along a second horizontal direction different from the first horizontal direction. In some embodiments, the sidewalls of the first and second straight segments of each of the stress-reducing circuit structures are abutted against each other by a plurality of vertical edges. In some embodiments, the straight segments of each of the stress-reducing circuit structures are interconnected by a plurality of curved segments having curved sidewalls. In some embodiments, the stress-reducing circuit structure includes a plurality of first stress-reducing circuit structures extending laterally along a first horizontal direction and a plurality of second stress-reducing circuit structures extending laterally along a second horizontal direction, and the stress-reducing circuit structures are arranged as an interconnect, wherein the first and second stress-reducing circuit structures are abutted in a grid pattern. In some embodiments, the dielectric material layer includes a die-side dielectric material layer, each of the die-side bump structures includes a horizontal surface contacting the horizontal surface of the die-side dielectric material layer, and a stress-reducing circuit structure contacts the horizontal surface of the die-side dielectric material layer, and the stress-reducing circuit structure has the same material composition and the same thickness as the die-side bump structure. In some embodiments, the dielectric material layer includes a package-side dielectric material layer, in which a package-side bump structure and a stress-reducing circuit structure are embedded, and the horizontal surface of the package-side bump structure and the horizontal surface of the stress-reducing circuit structure that do not contact the dielectric material layer or the redistributed interconnect structure are located in the same horizontal plane. In some embodiments, the stress-reducing circuit structure has the same material composition and the same thickness as the package-side bump structure. In some embodiments, the stress-reducing circuit structure is embedded in the dielectric material layer and located between a first horizontal plane and a second horizontal plane, the first horizontal plane including the interface between the package-side bump structure and a first subset of the redistributed interconnect structure, and the second horizontal plane including the interface between the die-side bump structure and a second subset of the redistributed interconnect structure. In some embodiments, the stress-reducing circuit structure has the same material composition and the same thickness as a subset of the redistributed interconnect structure, which may be different from or the same as one of the first and second subsets.

[0153] According to other embodiments of this disclosure, an organic interposer layer is provided. The organic interposer layer includes multiple dielectric material layers, multiple package-side bump structures, multiple die-side bump structures, and multiple stress-reducing circuit structures. Multiple redistributed interconnect structures are embedded within the dielectric material layers. The package-side bump structures are located on a first side of the dielectric material layers and connected to a package-side subset of the redistributed interconnect structures. The die-side bump structures are located on a second side of the dielectric material layers and connected to a die-side subset of the redistributed interconnect structures. The die-side bump structures include multiple first die-side bump structures located in a first region and multiple second die-side bump structures located in a second region. In a plan view, the second region is laterally spaced from the first region by a gap region, in which no die-side bump structures are present. The stress-reducing circuit structures are located above or within the dielectric material layers within the gap region in the plan view. The stress-reducing circuit structures are at the same horizontal height as a metal component selected from the package-side bump structures, the redistributed interconnect structures, and the die-side bump structures. The stress-relief circuit structure comprises materials different from those used in metal components.

[0154] In some embodiments, the dielectric material layer includes a grain-side dielectric material layer, each of the grain-side bump structures includes a horizontal surface contacting the horizontal surface of the grain-side dielectric material layer, and a stress-reducing circuit structure contacts the horizontal surface of the grain-side dielectric material layer. The stress-reducing circuit structure has a different material composition or a different thickness than the grain-side bump structure. In some embodiments, the dielectric material layer includes a package-side dielectric material layer, with a package-side bump structure and a stress-reducing circuit structure embedded within the package-side dielectric material layer. The horizontal surface of the package-side bump structure and the horizontal surface of the stress-reducing circuit structure, which do not contact the dielectric material layer or the redistributed interconnect structure, are located in the same horizontal plane, and the stress-reducing circuit structure has a different material composition or a different thickness than the package-side bump structure. In some embodiments, the stress-reducing circuit structure is embedded within the dielectric material layer and located between a first horizontal plane and a second horizontal plane. The first horizontal plane includes the interface between the package-side bump structure and a first subset of the redistributed interconnect structure, and the second horizontal plane includes the interface between the grain-side bump structure and a second subset of the redistributed interconnect structure. The stress-reducing circuit structure has a different material composition than the redistributed interconnect structure.

[0155] According to other embodiments of this disclosure, a method for forming an organic interposer is provided. The method includes forming a plurality of package-side bump structures embedded within a package-side dielectric material layer over a carrier substrate. The method also includes forming a plurality of interconnect-level dielectric material layers and a plurality of redistributed interconnect structures over the package-side bump structures. The method further includes forming a die-side dielectric material layer over the interconnect-level dielectric material layer. The method also includes forming a plurality of die-side bump structures over the die-side dielectric material layer. The die-side bump structures include a plurality of first die-side bump structures located in a first region and a plurality of second die-side bump structures located in a second region. In a plan view, the second region is laterally spaced from the first region by a gap region, in which no die-side bump structures are present. Furthermore, the method includes forming a plurality of stress-reducing circuit structures within or above one of the package-side dielectric material layer, the interconnect-level dielectric material layer, or the die-side dielectric material layer within the gap region in a plan view. Each of the stress-relief circuit structures includes a plurality of straight segments extending laterally along their respective horizontal directions, and the stress-relief circuit structure has at least one of the following features: the stress-relief circuit structure is not electrically connected to the redistributed interconnect structure; and the stress-relief circuit structure is located at the same horizontal height as the package-side bump structure or the die-side bump structure.

[0156] In some embodiments, the stress-reducing circuit structure comprises the same material and is located at the same horizontal level as one of the package-side bump structure, redistributed interconnect structure, and grain-side bump structure. In some embodiments, the stress-reducing circuit structure is located at the same horizontal level as a metal component selected from the group consisting of package-side bump structure, redistributed interconnect structure, and grain-side bump structure, and the stress-reducing circuit structure comprises a different material from the metal component. In some embodiments, the Young's modulus of the material of the stress-reducing circuit structure is smaller than the Young's modulus of the metal component. In some embodiments, the stress-reducing circuit structure is formed by the following steps: depositing a preform material layer over a carrier substrate, a package-side dielectric material layer, an interconnect-level dielectric material layer, or a grain-side dielectric material layer; applying a photoresist layer over the preform material layer and patterning the photoresist layer; and transferring the pattern in the photoresist layer to the preform material layer. The patterned portion of the preform material layer includes the stress-reducing circuit structure, and each of the stress-reducing circuit structures includes a set of parallel straight line segments.

[0157] The foregoing outlines features of numerous embodiments, enabling those skilled in the art to better understand this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from its inventive spirit and scope.

Claims

1. An organic interposer, comprising: a plurality of dielectric material layers embedding a plurality of redistribution interconnect structures; a plurality of package-side bump structures on a first side of the dielectric material layers and connected to a package-side subset of the redistribution interconnect structures; a plurality of die-side bump structures on a second side of the dielectric material layers and connected to a die-side subset of the redistribution interconnect structures, wherein the die-side bump structures comprise a plurality of first die-side bump structures in a first area and a plurality of second die-side bump structures in a second area laterally spaced apart from the first area by a gap area in a plan view in which no die-side bump structures are present; and a plurality of stress mitigation line structures on or in the dielectric material layers in a range of the gap area in the plan view, wherein the stress mitigation line structures comprise a same material and are at a same horizontal level as one of the package-side bump structures, the redistribution interconnect structures, and the die-side bump structures, wherein: the dielectric material layers comprise a die-side dielectric material layer; the die-side bump structures each comprise a horizontal plane in contact with a horizontal plane of the die-side dielectric material layer; the stress mitigation line structures are in contact with the horizontal plane of the die-side dielectric material layer; and the stress mitigation line structures have a same material composition and a same thickness as the die-side bump structures.

2. The organic interposer of claim 1, wherein, each of the stress mitigation line structures in the range of the gap area in the plan view comprises a plurality of straight segment portions extending laterally along respective, different horizontal directions and is not electrically connected to the redistribution interconnect structures.

3. The organic interposer of claim 1, wherein, each of the stress mitigation line structures comprises: a plurality of first straight segment portions extending laterally along a first horizontal direction; and a plurality of second straight segment portions extending laterally along a second horizontal direction different from the first horizontal direction.

4. The organic interposer of claim 3, wherein, side walls of the first straight segment portions and side walls of the second straight segment portions of each of the stress mitigation line structures are adjoined to each other by a plurality of vertical edges.

5. The organic interposer of claim 2, wherein, the straight segment portions are connected to each other by a plurality of curved segment portions having curved side walls.

6. The organic interposer of claim 1, wherein: the stress mitigation line structures comprise a plurality of first stress mitigation line structures extending laterally along a first horizontal direction and a plurality of second stress mitigation line structures extending laterally along a second horizontal direction; and the stress mitigation line structures are arranged as an interconnect mesh in which the first stress mitigation line structures and the second stress mitigation line structures are adjoined in a grid pattern.

7. The organic interposer of claim 1, wherein: the dielectric material layers comprise a package-side dielectric material layer embedding the package-side bump structures and the stress mitigation line structures; the organic interposer comprises a plurality of additional stress mitigation line structures having horizontal planes not in contact with the dielectric material layers or the redistribution interconnect structures; and and a horizontal plane of the package-side bump structures and the stress mitigation line structures are located in a same horizontal plane.

8. The organic interposer of claim 7, wherein, the stress mitigation line structures have a same material composition and a same thickness as the package-side bump structures.

9. The organic interposer of claim 1, wherein, a plurality of additional stress mitigation line structures are embedded within the dielectric material layers and are located between a first horizontal plane comprising an interface between the package-side bump structures and a first subset of the redistribution interconnect structures and a second horizontal plane comprising an interface between the die-side bump structures and a second subset of the redistribution interconnect structures.

10. The organic interposer of claim 9, wherein, the stress mitigation line structures have a same material composition and a same thickness as a subset of the redistribution interconnect structures that is different from or the same as one of the first subset and the second subset.

11. An organic interposer, comprising: a plurality of dielectric material layers embedding a plurality of redistribution interconnect structures; a plurality of package-side bump structures located on a first side of the dielectric material layers and connected to a package-side subset of the redistribution interconnect structures; a plurality of die-side bump structures located on a second side of the dielectric material layers and connected to a die-side subset of the redistribution interconnect structures, wherein the die-side bump structures include a plurality of first die-side bump structures located in a first region and a plurality of second die-side bump structures located in a second region laterally spaced apart from the first region by a gap region in which there are no die-side bump structures in a plan view; and a plurality of stress mitigation line structures located on or within the dielectric material layers in a range of the gap region in the plan view, wherein: the stress mitigation line structures are located at a same horizontal level as a metal component selected from the package-side bump structures, the redistribution interconnect structures, and the die-side bump structures; the stress mitigation line structures comprise a different material than the metal component; the dielectric material layers comprise a package-side dielectric material layer embedding the package-side bump structures and the stress mitigation line structures; a horizontal plane of the package-side bump structures and the stress mitigation line structures not in contact with the dielectric material layers or the redistribution interconnect structures are located in a same horizontal plane; and the stress mitigation line structures have a different material composition or a different thickness than the package-side bump structures.

12. The organic interposer of claim 11, wherein: the dielectric material layers comprise a die-side dielectric material layer; the die-side bump structures each comprise a horizontal plane in contact with a horizontal plane of the die-side dielectric material layer; a plurality of additional stress mitigation line structures are in contact with the horizontal plane of the die-side dielectric material layer; and the additional stress mitigation line structures have a different material composition or a different thickness than the die-side bump structures.

13. The organic interposer of claim 11, wherein: the organic interposer comprises a plurality of additional stress mitigation line structures; the additional stress mitigation line structures are embedded within the dielectric material layers and are located between a first horizontal plane comprising interfaces between the package side bump structures and a first subset of the redistribution interconnect structures and a second horizontal plane comprising interfaces between the die side bump structures and a second subset of the redistribution interconnect structures; and the additional stress mitigation line structures have a different material composition than the redistribution interconnect structures.

14. A method of forming an organic interposer, comprising: forming a plurality of package side bump structures embedded within a package side dielectric material layer over a carrier substrate; forming a plurality of interconnect level dielectric material layers and a plurality of redistribution interconnect structures over the package side bump structures; forming a die side dielectric material layer over the interconnect level dielectric material layers; forming a plurality of die side bump structures over the die side dielectric material layer, wherein the die side bump structures comprise a plurality of first die side bump structures located in a first region and a plurality of second die side bump structures located in a second region laterally spaced apart from the first region by a gap region in a plan view in which there are no die side bump structures; forming a plurality of stress mitigation line structures within or over one of the package side dielectric material layer, the interconnect level dielectric material layers, or the die side dielectric material layer in a range of the gap region in the plan view, wherein each of the stress mitigation line structures located in the range of the gap region in the plan view comprises a plurality of straight segment portions extending laterally along respective, different horizontal directions, and the stress mitigation line structures have at least one feature selected from the following: the stress mitigation line structures are not electrically connected to the redistribution interconnect structures; and the stress mitigation line structures are located at a same horizontal level as the package side bump structures or the die side bump structures.

15. The method of forming an organic interposer of claim 14, wherein, the stress mitigation line structures comprise a same material and are located at a same horizontal level as one of the package side bump structures, the redistribution interconnect structures, and the die side bump structures.

16. The method of forming an organic interposer of claim 14, wherein, the stress mitigation line structures are located at a same horizontal level as a metal component selected from: the package side bump structures; the redistribution interconnect structures; and the die side bump structures, and the stress mitigation line structures comprise a different material than the metal component.

17. The method of forming an organic interposer of claim 16, wherein, a Young's modulus of a material of the stress mitigation line structures is less than a Young's modulus of the metal component.

18. The method of forming an organic interposer of claim 14, wherein, the stress mitigation line structures are formed by: depositing a green material layer over the carrier substrate, the package side dielectric material layer, the interconnect level dielectric material layers, or the die side dielectric material layer; applying a photoresist layer over the green material layer and patterning the photoresist layer; and transferring the pattern in the photoresist layer to the green material layer, wherein: the patterned portions of the green material layer comprise the stress mitigation line structures; and each of the stress mitigation line structures respectively comprises a set of straight segment portions parallel to each other. ​ ​

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