Devices and Systems with Ball Grid Arrays and Associated Microelectronic Devices and Device Packages

Abstract

This application relates to devices and systems having ball grid arrays and associated microelectronic devices and device packages. A device such as a semiconductor device package may include, for example, a device substrate that includes semiconductor material and bonding pads coupled to an active surface of the device substrate. A package substrate may be secured to the device substrate and configured to route signals to / from the bonding pads. A ball grid array may be supported on and electrically connected to the package substrate. Each ball of the ball grid array that is positioned and configured to carry a clock signal or a strobe signal may be located in a center column of the ball grid array.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of the priority date of U.S. Provisional Patent Application No. 63 / 069,865, filed Aug. 25, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to techniques for configuring ball grid arrays of semiconductor device packages. More specifically, the disclosed embodiments relate to ball grid arrays and signal routing between associated ball grid arrays and connected semiconductor devices, embodiments of which can improve signal quality, reduce crosstalk, support higher speed data transfer, and improve power distribution and delivery. Background Art

[0004] An important purpose of packaging a semiconductor device (e.g., a semiconductor die) is to connect the device to a higher-level package of an electronic system. One aspect of packaging is to convert signals from relatively small features of the die (e.g., bond pads or re-wired bond pads) to larger and more widely spaced connection locations of the next higher-level package (e.g., a circuit board). A favorable packaging configuration is the so-called ball grid array (BGA) package, in which conductive traces extend from locations on one major surface of a package substrate that is arranged and spaced to connect to closely spaced multiple rows of bond pads of a die (positioned in a generally centrally located row on the major surface of the package substrate) to an array of discrete conductive elements, which typically exist in the form of solder bumps or solder balls, arranged in rows and columns and at a larger pitch (i.e., center-to-center spacing) on the opposite major surface of the package substrate. A robust coupling between the device and the higher-level package of the system is crucial, especially at higher signal speeds.

[0005] Internal die-level signal optimization for various performance aspects such as power, latency, and internal jitter reduction can depend on die bond pad order to minimize data path and clock tree lengths, deliver sufficient power to the circuit through an appropriate number of interleaved power and ground connections, and / or minimize the overall die size to reduce cost. However, the ball pattern and pitch of the BGA, or the definition of "balls", are typically specified by industry-wide (i.e., JEDEC) standards and take into account the applications in which the microelectronic device package is expected to operate. Thus, the opportunity for performance optimization in the signal path of the package substrate is limited. As signal speeds increase with increasing bandwidth, higher clock speeds, and reduced ball pitch, the problem of signal crosstalk due to signal coupling between adjacent balls is exacerbated. In a specific example, increasing the memory capacity and operating speed of double data rate (DDR) dynamic random access memory (DRAM) in the form of synchronous DRAM (SDRAM) and graphics double data rate (GDDR) DRAM presents challenges in this regard. SUMMARY OF THE INVENTION

[0006] In some embodiments, a device (e.g., a semiconductor device package) in accordance with the present disclosure can include, for example, a device substrate that includes a semiconductor material and bond pads coupled to an active surface of the device substrate facing a package substrate. The package substrate can be fixed to the device substrate and is configured to route signals to / from the bond pads. A ball grid array can be supported on and electrically connected to the package substrate. Each ball of the ball grid array that is positioned and configured to carry a clock signal or a strobe signal can be located in a center column of the ball grid array.

[0007] In other embodiments, a device in accordance with the present disclosure can include a first memory device and a second memory device. The first memory device can include a device substrate that includes a semiconductor material and bond pads coupled to an active surface of the device substrate. The package substrate can be fixed to the device substrate and is configured to route signals to / from the bond pads. A ball grid array can be supported on and electrically connected to the package substrate. A printed circuit board can be inserted between the first memory device and the second memory device and fixed to each of them. Each ball of the ball grid array of the first memory device that is positioned and configured to carry a clock signal or a strobe signal can be located in a center column of the ball grid array.

[0008] In other embodiments, a system in accordance with the present disclosure may include a central processing unit (CPU) and at least one memory device coupled to the CPU. The one or more memory devices may include a device substrate that includes semiconductor material and bonding pads coupled to an active surface of the device substrate. A package substrate may be secured to the device substrate and configured to route signals to / from the bonding pads. A ball grid array may be supported on and electrically connected to the package substrate. Each ball of the ball grid array that is positioned and configured to carry a clock signal or a strobe signal may be located in a center column of the ball grid array.

[0009] In other embodiments, a device may include a first memory device that includes a device substrate that includes semiconductor material and bonding pads coupled to an active surface of the device substrate. A package substrate may be secured to the device substrate, and the device substrate may be secured to the package substrate by direct chip attach. The package substrate may be configured to route signals to / from the bonding pads. A first ball grid array may be supported on and electrically connected to the package substrate. A second memory device may include a second ball grid array. A printed circuit board may be inserted between the first ball grid array of the first memory device and the second ball grid array of the second memory device and secured to each of them, and the second ball grid array of the second memory device may be rotationally symmetric across the printed circuit board relative to the first ball grid array of the first memory device. Each ball of the ball grid array of the first memory device that is positioned and configured to carry a clock signal or a strobe signal may be located in a center column of the ball grid array. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Although the present disclosure is summarized using claims directed to particular embodiments that are specifically recited and claimed, various features and advantages of embodiments within the scope of the present disclosure may be more readily determined from the following description when read in conjunction with the drawings, in which:

[0011] Figure 1 is a schematic diagram of a ball grid array in accordance with the present disclosure;

[0012] Figure 2 is a schematic diagram of another embodiment of a ball grid array in accordance with the present disclosure;

[0013] Figure 3 is a schematic diagram of a ball grid array at the current state of the art known to the inventors;

[0014] Figure 4 is a schematic cross-sectional side view of a semiconductor device package that includes a ball grid array in accordance with the present disclosure;

[0015] Figure 5 is a schematic cross-sectional side view of a semiconductor device package at the current state of the art known to the inventors;

[0016] Figure 6is a schematic cross-sectional side view of an assembly of a semiconductor device package including a ball grid array in accordance with the present disclosure;

[0017] Figure 7 is a schematic cross-sectional side view of an assembly of the current state of the art of semiconductor device packages known to the present inventors;

[0018] Figure 8 is a schematic cross-sectional side view of another embodiment of a semiconductor device package including a ball grid array in accordance with the present disclosure;

[0019] Figure 9 is a schematic cross-sectional side view of another embodiment of a semiconductor device package including a ball grid array in accordance with the present disclosure; and

[0020] Figure 10 is a block diagram of an electronic system incorporating a memory configured as a BGA package in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The disclosed embodiments generally relate to ball grid arrays and signal routing between associated ball grid arrays and connected semiconductor devices, and embodiments thereof may improve signal quality, reduce crosstalk, support higher speed data transfer, and improve power distribution and delivery. More specifically, embodiments of ball grid arrays and signal routing between associated ball grid arrays and associated semiconductor devices are disclosed, where the semiconductor devices may locate balls of the ball grid array configured to carry clock signals or strobe signals in a center column of the ball grid array. For example, the ball grid array may be at least substantially reflection symmetric across the center column of the ball grid array, and those balls configured to carry clock signals or strobe signals may be located within the center column.

[0022] In some embodiments, a ball grid array in accordance with the present disclosure may locate those balls of the ball grid array configured to carry clock signals or strobe signals away from the perimeter of the ball grid array. For example, there may be no balls of the ball grid array configured to carry clock signals or strobe signals at the perimeter of the ball grid array, and all balls of the ball grid array located at the perimeter of the ball grid array may be configured to carry signals other than clock signals and strobe signals, reference voltages, or connections to ground. More specifically, at least one ball (e.g., at least one row) may be inserted between any ball at the perimeter of the ball grid array and the nearest ball configured to carry a clock signal or strobe signal.

[0023] In some embodiments, the ball grid array according to the present disclosure may position those balls of the ball grid array configured to carry clock signals or strobe signals away from those balls configured to carry data signals. Additionally, those balls configured to carry data signals may be positioned to reduce (e.g., eliminate) the proximity between the corresponding balls configured to carry data signals. For example, at least one ball (e.g., at least one column) may be inserted between any ball configured to carry a clock signal or a strobe signal and the nearest ball configured to carry a data signal. As another example, those balls of the ball grid array positioned and configured to carry data signals may be positioned to be diagonally adjacent only to any other directly adjacent balls configured to carry another data signal. More precisely, those balls of the ball grid array positioned and configured to carry data signals may be positioned to be diagonally adjacent to no more than two other directly adjacent balls configured to carry another data signal.

[0024] As used herein, the terms “substantially” and “about” when referring to a given parameter, property, or condition mean and include the degree to which the given parameter, property, or condition is understood by one of ordinary skill in the art to satisfy a degree of difference (e.g., within acceptable manufacturing tolerances). For example, a parameter that is substantially or about a specified value may be at least about 90% of the specified value, at least about 95% of the specified value, at least about 99% of the specified value, or even at least about 99.9% of the specified value.

[0025] The terms “memory” and “memory device” as used herein include, but are not limited to, microelectronic devices that present a memory function, but do not include embodiments that cover transient signals. For example, a system-on-chip (SoC) is covered in the sense of a memory device. By way of non-limiting example, as described herein, unless otherwise specified, a memory device generally may include a packaged semiconductor device having a ball grid array and a signal routing configuration.

[0026] The term “ball” as used herein in connection with a ball grid array (or other arrayed electrical interconnection) means and includes discrete masses and structures of conductive material positioned and configured in an array to connect a semiconductor device package to other devices, components, and structures (e.g., an inserter, a printed circuit board, etc.) of an electrical system. For example, the term “ball” includes solder balls or solder joints and other discrete conductive elements, including but not limited to (e.g., metal) posts, studs, columns, bolts, or other shapes for the foregoing purposes.

[0027] As used herein in connection with the balls of a ball grid array, the terms "lateral proximity" and "longitudinal proximity" respectively denote and include the balls that are located directly to the left, right, above, or below a given ball when the ball grid array is parallel to the drawing plane and the geometric centers of the balls in the ball grid array are at least substantially aligned in a common horizontal or vertical plane. For example, the balls in a ball grid array having balls with lateral and longitudinal proximity can be combined to form at least a substantially cross or plus sign within at least a substantially square rhombus using lines connecting the geometric centers of the respective balls. Balls, pads, or components with lateral proximity or longitudinal proximity may also be referred to as adjacent, contiguous, side-by-side, or abutting each other because they may each have a side, edge, or point that is adjacent, contiguous, side-by-side, or abutting another ball, pad, or component, with no other such components therebetween.

[0028] As used herein in connection with a ball grid array, the term "diagonal proximity" denotes and includes the balls that are located directly above and to the right, above and to the left, below and to the right, and below and to the left of a given ball when the BGA is parallel to the drawing plane and the geometric centers of the balls in the ball grid array are at least substantially aligned in a common oblique (i.e., diagonal) plane. For example, the balls in a ball grid array having balls that are diagonally proximate to a given ball in all directions can be combined to form at least a substantially "X" shape within at least a substantially square using lines connecting the geometric centers of the respective balls. Balls, pads, or components with diagonal proximity may also be referred to as adjacent, contiguous, side-by-side, or abutting each other because they may each have a point that is adjacent, contiguous, side-by-side, or abutting another ball, pad, or component, with no other such components therebetween.

[0029] As used herein in connection with a ball grid array, the term "surrounding" denotes and includes the balls that are laterally, longitudinally, and diagonally proximate to a given ball when the BGA is parallel to the drawing plane and the geometric centers of the balls in the ball grid array are at least substantially aligned in a common vertical, horizontal, and diagonal plane. For example, the balls surrounding other balls in a ball grid array can together form a three-by-three square matrix using lines connecting the geometric centers of the respective balls.

[0030] The illustrations presented in this disclosure are not meant to be actual views of any particular semiconductor device package, ball grid array, or its components, but are merely idealized representations for describing illustrative embodiments. Accordingly, the drawings are not necessarily to scale.

[0031] Figure 1FIG. 0 is a schematic diagram of a ball grid array 100 in accordance with the present disclosure, including markings of signals carried by respective balls 102. Each field in the schematic diagram may represent the position of a single ball 102 and the associated signals to be input and / or output via the balls 102 in the ball grid array 100. Each ball 102 of the ball grid array 100 that is positioned and configured to carry a clock signal (CK) or a strobe signal (DQS) may be located in the center column 104 of the ball grid array 100. For example, the ball grid array 100 may include an odd number of columns (e.g., nine), and the center column 104 in which those balls 102 configured to carry a clock signal (CK) or a strobe signal (DQS) are located may have an equal number of columns on each lateral side of the center column 104.

[0032] In some embodiments, each ball 102 of the ball grid array 100 that is positioned and configured to carry a clock signal (CK) or a strobe signal (DQS) may be laterally and longitudinally spaced from the closest ball 102 of the ball grid array 100 that is positioned and configured to carry a data signal (DQ or CA) by at least one column of the ball grid array 100. For example, at least one ball 102 of the ball grid array 100 configured to carry a reference voltage or connected to ground (VSS) may be laterally inserted between each ball 102 configured to carry a clock signal (CK) or a strobe signal (DQS) and the closest ball 102 configured to carry a data signal (DQ or CA). More precisely, each ball 102 configured to carry a data signal (DQ or CA) may be located in a column of the ball grid array 100 that is spaced from the center column 104 by at least one other column.

[0033] Each ball 102 of the ball grid array 100 that is positioned and configured to carry a clock signal (CK) or a strobe signal (DQS) may be spaced from the perimeter of the ball grid array 100 by at least one row, for example. More precisely, at least one other ball 102 of the ball grid array 100 configured to carry a signal other than a clock signal (CK), a strobe signal (DQS), or a data signal (DQ or CA) (e.g., other signal symbols) may be inserted, for example, between a given ball 102 configured to carry a clock signal (CK) or a strobe signal (DQS) and the closest ball 102 at the outer perimeter of the ball grid array 100. As a specific non-limiting example, at least one other ball 102 of the ball grid array 100 configured to carry a signal other than a clock signal (CK), a strobe signal (DQS), or a data signal (DQ or CA) may be inserted between a given ball 102 configured to carry a clock signal (CK) or a strobe signal (DQS) and the closest ball 102 at the longitudinal end of the center column 104 of the ball grid array 100.

[0034] Figure 1The ball grid array 100 shown may be at least substantially symmetric across the center column 104. For example, in the columns of the non-center columns 104 of the ball grid array 100, about 15% or less of the balls 102 of the ball grid array 100 may be different from the corresponding balls 102 of the ball grid array 100 in the positions reflected across the center column 104. More precisely, about 5% to about 10% (e.g., about 7%, about 8%) of the balls 102 of the ball grid array 100 in the columns of the non-center columns 104 of the ball grid array 100 may be different from the corresponding balls 102 of the ball grid array 100 in the positions mirror-imaged across the center column 104.

[0035] In some embodiments, each ball 102 of the ball grid array 100 that is positioned and configured to carry data signals (DQ or CA) may be positioned to be diagonally adjacent only to any other directly adjacent ball 102 of the ball grid array 100 that is positioned and configured to carry data signals (DQ or CA). For example, each ball 102 of the ball grid array 100 that is positioned and configured to carry data signals (DQ or CA) may be positioned to be diagonally adjacent only to no more than three other directly adjacent balls 102 of the ball grid array 100 that are positioned and configured to carry another data signal (DQ or CA). More precisely, each ball 102 of the ball grid array 100 that is positioned and configured to carry data signals (DQ or CA) may be positioned to be diagonally adjacent only to no more than two (e.g., zero, one, two) other directly adjacent balls 102 of the ball grid array 100 that are positioned and configured to carry another data signal (DQ or CA).

[0036] The periphery of the ball grid array 100 may, for example, be at least substantially free of balls 102 that are positioned and configured to carry data signals (DQ or CA). In other words, each ball 102 of the ball grid array 100 that is positioned and configured to carry data signals (DQ or CA) may be located within the interior of the periphery of the ball grid array 100. For example, at least one other ball 102 of the ball grid array 100 that is configured to carry a signal other than a clock signal (CK), a strobe signal (DQS), or a data signal (DQ or CA) (e.g., configured to be connected to a reference voltage or ground (VSS)) may be longitudinally positioned outward (e.g., closer to the outside of the ball grid array 100 relative to the given ball) from a given ball 102 that is positioned and configured to carry data signals (DQ or CA). As another example, at least one other ball 102 of the ball grid array 100 that is configured to carry a signal other than a clock signal (CK), a strobe signal (DQS), or a data signal (DQ or CA) (e.g., configured to be connected to a reference voltage or ground (VSS)) may be laterally positioned outward (e.g., closer to the outside of the ball grid array 100 relative to the given ball) from a given ball 102 that is positioned and configured to carry data signals (DQ or CA).

[0037] Positioning those balls 102 of the ball grid array 100 configured to carry data signals (DQ or CA) to be diagonally adjacent to any other directly adjacent balls 102 positioned and configured to carry data signals (DQ or CA) and maintaining the perimeter of the ball grid array 100 to be at least substantially free of balls 102 positioned and configured to carry data signals (DQ or CA) can improve signal quality. For example, such positioning and layout of the balls 102 positioned and configured to carry data signals (DQ or CA) can reduce the overlap intensity and extent among the magnetic fields induced by the signals carried by the balls 102 positioned and configured to carry data signals (DQ or CA). This reduction in the induced magnetic fields can cause crosstalk to be correspondingly reduced, thereby resulting in higher signal quality and fidelity. The improvement in signal quality and fidelity can be particularly significant when the signals carried by those balls 102 positioned and configured to carry data signals (DQ or CA) are high-frequency signals (i.e., signals operating at frequencies between about 10 GHz and about 45 GHz or possibly higher frequencies) and / or high-bandwidth signals (i.e., signals capable of transmitting data at baud rates between about 15 gigasymbols per second and about 20 gigasymbols per second or possibly higher baud rates).

[0038] In some embodiments, each ball 102 of the ball grid array 100 positioned to be laterally and longitudinally adjacent to every other ball 102 of the ball grid array 100 positioned and configured to carry data signals (DQ or CA) can be configured to carry a voltage (VDD, VDDQ, VDDLL), connected to ground (VSS), or connected to a calibration circuit (ZQ). For example, about 75% to about 90% of the balls 102 around a given ball 102 positioned and configured to carry data signals (DQ or CA) can themselves be positioned and configured to carry a voltage (VDD, VDDQ, VDDLL), connected to ground (VSS), or connected to a calibration circuit (ZQ). More precisely, about 6 to about 7 balls 102 around a given ball 102 positioned and configured to carry data signals (DQ or CA) can themselves be positioned and configured to, for example, carry a voltage (VDD, VDDQ, VDDLL), connected to ground (VSS), or connected to a calibration circuit (ZQ).

[0039] Figure 1The number of balls 102 in the ball grid array 100 shown and configured to carry data signals (DQ or CA) can be about one - eighth to about one - quarter of the number of balls 102 in the ball grid array 100 positioned and configured to carry voltage or connected to ground (VSS, VSSDLL, VDD, VDDQ, VDDLL, VPP). For example, the number of balls 102 of the ball grid array 100 positioned and configured to carry data signals (DQ or CA) can be between about 12 and about 20 (e.g., about 16). Continuing the example, the number of balls 102 of the ball grid array 100 positioned and configured to carry voltage or connected to ground (VSS, VSSDLL, VDD, VDDQ, VDDLL, VPP) can be between about 80 and about 90 (e.g., about 86).

[0040] In some embodiments, the number of balls 102 of the ball grid array positioned and configured to carry data signals (DQ or CA) can be about one - quarter to about one - half of the number of balls 102 of the ball grid array 100 positioned and configured to be connected to the core system voltage (VSS) or the core system ground (VSS). For example, the number of balls 102 of the ball grid array 100 positioned and configured to carry data signals (DQ or CA) can be between about 12 and about 20 (e.g., about 16). Continuing the example, the number of balls 102 of the ball grid array 100 positioned and configured to be connected to the core system voltage (VSS) or the core system ground (VSS) can be between about 40 and about 55 (e.g., about 45, about 52).

[0041] The number of balls 102 of the ball grid array 100 positioned and configured to carry data signals (DQ or CA) can be about two - fifths to about nine - tenths of the number of balls 102 of the ball grid array 100 positioned and configured to be connected to the input / output memory supply voltage (VDD). For example, the number of balls 102 of the ball grid array 100 positioned and configured to carry data signals (DQ or CA) can be between about 12 and about 20 (e.g., about 16). Continuing the example, the number of balls 102 of the ball grid array 100 positioned and configured to be connected to the input / output memory supply voltage (VDD) can be between about 15 and about 25 (e.g., about 18, about 21).

[0042] In some embodiments, the number of balls 102 of ball grid array 100 that are positioned and configured to carry data signals (DQ or CA) may be approximately equal to the number of balls 102 of ball grid array 100 that are positioned and configured to connect to the output driver voltage (VDDQ). For example, the number of balls 102 of ball grid array 100 that are positioned and configured to carry data signals (DQ or CA) may be between approximately 12 and 20 (e.g., approximately 16). Continuing the example, the number of balls 102 of ball grid array 100 that are positioned and configured to connect to the output driver voltage (VDDQ) may be between approximately 12 and 20 (e.g., approximately 16).

[0043] Figure 1 The number of balls 102 of the illustrated ball grid array 100 that are positioned and configured to carry data signals (DQ or CA) may be from approximately four times to approximately eight times the number of balls 102 of ball grid array 100 that are positioned and configured to connect to the word line voltage (VPP). For example, the number of balls 102 of ball grid array 100 that are positioned and configured to carry data signals (DQ or CA) may be between approximately 12 and 20 (e.g., approximately 16). Continuing the example, the number of balls 102 of ball grid array 100 that are positioned and configured to connect to the word line voltage (VPP) may be between approximately 2 and 4 (e.g., approximately 4).

[0044] In some embodiments, the total number of balls 102 in ball grid array 100 may be between approximately 100 and 150. For example, the total number of balls 102 in ball grid array 100 may be between approximately 115 and 120 (e.g., approximately 117).

[0045] Figure 2 is a schematic diagram of another embodiment of ball grid array 200 according to the present disclosure. Figure 2 The ball grid array 200 of may exhibit many of the same or similar features as Figure 1 the ball grid array 100 of. For example, each ball 102 of ball grid array 100 that is positioned and configured to carry a clock signal (CK) or a strobe signal (DQS) may be located in the central column 104 of ball grid array 100. Each ball 102 of ball grid array 200 that is positioned and configured to carry a clock signal (CK) or a strobe signal (DQS) may also be laterally and longitudinally spaced apart from the closest ball 102 of ball grid array 100 that is positioned and configured to carry data signals (DQ or CA) by at least one column of ball grid array 200. Each ball 102 of ball grid array 200 that is positioned and configured to carry a clock signal (CK) or a strobe signal (DQS) may be spaced apart from the perimeter of ball grid array 200 by at least one row, for example. Figure 2The ball grid array 200 shown may be at least substantially reflection symmetric across the central column 104. Each ball 102 of the ball grid array 200 that is positioned and configured to carry data signals (DQ or CA) may be positioned to be diagonally adjacent only to any other directly adjacent ball 102 of the ball grid array 100 that is positioned and configured to carry data signals (DQ or CA). The perimeter of the ball grid array 200 may be, for example, at least substantially free of balls 102 that are positioned and configured to carry data signals (DQ or CA). Each ball 102 of the ball grid array 200 that is positioned laterally and longitudinally adjacent to every other ball 102 of the ball grid array 200 that is positioned and configured to carry data signals (DQ or CA) may be configured to carry a voltage or be connected to ground (VDD, VDDQ, VSS).

[0046] Figure 1 between the ball grid array 100 and Figure 2 a significant difference between the ball grid array 200 is that Figure 2 the balls 102 shown configured to carry control signals (CS) may be in the same central column 104 as the balls 102 respectively configured to carry clock signals (CK) or strobe signals (DQS), rather than in adjacent columns, as Figure 1 shown in. This configuration may further increase the reflection symmetry of the ball grid array 200 across the central column 104. To reduce crosstalk, the balls 102 configured to carry control signals (CS) may not be positioned longitudinally or laterally adjacent to any of the balls 102 configured to carry clock signals (CK) or strobe signals (DQS), as in Figure 1 and Figure 2 shown in. More precisely, at least one ball 102 (e.g., at least one row) of the ball grid array 200 may be inserted, for example, between the balls 102 configured to carry control signals (CS) and each closest ball 102 configured to carry clock signals (CK) or strobe signals (DQS), as Figure 2 shown in.

[0047] Figure 1 between the ball grid array 100 and Figure 2 another significant difference between the ball grid array 200 is that the balls 102 configured to be connected to the calibration circuit (ZQ) may be in different portions of the perimeter of the ball grid array 200. For example, the balls 102 configured to be connected to the Figure 2 calibration circuit (ZQ) shown in may be in the top row (row A) of the ball grid array 200 (when oriented as Figure 2 shown in), while the balls 102 configured to be connected to the Figure 1 calibration circuit (ZQ) shown in may be in the rightmost column (column 9) of the ball grid array 100 (when oriented as Figure 1 shown in).

[0048] Another notable difference is thatFigure 1 and Figure 2 the number of balls 102 configured to carry voltage or connected to ground (VSS, VDD, VPP) between and the presence of balls 102 configured to carry certain specific reference voltages (VSSDLL) can be different, while Figure 1 the ball grid array 100 of Figure 2 and other differences between the ball grid array 200 of will be obvious to those skilled in the art. For example, Figure 2 the number of balls 102 configured to be connected to the core system voltage (VSS) or the core system ground (VSS) in can be about seven more balls 102 than in Figure 1 . Figure 2 the number of balls 102 configured to be connected to the input / output memory supply voltage (VDD) in can be about three fewer balls 102 than in Figure 1 . Figure 2 the number of balls 102 configured to be connected to the word line voltage (VPP) in can be about two fewer balls 102 than in Figure 1 . Finally, Figure 2 the number of balls 102 configured to be connected to certain specific reference voltages (VSSDLL) in can be about two fewer balls 102 than in Figure 1 .

[0049] In some embodiments, the specific layout of the clock signal (CK) and / or the strobe signal (DQS) in the center column 104 of a given ball grid array can be different from Figure 1 and 2 the layout shown in. For example, one or more balls 102 positioned and configured to carry the clock signal (CK) can be configured to carry or one or more balls 102 positioned and configured to carry the strobe signal (DQS) can be modified to carry the write clock (WCK) signal or the read clock (RCK) signal. More precisely, Figure 1 and 2 a pair of balls 102 shown in as being positioned and configured to carry the strobe signal (DQS) can be respectively replaced, for example, by balls 102 positioned and configured to carry the write clock (WCK) and the read clock (RCK) signals.

[0050] Figure 3 is a schematic diagram of a ball grid array 300 at the current state of the art known to the inventor. As Figure 3 shown, the ball grid array 300 may not be Figure 1 the ball grid array 100 of Figure 2 and the ball grid array 200 of symmetric. For example, Figure 3The ball grid array 300 may not have any central columns 104 around which a reflection symmetry is formed. Since clock signals (CK) and strobe signals (DQS) tend to be differential signals, it may not be practical to position the balls 102 configured to carry those signals on opposite sides of the central gap 302. Additionally, the ball grid array 300 may have fewer available columns and fewer balls 102 associated with a given signal, enabling a more compact packing of extremely important signals (such as data signals (DQ and CA)). Finally, the ball grid array 300 may have more balls 102 dedicated to carrying data signals (DQ or CA), enabling a more compact packing.

[0051] When compared with Figure 3 the ball grid array 300 of Figure 1 the ball grid array 100 of Figure 2 and the ball grid array 200 of Figure 1 the ball grid array 100 of Figure 2 and the ball grid array 200 of Figure 3 the increased symmetry and spacing between extremely important signals provided can reduce crosstalk between the balls 102, thereby improving signal quality. Additionally,

[0052] Figure 4 is a ball grid array 100 that includes Figure 1 or Figure 2Schematic cross-sectional side view of semiconductor device package 400 of ball grid array 200. Semiconductor device package 400 may include device substrate 402, which includes semiconductor material capable of forming and / or supporting an integrated circuit system. More specifically, device substrate 402 may include: an active surface 404 in which an integrated circuit system is embedded and / or supported thereon; bonding pads 406 (which may also be characterized as "die pads") on and coupled to active surface 404, which are operatively connected to the integrated circuit system and configured to provide input and output connections to the integrated circuit system; and an inactive surface 408 on the side of device substrate 402 opposite to active surface 404. As a specific non-limiting example, device substrate 402 may include: an active surface 404 having an integrated circuit system configured as a memory (e.g., double data rate (GDDR) type 5 or higher synchronous dynamic random access memory (SDRAM)); bonding pads 406 that form at least substantially centrally positioned rows on active surface 404 and away from its lateral outer periphery; and an inactive surface 408 that does not have any integrated circuit system located on the side of device substrate 402 opposite to active surface 404. In at least some embodiments, although the surface 404 that loads the integrated circuit system is characterized as an "active" surface, device substrate 402 may be an electrically passive substrate.

[0053] The encapsulation substrate 410 can be generally configured to route signals to / from the device substrate 402 and provide a more convenient connection configuration when compared to the size of the bonding pads 406 of the device substrate 402 itself. For example, the encapsulation substrate 410 can be configured as a printed circuit board (PCB), an interposer, or other structure for routing electrical signals to / from the bonding pads 406 of the device substrate 402. More specifically, the encapsulation substrate 410 can include selectively positioned regions of conductive and dielectric materials, and the conductive materials can be operatively connected and mechanically fixed to the bonding pads 406 of the device substrate 402 by conductive elements 412 (e.g., copper pillars) inserted between the encapsulation substrate 410 and the device substrate 402. As a specific non-limiting example, the encapsulation substrate 410 can include a conductive material input platform 414 that contacts the conductive elements 412 (and thus the bonding pads 406), a dielectric material layer 416, via holes 418 of conductive material that are positioned and configured to carry signals received from the device substrate 402 at the input platform 414 longitudinally through at least a portion of the thickness of the encapsulation substrate 410 (i.e., in a direction at least substantially perpendicular to the active surface 404 of the device substrate 402), traces 420 of conductive material that are positioned and configured to carry signals received from the device substrate 402 at the input platform 414 laterally along the surface of the dielectric material layer 416 (i.e., in a direction at least substantially parallel to the active surface 404 of the device substrate 402), and an output platform 424 of conductive material located on the side of the encapsulation substrate 410 opposite the device substrate 402, the output platform 424 being configured to output signals routed from the input platform 414 through the traces 420 and via holes 418 to the output platform 424. Suitable conductive materials for the traces 420, conductive elements 412, and any other conductive structures of the encapsulation substrate 410 can include, for example, aluminum, gold, copper, and alloys and combinations thereof. Suitable dielectric materials for the remainder of the encapsulation substrate 410 (e.g., layer 416) can include, for example, dielectric polymer resins.

[0054] A ball grid array 100 or 200 (or other electrical interconnection including discrete conductive elements) can be supported on and electrically connected to a side of the package substrate 410 opposite the device substrate 402. For example, the ball grid array 100 or 200 can include balls 102 of conductive material supported on and fixed to the output platform 424 of the package substrate 410, and the balls 102 can be distributed in an array to form a repeating geometric pattern. More specifically, the balls 102 of the ball grid array 100 or 200 can be positioned to form a rectangular (e.g., square) grid formed by lines interconnecting the geometric centers of adjacent balls 102, where the geometric centers of adjacent balls 102 form at least substantially the vertices of the rectangle. As a specific non-limiting example, the balls 102 of the ball grid array 100 or 200 can be distributed across the entire major surface 426 of the package substrate 410, which can be formed by a direct chip attach configuration, where the ball grid array 100 or 200 does not have a discontinuous portion that would form an open area or gap underlying the bonding pads 406 of the device substrate 402. The material of the balls 102 can include, for example, solder (e.g., tin / silver solder). In some packages, the ball grid array 100 or 200 can be located on the bottom side of the package substrate 410 and can bridge the space between the package substrate 410 and a connected device or structure (e.g., a PCB, a chip, another package substrate), as shown and discussed in more detail in conjunction with Figure 6 and described more fully.

[0055] The ball grid array 100 or 200 according to the present disclosure, including the density of the balls 102 and the shape of the ball grid array 100 or 200, can be facilitated by a direct chip attach for connecting the device substrate 402 to the package substrate 410. In such a configuration, at least the active surface 404 of the device substrate 402 closest to the package substrate 410 can face and be located near the input platform 414 on the package substrate 410. Additionally, the connection between the device substrate 402 closest to the package substrate 410 can be formed by non-line bonded conductive elements 412, such as balls, bumps, pillars, columns, posts, or other shapes that facilitate a closer proximity and a reduced conductive path length compared to wire bonding. In Figure 4 an embodiment, the semiconductor device package 400 includes a single device substrate 402 directly chip attached to the package substrate 410, which can also be referred to as a single die package (SDP) configuration. Additional direct chip attach configurations are described in more detail in conjunction with Figure 8 and Figure 9 Although the device substrate 402 shown in Figure 5 can be specifically configured as a DRAM device (e.g., SDRAM), the ball grid array 100 or 200 according to the present disclosure can be advantageously deployed with other types of memory devices or non-memory devices.

[0056] In summary, a semiconductor device package according to the present disclosure may include, for example, a device substrate that includes a semiconductor material and bonding pads coupled to an active surface of the device substrate facing the package substrate. The package substrate may be fixed to the device substrate and is configured to route signals to / from the bonding pads. A ball grid array may be supported on and electrically connected to the package substrate. Each ball of the ball grid array that is positioned and configured to carry a clock signal or a strobe signal may be located in a center column of the ball grid array.

[0057] Figure 5 is a schematic cross-sectional side view of a semiconductor device package 500 at the current state of the art known to the inventors. Specifically, Figure 5 illustrates a configuration in which wire bonds 502 extend from bonding pads 504 on an active surface 506 of a device substrate 508 through a window 510 in a package substrate 512 to an input platform 514 located on a side of the package substrate 512 opposite the device substrate 508. In such a configuration, an output platform 516 may be on the same side of the package substrate 512 as the input platform 514, and they may both be on a side of the package substrate 512 opposite the device substrate 508. As Figure 5 configured, the configuration may alternatively be referred to as a "board-on-chip" connection between the device substrate 508 and the package substrate 512.

[0058] When using a board-on-chip connection, the ball grid array 520 may include gaps 522 underlying the bonding pads 504 of the device substrate 508, where no balls 518 of the ball grid array 520 may be positioned. Because of such gaps 522, balls 518 for differential signals such as, for example, Figure 1 and 2 clock signal (CK) and strobe signal (DQS)) of may create an asymmetry with respect to balls 518 located in the same positions across the gaps 522. Thus, Figure 5 the ball grid array 520 may be asymmetric in a manner similar to the symmetric manner of the ball grid arrays 100 and 200 of Figure 1 and 2 , and these asymmetries may directly reduce signal quality and increase the probability that downstream signal routing techniques may further reduce signal quality. Thus, Figure 1 and 2 the ball grid arrays 100 and 200 may produce higher signal quality, particularly for high-speed, high-bandwidth, or high-speed and high-bandwidth data signals. Additionally, when compared to the routing complexity of accommodating corresponding centered balls 102 (see Figure 1 , 2 ), the ball grid arrays according to the present disclosure, such as Figure 1 and 2The ball grid arrays 100 and 200 can reduce the routing complexity introduced when accommodating off-center balls 518 (see Figure 1 and 2 ) configured to carry a clock signal (CK) and / or a strobe signal (DQS) in an on-board connection, such as Figure 5 as shown in

[0059] Figure 6 is a schematic cross-sectional side view of an assembly 600 of a semiconductor device package 400 that includes multiple ball grid arrays 100 each including Figure 1 or Figure 2 the ball grid array 200. The semiconductor device package 400 can be interconnected to a shared printed circuit board 602 using the ball grid array 100 or 200 of the semiconductor device package 400. More specifically, the printed circuit board 602 can be inserted between a first semiconductor device package 400 and a second semiconductor device package 400 and fixed to each of them. As a specific non-limiting example, the first semiconductor device package 400 can be located on and fixed to a first side of the printed circuit board 602 using its ball grid array 100 or 200, and the second semiconductor device package 400 can be located on and fixed to an opposite second side of the printed circuit board 602 using its ball grid array 100 or 200. The ball grid array 100 or 200 of the second semiconductor device package 400 can be rotationally symmetric about an axis centered within the printed circuit board 602 with respect to the ball grid array 100 or 200 of the first semiconductor device package 400, and the axis extends parallel to the center column 104 of the ball grid array 100 or 200. This configuration can alternatively be referred to as a "clam shell" connection of the semiconductor device package 400 to the printed circuit board 602.

[0060] The printed circuit board 602 can include electrical conductors 604 (e.g., pads, vias, traces) located within the printed circuit board 602, and the electrical conductors 604 are electrically connected to the balls 102 of the ball grid array 100 or 200 of the semiconductor device package 400. A first ball 606 of the ball grid array 100 or 200 of the first semiconductor device package 400 can be positioned and configured to carry a clock signal or a strobe signal, and a second ball 608 of the ball grid array 100 or 200 of the second semiconductor device package 400 can be similarly positioned and configured to carry a clock signal or a strobe signal. The electrical conductors 604 connected to the first ball 606 and the second ball 608 can extend at least substantially perpendicular to the main surface 610 of the printed circuit board 602 at least substantially across the entire distance between the first ball 606 and the second ball 608. This direct vertical interconnection between the first ball 606 and the second ball 608 can maintain and improve signal quality. Traces 612 can optionally extend laterally outward from the vertically extending electrical conductors 604.

[0061] Although Figure 6The assembly 600 shown may be specifically shown as a semiconductor device package 400 configured to connect to a memory device of a printed circuit board 602 configured as a dual in-line memory module (DIMM), but the ball grid arrays 100 or 200 according to the present disclosure may be advantageously deployed with other types of memory devices, non-memory devices, other types of printed circuit boards, or non-printed circuit board substrates.

[0062] In summary, an apparatus according to the present disclosure may include a first memory device and a second memory device. The first memory device may include a device substrate including a semiconductor material and bonding pads coupled to an active surface of the device substrate. A package substrate may be fixed to the device substrate and configured to route signals to / from the bonding pads. A ball grid array may be supported on and electrically connected to the package substrate. A printed circuit board may be inserted between and fixed to each of the first memory device and the second memory device. Each ball of the ball grid array of the first memory device positioned and configured to carry a clock signal or a strobe signal may be located in a center column of the ball grid array.

[0063] Figure 7 FIG. 700 is a schematic cross-sectional side view of a state-of-the-art assembly 700 of a semiconductor device package 500 known to the inventors. To interconnect the asymmetric balls 518 of the ball grid array 520, an electrical conductor 704 extending between corresponding balls 518 (such as those configured to carry a clock signal or a strobe signal) may include an asymmetrically laterally extending trace 706. At least a portion of the trace 706 may be aligned with a gap 522 in the ball grid array 520 and extend laterally across the gap, thereby forming a part of the distance between the interconnected balls 518.

[0064] This asymmetry in the ball grid array 520 and the downstream routing of the electrical conductor 704 in the printed circuit board 702 may create an asymmetry in the electric fields generated by the signals carried by the balls 518 and the electrical conductor 704. These asymmetries in the electric fields may create different levels of crosstalk among the electrical conductors, thereby degrading the signal quality. Improvements in the ball grid arrays 100 and 200 of Figure 1 and Figure 2 may improve the signal quality, particularly in high-speed, high-bandwidth, or high-speed and high-bandwidth scenarios. Additionally, when compared to state-of-the-art methods (such as those depicted in Figure 7 ), the ball grid arrays according to the present disclosure, such as Figure 1 and 2Ball grid arrays 100 and 200 can reduce (e.g., eliminate) the dependence on trace 706 and trace segments for routing signals. The reduction in the dependence on trace 706 and trace segments achieved by the ball grid arrays according to the present disclosure can free up space for other signal routing and / or the shape of trace 706, thereby enabling more reliable power delivery.

[0065] Figure 8 is a schematic cross-sectional side view of another embodiment of a semiconductor device package 800 including ball grid array 100 or 200 according to the present disclosure. More specifically, Figure 8 depicts another embodiment of a direct chip attachment connection between device substrate 402 and package substrate 410. For example, semiconductor device package 800 may include a stack of device substrates 402 that are interconnected with each other and supported on package substrate 410. Device substrates 402 may be interconnected with each other by mutually aligned conductive vias 418 (e.g., through-silicon vias (TSVs)) that longitudinally extend through device substrate 402. This configuration may also be characterized as a "three-dimensional stack" (3DS), and may enable device substrates 402 to be stacked such that the lateral sides of device substrates 402 are at least substantially aligned with each other (e.g., at least substantially flush with each other). Semiconductor device package 800 may be connected to printed circuit board 602 in a manner similar or identical to that described in connection with Figure 6 is connected to printed circuit board 602 in a manner similar or identical to that described in connection with

[0066] Figure 9 is a schematic cross-sectional side view of another embodiment of a semiconductor device package 900 including ball grid array 100 or 200 according to the present disclosure. More specifically, Figure 9 depicts another embodiment of a direct chip attachment connection between device substrate 402 and package substrate 410. As a specific non-limiting example, Figure 9 may depict the bottommost device substrate 402 attached to package substrate 410 in a flip-chip direct chip attachment configuration, where overlying device substrates 402 are interconnected with each other and to the bottommost device substrate 402 by wire bonds 902. For example, semiconductor device package 900 may include a stack of device substrates 402 that are interconnected with each other and supported on package substrate 410. Device substrates 402 may be interconnected with each other by wire bonds 902 located near the lateral periphery of device substrate 402. This configuration may also be characterized as a "hybrid three-dimensional stack" (hybrid 3DS), and may enable device substrates 402 to be stacked such that the lateral sides of device substrates 402 are laterally offset from each other in a so-called "shingled stack" (e.g., forming a stepped shape). Semiconductor device package 900 may be connected to printed circuit board 602 in a manner similar or identical to that described in connection with Figure 6 is connected to printed circuit board 602 in a manner similar or identical to that described in connection with

[0067] Figure 10FIG. 1000 is a block diagram of an electronic system 1000 incorporating memories 1016, 1018, 1024 configured as BGA packages according to embodiments of the present disclosure. The electronic system 1000 may include various semiconductor devices fabricated according to embodiments of the present disclosure. For example, the electronic system 1000 may be any of a variety of types, such as a computer, a tablet computer, a cellular phone, a smart phone, a control circuit, or other electronic device. The electronic system 1000 may include one or more processors 1002, such as microprocessors, for controlling system functions and processing requests in the electronic system 1000.

[0068] The electronic system 1000 may include a power supply 1004 operatively coupled to the processor 1002. For example, if the electronic system 1000 is a portable system, the power supply 1004 may include one or more of a fuel cell, a power harvesting device, a permanent battery, a replaceable battery, and / or a rechargeable battery. The power supply 1004 may also include an AC adapter; thus, the electronic system 1000 may be plugged into, for example, a wall outlet. The power supply 1004 may also include a DC adapter such that the electronic system 1000 may be plugged into, for example, a vehicle cigarette lighter or a vehicle power port.

[0069] Various other devices may be coupled to the processor 1002 depending on the functions performed by the electronic system 1000. For example, a user interface 1006 may be coupled to the processor 1002. The user interface 1006 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styli, touchscreens, voice recognition systems, microphones, or combinations thereof. A display 1008 may also be coupled to the processor 1002. The display 1008 may include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or combinations thereof. In addition, an RF subsystem / baseband processor 1010 may also be coupled to the processor 1002. The RF subsystem / baseband processor 1010 may include an antenna coupled to an RF receiver and an RF transmitter (not shown). One or more communication ports 1012 may also be coupled to the processor 1002. The communication ports 1012 may be used to couple to one or more peripheral devices 1014, such as a modem, a printer, a computer, a scanner, or a camera, or to couple to a network, such as a local area network, a remote area network, an intranet, or the Internet.

[0070] The processor 1002 can control the electronic system 1000 by implementing software programs stored in memories 1016 and 1018. The software programs can include, for example, an operating system, database software, graphics software, word processing software, media editing software, or media playback software. Memories 1516 and 1518 are operatively coupled to the processor 1002 to store and facilitate the execution of various programs. For example, the processor 1002 can be coupled to a system memory 1016, which can include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) compliant with double data rate (DDR) and / or graphics DDR (GDDR) standards (DDR4, DDR5, DDR6)), static random access memory (SRAM), particle track memory, and other known memory types. The system memory 1016 can include volatile memory, non-volatile memory, or a combination thereof. The system memory 1016 is typically larger so that it can store dynamically loaded applications and data. In some embodiments, the system memory 1016 can include one or more ball grid arrays (or other arranged electrical interconnects) and associated signal configurations according to the present disclosure, such as the ball grid arrays and associated signal configurations described above.

[0071] The processor 1002 can also be coupled to a non-volatile memory 1018, which does not indicate that the system memory 1016 must be volatile. The non-volatile memory 1018 can include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with the system memory 1016. The size of the non-volatile memory 1018 is typically chosen to be large enough to store any required operating system, application programs, and fixed data. Additionally, the non-volatile memory 1018 can include a mass storage device, such as a disk drive memory, such as a hybrid drive including resistive memory or other types of non-volatile solid-state memory. In some embodiments, the non-volatile memory 1018 can include one or more ball grid arrays (or other arranged electrical interconnects) and associated signal routing configurations according to the present disclosure, such as the ball grid arrays and associated signal routing configurations described above.

[0072] In some embodiments, the electronic system 1000 may include a graphics subsystem connected to the processor 1002, such as a graphics card 1020. For example, each of the graphics card 1020 and the processor 1002 may be connected to and supported on a motherboard in their respective sockets (e.g., a peripheral component interconnect express (PCIe) socket for the graphics card 1020, a CPU socket for the processor 1002). The graphics card 1020 may include its own processing means, such as a graphics processing unit (GPU) or a field programmable gate array (FPGA) 1022. The GPU or FPGA 1022 may be configured to process graphics-related tasks and may be a dedicated device for processing graphics-related tasks in order to speed up the creation of images destined for the frame buffer of the display 1008. The graphics card 1020 may also include a memory bank, such as a graphics memory block 1024, which may include one or more high-speed memory devices connected to the GPU or FPGA 1022 and configured to store and facilitate the acceleration of graphics-related data. More specifically, the graphics memory block 1024 may include one or more sets of devices configured as dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) compliant with the double data rate (DDR) and / or graphics DDR (GDDR) standards (GDDR5, GDDR6, GDDR7)). In some embodiments, one or more of the graphics subsystem, the graphics card 1020, the GPU or FPGA 1022, and / or the graphics memory block 1024 may include one or more ball grid arrays (or other arranged electrical interconnects) and associated signal routing configurations according to the present disclosure, such as the ball grid arrays and associated signal routing configurations described above. For example, one or more balls of the graphics memory block 1024 may be configured to transfer data, command / address information, or both from the GPU or FPGA 1022 with the processor 1002.

[0073] In summary, a system according to the present disclosure may include a central processing unit (CPU) and at least one memory device connected to the CPU. The one or more memory devices may include a device substrate that includes a semiconductor material and bonding pads coupled to an active surface of the device substrate. A package substrate may be fixed to the device substrate and configured to route signals to / from the bonding pads. A ball grid array may be supported on and electrically connected to the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

[0074] Additional non-limiting embodiments within the scope of the present disclosure include:

[0075] Example 1: A device, comprising: a device substrate including a semiconductor material and bonding pads coupled to an active surface of the device substrate; a package substrate fixed to the device substrate, the package substrate configured to route signals to / from the bonding pads; and a ball grid array supported on and electrically connected to the package substrate; wherein each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal is located in a center column of the ball grid array.

[0076] Example 2: The device according to Example 1, wherein each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal is laterally and longitudinally spaced apart from the closest ball of the ball grid array positioned and configured to carry data signals by at least one column of the ball grid array.

[0077] Example 3: The device according to Example 1 or Example 2, wherein each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal is spaced apart from a perimeter of the ball grid array by at least one row.

[0078] Example 4: The device according to any one of Examples 1 to 3, wherein the device substrate is fixed to the package substrate by direct chip attachment.

[0079] Example 5: The device according to any one of Examples 1 to 4, wherein the ball grid array is at least substantially reflection symmetric across the center column.

[0080] Example 6: The device according to any one of Examples 1 to 5, wherein each ball of the ball grid array positioned and configured to carry data signals is positioned to be diagonally adjacent to only any other directly adjacent ball of the ball grid array positioned and configured to carry data signals.

[0081] Example 7: The device according to any one of Examples 1 to 6, wherein a perimeter of the ball grid array is at least substantially free of balls positioned and configured to carry data signals.

[0082] Example 8: The device according to any one of Examples 1 to 7, wherein each ball of the ball grid array positioned laterally and longitudinally adjacent to each ball of the ball grid array positioned and configured to carry data signals is configured to carry a voltage, connected to ground, or connected to a calibration circuit.

[0083] Example 9: The device according to any one of Examples 1 to 8, wherein a number of the balls of the ball grid array positioned and configured to carry data signals is about one-eighth to about one-fourth of a number of the balls of the ball grid array positioned and configured to carry a voltage or connected to ground.

[0084] Example 10: The apparatus according to Example 9, wherein the number of balls of the ball grid array that are positioned and configured to carry data signals is from about one - quarter to about one - half of the number of balls of the ball grid array that are positioned and configured to connect to a core system voltage or a core system ground.

[0085] Example 11: The apparatus according to Example 9, wherein the number of balls of the ball grid array that are positioned and configured to carry data signals is from about two - fifths to about nine - tenths of the number of balls of the ball grid array that are positioned and configured to connect to an input / output memory supply voltage.

[0086] Example 12: The apparatus according to any one of Examples 9 to 11, wherein the number of balls of the ball grid array that are positioned and configured to carry data signals is approximately equal to the number of balls of the ball grid array that are positioned and configured to connect to an output driver voltage.

[0087] Example 13: The apparatus according to any one of Examples 9 to 11, wherein the number of balls of the ball grid array that are positioned and configured to carry data signals is approximately four times the number of balls of the ball grid array that are positioned and configured to connect to a word - line voltage.

[0088] Example 14: The apparatus according to any one of Examples 1 to 13, wherein the total number of balls in the ball grid array is between about 115 and about 120.

[0089] Example 15: An apparatus, comprising: a first memory device, comprising: a device substrate including a semiconductor material and bond pads coupled to an active surface of the device substrate; a package substrate fixed to the device substrate, the package substrate configured to route signals to / from the bond pads; and a ball grid array supported on and electrically connected to the package substrate; a second memory device; and a printed circuit board inserted between and fixed to each of the first memory device and the second memory device; wherein each ball of the ball grid array of the first memory device that is positioned and configured to carry a clock signal or a strobe signal is located in a center column of the ball grid array.

[0090] Example 16: The apparatus according to Example 15, wherein the second memory device includes a second ball grid array that is a rotational mirror image across the printed circuit board with respect to the ball grid array of the first memory device.

[0091] Example 17: The apparatus according to Example 16, wherein the printed circuit board includes electrical conductors located within the printed circuit board, the electrical conductors being electrically connected to a first ball in the ball grid array of the first memory device that is positioned and configured to carry a clock signal or a strobe signal, the electrical conductors being electrically connected to a second ball in the ball grid array of the second memory device that is positioned and configured to carry a clock signal or a strobe signal, the electrical conductors extending at least substantially perpendicular to a main surface of the printed circuit board at least substantially across an entire distance between the first ball and the second ball.

[0092] Example 18: The apparatus according to Example 16 or Example 17, wherein the device substrate of the first memory device is fixed to the package substrate by direct chip attachment.

[0093] Example 19: The apparatus according to Example 18, wherein the first memory device is configured as a single die package and includes a stack of device substrates interconnected with each other through through-silicon vias, or includes a stack of device substrates interconnected with each other through wire bonding.

[0094] Example 20: A system, comprising: a central processing unit (CPU); and at least one memory device connected to the CPU, the at least one memory device including: a device substrate including a semiconductor material and bonding pads coupled to an active surface of the device substrate; a package substrate fixed to the device substrate, the package substrate being configured to route signals to / from the bonding pads; and a ball grid array supported on and electrically connected to the package substrate; wherein each ball of the ball grid array that is positioned and configured to carry a clock signal or a strobe signal is located in a central column of the ball grid array.

[0095] Example 21: An apparatus, comprising: a first memory device, including: a device substrate including a semiconductor material and bonding pads coupled to an active surface of the device substrate; a package substrate fixed to the device substrate, the device substrate being fixed to the package substrate by direct chip attachment, the package substrate being configured to route signals to / from the bonding pads; and a first ball grid array supported on and electrically connected to the package substrate; a second memory device including a second ball grid array; and a printed circuit board inserted between and fixed to each of the first ball grid array of the first memory device and the second ball grid array of the second memory device, the second ball grid array of the second memory device being rotationally symmetric across the printed circuit board with respect to the first ball grid array of the first memory device; wherein each ball of the ball grid array of the first memory device that is positioned and configured to carry a clock signal or a strobe signal is located in a central column of the ball grid array.

[0096] Although certain illustrative embodiments have been described in connection with the figures, those skilled in the art will recognize and understand that the scope of the present disclosure is not limited to the embodiments expressly shown and described herein. In fact, many additions, deletions, and modifications can be made to the embodiments described in the present disclosure to produce embodiments within the scope of the present disclosure, such as those particularly claimed, including statutory equivalents. Additionally, the features of one disclosed embodiment can be combined with the features of another disclosed embodiment while still remaining within the scope of the present disclosure.

Claims

1. An apparatus, comprising: a device substrate including a semiconductor material and bond pads coupled to an active surface of the device substrate; a package substrate fixed to the device substrate, the package substrate configured to route signals to / from the bond pads; and a ball grid array supported on and electrically connected to the package substrate; wherein each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal is located in a center column of the ball grid array.

2. The apparatus according to claim 1, wherein each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal is laterally and longitudinally spaced apart from the closest ball of the ball grid array positioned and configured to carry a data signal by at least one column of the ball grid array.

3. The apparatus according to claim 1, wherein each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal is spaced apart from a perimeter of the ball grid array by at least one row.

4. The apparatus according to claim 1, wherein the device substrate is fixed to the package substrate by direct chip attachment.

5. The apparatus according to claim 1, wherein the ball grid array is at least reflection symmetric across the center column.

6. The apparatus according to claim 1, wherein each ball of the ball grid array positioned and configured to carry a data signal is positioned to be diagonally adjacent to only any other directly adjacent ball of the ball grid array positioned and configured to carry a data signal.

7. The apparatus according to claim 1, wherein a perimeter of the ball grid array is at least free of balls positioned and configured to carry a data signal.

8. The apparatus according to claim 1, wherein each ball of the ball grid array positioned laterally and longitudinally adjacent to each ball of the ball grid array positioned and configured to carry a data signal is configured to carry a voltage, connected to ground, or connected to a calibration circuit.

9. The apparatus according to any one of claims 1 to 8, wherein a number of the balls of the ball grid array positioned and configured to carry a data signal is one-eighth to one-fourth of a number of the balls of the ball grid array positioned and configured to carry a voltage or connected to ground.

10. The apparatus according to claim 9, wherein the number of the balls of the ball grid array positioned and configured to carry a data signal is one-fourth to one-half of a number of the balls of the ball grid array positioned and configured to be connected to a core system voltage or a core system ground.

11. The apparatus according to claim 9, wherein the number of the balls of the ball grid array positioned and configured to carry a data signal is two-fifths to nine-tenths of a number of the balls of the ball grid array positioned and configured to be connected to an input / output memory supply voltage.

12. The apparatus according to claim 9, wherein the number of the balls of the ball grid array positioned and configured to carry a data signal is equal to the number of the balls of the ball grid array positioned and configured to be connected to an output driver voltage. ​ 13. The apparatus according to claim 9, wherein the number of balls of the ball grid array positioned and configured to carry data signals is four times the number of balls of the ball grid array positioned and configured to be connected to a word line voltage.

14. The apparatus according to any one of claims 1 to 8, wherein the total number of balls in the ball grid array is between 115 and 120.

15. An apparatus, which comprises: A first memory device, comprising: A device substrate, which comprises a semiconductor material and bonding pads coupled to an active surface of the device substrate; A package substrate, which is fixed to the device substrate, the package substrate being configured to route signals to / from the bonding pads; and A ball grid array, which is supported on and electrically connected to the package substrate; A second memory device; and A printed circuit board, which is inserted between the first memory device and the second memory device and fixed to each of them; wherein each ball of the ball grid array of the first memory device positioned and configured to carry a clock signal or a strobe signal is located in a central column of the ball grid array.

16. The apparatus according to claim 15, wherein the second memory device comprises a second ball grid array, the second ball grid array being a rotational mirror image across the printed circuit board with respect to the ball grid array of the first memory device.

17. The apparatus according to claim 16, wherein the printed circuit board comprises electrical conductors located within the printed circuit board, the electrical conductors being electrically connected to a first ball of the ball grid array of the first memory device positioned and configured to carry a clock signal or a strobe signal, the electrical conductors being electrically connected to a second ball of the ball grid array of the second memory device positioned and configured to carry a clock signal or a strobe signal, the electrical conductors extending at least perpendicular to a main surface of the printed circuit board at least across an entire distance between the first ball and the second ball.

18. The apparatus according to claim 16 or claim 17, wherein the device substrate of the first memory device is fixed to the package substrate by direct chip attachment.

19. The apparatus according to claim 18, wherein the first memory device is configured as a single die package, comprising a stack of device substrates interconnected by through-silicon vias, or comprising a stack of device substrates interconnected by wire bonding.

20. A system, which comprises: A central processing unit CPU; and At least one memory device connected to the CPU, the at least one memory device comprising: A device substrate, which comprises a semiconductor material and bonding pads coupled to an active surface of the device substrate; A package substrate, which is fixed to the device substrate, the package substrate being configured to route signals to / from the bonding pads; and A ball grid array, which is supported on and electrically connected to the package substrate; wherein each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal is located in a central column of the ball grid array.

21. An apparatus, which comprises: A first memory device, comprising: A device substrate including a semiconductor material and bond pads coupled to an active surface of the device substrate; A package substrate fixed to the device substrate, the device substrate being fixed to the package substrate by direct chip attachment, the package substrate configured to route signals to / from the bond pads; and A first ball grid array supported on and electrically connected to the package substrate; A second memory device including a second ball grid array; and A printed circuit board inserted between and fixed to each of the first ball grid array of the first memory device and the second ball grid array of the second memory device, the second ball grid array of the second memory device being rotationally symmetric across the printed circuit board relative to the first ball grid array of the first memory device; Wherein each ball in the ball grid array of the first memory device that is positioned and configured to carry a clock signal or a strobe signal is located in a center column of the ball grid array.

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