Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor element and a method of manufacturing the same. The semiconductor element has a first isolation layer, a second isolation layer, a conductive plug, and a plurality of gap spacers. The first isolation layer is disposed on a substrate. The conductive plug is disposed in the first isolation layer and penetrates the second isolation layer. The gap spacers are disposed on sidewalls of the conductive plug.

Description

TECHNICAL FIELD

[0001] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 002,278, filed August 25, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method of fabricating the same. In particular, the present disclosure relates to a semiconductor device having a landing pad with at least one self-aligned selectively grown pillar and a plurality of gap spacers disposed on sidewalls of the self-aligned selectively grown pillar. BACKGROUND

[0003] The semiconductor industry faces many challenges in pursuing device miniaturization, which includes rapid scaling of nanoscale features. These issues include the introduction of complex fabrication steps, such as multiple lithography steps, and the integration of high performance materials. To maintain the pace of device miniaturization, selective deposition has shown promise as it has the potential to remove expensive lithography steps by simplifying the integration scheme.

[0004] Selective deposition of materials can be achieved in different ways. A chemical precursor can be selectively reacted with one surface over another (metal or dielectric). Process parameters such as pressure, substrate temperature, partial pressure of precursor, and / or gas flow can be adjusted to tune the chemical kinetics of a particular surface reaction. Another possible approach includes surface pretreatment, which can be used to activate or deactivate a surface of interest for an incoming thin film deposition precursor.

[0005] Self-aligned metal oxide pillars can be formed via oxidation of gap-filled metal films. Metal is deposited on a structure of holes or trenches, which is then oxidized to form metal oxide. The volume expansion during oxidation pushes a pillar out of the hole or trench. The pillar grows from metal only, from bottom to top, selectively.

[0006] In existing DRAMs (dynamic random access memories) having a capacitor-over-bitline (COB) structure, as a size of a buried contact (BC) is reduced and an aspect ratio is increased, a technique for forming a stable BC by using a landing pad without performing an etching process of the BC to secure a lithography alignment margin has been proposed. Generally, the technique uses a single process to simultaneously form a bitline landing pad for connection to a bitline and a storage node landing pad for connection to a storage node. This reduces an etching depth required in an etching process of forming the BC and secures a required alignment margin in the etching process.

[0007] However, according to further restrictions of design rules, due to an increase in integration, a gap between the landing pads is reduced to 0.1 mm. This makes it substantially difficult to prevent a stringer or a bridge phenomenon from occurring. In order to prevent the stringer or the bridge phenomenon from occurring due to the restrictions of the design rules, a method has been proposed in which only the bitline landing pad is formed and a BC of the storage node is directly connected to an active region of a semiconductor substrate by self-alignment.

[0008] The foregoing "background" description is provided for the purpose of making a 35 SUMMARY

[0009] An embodiment of the present disclosure provides a semiconductor element having a first isolation layer, a second isolation layer, a conductive plug, and a plurality of gap spacers. The first isolation layer is disposed on a substrate. The second isolation layer is disposed on the first isolation layer. The conductive plug is disposed in the first isolation layer and penetrates the second isolation layer. The gap spacers are disposed on sidewalls of the conductive plug.

[0010] In some embodiments, the semiconductor element further includes a conductive line disposed in the first isolation layer and under the conductive plug.

[0011] In some embodiments, an upper surface of the conductive line is lower than a surface of the first isolation layer.

[0012] In some embodiments, the substrate comprises a semiconductor material.

[0013] In some embodiments, the gap sub comprises an electrically conductive material.

[0014] Another embodiment of the present disclosure provides a method of fabricating a semiconductor device. The method comprises: forming a first isolation layer on a substrate; forming a plurality of recesses in the first isolation layer; forming an electrically conductive line in at least one recess; forming a self-aligned selectively grown post on the electrically conductive line; selectively forming a plurality of gap subs on sidewalls of the self-aligned selectively grown post; depositing a second isolation layer to fill gaps between two adjacent self-aligned selectively grown posts; removing the second isolation layer on the self-aligned selectively grown post; removing the self-aligned selectively grown post to form a plurality of trenches; and depositing an electrically conductive material in the trenches.

[0015] In some embodiments, the step of forming a plurality of recesses in the first isolation layer is performed by an etching process.

[0016] In some embodiments, the step of forming the electrically conductive line in the at least one recess further comprises: depositing an electrically conductive layer in the recess; planarizing the electrically conductive layer to a surface of the first isolation layer; and recessing the electrically conductive layer below the surface of the first isolation layer to form the electrically conductive line.

[0017] In some embodiments, in the step of forming the self-aligned selectively grown post on the electrically conductive line, a top of the self-aligned selectively grown post is higher than the surface of the first isolation layer.

[0018] In some embodiments, a height between the top of the self-aligned selectively grown post and the surface of the first isolation layer is approximately between about and about 10 pm.

[0019] In some embodiments, the method of fabricating a semiconductor device further comprises exposing the first isolation layer to a carbon precursor before the step of forming the self-aligned selectively grown post on the electrically conductive line.

[0020] In some embodiments, the step of selectively forming a plurality of gap subs on sidewalls of the self-aligned selectively grown post further comprises: depositing an electrically conductive layer on the surface of the first isolation layer, on the top of the self-aligned selectively grown post, and on sidewalls of the self-aligned selectively grown post; and removing the electrically conductive layer on the surface of the first isolation layer and on the top of the self-aligned selectively grown post.

[0021] In some embodiments, the step of removing the electrically conductive layer on the surface of the first isolation layer and on the top of the self-aligned selectively grown post is performed by a gap sub etching process.

[0022] In some embodiments, after the step of selectively forming the spacer on the self-aligned selective growth post, the self-aligned selective growth post is separated by the spacer.

[0023] In some embodiments, the step of removing the isolation layer on the self-aligned selectively grown stud is performed by a chemical-mechanical planarization.

[0024] In some embodiments, after the step of removing the second isolation layer on the self-aligned selective growth post, a top of the second isolation layer is flush with or slightly below the top of the self-aligned selective growth post.

[0025] In some embodiments, the step of removing the self-aligned selectively grown studs to form the trench is performed by an etching process.

[0026] In some embodiments, the etching process is one or more dry etching or wet etching processes.

[0027] In some embodiments, the self-aligned selective growth studs extend generally orthogonally from the upper surfaces of the recessed conductive lines.

[0028] In some embodiments, after the step of depositing the conductive material in the trench, the conductive material is further planarized onto a top of the second insulating layer to form a conductive post.

[0029] Because of the design of the semiconductor device disclosed herein, a landing pad (conductive post) is formed with multiple conductive spacers. Therefore, beaming and bridging phenomena caused by design rule limitations can be prevented.

[0030] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0031] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0032] Figure 1 A flow diagram of a method for selectively depositing a carbon film or forming a carbon pillar, in accordance with some embodiments of the present disclosure.

[0033] Figure 2 A cross-sectional view of an example substrate for selectively depositing a carbon film, in accordance with some embodiments of the present disclosure.

[0034] Figure 3 A cross-sectional view of an example substrate having a carbon film selectively deposited thereon, in accordance with some embodiments of the present disclosure.

[0035] Figure 4 A cross-sectional view of an example substrate for forming a carbon pillar, in accordance with some embodiments of the present disclosure.

[0036] Figure 5 A cross-sectional view of an example substrate having a carbon pillar formed thereon, in accordance with some embodiments of the present disclosure.

[0037] Figure 6 A flow diagram of a method of fabricating a semiconductor device, in accordance with an embodiment of the present disclosure.

[0038] Figure 7 A cross-sectional view of a substrate of a semiconductor device, in accordance with some embodiments of the present disclosure.

[0039] Figure 8 A cross-sectional view of the substrate of the semiconductor device providing a complete self-aligned via, in accordance with some embodiments of the present disclosure.

[0040] Figure 9 A cross-sectional view of the substrate of the semiconductor device of Figure 8 after deposition of a conductive material, in accordance with some embodiments of the present disclosure.

[0041] Figure 10 A cross-sectional view of the substrate of the semiconductor device of Figure 9 after planarizing the conductive material to form conductive lines, in accordance with some embodiments of the present disclosure.

[0042] Figure 11 A cross-sectional view of the substrate of the semiconductor device of Figure 10 after recessing the conductive lines, in accordance with some embodiments of the present disclosure.

[0043] Figure 12 and Figure 13 A cross-sectional view of the substrate of the semiconductor device of Figure 11 after forming carbon pillars on the conductive lines, in accordance with some embodiments of the present disclosure.

[0044] Figure 14 andFigure 15 FIG. 1 illustrates a cross-sectional view of a substrate of a semiconductor element according to some embodiments of the present disclosure. Figure 13 FIG. 2 illustrates a cross-sectional view of the substrate of the semiconductor element of FIG. 1 after a first isolation layer is deposited to surround the carbon pillars.

[0045] Figure 16 FIG. 3 illustrates a cross-sectional view of the substrate of the semiconductor element of FIG. 1 after the first isolation layer is planarized. Figure 15 FIG. 4 illustrates a cross-sectional view of the substrate of the semiconductor element of FIG. 1 after a second isolation layer is deposited to surround the carbon pillars.

[0046] Figure 17 FIG. 5 illustrates a cross-sectional view of the substrate of the semiconductor element of FIG. 1 after the second isolation layer is planarized. Figure 16 FIG. 6 illustrates a cross-sectional view of the substrate of the semiconductor element of FIG. 1 after the carbon pillars are removed to form trenches.

[0047] Figure 18 FIG. 7 illustrates a cross-sectional view of the substrate of the semiconductor element of FIG. 1 after a conductive material is deposited in the trenches. Figure 17 FIG. 8 illustrates a cross-sectional view of the substrate of the semiconductor element of FIG. 1 after the conductive material is planarized to form a landing pad.

[0048] Figure 19 FIG. 9 illustrates a cross-sectional view of the substrate of the semiconductor element of FIG. 1 after a second material is deposited to surround the landing pad. Figure 18 FIG. 10 illustrates a cross-sectional view of the substrate of the semiconductor element of FIG. 1 after the second material is planarized to form a second landing pad.

[0049] Figure 20 FIG. 11 illustrates a cross-sectional view of the substrate of the semiconductor element of FIG. 1 after a third material is deposited to surround the second landing pad. Figure 19 FIG. 12 illustrates a cross-sectional view of the substrate of the semiconductor element of FIG. 1 after the third material is planarized to form a third landing pad.

[0050] Wherein, the reference signs are explained as follows:

[0051] 10: method

[0052] 100: substrate

[0053] 110: first material

[0054] 115: exposed first material surface

[0055] 120: second material

[0056] 125: exposed second material surface

[0057] 200: method

[0058] 201: step

[0059] 203: step

[0060] 205: step

[0061] 207: step

[0062] 300: base

[0063] 305: base feature

[0064] 310: first material

[0065] 312: bottom

[0066] 315: exposed first surface

[0067] 320: second material

[0068] 322: sidewall

[0069] 325: exposed second surface

[0070] 330: carbon stud

[0071] 335: side

[0072] 401: base

[0073] 402: first isolation layer

[0074] 403: surface

[0075] 404: recess

[0076] 503: first conductive layer

[0077] 603: conductive line

[0078] 702: trench

[0079] 703: conductive line

[0080] 704: sidewall

[0081] 705: upper surface

[0082] 801: self-aligned selectively grown stud

[0083] 801': carbon precursor

[0084] 803: gap

[0085] 901: second isolation layer

[0086] 901': top

[0087] 902: sidewall

[0088] 903: top

[0089] 1002: conductive layer

[0090] 1003: gap sub

[0091] 1101: trench

[0092] 1201 : electrically conductive material

[0093] 1203 : electrically conductive post

[0094] D1 : first material dimension

[0095] H1 : height

[0096] S11 : step

[0097] S13 : step

[0098] S15 : step

[0099] S17 : step

[0100] S19 : step

[0101] S21 : step

[0102] S23 : step

[0103] S25 : step

[0104] S27 : step

[0105] T1 : first thickness

[0106] T2 : second thickness DETAILED DESCRIPTION

[0107] The following description describes specific examples of components and configurations to simplify the present disclosure. These specific examples are merely intended to provide examples for discussion and are not intended to limit the scope of the present disclosure. For example, when a first component is described as being formed on a second component, this can include embodiments where the first and second components are formed in direct contact with each other, or where additional components are formed between the first and second components such that the first and second components do not directly contact each other. In addition, embodiments of the present disclosure can repeatedly refer to reference numerals and / or letters in many examples. These repetitions are intended to simplify and clarify, and do not inherently represent a particular relationship between the various embodiments and / or configurations being discussed, unless specifically stated otherwise in the text.

[0108] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein to describe one element's or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0109] It will be understood that when a component is referred to as being "on", "connected to", or "coupled to" another component, it can be directly on, connected, or coupled to the other component, or intervening components can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element, there are no intervening components present. It will also be understood that, although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0110] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0111] Unless otherwise indicated herein, the terms such as "same", "equal", "planar", or "coplanar" as used herein do not necessarily mean an exact, complete identical orientation, layout, location, shape, size, amount, or other measure, but rather mean an orientation, layout, location, shape, size, amount, or other measure that is approximately the same within acceptable variations, which can occur, for example, due to manufacturing processes. The term "substantially" can be used herein to express this meaning. For example, substantially the same, substantially equal, or substantially planar can mean exactly the same, equal, or planar, or can mean the same, equal, or planar within acceptable variations, which can occur, for example, due to manufacturing processes.

[0112] As used herein, the term "substrate," "substrate surface," or the like, refers to any substrate or material surface positioned to be processed by a treatment process. Exemplary substrates upon which process can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material(s) over which films can be formed, including combinations thereof. Substrates include, for example, semiconductor wafers. Substrates can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, or otherwise produce or graft desired chemical moieties to impart desired chemical functionality, anneal and / or bake the substrate surface. In addition to processing directly on the surface of the substrate itself, in the present disclosure any of the film processing steps disclosed can also be performed on an underlayer formed on the substrate as is disclosed in more detail below, and the term "substrate surface" is intended to include such underlayer as the context indicates. Thus, for example, where a film / layer or portion of a film / layer has been deposited on a substrate surface, the exposed surface of this newly deposited film / layer can also become the substrate surface. The composition of a given substrate surface will depend on the type of film to be deposited and the particular chemistry used.

[0113] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to mean a gas that includes species that react with a substrate surface.

[0114] Some embodiments of the present disclosure provide a method of selectively depositing a carbon film. In some embodiments, the carbon film is selectively deposited on a metal-containing surface over a different surface. As used in this specification and the appended claims, the phrase "selectively depositing a film on one surface over another surface" or similar phrases means that a first amount of film is deposited on the first surface and a second amount of film is deposited on the second surface, where the second amount of film is less than the first amount of film or no film is deposited on the second surface.

[0115] The term "over" as used in this context does not mean a physical orientation of one surface on another surface, but rather a relationship of the thermodynamics or kinetics of chemical reactions of a surface relative to other surfaces. For example, selectively depositing a carbon film on a metal surface over a dielectric surface means that the carbon film is deposited on the metal surface and little or no carbon film is deposited on the dielectric surface; or the formation of a carbon film on the metal surface is thermodynamically or kinetically favored over the formation of a carbon film on the dielectric surface.

[0116] Some embodiments of the present disclosure advantageously provide a method of selectively depositing a carbon film on a first surface over a second surface. Some embodiments of the present disclosure provide a method of depositing a carbon film that is performed at relatively low temperatures. Some embodiments of the present disclosure advantageously provide for depositing a carbon film without the use of plasma reactants or treatments. In some embodiments, the first surface comprises a metal and the second surface comprises a dielectric material.

[0117] Reference will now be made to the drawings, Figure 2 is a cross-sectional schematic view of an example substrate 100 in accordance with one or more embodiments of the present disclosure. Substrate 100 includes a first material 110 and a second material 120. First material 110 has an exposed first material surface 115. Second material 120 has an exposed second material surface 125.

[0118] The first material 110 includes a metal. In some embodiments, the metal includes or consists essentially of one or more of Ti, Co, Ni, Cu, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Pt, or Au. In some embodiments, the metal includes or consists essentially of one or more of Ti, Hf, Ta, or W. In some embodiments, the metal includes or consists essentially of one or more of Co, Ni, Ru, Rh, Pd, or Re. In some embodiments, the metal includes or consists essentially of one or more of Cu, Pd, Ag, Ir, Pt, or Au. As used in this specification and the appended claims, the term "consists essentially of or similar terminology means that the primary materials or ingredients are greater than or equal to about 95%, 98%, 99%, or 99.5% of the stated material.

[0119] In some embodiments, the first material 110 includes a substantially pure metal or metal alloy. In other words, the first material 110 can consist essentially of metal atoms. In some embodiments, the first material 110 includes metal elements and non-metal elements. In some embodiments, the first material 110 includes a metal nitride, metal carbide, metal silicide, metal oxide, metal sulfide, metal selenide, metal telluride, or combinations thereof.

[0120] In some embodiments, the second material 120 includes a dielectric material. In some embodiments, the second material 120 includes silicon.

[0121] Figure 1 A flow diagram of a method 200 for forming a carbon film on a substrate 100 is shown in accordance with some embodiments of the present disclosure. The method 200 generally begins at step 201 by providing a substrate on which a carbon film is to be formed. As used in this context, the term "provided" means that the substrate is placed in a location or environment for further processing.

[0122] At step 203, a carbon film is formed on the substrate 100. The carbon film can be formed via a chemical vapor deposition (CVD) process or similar process. See, e.g., U.S. Patent No. 6,309,792, which is incorporated herein by reference in its entirety. Figure 3At step 203, the substrate 100 is exposed to a carbon precursor to form a carbon film 130 on the exposed first material surface 115 and on the exposed second material surface 125. The carbon film 130 on the exposed first material surface 115 has a first thickness Tl, and the carbon film 130 on the exposed second material surface 125 has a second thickness T2. The first thickness Tl is greater than the second thickness T2. For ease of understanding, Figure 3 The second thickness T2 is illustrated in FIG. 2B. In some embodiments, the second thickness T2 is minimal or non-existent.

[0123] The selectivity of a deposition process generally refers to the ratio of growth rates. For example, if a film grows on one surface 25 times faster than on a different surface, the process is described as having a selectivity of 25: 1. In this regard, a higher ratio indicates a more selective process. In some embodiments, the method has a selectivity that is greater than or equal to about 10: 1, greater than or equal to about 25: 1, greater than or equal to about 50: 1, or greater than or equal to about 100: 1.

[0124] The carbon precursor can include any suitable carbon-containing species. In some embodiments, the carbon precursor consists essentially of carbon and hydrogen atoms. In some embodiments, the carbon precursor includes a C1-C4 hydrocarbon, a C1-C6 hydrocarbon, or a C1-C8 hydrocarbon. As used in this regard, C1-C4 or the like means having a number of carbon atoms that is between 1 and 4. In some embodiments, the carbon precursor includes at least one unsaturated bond. In some embodiments, the carbon precursor includes or consists essentially of one or more of C2H2, C2H4, C3H6, or CH4. For gaseous compositions, the term "consists essentially of" means that the active components of the composition, excluding diluents, carriers, or inert gases.

[0125] In some embodiments, the substrate is exposed to a carbon precursor that includes an additional reactant or diluent. In some embodiments, the additional reactant or diluent includes or consists essentially of hydrogen (H2), nitrogen (N2), or argon (Ar). In some embodiments, hydrogen (H2) is not provided as a diluent, carrier, or inert gas when provided as part of the carbon precursor.

[0126] The flow rate of the carbon precursor can be any suitable flow rate, including a flow rate between about 1 and about 5000 seem, or between about 2 and about 4000 seem, or between about 3 and about 3000 seem, or between about 5 and about 2000 seem, or between about 10 and about 2000 seem, but is not limited thereto.

[0127] The carbon precursor can be provided so as to establish any suitable pressure about the substrate (e.g., within a processing chamber), including a pressure between about 1 Torr and about 3000 Torr, or between about 2 Torr and about 1500 Torr, or between about 100 Torr and about 1000 Torr, or between about 500 Torr and about 1000 Torr, but is not limited thereto. In some embodiments, the substrate is exposed to the carbon precursor at about atmospheric pressure (e.g., 760 Torr).

[0128] The temperature of the substrate during deposition can be controlled, for example, by setting a temperature of a substrate support. In some embodiments, the substrate is maintained at a temperature between about 100 °C and about 700 °C, between about 100 °C and about 500 °C, or between about 300 °C and about 500 °C. In some embodiments, the substrate is maintained at a temperature less than or equal to about 700 °C, less than or equal to about 500 °C, or less than or equal to about 300 °C.

[0129] The time period during which the substrate is exposed to the carbon precursor gas can be any suitable amount of time, which is the amount of time required to allow a predetermined thickness of carbon film to form on the exposed first material surface. For example, the substrate can be exposed to the carbon precursor for a period of time between about 10 minutes and about 5 hours, or between about 30 minutes and about 3 hours, or between about 1 hour and about 2 hours.

[0130] In some embodiments, the rate of carbon film formation is greater than or equal to about 20 nm / hour, greater than or equal to 25 nm / hour, greater than or equal to about 30 nm / hour, greater than or equal to 40 nm / hour, or greater than or equal to 50 nm / hour. In some embodiments, the rate of carbon film formation is between about 25 nm / hour and about 50 nm / hour.

[0131] In some embodiments, the method of selectively depositing a carbon film is performed as a thermal process without the use of a plasma reactant. In other words, in some embodiments, the method is performed without plasma.

[0132] Next, at step 205, a determination is made as to whether the metal film has reached a predetermined thickness. If not, the method 200 returns to step 203 to continue forming the metal film until the predetermined thickness is reached. Once the predetermined thickness has been reached, the method 200 can terminate or proceed to step 207 to perform optional subsequent processing.

[0133] Some embodiments of the disclosure provide a method of forming a carbon pillar. In some embodiments, the carbon pillar is selectively formed on a metal-containing surface that is over a different surface.

[0134] Some embodiments of the disclosure advantageously provide a method of forming a carbon pillar on a first surface that is over a second surface. Some embodiments of the disclosure provide a method of forming a carbon pillar that is performed at relatively low temperatures. Some embodiments of the disclosure advantageously provide a method of forming a carbon pillar without the use of plasma reactants or processing. Some embodiments of the disclosure provide a method of forming a carbon pillar that provides a pillar without a mushroom effect. In some embodiments, the first surface comprises a metal and the second surface comprises a dielectric material.

[0135] Referring to the drawings, Figure 4 is a schematic diagram of an example substrate 300 that illustrates one or more embodiments of the disclosure. The substrate 300 includes a first material 310 and a second material 320. The first material 310 has an exposed first surface 315, and the exposed first surface 315 has a first material dimension Dl. The second material 320 has an exposed second surface 325. The exposed first surface 315 and the exposed second surface 325 form the substrate surface. In some embodiments, the first material 310 comprises a metal-containing material. In some embodiments, the second material 320 comprises a dielectric material. As such, the first material 310 can be considered a first metal-containing material, and the second material 320 can be considered a second dielectric material.

[0136] The first material 310 comprises a metal. In some embodiments, the metal comprises or consists essentially of one or more of Co, Ni, Ru, Rh, Pd, or Re. Without being bound by theory, the inventors have found that these metals both catalyze carbon deposition and have a high level of carbon solubility. These factors combine to allow a deposition process that goes from a vapor precursor to a dissolved carbon species, and then solidifies to deposit a carbon pillar. Without being bound by theory, it is believed that this mechanism provides orthogonal growth rather than mushrooming of the carbon pillar.

[0137] In some embodiments, the first material 310 comprises a substantially pure metal or a metal alloy. In other words, the first material 310 may be composed of multiple metal atoms. In some embodiments, the first material 310 comprises multiple metallic elements and multiple non-metallic elements. In some embodiments, the first material 310 comprises a metal nitride, a metal carbide, a metal silicide, a metal oxide, a metal sulfide, a metal selenide, a metal telluride, or a combination thereof.

[0138] In some embodiments, the second material 320 comprises a dielectric material. In some embodiments, the second material 320 comprises silicon.

[0139] In some embodiments, such as Figure 4 As shown, the exposed first surface 315 is recessed from the exposed second surface 325 to form a substrate feature 305. The substrate feature 305 includes at least one sidewall 322 of the second material 320 and a bottom 312 exposing the first surface 315.

[0140] Accordingly, in some embodiments, the substrate 300 does not include such Figure 4 Feature 305 is shown. For these embodiments, the substrate 300 may have a surface such as... Figure 2 The substrate 100. In other words, in some embodiments, the exposed first surface and the exposed second surface are substantially coplanar. As used in this specification and the appended claims, the term "substantially coplanar" means that the exposed first surface and the exposed second surface are coplanar within ±2 nm.

[0141] The method for forming carbon emboli is similar to, for example... Figure 1 The method shown is for forming a carbon film. Method 200 typically begins with step 201, which involves providing a substrate on which a carbon stud is formed.

[0142] In step 203, a carbon stud is formed on the substrate. The carbon stud can be formed via a chemical vapor deposition (CVD) process or a similar process. Please refer to [reference needed]. Figure 5 In step 203, the substrate 300 is exposed in a carbon precursor to form a carbon stud 330 comprising a carbon material. The carbon stud 330 extends on the exposed second surface 325. The carbon stud 330 has a first dimension D1 that is substantially the same as that of the exposed first surface 315. In some embodiments, substantially no carbon material is deposited on the exposed second surface 325.

[0143] In some embodiments, the carbon pillars 330 have a plurality of sides 335 that are substantially orthogonal to the substrate surface. In some embodiments, the carbon pillars 330 have a plurality of sides 335 that are substantially orthogonal to the exposed second surface 325. As used in this regard, a surface can be described as being substantially orthogonal when the angle formed at the interface of the surface is 90° ± 10°.

[0144] The reactants and process parameters used for selective deposition of a carbon film as described above are the same as the reactants and process parameters used to form the carbon pillars.

[0145] Next, at step 205, it is determined whether the carbon pillars have reached a predetermined thickness. If the predetermined thickness has not been reached, the method 200 returns to step 203 to continue forming the carbon pillars until the predetermined thickness is reached. Once the predetermined thickness has been reached, the method 200 can terminate or proceed to step 207 to perform optional post processing.

[0146] Some embodiments of the present disclosure provide methods of forming a plurality of fully self-aligned vias. In one embodiment, a first metallization layer is formed, the first metallization layer including a set of first conductive lines extending in a first direction on a first isolation layer on a substrate. A second isolation layer is formed on the first isolation layer. A second metallization layer is formed, the second metallization layer including a set of second conductive lines on a third isolation layer above the first metallization layer. The set of second conductive lines extends in a second direction. A via is formed between the first metallization layer and the second metallization layer. The via is self-aligned to one of the first conductive lines in the second direction. The via is self-aligned to one of the second conductive lines in the first direction, as described in further detail below. In one embodiment, the first and second directions are at an angle to each other. In one embodiment, the first and second directions are substantially orthogonal to each other.

[0147] In one embodiment, a fully self-aligned via is fabricated using a selective pillar deposition technique. In one embodiment, the conductive lines on a first isolation layer on a substrate are recessed. The conductive lines extend in a first direction on the first isolation layer. Pillars are formed on the recessed conductive lines. A second isolation layer is deposited between the pillars. The pillars are removed to form trenches. An isolation layer is deposited to fill a gap between two adjacent self-aligned selectively grown pillars. The isolation layer on the self-aligned selectively grown pillars is removed. The self-aligned selectively grown pillars are removed to form trenches. A conductive material is deposited in the trenches, as described in further detail below.

[0148] In one embodiment, a fully self-aligned via is a via that is self-aligned to each wire in a lower metallization layer and an upper metallization layer in at least two directions. In one embodiment, a fully self-aligned via is defined by a hard mask in one direction and a lower layer of isolation in another direction, as described in further detail below.

[0149] One or more embodiments provide fully self-aligned vias that advantageously eliminate via misalignment problems and avoid shorting to the wrong metal line. The fully self-aligned vias provide lower via resistance and capacitance advantages compared to conventional vias. Embodiments of the self-aligned vias provide full alignment between the via and the conductive line in the metallization layer with substantially no error and advantageously improve device yield and reduce device cost.

[0150] When the vias are printed close together, i.e., closer than the minimum pitch that lithography can achieve, the via mask layer set is split into multiple masks. For example, instead of defining a via to metal with a single lithography-etch sequence, two or more lithography-etch sequences are used to avoid shorting the closely spaced vias. Some embodiments of the disclosure are directed to a pillar growth process where all vias are defined as cross-overs between two metal layers so that adjacent vias will not short together. In some embodiments, multiple vias can be defined using a large lithography feature placed over multiple cross-over points. In this case, all areas of the metal layer under the defined large lithography opening will form a via.

[0151] Further, the disclosed method advantageously provides pillars that are easier to remove than oxide pillars. In some embodiments, the carbon pillars are removed by a dry etch process. Without being bound by theory, it is believed that using a dry etch process to remove the carbon pillars is easier than performing an oxygen based ashing process, which is typically used to etch metal oxide materials.

[0152] In the following description, numerous specific details are set forth such as particular materials, chemicals, dimensions, processes, etc. in order to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to one of ordinary skill in the art that one or more embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known semiconductor manufacturing procedures, techniques, materials, equipment, etc. are not described in detail in order to avoid unnecessarily obscuring the description. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation.

[0153] One or more embodiments of the present disclosure are directed to methods and apparatuses for providing a plurality of fully self-aligned vias. Various aspects of the present disclosure are described in terms of detailed processes shown in the figures. One having ordinary skill in the art will understand that the scope of the present disclosure is not limited to the specific details described in the figures and that some portions of this process can be modified or omitted.

[0154] Figure 6 A flowchart of a method 10 for fabricating a semiconductor device according to one embodiment of the present disclosure is shown. According to some embodiments, the method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, and S27. Figure 6 The steps S11-S27 are described in conjunction with the following figures.

[0155] Figures 7 to 10 A cross-sectional view of a substrate 401 according to some embodiments to provide a fully self-aligned via or air gap is shown. Referring to Figure 10 A lower metallization layer (Mx) including a set of conductive lines 603 is formed on the substrate 401 on the isolation layer 402. The method can start from Figure 7 and Figure 8 wherein a plurality of recesses 404 are formed in the isolation layer 402. Referring to Figure 5 A conductive layer 503 is deposited in the recesses 404. Referring to Figure 6 If desired, the conductive layer 503 is planarized to the surface of the isolation layer 402.

[0156] Referring to Figure 7 At step S11, a first isolation layer 402 is formed on a substrate 401. In some embodiments, the substrate 401 includes a semiconductor material, such as Si, C, Ge, SiGe, GaAs, InP, InGaAs, InAlAs, other semiconductor materials, or any combination thereof. In some embodiments, the substrate 401 is a semiconductor-on-insulator (SOI) substrate, which includes a bulk lower semiconductor, an intermediate isolation layer, and an upper single-crystalline layer. The upper single-crystalline layer can include any of the materials listed above, such as silicon (Si). In different embodiments, the substrate 401 can be an organic, ceramic, glass, or semiconductor substrate, for example. Although several examples of materials that can form the substrate are described herein, materials that can be used as the basis for passive and active electronic elements (such as transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic elements, or any other electronic elements) fall within the spirit and scope of the present disclosure.

[0157] In some embodiments, the substrate 401 includes one or more metallized inner connection layers for substrate circuitry. In some embodiments, the substrate 401 includes a plurality of inner connections, for example, vias, configured to connect the metallized layers. In some embodiments, the substrate 401 includes a plurality of electronic elements, such as transistors, memory, capacitors, resistors, optoelectronic elements, switches, or any other active and passive electronic elements, disposed apart by an electrically isolating layer. For example, an interlayer dielectric, a shallow trench isolation layer, or any other isolation layer known to one of ordinary skill in the art of electronic element fabrication. In some embodiments, the substrate includes one or more buffer layers to accommodate a lattice mismatch between the substrate 401 and one or more layers on the substrate 401, and to limit lattice dislocations and defects.

[0158] The first isolation layer 402 can be any material suitable for isolating adjacent elements and avoiding electrical leakage. In some embodiments, the electrically isolating layer 402 is an oxide layer, such as silicon dioxide, or any other electrically isolating layer determined by an electronic element design. In some embodiments, the first isolation layer 402 includes an interlayer dielectric (ILD). In some embodiments, the first isolation layer 402 is a low dielectric constant dielectric including materials such as silicon dioxide, silicon oxide, carbon doped oxide (CDO) such as carbon doped silicon dioxide, porous silicon dioxide, silicon nitride, or any combination thereof, but is not limited thereto.

[0159] In some embodiments, the first isolation layer 402 includes a dielectric material having a dielectric constant (k value) of less than 5. In some embodiments, the first isolation layer 402 includes a dielectric material having a dielectric constant (k value) of less than 2. In some embodiments, the first isolation layer 402 includes a nitride, an oxide, a polymer, a phosphosilicate glass, a fluorosilicate glass (SiOF), an organosilicate glass (SiOCH), other electrically isolating layer determined by an electronic element design, or any combination thereof. In some embodiments, the first isolation layer 402 can include polyimide, epoxy, photodefinable materials such as benzocyclobutene, and WPR series materials, or spin-on-glass.

[0160] In some embodiments, the first isolation layer 402 is a low-k ILD to insulate a metal line on the substrate 401 from other metal lines. In some embodiments, the first isolation layer 402 has a thickness of between about 10 nm and about 2 μm.

[0161] In some embodiments, the first isolation layer 402 is deposited using one of a variety of deposition techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating, or other deposition techniques known to one of ordinary skill in the art of microelectronic device fabrication, without limitation.

[0162] In some embodiments, the first isolation layer 402 is of a similar composition as the second material 120 described above.

[0163] Referring to Figure 8 At step S13, a plurality of recesses 404 are formed in the first isolation layer 402. In some embodiments, the first isolation layer 402 is patterned and etched using a hard mask to form the recesses 404 using one or more patterning and etching techniques known to one of ordinary skill in the art of microelectronic device fabrication. In some embodiments, the dimensions of the recesses 404 in the first isolation layer 402 are determined by the dimensions of the conductive lines 603 formed in a subsequent process.

[0164] Referring to Figure 9 , Figure 10 and Figure 11 At step S15, a conductive line 703 is formed in at least one of the recesses 404. In some embodiments, the lower metallization layer Mx including the conductive lines 603 is part of a back end of line metallization for an electronic device. Referring to Figure 9 A conductive layer 503 is deposited in the recesses 404. In some embodiments, forming the conductive lines 603 includes filling the recesses 404 with a layer of conductive material. In some embodiments, a base layer (not shown) is first deposited on the inner sidewalls and bottom of the recesses 404, and then the conductive layer 503 is deposited on the base layer. In some embodiments, the base layer includes a conductive seed layer (not shown) deposited on a conductive barrier layer (not shown). The seed layer can include copper, and the conductive barrier layer can include aluminum, titanium, tantalum nitride, or similar metals. The conductive barrier layer can be used to prevent diffusion of the conductive material from the seed layer, such as copper, into the first isolation layer 402. In addition, the conductive barrier layer can be used to provide adhesion for the seed layer, such as copper.

[0165] In some embodiments, to form the base layer, a conductive barrier layer is deposited on the sidewalls and bottom of the recess 404, and then the seed layer is deposited on the conductive barrier layer. In another embodiment, the conductive base layer includes a seed layer that is deposited directly on the sidewalls and bottom of the recess 404. Each of the conductive barrier layer and the seed layer can be deposited using any thin film deposition technique known to one of ordinary skill in the art of semiconductor fabrication, such as sputtering, blanket deposition, or the like. In one embodiment, each of the conductive barrier layer and the seed layer has a thickness that is approximately between about 1 nm and about 100 nm. In some embodiments, the barrier layer can be a thin dielectric that has been etched to establish electrical conductivity to the underlying metal layer. In some embodiments, the barrier layer can be omitted entirely, and a "self-forming barrier" can be created using appropriate doping of the copper line.

[0166] In some embodiments, the conductive layer 503, such as copper, is deposited on the seed layer of the copper base layer by an electroplating process. In some embodiments, the conductive layer is deposited into the recess 404 using a damascene process known to one of ordinary skill in the art of microelectronic device fabrication. In one embodiment, the conductive layer 503 is deposited on the seed layer in the recess 404 using a selective deposition technique, such as electroplating, electroless plating, a CVD, PVD, MBE, MOCVD, ALD, spin-on, or other deposition technique known to one of ordinary skill in the art of microelectronic device fabrication, without limitation.

[0167] In some embodiments, the material selection for the conductive layer 503 for the conductive line 603 determines the material selection for the seed layer. For example, if the material for the conductive line 603 includes copper, then the material for the seed layer also includes copper. In some embodiments, for example, the conductive line 603 includes a metal, such as Cu, Ru, Ni, Co, Cr, Fe, Mn, Ti, Al, Hi, Ta, W, V, Mo, Pd, Au, Ag, Pt, In, Sn, Pb, Sb, Bi, Zn, Cd, or any combination thereof.

[0168] In further embodiments, examples of conductive materials for the conductive line 603 for the metallization layer Mx are a metal, a metal alloy, a metal carbide, other conductive material, or any combination thereof, and the metal is, for example, copper, tantalum, tungsten, ruthenium, titanium, hafnium, zirconium, aluminum, silver, tin, lead, the metal carbide is, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, without limitation.

[0169] In some embodiments, the conductive lines are composed of a first material 110 similar to that described above.

[0170] Referring to Figure 10 , the conductive layer 503 is planarized to a surface 403 of the first isolation layer 402 (to form the conductive lines 603). In some embodiments, portions of the conductive layer 503 are removed so that the upper portions of the conductive lines 603 are flush with the upper portions of the first isolation layer 402, using a chemical mechanical polishing (CMP) technique well known in the art of microelectronic device fabrication.

[0171] In a non-limiting example, the conductive lines 603 have a thickness of between about 15 nm and about 1000 nm. In a non-limiting example, the conductive lines 603 have a thickness of between about 20 nm and about 200 nm. In a non-limiting example, the conductive lines 603 have a width of between about 5 nm and about 500 nm. In a non-limiting example, the spacing between the conductive lines 603 is between about 2 nm and about 500 nm. In a more specific non-limiting example, the spacing between the conductive lines 603 is between about 5 nm and about 50 nm.

[0172] In some embodiments, the lower metallization layer Mx is configured to be connected to other metallization layers (not shown). In some embodiments, the metallization layer Mx is configured to provide electrical connections to a plurality of electronic elements, such as transistors, memory, capacitors, resistors, optoelectronic elements, switches, and any other active or passive electronic elements, separated by an electrical isolation layer, such as an interlayer dielectric, a trench isolation layer, or any other isolation layer well known in the art of electronic device fabrication.

[0173] Referring to Figure 11 , the conductive layer (e.g., the conductive lines 603) is recessed below the surface 403 of the first isolation layer 402, thereby forming conductive lines (the recessed conductive lines 703). That is, the conductive lines 603 are recessed to a predetermined depth to form the recessed conductive lines 703. As Figure 11 shown, a plurality of trenches 702 are formed in the first isolation layer 402. Each trench 702 has a plurality of sidewalls 704, which are portions of the first isolation layer 402, and a bottom, which is an upper surface 705 of the recessed conductive lines 603.

[0174] In some embodiments, the depth of the trench 702 is from about 10 nm to about 500 nm. In some embodiments, the depth of the trench 702 is from about 10% to about 100% of the thickness of the conductive line. In some embodiments, the conductive line 603 is recessed using one or more of wet etching, dry etching, or a combination thereof, of electronic device fabrication well known to those having ordinary skill in the art.

[0175] Referring to Figure 12 and Figure 13 At step S17, a self-aligned selectively grown stud 801 is formed on the (recessed) conductive line 703. Referring to Figure 12 In some embodiments, prior to step S17, the first isolation layer 402 is exposed to a carbon precursor 801'. The self-aligned selectively grown stud 801 can be formed according to the method described herein for forming the carbon stud 330. As Figure 12 and Figure 13 The array of self-aligned selectively grown studs 801 has the same pattern as the set of recessed conductive lines 703. In some embodiments, the self-aligned selectively grown studs 801 extend substantially orthogonally from the respective upper surfaces 705 of the recessed conductive lines 703. As Figure 13 illustrated, the self-aligned selectively grown studs 801 extend substantially orthogonally from the respective upper surfaces of the recessed conductive lines 703. As Figure 13 illustrated, the self-aligned selectively grown studs 801 extend in the same direction as the conductive lines 603. As Figure 13 illustrated, the self-aligned selectively grown studs 801 are disposed apart by gaps 803. In some embodiments, a height H1 of the self-aligned selectively grown studs 801 is approximately between about and about 10 μιη.

[0176] Referring to Figure 14 and Figure 15 At step S19, gap sub 1003s are selectively formed on the respective sidewalls 902 of the self-aligned selectively grown studs 801. Referring to Figure 14 A conductive layer 1002 is deposited on the surface 403 of the first isolation layer 402, on the top 903 of the self-aligned selectively grown studs 801, and on the respective sidewalls 902 of the self-aligned selectively grown studs 801. Then, referring to Figure 15 The conductive layer 1002 on the surface 403 of the first isolation layer 402 and on the top 903 of the self-aligned selectively grown studs 801 is removed. In some embodiments, the removal of the conductive layer 1002 on the surface 403 of the first isolation layer 402 and on the top 903 of the self-aligned selectively grown studs 801 is performed by a gap sub etching process.

[0177] Referring to Figure 16 At step S21, a second isolation layer 901 is deposited to fill up the gaps 803 between adjacent two self-aligned selective growth pillars 801. In some embodiments, after step S19, the self-aligned selective growth pillars 801 are separated by the gaps 803. As shown, the second isolation layer 901 is deposited on the gap sub 1003 formed at the sidewalls 902 of the self-aligned selective growth pillars 801, at the top 903 of the self-aligned selective growth pillars 801, and via the gaps 803 which are on some portions of the isolation layer 402 between the self-aligned selective growth pillars 801. Figure 16

[0178] In some embodiments, the second isolation layer 901 is a low-k gap-fill layer. In one embodiment, the second isolation layer 901 is a flowable silicon oxide (FSiOx) layer. In some embodiments, the second isolation layer 901 is an oxide layer, such as silicon dioxide or other electrically insulating layer as determined by an electronic device design. In some embodiments, the second isolation layer 901 is an ILD. In some embodiments, the second isolation layer 901 is a low-k dielectric, including, but not limited to, materials such as silicon dioxide, silicon oxide, a carbon-based material such as a porous carbon film, a carbon-doped oxide (CDO) such as carbon-doped silicon dioxide, porous silicon dioxide, porous silicon-oxygen-carbon-hydrogen (SiOCH), silicon nitride, or any combination thereof. In some embodiments, the second isolation layer 901 is a dielectric material having a dielectric constant (k-value) less than 3. In some embodiments, the second isolation layer 901 is a dielectric material having a dielectric constant (k-value) close to between about 2.2 and about 2.7. In some embodiments, the second isolation layer 901 is a dielectric material having a dielectric constant (k-value) less than 2. In some embodiments, the second isolation layer 901 is a dielectric layer as described above for the first isolation layer 402.

[0179] In some embodiments, the second isolation layer 901 is a low-k ILD to insulate a metal line from other metal lines. In some embodiments, the second isolation layer 901 is deposited using a deposition technique such as CVD, spin-on, ALD, PVD, MBE, MOCVD, or other low-k ILD deposition technique known to one of ordinary skill in the art of microelectronic device fabrication.

[0180] Referring to Figure 17 ​At step S23, the second isolation layer 901 on the self-aligned selective growth stud 801 is removed. In some embodiments, the second isolation layer 901 is removed by chemical-mechanical planarization (CMP) to expose the top portions 903 of the self-aligned selective growth studs 801. The CMP process can be any suitable planarization process known to those having ordinary skill in the art. In some embodiments, the second isolation layer 901 is deposited such that the top of the second isolation layer 901 is flush or slightly lower than the top portions 903 of the self-aligned selective growth studs 801, and no CMP process is performed.

[0181] Referring to Figure 18 At step S25, the self-aligned selective growth studs 801 are removed to form a plurality of trenches 1101. The etching process can be performed in this portion of the process or in conjunction with any other portion of the etching process by any suitable etching technique known to those having ordinary skill in the art. In some embodiments, the etching process is one or more of a dry etching or a wet etching.

[0182] Referring to Figure 19 At step S27, a conductive material 1201 is deposited in the trenches 1101. Referring to Figure 20 After step S27, the conductive material 1201 is planarized to a top portion 901' of the second isolation layer 901 (as shown in Figure 17 to form a conductive stud 1203. That is, a landing pad (the conductive stud 1203) is formed with a plurality of conductive gap sub 1003.

[0183] Due to the design of the semiconductor device of the present disclosure, a landing pad (the conductive stud 1203) is formed with a plurality of conductive gap sub 1003. Therefore, the girder and bridge phenomenon due to the limitation of design rules can be prevented.

[0184] An embodiment of the present disclosure provides a semiconductor device having a first isolation layer, a second isolation layer, a conductive stud, and a plurality of gap sub. The first isolation layer is disposed on a substrate. The second isolation layer is disposed on the first isolation layer. The conductive stud is disposed in the first isolation layer and penetrates through the second isolation layer. The gap sub is disposed on sidewalls of the conductive stud.

[0185] Another embodiment of the present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first isolation layer on a substrate; forming a plurality of recesses in the first isolation layer; forming a conductive line in at least one of the recesses; forming a self-aligned selective growth post on the conductive line; selectively forming a plurality of gap sub on sidewalls of the self-aligned selective growth post; depositing a second isolation layer to fill gaps between adjacent self-aligned selective growth posts; removing the second isolation layer on the self-aligned selective growth post; removing the self-aligned selective growth post to form a plurality of trenches; and depositing a conductive material in the trenches.

[0186] While the present disclosure and its advantages have been disclosed in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes can be under taken in an alternative order, and / or the processes described can be modified or combined. Furthermore, where materials are referred to as those that are presently preferred, it is intended to include other similar materials as such become known in the art.

[0187] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the disclosure of one or more embodiments of the present application is intended to be illustrative, but not limiting, of the scope of the present application.

Claims

1. A method for fabricating a semiconductor device, comprising: A first isolation layer is formed on a substrate; Multiple recesses are formed in the first isolation layer; A conductive line is formed in at least one recess; A self-aligned selective growth post is formed on the conductive line; Multiple spacers are selectively formed on each sidewall of the self-aligned selectively grown stud. A second isolation layer is deposited to fill the gaps between two adjacent self-aligned selectively grown plugs. Remove the second isolation layer from the self-aligned selective growth stud; Remove the self-aligned selectively grown studs to form multiple trenches; as well as A conductive material is deposited in the trench.

2. The method for fabricating a semiconductor device as claimed in claim 1, wherein the step of forming a plurality of recesses in the first isolation layer is performed by an etching process.

3. The method for fabricating a semiconductor element as claimed in claim 1, wherein the step of forming the conductive line in the at least one recess further comprises: A conductive layer is deposited in the depression; Planarize the conductive layer onto a surface of the first insulating layer; as well as The conductive layer is recessed below the surface of the first insulating layer to form the conductive line.

4. The method for fabricating a semiconductor element as claimed in claim 3, wherein in the step of forming the self-aligned selective growth post on the conductive line, a top of the self-aligned selective growth post is higher than the surface of the first insulating layer.

5. The method for fabricating a semiconductor device as claimed in claim 4, wherein a height between the top of the self-aligned selective growth post and the surface of the first insulating layer is intermediate to... Between 10μm and 10μm.

6. The method for fabricating a semiconductor element as claimed in claim 4, further comprising exposing the first isolation layer in a carbon precursor prior to the step of forming the self-aligned selective growth post on the conductive line.

7. The method for fabricating a semiconductor device as claimed in claim 4, wherein the step of selectively forming the spacers on each sidewall of the self-aligned selective growth post further comprises: A conductive layer is deposited on the surface of the first insulating layer, on the top of the self-aligned selective growth post, and on each sidewall of the self-aligned selective growth post. as well as Remove the conductive layer from the surface of the first insulating layer and from the top of the self-aligned selectively grown stud.

8. The method of fabricating a semiconductor element as claimed in claim 7, wherein the step of removing the conductive layer on the surface of the first isolation layer and on the top of the self-aligned selectively grown post is performed by a spacer etching process.

9. The method for fabricating a semiconductor element as claimed in claim 7, wherein after the step of selectively forming the spacer on the self-aligned selective growth post, the self-aligned selective growth post is separated by the gap.

10. The method for fabricating a semiconductor device as claimed in claim 7, wherein the step of removing the isolation layer on the self-aligned selective growth post is performed by a chemical mechanical planarization.

11. The method of fabricating a semiconductor device as claimed in claim 7, wherein after the step of removing the second isolation layer on the self-aligned selective growth post, a top of the second isolation layer is flush with or slightly lower than the top of the self-aligned selective growth post.

12. The method of fabricating a semiconductor device as claimed in claim 11, wherein the step of removing the self-aligned selective growth pillars to form the trench is performed by an etching process.

13. The method for fabricating a semiconductor device as claimed in claim 12, wherein the etching process is one or more dry etching or wet etching processes.

14. The method of fabricating a semiconductor element as claimed in claim 3, wherein the self-aligned selective growth studs extend substantially orthogonally from each of the upper surfaces of the recessed conductive lines.

15. The method for fabricating a semiconductor element as claimed in claim 1, wherein after the step of depositing the conductive material in the trench, the method further comprises planarizing the conductive material onto a top of the second insulating layer to form a conductive post.

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