Semiconductor device

Abstract

Semiconductor devices are provided. The semiconductor devices include a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etching stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etching stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etching stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer and a second barrier layer between the conductive pattern and the lower interconnection line. The first barrier layer has a greater resistivity than a resistivity of the second barrier layer. A nitrogen concentration in the first barrier layer is greater than a nitrogen concentration in the second barrier layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0106870, filed on August 25, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing such semiconductor devices, and more specifically, to semiconductor devices including field-effect transistors and methods for manufacturing such semiconductor devices. Background Technology

[0003] Semiconductor devices can include integrated circuits containing metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices have decreased, MOSFETs have also been scaled down. The operating characteristics of semiconductor devices deteriorate due to the reduction in MOSFET size. Therefore, various methods have been investigated to form semiconductor devices with excellent performance while overcoming the limitations caused by high integration density. Summary of the Invention

[0004] Embodiments of the present invention can provide a semiconductor device with improved electrical characteristics and a method for manufacturing the semiconductor device.

[0005] According to some embodiments of the present invention, a semiconductor device may include: a transistor on a substrate; a first interlayer insulating layer on the transistor; a lower interconnect in the first interlayer insulating layer; an etch stop layer on the first interlayer insulating layer and the lower interconnect; a second interlayer insulating layer on the etch stop layer; and an upper interconnect in the second interlayer insulating layer. The upper interconnect may include a via portion extending through the etch stop layer and contacting the lower interconnect. The via portion may include a blocking pattern and a conductive pattern on the blocking pattern. The blocking pattern may include a first blocking layer between the conductive pattern and the second interlayer insulating layer and a second blocking layer between the conductive pattern and the lower interconnect. The resistivity of the first blocking layer may be greater than that of the second blocking layer, and the nitrogen (N) concentration in the first blocking layer may be greater than that in the second blocking layer.

[0006] According to some embodiments of the present invention, a semiconductor device may include: a transistor located on a substrate; a first interlayer insulating layer located on the transistor; a lower interconnect located in the first interlayer insulating layer; an etch stop layer located on the first interlayer insulating layer and the lower interconnect; a second interlayer insulating layer located on the etch stop layer; and an upper interconnect located in the second interlayer insulating layer. The upper interconnect may include a via portion extending through the etch stop layer and contacting the lower interconnect. The via portion may include a blocking pattern and a conductive pattern located on the blocking pattern. The blocking pattern may include a first portion located between the conductive pattern and the second interlayer insulating layer and a second portion located between the conductive pattern and the lower interconnect. The first portion of the blocking pattern may have a first nitrogen concentration, and the second portion of the blocking pattern may have a second nitrogen concentration. The first nitrogen concentration may be greater than the second nitrogen concentration. The first portion of the blocking pattern may have a first thickness, and the second portion of the blocking pattern may have a second thickness. The first thickness may be greater than the second thickness.

[0007] According to some embodiments of the present invention, a semiconductor device may include: a substrate including an active region; a device isolation layer defining an active pattern on the active region, wherein the device isolation layer covers a sidewall of a lower portion of each of the active patterns, and an upper portion of each of the active patterns protrudes over the device isolation layer; a pair of source / drain patterns located in the upper portion of each of the active patterns; a channel pattern located between the pair of source / drain patterns; a gate electrode intersecting the channel pattern and extending along a first direction; and gate spacers located on opposite sidewalls of the gate electrodes and extending together with the gate electrodes along the first direction. A gate dielectric pattern is located between the gate electrode and the channel pattern, and between the gate electrode and the gate spacer; a gate overlay pattern is located on the top surface of the gate electrode and extends along a first direction with the gate electrode; a first interlayer insulating layer is located on the gate overlay pattern; an active contact extends through the first interlayer insulating layer and is electrically connected to at least one of the paired source / drain patterns; a first metal layer is located in a second interlayer insulating layer on the first interlayer insulating layer; a second metal layer is located in a third interlayer insulating layer on the second interlayer insulating layer; and an etch stop layer is located between the second and third interlayer insulating layers. The first metal layer may include a lower interconnect extending along a second direction intersecting the first direction, the lower interconnect being electrically connected to the active contact. The second metal layer may include an upper interconnect extending along the first direction. The upper interconnect may include a via portion extending through the etch stop layer and contacting the lower interconnect. The via portion may include a blocking pattern and a conductive pattern located on the blocking pattern. The blocking pattern may include a first portion located between the conductive pattern and the third interlayer insulating layer and a second portion located between the conductive pattern and the lower interconnect. The first part of the blocking pattern can have a first nitrogen concentration, and the second part of the blocking pattern can have a second nitrogen concentration. The first nitrogen concentration can be greater than the second nitrogen concentration.

[0008] According to some embodiments of the present invention, a method for manufacturing a semiconductor device may include the following steps: forming a transistor on a substrate; forming a first interlayer insulating layer on the transistor; forming a lower interconnect in the first interlayer insulating layer; forming an etch stop layer on the first interlayer insulating layer and the lower interconnect; forming a second interlayer insulating layer on the etch stop layer; and forming an upper interconnect in the second interlayer insulating layer. The steps of forming the upper interconnect may include: patterning a second interlayer insulating layer to form an interconnect via extending through the second interlayer insulating layer and an etch stop layer to expose a portion of the upper surface (e.g., top surface) of the lower interconnect; selectively forming a metal deposition suppression layer on said portion of the upper surface of the lower interconnect; forming a first barrier layer in the interconnect via, the first barrier layer being formed on the sidewalls (e.g., inner sidewalls) of the interconnect via, excluding the metal deposition suppression layer; selectively removing the metal deposition suppression layer to re-expose said portion of the upper surface of the lower interconnect; forming a second barrier layer in the interconnect via having a lower resistivity than the first barrier layer, the second barrier layer covering said portion of the upper surface of the lower interconnect; and forming a conductive layer in the interconnect via on the second barrier layer (e.g., forming a conductive layer filling the interconnect on the second barrier layer). Attached Figure Description

[0009] The inventive concept will become clearer when taken into consideration the accompanying drawings and detailed description.

[0010] Figure 1 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention.

[0011] Figure 2A , Figure 2B , Figure 2C and Figure 2D They are respectively along Figure 1 A sectional view taken from lines A-A', B-B', C-C', and D-D'.

[0012] Figure 3 yes Figure 2A An enlarged sectional view of region "M".

[0013] Figure 4A It is shown Figure 3 A graph showing the results of elemental analysis along the fourth direction for the via portion of the upper interconnect.

[0014] Figure 4B It is shown Figure 3 A graph showing the results of elemental analysis along the fifth direction for the via portion of the upper interconnect.

[0015] Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention.

[0016] Figure 6 , Figure 8A , Figure 10A , Figure 12A and Figure 14A They are respectively along Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 A sectional view taken by line A-A'.

[0017] Figure 8B , Figure 10B , Figure 12B and Figure 14B They are respectively along Figure 7 , Figure 9 , Figure 11 and Figure 13 The sectional view taken by line B-B'.

[0018] Figure 10C , Figure 12C and Figure 14C They are respectively along Figure 9 , Figure 11 and Figure 13 A sectional view taken by line C-C'.

[0019] Figure 10D , Figure 12D and Figure 14D They are respectively along Figure 9 , Figure 11 and Figure 13 A sectional view taken by line D-D'.

[0020] Figures 15 to 19 This is used to illustrate methods for forming interconnects according to some embodiments of the present invention. Figure 14A An enlarged sectional view of region "M".

[0021] Figures 20 to 29 These are semiconductor devices used to illustrate some embodiments of the concept according to the present invention. Figure 2A An enlarged sectional view of region "M".

[0022] Figure 30 These are semiconductor devices used to illustrate some embodiments of the concept according to the present invention. Figure 2A An enlarged sectional view of region "N".

[0023] Figure 31A , Figure 31B , Figure 31C and Figure 31DThese are semiconductor devices used to illustrate some embodiments of the concept according to the present invention, respectively along... Figure 1 A sectional view taken from lines A-A', B-B', C-C', and D-D'.

[0024] Figure 32 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention.

[0025] Figure 33A , Figure 33B , Figure 33C and Figure 33D They are respectively along Figure 32 A sectional view taken from lines A-A', B-B', C-C', and D-D'.

[0026] Figures 34 to 36 This is for illustrating some embodiments of a semiconductor device according to the present invention. Figure 1 A sectional view taken by line C-C'. Detailed Implementation

[0027] Figure 1 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention. Figure 2A , Figure 2B , Figure 2C and Figure 2D They are respectively along Figure 1 A sectional view taken from lines A-A', B-B', C-C', and D-D'. Figure 3 yes Figure 2A An enlarged sectional view of region "M".

[0028] Reference Figure 1 and Figures 2A to 2D The logic unit LC can be disposed on the substrate 100. In this specification, the logic unit LC can refer to a logic element (e.g., an inverter, a flip-flop, etc.) used to perform a specific function. The logic unit LC can also refer to a standard cell. In other words, the logic unit LC can include transistors constituting the logic element and interconnects connecting the transistors to each other.

[0029] The substrate 100 may include a first active region PR and a second active region NR. In some embodiments, the first active region PR may be a PMOSFET region, and the second active region NR may be an NMOSFET region. The substrate 100 may be a semiconductor substrate comprising, for example, silicon, germanium, or silicon-germanium, or may be a compound semiconductor substrate. In some embodiments, the substrate 100 may be a silicon substrate.

[0030] The first active region PR and the second active region NR may be defined by a second trench TR2 formed in the upper portion of the substrate 100. The second trench TR2 may be disposed between the first active region PR and the second active region NR. The first active region PR and the second active region NR may be spaced apart from each other along a first direction D1 and the second trench TR2 may be disposed between the first active region PR and the second active region NR. Each of the first active region PR and the second active region NR may extend along a second direction D2 that intersects the first direction D1. As used herein, “element A extends along direction X” (or similar language) means that element A extends longitudinally along direction X. The term “intersecting” as used herein may be interchanged with “traverse”.

[0031] A first active pattern AP1 can be disposed on a first active region PR, and a second active pattern AP2 can be disposed on a second active region NR. The first active pattern AP1 and the second active pattern AP2 can extend parallel to each other along a second direction D2. The first active pattern AP1 and the second active pattern AP2 can be portions of the substrate 100 protruding in a vertical direction (i.e., a third direction D3). A first trench TR1 can be defined between adjacent first active patterns AP1 and between adjacent second active patterns AP2. The first trench TR1 can be shallower than the second trench TR2.

[0032] The device isolation layer ST can fill the first trench TR1 and the second trench TR2. The device isolation layer ST can be covered, for example, with a silicon oxide layer. The upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 can protrude vertically above the device isolation layer ST (see...). Figure 2D Each of the upper portions of the first active pattern AP1 and the second active pattern AP2 may have a fin shape. The device isolation layer ST may not cover the upper portions of the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may cover the sidewalls of the lower portion of the first active pattern AP1 and the lower portion of the second active pattern AP2. As used herein, "element A covers element B" (or similar language) means that element A is on and / or stacked with element B, but does not necessarily mean that element A completely covers element B.

[0033] A first source / drain pattern SD1 can be disposed in the upper portion of a first active pattern AP1. The first source / drain pattern SD1 can be a doped region (i.e., a region including dopant) having a first conductivity type (e.g., P-type). A first channel pattern CH1 can be disposed between a pair of first source / drain patterns SD1. A second source / drain pattern SD2 can be disposed in the upper portion of a second active pattern AP2. The second source / drain pattern SD2 can be a doped region (i.e., a region including dopant) having a second conductivity type (e.g., N-type). A second channel pattern CH2 can be disposed between a pair of second source / drain patterns SD2.

[0034] The first source / drain pattern SD1 and the second source / drain pattern SD2 may comprise epitaxial patterns formed by, for example, a selective epitaxial growth (SEG) process. In some embodiments, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be coplanar with the top surfaces of the first channel pattern CH1 and the second channel pattern CH2. In some embodiments, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the top surfaces of the first channel pattern CH1 and the second channel pattern CH2. As used herein, "component A is higher than component B" (or similar language) means that component A is higher than component B relative to the substrate, and therefore, the substrate is closer to component B than component A.

[0035] The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) whose lattice constant is greater than that of the semiconductor element of the substrate 100. Therefore, the first source / drain pattern SD1 may provide compressive stress to the first channel pattern CH1. For example, the second source / drain pattern SD2 may include the same semiconductor element as the semiconductor element of the substrate 100 (e.g., silicon).

[0036] The gate electrode GE may extend along a first direction D1 to intersect with the first active pattern AP1 and the second active pattern AP2. The gate electrode GE may be arranged along a second direction D2 at a specific pitch. In some embodiments, such as Figure 1As shown, the gate electrodes GE can be spaced evenly apart from each other along the second direction D2. The gate electrodes GE can be vertically stacked with the first channel pattern CH1 and the second channel pattern CH2. Each of the gate electrodes GE can extend around the top surface and two sidewalls of each of the first channel pattern CH1 and the second channel pattern CH2, or on the top surface and two sidewalls of each of the first channel pattern CH1 and the second channel pattern CH2. As used herein, "element A is vertically stacked with element B" (or similar language) means that at least one vertical line intersecting both element A and element B can be drawn. Furthermore, "element A surrounds element B" (or similar language) means that element A is at least partially located around element B, but does not necessarily mean that element A completely surrounds element B.

[0037] Refer again Figure 2D The gate electrode GE can be disposed on the first top surface TS1 of the first channel pattern CH1 and at least one first sidewall SW1 of the first channel pattern CH1. The gate electrode GE can be disposed on the second top surface TS2 of the second channel pattern CH2 and at least one second sidewall SW2 of the second channel pattern CH2. In other words, the transistor according to some embodiments of the present invention can be a three-dimensional (3D) field-effect transistor (e.g., a fin field-effect transistor (FinFET)) in which the gate electrode GE three-dimensionally surrounds the channel patterns CH1 and CH2.

[0038] Still refer to Figure 1 and Figures 2A to 2D A pair of gate spacers GS may be disposed on opposite sidewalls of each of the gate electrodes GE. The gate spacers GS may extend along the gate electrode GE in a first direction D1. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be coplanar with the top surface of the first interlayer insulating layer 110, which will be described later. The gate spacers GS may include, for example, SiCN, SiCON, and / or SiN. In some embodiments, each of the gate spacers GS may have a multilayer structure formed of at least two of SiCN, SiCON, and SiN. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] A gate cover pattern GP may be disposed on each of the gate electrodes GE. The gate cover pattern GP may extend along the gate electrode GE in a first direction D1. The gate cover pattern GP may include, for example, a material having etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described later. For example, the gate cover pattern GP may include, for example, SiON, SiCN, SiCON and / or SiN.

[0040] A gate dielectric pattern GI can be disposed between the gate electrode GE and the first active pattern AP1, and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI can extend along the bottom surface of the gate electrode GE on the gate dielectric pattern GI. For example, the gate dielectric pattern GI can cover the first top surface TS1 and the first sidewall SW1 of the first channel pattern CH1. The gate dielectric pattern GI can cover the second top surface TS2 and the second sidewall SW2 of the second channel pattern CH2. The gate dielectric pattern GI can cover the top surface of the device isolation layer ST below the gate electrode GE (see...). Figure 2D ).

[0041] In some embodiments, the gate dielectric pattern GI may include, for example, a high-k dielectric material whose dielectric constant is higher than that of silicon oxide (e.g., silicon dioxide). High-k dielectric materials may include hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0042] The gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern may be disposed on the gate dielectric pattern GI and may be adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal pattern may include work function metal for adjusting the threshold voltage of the transistor. The desired threshold voltage can be obtained by adjusting the thickness and composition of the first metal pattern.

[0043] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In some embodiments, in addition to nitrogen (N), the first metal pattern may include titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and / or molybdenum (Mo). In some embodiments, the first metal pattern may also include carbon (C). In some embodiments, the first metal pattern may include a plurality of stacked work function metal layers.

[0044] The second metal pattern may include a metal having a lower resistance than the first metal pattern. For example, the second metal pattern may include tungsten (W), aluminum (Al), titanium (Ti), and / or tantalum (Ta).

[0045] A first interlayer insulating layer 110 may be disposed on a substrate 100. The first interlayer insulating layer 110 may cover a gate spacer GS and a first source / drain pattern SD1 and a second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate overlay pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 and the gate overlay pattern GP. A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. For example, each of the first to fourth interlayer insulating layers 140 may include a silicon oxide layer.

[0046] A pair of isolation structures DB can be respectively disposed on opposite sides of the logic cell LC, spaced apart along the second direction D2, or adjacent to the opposite sides of the logic cell LC, spaced apart along the second direction D2. The isolation structure DB can extend parallel to the gate electrode GE along the first direction D1. The pitch between the isolation structure DB and its adjacent gate electrode GE can be equal to the pitch between the gate electrodes GE. In some embodiments, such as... Figure 1 As shown, the isolation structure DB can be spaced apart from the nearest gate electrode GE in the second direction D2 by a distance that can be equal to the distance between two adjacent gate electrodes GE.

[0047] The isolation structure DB can penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and can extend into the first active pattern AP1 and the second active pattern AP2. The isolation structure DB can penetrate the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2. The isolation structure DB isolates the first active region PR and the second active region NR of the logic cell LC from the active regions of adjacent logic cells.

[0048] The active contact AC can penetrate the second interlayer insulation layer 120 and the first interlayer insulation layer 110 to be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. Each of the active contacts AC can be disposed between a pair of gate electrodes GE.

[0049] In some embodiments, the active contact AC can be a self-aligning contact. In other words, the active contact AC can be formed to be self-aligned using the gate cover pattern GP and the gate spacer GS. For example, the active contact AC can cover at least a portion of the sidewall of the gate spacer GS. Even if not shown in the figures, the active contact AC can also cover a portion of the top surface of the gate cover pattern GP.

[0050] The silicide pattern SC can be disposed between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to the source / drain pattern SD1 or SD2 through the silicide pattern SC. The silicide pattern SC can include metal silicides, and can include, for example, titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and / or cobalt silicide.

[0051] The gate contact GC can penetrate the second interlayer insulating layer 120 and the gate cover pattern GP to connect (e.g., electrically connect) to the gate electrode GE. In some embodiments, such as Figure 2D As shown, the gate contact GC can contact the gate electrode GE. Figure 1 As shown, when viewed in a plan view, the gate contact GC can be disposed between the first active region PR and the second active region NR. The bottom surface of the gate contact GC can contact the top surface of the gate electrode GE. The top surface of the gate contact GC can be coplanar with the top surface of the second interlayer insulating layer 120.

[0052] Each of the active contact AC and the gate contact GC may include a first conductive pattern FM1 and a first blocking pattern BM1 surrounding the first conductive pattern FM1. For example, the first conductive pattern FM1 may include aluminum, copper, tungsten, molybdenum, ruthenium, and / or cobalt. The first blocking pattern BM1 may cover the bottom surface and sidewalls of the first conductive pattern FM1. The first blocking pattern BM1 may include a metal layer / metal nitride layer (e.g., a metal layer and a metal nitride layer stacked on the metal layer). The metal layer may include, for example, a titanium layer, a tantalum layer, a tungsten layer, a nickel layer, a cobalt layer, and / or a platinum layer. The metal nitride layer may include, for example, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, and / or a platinum nitride (PtN) layer.

[0053] The first metal layer M1 can be disposed in the third interlayer insulating layer 130. The first metal layer M1 may include a first lower interconnect LIL1, a second lower interconnect LIL2, and a lower via VI. The lower via VI can be disposed below the first lower interconnect LIL1 and the second lower interconnect LIL2.

[0054] The first lower interconnect LIL1 may cross with the logic cell LC and may extend along the second direction D2. Each of the first lower interconnects LIL1 may be a power interconnect. For example, a drain voltage VDD or a source voltage VSS may be applied to the first lower interconnect LIL1.

[0055] Reference Figure 1A first cell boundary CB1 extending along the second direction D2 can be defined at the logic cell LC. A second cell boundary CB2 extending along the second direction D2 at the logic cell LC can be defined on the opposite side of the first cell boundary CB1. A first lower interconnect LIL1 to which the drain voltage VDD (i.e., the power supply voltage) is applied can be disposed on the first cell boundary CB1. The first lower interconnect LIL1 to which the drain voltage VDD is applied can extend along the first cell boundary CB1 in the second direction D2. A first lower interconnect LIL1 to which the source voltage VSS (i.e., the ground voltage) is applied can be disposed on the second cell boundary CB2. The first lower interconnect LIL1 to which the source voltage VSS is applied can extend along the second cell boundary CB2 in the second direction D2.

[0056] The second lower interconnect LIL2 can be disposed between the first lower interconnect LIL1 to which the drain voltage VDD is applied and the first lower interconnect LIL1 to which the source voltage VSS is applied. The second lower interconnects LIL2 can extend parallel to each other along the second direction D2. When viewed in a plan view, each of the second lower interconnects LIL2 can have a line shape or a strip shape. The second lower interconnects LIL2 can be arranged along the first direction D1 at a specific pitch. In some embodiments, such as Figure 1 As shown, the second lower interconnects LIL2 can be spaced evenly apart from each other along the first direction D1.

[0057] Refer again Figure 2C The line width of each of the first lower interconnects LIL1 can be a first width W1 in the first direction D1. The line width of each of the second lower interconnects LIL2 can be a second width W2 in the first direction D1. The second width W2 can be smaller than the first width W1. For example, the second width W2 can be less than 12 nm. The first width W1 can be greater than 12 nm.

[0058] Each of the first lower interconnect LIL1 and the second lower interconnect LIL2 may include a second conductive pattern FM2 and a second barrier pattern BM2 surrounding the second conductive pattern FM2. The cross-section of the second barrier pattern BM2 may have a U-shape. The top surface of the second barrier pattern BM2 may be substantially coplanar with the top surface of the third interlayer insulating layer 130. In some embodiments, the top surface of the second barrier pattern BM2 may be lower than the top surface of the third interlayer insulating layer 130.

[0059] The second barrier pattern BM2 can improve the adhesion between the lower interconnect LIL1 or LIL2 and the third interlayer insulation layer 130. The second barrier pattern BM2 can be used as a barrier to reduce or prevent the diffusion of metallic elements from the second conductive pattern FM2 into the third interlayer insulation layer 130. The second barrier pattern BM2 may include, for example, a tantalum nitride (TaN) layer, a titanium nitride (TiN) layer, a tantalum oxide (TaO) layer, a titanium oxide (TiO) layer, a manganese nitride (MnN) layer, and / or a manganese oxide (MnO) layer.

[0060] The second conductive pattern FM2 may be disposed on the second barrier pattern BM2. The second barrier pattern BM2 may cover the bottom surface and sidewalls of the second conductive pattern FM2. The second conductive pattern FM2 may have the largest volume among the metal patterns constituting each of the lower interconnects LIL1 or LIL2. For example, the second conductive pattern FM2 may include copper (Cu), ruthenium (Ru), cobalt (Co), tungsten (W), or molybdenum (Mo).

[0061] Even if not shown in the accompanying drawings, a metallic overlay pattern may be further disposed on the second conductive pattern FM2. The metallic overlay pattern may be a thin layer covering the top surface of the second conductive pattern FM2 and having a uniform thickness. The metallic overlay pattern may include ruthenium (Ru), cobalt (Co), or graphene.

[0062] Some of the lower vias VI can be positioned between the active contact AC and the first lower interconnect LIL1 and the second lower interconnect LIL2. Others of the lower vias VI can be positioned between the gate contact GC and the second lower interconnect LIL2.

[0063] An etch stop layer (ESL) can be disposed between the third interlayer insulating layer 130 and the fourth interlayer insulating layer 140. The ESL can directly cover the first lower interconnect LIL1 and the second lower interconnect LIL2. The ESL can cover the top surface of the third interlayer insulating layer 130. In some embodiments, such as... Figure 2C As shown, the etch stop layer ESL can contact the upper surfaces of some of the first lower interconnects LIL1 and the second lower interconnects LIL2, as well as the upper surface of the third interlayer insulating layer 130.

[0064] An etch stop layer (ESL) may comprise a single layer or multiple stacked layers. In some embodiments, the etch stop layer (ESL) may comprise a metal oxide layer and / or a metal nitride layer comprising, for example, Al, Zr, Y, Hf, and / or Mo. In some embodiments, the etch stop layer (ESL) may comprise a silicon oxide layer and / or a silicon nitride layer.

[0065] The second metal layer M2 can be disposed within the fourth interlayer insulating layer 140. The second metal layer M2 may include upper interconnect lines UIL. The upper interconnect lines UIL may extend along the first direction D1 and may extend parallel to each other. Figure 1 As shown, when viewed in a plan view, each of the upper interconnects UIL can have a line shape or a strip shape. The upper interconnects UIL can be arranged along the second direction D2.

[0066] The upper interconnect UIL may include a line portion (LIP) and a via portion (VIP). The line portion (LIP) may be disposed in the upper portion of the fourth interlayer insulating layer 140 and may extend along the first direction D1. The via portion (VIP) may be disposed in the lower portion of the fourth interlayer insulating layer 140 and may extend from the line portion (LIP) toward the first metal layer M1. In some embodiments, the via portion (VIP) may be a via disposed between the line portion (LIP) and the first metal layer M1 to connect the line portion (LIP) to the first metal layer M1. The via portion (VIP) may penetrate the fourth interlayer insulating layer 140 and the etch stop layer (ESL) to extend toward the first metal layer M1.

[0067] Line portions (LIPs) and via portions (VIPs) can be connected to each other within a single body to form a single conductor (i.e., a single on-line interconnect (UIL). Line portions (LIPs) and via portions (VIPs) can be formed into a single on-line interconnect (UIL) using a dual damascene process.

[0068] Reference Figure 3 The upper interconnect UIL is described in more detail. The upper interconnect UIL may include a third blocking pattern BM3 and a third conductive pattern FM3 located on the third blocking pattern BM3.

[0069] The third barrier pattern BM3 can be used as a barrier to reduce or prevent the diffusion of metallic elements from the third conductive pattern FM3 into the fourth interlayer insulating layer 140. The third barrier pattern BM3 may include a first barrier layer BAP1 and a second barrier layer BAP2.

[0070] Reference Figure 3 The first barrier layer BAP1 may be disposed between the third conductive pattern FM3 and the fourth interlayer insulating layer 140, and may extend in the vertical direction (i.e., the third direction D3). The first barrier layer BAP1 may not be disposed between the third conductive pattern FM3 and the second lower interconnect LIL2. In other words, the first barrier layer BAP1 may not be included in the portion extending along the second direction D2 between the third conductive pattern FM3 and the second lower interconnect LIL2.

[0071] The second barrier layer BAP2 may be disposed between the first barrier layer BAP1 and the third conductive pattern FM3, and may include a portion extending along a third direction D3. Furthermore, the second barrier layer BAP2 may be disposed between the third conductive pattern FM3 and the second lower interconnect LIL2, and may extend along a second direction D2. In other words, the cross-section of the second barrier layer BAP2 may have a U-shape. The second barrier layer BAP2 may cover the second top surface TOS2 of the second lower interconnect LIL2. In other words, the third conductive pattern FM3 can be electrically connected to the second lower interconnect LIL2 through the second barrier layer BAP2. In some embodiments, the second barrier layer BAP2 may contact the second top surface TOS2 of the second lower interconnect LIL2.

[0072] The first barrier layer BAP1 may include, for example, a tantalum nitride (TaN) layer, a titanium nitride (TiN) layer, a tantalum oxide (TaO) layer, a titanium oxide (TiO) layer, a manganese nitride (MnN) layer, and / or a manganese oxide (MnO) layer. The second barrier layer BAP2 may include a material whose resistivity is lower than that of the first barrier layer BAP1. The second barrier layer BAP2 may include, for example, a tantalum layer, a titanium layer, a tungsten layer, a nickel layer, a cobalt layer, a platinum layer, and / or a graphene layer. For example, in some embodiments, the first barrier layer BAP1 may be a tantalum nitride (TaN) layer, and the second barrier layer BAP2 may be a tantalum (Ta) layer. As used herein, the term "resistivity" may be used interchangeably with "resistivity coefficient".

[0073] In some embodiments, as will be described later Figure 4A As shown, the first barrier layer BAP1 may contain a relatively high concentration of nitrogen (N). The concentration of nitrogen (N) in the first barrier layer BAP1 may be in the range of 10 at% to 60 at%. In some embodiments, the concentration of nitrogen (N) in the first barrier layer BAP1 may be in the range of 40 at% to 60 at%.

[0074] As will be described later Figure 4B As shown, the second barrier layer BAP2 may contain a relatively low concentration of nitrogen (N), or may contain no nitrogen (N) at all. The concentration of nitrogen (N) in the second barrier layer BAP2 may be in the range of 0 at% to 5 at%. In other words, the second barrier layer BAP2 may contain no nitrogen (N), or may contain nitrogen (N) with a concentration of less than 5 at%. Because the second barrier layer BAP2 contains no nitrogen (N) or contains a small amount of nitrogen (N), the resistivity of the second barrier layer BAP2 may be lower than that of the first barrier layer BAP1.

[0075] The third conductive pattern FM3 may include a first conductive layer MEP1 and a second conductive layer MEP2. The first conductive layer MEP1 may be disposed between the third barrier pattern BM3 and the second conductive layer MEP2. The cross-section of the first conductive layer MEP1 may have a U-shape. The first conductive layer MEP1 can improve the adhesion between the second conductive layer MEP2 and the third barrier pattern BM3.

[0076] Among the conductive layers constituting the interconnect UIL, the second conductive layer MEP2 may have the largest volume. The second conductive layer MEP2 may contain a metal with relatively low resistivity. The first conductive layer MEP1 and the second conductive layer MEP2 may comprise different metals selected from the group consisting of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), aluminum (Al), silver (Ag), and gold (Au). For example, in some embodiments, the first conductive layer MEP1 may comprise cobalt (Co), and the second conductive layer MEP2 may comprise copper (Cu).

[0077] The first barrier layer BAP1 may have a first thickness T1 in the second direction D2. The second barrier layer BAP2 may have a second thickness T2 in the third direction D3 on the second top surface TOS2 of the second lower interconnect LIL2. The first conductive layer MEP1 may have a third thickness T3 in the third direction D3 on the second top surface TOS2 of the second lower interconnect LIL2. The first thickness T1 may be greater than the second thickness T2. The third thickness T3 may be greater than the first thickness T1. For example, the first thickness T1 may be in the range of 1 nm to 2 nm. The second thickness T2 may be less than 1 nm. The third thickness T3 may be in the range of 2 nm to 3 nm.

[0078] The top surface of the second lower interconnect LIL2 may include a first top surface TOS1 and a second top surface TOS2. The first top surface TOS1 may be located at a first horizontal level LV1, and the second top surface TOS2 may be located at a second horizontal level LV2, which is lower than the first horizontal level LV1. Because the second top surface TOS2 is lower than the first top surface TOS1, the first recess RS1 may be defined in the upper portion of the second lower interconnect LIL2. In other words, the bottom of the first recess RS1 may be the second top surface TOS2. The etch stop layer ESL may cover the first top surface TOS1 of the second lower interconnect LIL2.

[0079] The lower portion of the via portion VIP of the upper interconnect UIL can penetrate the etch stop layer ESL and can be disposed in the first recess RS1. The first barrier layer BAP1 can have a first bottom surface BS1. The first bottom surface BS1 can be spaced apart from the second top surface TOS2 along the third direction D3. The first bottom surface BS1 can be higher than the second top surface TOS2.

[0080] The second barrier layer BAP2 can fill the first recess RS1. The second barrier layer BAP2 can have a second bottom surface BS2. The second bottom surface BS2 can be located at the same level as the second top surface TOS2 (i.e., the second level LV2). In other words, the second bottom surface BS2 can completely cover the second top surface TOS2. The second barrier layer BAP2 can cover the inner wall of the first recess RS1. The second barrier layer BAP2 can cover the first bottom surface BS1 of the first barrier layer BAP1.

[0081] According to an embodiment of the present invention, the upper interconnect UIL and the lower interconnect LIL1 or LIL2 can be electrically connected to each other through a second barrier layer BAP2 having a relatively low resistivity (e.g., a second barrier layer BAP2 having a lower resistivity than the first barrier layer BAP1), instead of through a first barrier layer BAP1 having a relatively high resistivity (e.g., a first barrier layer BAP1 having a higher resistivity than the second barrier layer BAP2). As a result, the contact resistance between the upper interconnect UIL and the lower interconnect LIL1 or LIL2 can be reduced, thereby improving the electrical characteristics of the semiconductor device.

[0082] Meanwhile, a first barrier layer BAP1 that can effectively suppress or block the diffusion of metal can be disposed between the upper interconnect UIL and the fourth interlayer insulation layer 140, thereby effectively reducing or preventing the diffusion of metal from the upper interconnect UIL into the fourth interlayer insulation layer 140.

[0083] Figure 4A It is shown Figure 3 The curve showing the results of element analysis of the via portion VIP of the upper interconnect UIL along the fourth direction D4. Figure 4B It is shown Figure 3 The graph shows the results of elemental analysis of the via portion VIP of the upper interconnect UIL along the fifth direction D5. Figure 4A and Figure 4B The results are shown when the first barrier layer BAP1 is a tantalum nitride (TaN) layer, the second barrier layer BAP2 is a tantalum (Ta) layer, the first conductive layer MEP1 is a cobalt (Co) layer, the second conductive layer MEP2 is a copper (Cu) layer, and the second conductive pattern FM2 is a copper (Cu) layer. The fourth direction D4 is the direction from the second conductive layer MEP2 to the fourth interlayer insulating layer 140, and is perpendicular to the third direction D3. The fifth direction D5 is the direction from the second conductive layer MEP2 to the second lower interconnect LIL2, and is parallel to the third direction D3.

[0084] Reference Figure 4ACopper (Cu), cobalt (Co), tantalum (Ta), and nitrogen (N) are sequentially detected along the fourth direction D4, starting from the center of the via portion VIP. This means that the elements of the second conductive layer MEP2, the first conductive layer MEP1, the second barrier layer BAP2, and the first barrier layer BAP1 are detected sequentially.

[0085] Reference Figure 4B Starting from the center of the via portion VIP, copper (Cu), cobalt (Co), tantalum (Ta), and copper (Cu) are sequentially detected along the fifth direction D5. This means that the elements of the second conductive layer MEP2, the first conductive layer MEP1, the second barrier layer BAP2, and the second conductive pattern FM2 of the second lower interconnect LIL2 are sequentially detected. Because the first barrier layer BAP1 does not exist along the fifth direction D5, therefore... Figure 4B As shown, neither tantalum (Ta) nor nitrogen (N) was detected together. Because nitrogen (N) is absent along the fifth direction D5, the via portion VIP... Figure 4B The resistivity of the corresponding first part can be compared with that of the via part VIP. Figure 4A The corresponding second part has low resistivity.

[0086] Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention. Figure 6 , Figure 8A , Figure 10A , Figure 12A and Figure 14A They are respectively along Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 A sectional view taken by line A-A'. Figure 8B , Figure 10B , Figure 12B and Figure 14B They are respectively along Figure 7 , Figure 9 , Figure 11 and Figure 13 The sectional view taken by line B-B'. Figure 10C , Figure 12C and Figure 14C They are respectively along Figure 9 , Figure 11 and Figure 13 A sectional view taken by line C-C'. Figure 10D , Figure 12D and Figure 14D They are respectively along Figure 9 , Figure 11 and Figure 13 A sectional view taken by line D-D'. Figures 15 to 19 This is used to illustrate methods for forming interconnects according to some embodiments of the present invention. Figure 14A An enlarged sectional view of region "M".

[0087] Reference Figure 5 and Figure 6 A substrate 100 can be configured including a first active region PR and a second active region NR. The first active region PR and the second active region NR can define logic cells LC on the substrate 100.

[0088] The substrate 100 can be patterned to form a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 can be formed on a first active region PR, and the second active pattern AP2 can be formed on a second active region NR. A first trench TR1 can be formed between the first active patterns AP1 and between the second active patterns AP2. The substrate 100 can be patterned to form a second trench TR2 between the first active region PR and the second active region NR. The second trench TR2 can be deeper than the first trench TR1.

[0089] A device isolation layer ST can be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. The device isolation layer ST may include an insulating material such as a silicon oxide layer. The device isolation layer ST can be recessed until the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 are exposed. Therefore, the upper portions of the first active pattern AP1 and the upper portions of the second active pattern AP2 can protrude vertically above the device isolation layer ST.

[0090] Reference Figure 7 , Figure 8A and Figure 8B The sacrificial pattern PP can be formed to intersect with the first active pattern AP1 and the second active pattern AP2. The sacrificial pattern PP can have a line shape or a strip shape extending along the first direction D1. The sacrificial pattern PP can be arranged along the second direction D2 at a specific pitch. In some embodiments, such as Figure 7 As shown, the sacrificial patterns PP can be spaced evenly apart from each other along the second direction D2.

[0091] For example, the step of forming the sacrificial pattern PP may include: forming a sacrificial layer on the entire top surface of the substrate 100, forming a hard mask pattern MA on the sacrificial layer, and using the hard mask pattern MA as an etch mask to pattern the sacrificial layer. The sacrificial layer may include, for example, polysilicon.

[0092] A pair of gate spacers GS can be formed on the opposite sidewalls of each of the sacrificial patterns PP. The step of forming the gate spacers GS may include: conformally forming a gate spacer layer over the entire top surface of the substrate 100, and anisotropically etching the gate spacer layer. For example, the gate spacer layer may include SiCN, SiCON, and / or SiN. In some embodiments, the gate spacer layer may be formed from a multilayer comprising at least two of SiCN, SiCON, and SiN.

[0093] Reference Figure 9 and Figures 10A to 10D A first source / drain pattern SD1 can be formed in the upper portion of the first active pattern AP1. A pair of first source / drain patterns SD1 can be formed on the opposite side of each of the sacrificial patterns PP, or a pair of first source / drain patterns SD1 can be formed adjacent to the opposite side of each of the sacrificial patterns PP.

[0094] Specifically, the upper portion of the first active pattern AP1 can be etched using a hard mask pattern MA and a gate spacer GS as an etching mask to form the first recessed region RSR1. The device isolation layer ST between the first active patterns AP1 can be recessed simultaneously with etching the upper portion of the first active pattern AP1 (see...). Figure 10C ).

[0095] In some embodiments, a first source / drain pattern SD1 can be formed by performing a selective epitaxial growth (SEG) process using the inner surface of the first recessed region RSR1 of the first active pattern AP1 as a seed layer. Because the first source / drain patterns SD1 are formed, a first channel pattern CH1 can be defined between a pair of first source / drain patterns SD1. For example, the SEG process can include a chemical vapor deposition (CVD) process and / or a molecular beam epitaxy (MBE) process. The first source / drain patterns SD1 can include semiconductor elements (e.g., SiGe) whose lattice constant is greater than that of the semiconductor elements of the substrate 100. In some embodiments, each of the first source / drain patterns SD1 can be formed from multiple stacked semiconductor layers.

[0096] In some embodiments, dopant may be added in situ (e.g., implanted or implanted) into the first source / drain pattern SD1 during the SEG process for forming the first source / drain pattern SD1. In some embodiments, dopant may be implanted or implanted into the first source / drain pattern SD1 after the SEG process for forming the first source / drain pattern SD1. The first source / drain pattern SD1 may be doped with dopant to have a first conductivity type (e.g., P-type).

[0097] A second source / drain pattern SD2 can be formed in the upper portion of the second active pattern AP2. A pair of second source / drain patterns SD2 can be formed on the opposite side of each of the sacrificial patterns PP, or a pair of second source / drain patterns SD2 can be formed adjacent to the opposite side of each of the sacrificial patterns PP.

[0098] Specifically, the upper portion of the second active pattern AP2 can be etched using a hard mask pattern MA and a gate spacer GS as an etching mask to form a second recessed region RSR2. In some embodiments, a second source / drain pattern SD2 can be formed by performing a SEG process using the inner surface of the second recessed region RSR2 of the second active pattern AP2 as a seed layer. Because the second source / drain pattern SD2 is formed, a second channel pattern CH2 can be defined between a pair of second source / drain patterns SD2. For example, the second source / drain pattern SD2 may include the same semiconductor element as the semiconductor element of the substrate 100 (e.g., silicon). The second source / drain pattern SD2 can be doped with a dopant to have a second conductivity type (e.g., N-type).

[0099] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed sequentially using different processes. In other words, the first source / drain pattern SD1 can be formed without simultaneously with the second source / drain pattern SD2.

[0100] Reference Figure 11 and Figures 12A to 12D A first interlayer insulating layer 110 can be formed to cover the first source / drain pattern SD1 and the second source / drain pattern SD2, the hard mask pattern MA, and the gate spacer GS. For example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0101] The first interlayer insulating layer 110 can be planarized until the top surface of the sacrificial pattern PP is exposed. The planarization process of the first interlayer insulating layer 110 can be performed using, for example, an etch-back process and / or a chemical mechanical polishing (CMP) process. The hard mask pattern MA can be completely removed during the planarization process. As a result, the top surface of the first interlayer insulating layer 110 can be substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0102] The gate electrode GE can be used to replace the sacrificial pattern PP. Specifically, the exposed sacrificial pattern PP can be selectively removed. Empty spaces can be formed by removing the sacrificial pattern PP. A gate dielectric pattern GI, a gate electrode GE, and a gate cover pattern GP can be formed in each of the empty spaces. The gate electrode GE can include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern can be formed of a work function metal capable of adjusting the threshold voltage of the transistor, and the second metal pattern can be formed of a low-resistance metal.

[0103] A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include, for example, a silicon oxide layer. Active contacts AC may be formed in the second interlayer insulating layer 120 and the first interlayer insulating layer 110. Silicate patterns SC may be formed in the upper portions of the first source / drain pattern SD1 and the second source / drain pattern SD2. The active contacts AC may penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 to be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 via the silicide pattern SC. A gate contact GC may be formed. The gate contact GC may penetrate the second interlayer insulating layer 120 and the gate cover pattern GP to be electrically connected to the gate electrode GE.

[0104] A pair of isolation structures DB can be formed on opposite sides of the logic cell LC, spaced apart along the second direction D2, or a pair of isolation structures DB can be formed adjacent to opposite sides of the logic cell LC, spaced apart along the second direction D2. The isolation structures DB can be formed at the locations of the two gate electrodes GE on the opposite side of the logic cell LC or at the locations of the two gate electrodes GE adjacent to the opposite side of the logic cell LC. For example, the step of forming the isolation structure DB may include: forming a hole that penetrates the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and the gate electrodes GE and extends into the first active pattern AP1 and the second active pattern AP2, and filling the hole with an insulating layer.

[0105] Reference Figure 13 and Figures 14A to 14D A third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120. A first metal layer M1 may be formed in the third interlayer insulating layer 130. The step of forming the first metal layer M1 may include forming a first lower interconnect LIL1, a second lower interconnect LIL2, and a lower via VI.

[0106] An etch stop layer (ESL) can be formed on the first metal layer M1. A fourth interlayer insulating layer (ESL) 140 can be formed on the ESL. The fourth interlayer insulating layer 140 can be patterned to form interconnect vias (UIH). The interconnect vias (UIH) can be formed using, for example, photolithography.

[0107] Each of the interconnect vias UIH may include a wire via LIH and a via VIH. A wire via LIH can be formed by recessing the upper portion of the fourth interlayer insulating layer 140. An etching process may be additionally performed on the wire via LIH to form a via VIH extending from the wire via LIH toward the first metal layer M1. The via VIH may expose the top surfaces of the underlying interconnects LIL1 and LIL2.

[0108] Refer again Figure 1 and Figures 2A to 2D The upper interconnect UIL can be formed by filling the interconnect via UIH with a conductive material. For example, the steps of forming the upper interconnect UIL may include: forming a third barrier pattern BM3 in the interconnect via UIH, and forming a third conductive pattern FM3 on the third barrier pattern BM3 that fills (e.g., completely fills) the interconnect via UIH. For example, the upper interconnect UIL can be formed by a dual damascene process.

[0109] Reference Figures 15 to 19 A method for forming interconnect UILs according to the present invention is described in detail. (Refer to...) Figure 15 The via VIH can be formed to extend from the line via LIH toward the second lower interconnect LIL2. In the etching process used to form the via VIH, the upper portion of the second lower interconnect LIL2 can be etched to form the first recess RS1. Therefore, the second lower interconnect LIL2 may include a first top surface TOS1 covered by the etch stop layer ESL and a second top surface TOS2 exposed by the via VIH.

[0110] A metal deposition suppression layer IHL can be formed on the inner surface of the first recess RS1. The step of forming the metal deposition suppression layer IHL may include providing an inhibitor into the interconnect via UIH. The inhibitor may include an organic compound containing carbon (C) as a primary element. The inhibitor can be selectively adsorbed onto the metal layer and may not be adsorbed onto inorganic layers such as silicon oxide or silicon nitride layers. Therefore, the metal deposition suppression layer IHL can be selectively formed only on the exposed surface of the second lower interconnect LIL2. The metal deposition suppression layer IHL may not be formed on the exposed surfaces of the etch stop layer ESL and the fourth interlayer insulating layer 140.

[0111] The metal deposition suppression layer IHL can be formed from a monolayer or a layer with a thickness of less than 1 nm. As described above, the metal deposition suppression layer IHL can be selectively formed only in the first recess RS1. The metal deposition suppression layer IHL can cover the second top surface TOS2 of the second lower interconnect LIL2.

[0112] Reference Figure 16The first barrier layer BAP1 can be formed in the interconnect UIH. The first barrier layer BAP1 may not be formed on the metal deposition suppression layer IHL. In other words, due to the metal deposition suppression layer IHL, the first barrier layer BAP1 can be selectively formed only on the exposed surfaces of the etch stop layer ESL and the fourth interlayer insulating layer 140. The first barrier layer BAP1 may not be formed on the second lower interconnect LIL2.

[0113] For example, the step of forming the first barrier layer BAP1 may include providing a precursor for the first barrier layer BAP1 into the interconnect via UIH. The step of forming the first barrier layer BAP1 may include, for example, using the precursor to perform atomic layer deposition (ALD) and / or chemical vapor deposition (CVD) processes. The precursor may not be adsorbed onto the metal deposition suppression layer IHL. The precursor may be selectively adsorbed only onto the etch stop layer ESL and the fourth interlayer insulating layer 140. Therefore, the first barrier layer BAP1 can be selectively formed on the inner sidewalls of the interconnect via UIH, excluding the first recess RS1. For example, the first barrier layer BAP1 may include a tantalum nitride (TaN) layer, a titanium nitride (TiN) layer, a tantalum oxide (TaO) layer, a titanium oxide (TiO) layer, a manganese nitride (MnN) layer, and / or a manganese oxide (MnO) layer.

[0114] Reference Figure 17 The metal deposition inhibition layer IHL can be selectively removed. For example, the metal deposition inhibition layer IHL may include organic compounds capable of combustion at relatively low temperatures. Therefore, the metal deposition inhibition layer IHL can be removed by performing an ashing process at a high temperature. The surface defining the first recess RS1 of the second lower interconnect LIL2 can be exposed by removing the metal deposition inhibition layer HIL. In other words, the second top surface TOS2 of the second lower interconnect LIL2 can be exposed.

[0115] Reference Figure 18 A second barrier layer BAP2 can be formed in the interconnect via UIH. The second barrier layer BAP2 can be conformally formed on the first barrier layer BAP1. The second barrier layer BAP2 can also be formed on the surface of the second lower interconnect LIL2 exposed by the removal of the metal deposition suppression layer HIL. In other words, the second barrier layer BAP2 can be formed to directly cover the exposed surface of the second lower interconnect LIL2 (e.g., the second top surface TOS2). Simultaneously, the inner sidewall of the interconnect via UIH can be covered by the first barrier layer BAP1. The first barrier layer BAP1 and the second barrier layer BAP2 can constitute a third barrier pattern BM3.

[0116] The second barrier layer BAP2 can be formed of a material whose resistivity is lower than that of the first barrier layer BAP1. For example, the second barrier layer BAP2 may include tantalum, titanium, tungsten, nickel, cobalt, platinum, and / or graphene. In other words, the exposed surface of the second lower interconnect LIL2 can be covered by a metal with low resistivity (e.g., lower than that of the first barrier layer BAP1).

[0117] Reference Figure 19 A third conductive pattern FM3, completely filling the interconnect via UIH, can be formed on the second barrier layer BAP2. The step of forming the third conductive pattern FM3 may include: conformally forming a first conductive layer MEP1 on the second barrier layer BAP2, and forming a second conductive layer MEP2 on the first conductive layer MEP1. For example, the first conductive layer MEP1 and the second conductive layer MEP2 may include different metals selected from the group consisting of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), aluminum (Al), silver (Ag), and gold (Au).

[0118] Figures 20 to 29 These are semiconductor devices illustrating some embodiments of the concept according to the present invention. Figure 2A An enlarged sectional view of region "M". For ease of explanation, references may be omitted. Figure 1 , Figures 2A to 2D and Figure 3 The description provided. In other words, the following text will primarily describe the current embodiment and... Figure 1 , Figures 2A to 2D and Figure 3 Differences between the embodiments.

[0119] Reference Figure 20 The first barrier layer BAP1 may have a first bottom surface BS1. The first bottom surface BS1 may contact at least a portion of the second top surface TOS2 of the second lower interconnect LIL2. The second barrier layer BAP2 may have a second bottom surface BS2. The second barrier layer BAP2 may cover the remaining portion of the second top surface TOS2 except for the portion that contacts the first bottom surface BS1. The second barrier layer BAP2 may cover 80% or more of the area of ​​the second top surface TOS2. The first bottom surface BS1 and the second bottom surface BS2 may be located at substantially the same level. For example, the first bottom surface BS1 and the second bottom surface BS2 may be located at a second level LV2, which is lower than the first level LV1. In some embodiments, the first bottom surface BS1 and the second bottom surface BS2 may be coplanar with each other.

[0120] Reference Figure 21 ,and Figure 20Similarly, the first bottom surface BS1 of the first barrier layer BAP1 and the second bottom surface BS2 of the second barrier layer BAP2 can cover the top surface TOS of the second lower interconnect LIL2. The second barrier layer BAP2 can cover 80% or more of the area of ​​the top surface TOS exposed by the via VIH. According to this embodiment, the first recess RS1 can be omitted. Therefore, the first bottom surface BS1 and the second bottom surface BS2 can be located at substantially the same level as the bottom surface of the etch stop layer ESL.

[0121] Reference Figure 22 The first bottom surface BS1 of the first barrier layer BAP1 can be spaced apart from the second top surface TOS2 of the second lower interconnect LIL2 along a third direction D3. A gap VD can be provided between the first bottom surface BS1 of the first barrier layer BAP1 and the second top surface TOS2 of the second lower interconnect LIL2. The second barrier layer BAP2 may not cover the first bottom surface BS1 of the first barrier layer BAP1. The gap VD can be formed in the remaining area of ​​the first recess RS1 that is not filled by the second barrier layer BAP2.

[0122] Reference Figure 23 The first bottom surface BS1 of the first barrier layer BAP1 can contact the first top surface TOS1 of the second lower interconnect LIL2. In other words, the first bottom surface BS1 of the first barrier layer BAP1 can be located at the first horizontal level LV1. The second bottom surface BS2 of the second barrier layer BAP2 can contact the second top surface TOS2 of the second lower interconnect LIL2. The second bottom surface BS2 of the second barrier layer BAP2 can be lower than the first bottom surface BS1.

[0123] Reference Figure 24 The third conductive pattern FM3 of the upper interconnect UIL can be formed by a single metal layer. In other words, it can be omitted. Figure 3 The first conductive layer MEP1 is one of the first conductive layers MEP1 and MEP2 constituting the third conductive pattern FM3. The third conductive pattern FM3 may include a metal selected from the group consisting of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), aluminum (Al), silver (Ag), and gold (Au). For example, the third conductive pattern FM3 may include copper (Cu).

[0124] Reference Figure 25 , can be omitted Figure 3 The third barrier pattern BM3 is formed by the second barrier layer BAP2 in the first barrier layer BAP1 and the second barrier layer BAP2. The third barrier pattern BM3 may not cover the surface of the second lower interconnect LIL2. The third barrier pattern BM3 may selectively cover only the inner sidewall of the interconnect UIH (i.e., the sidewall of the etch stop layer ESL and the sidewall of the fourth interlayer insulating layer 140).

[0125] The first conductive layer MEP1 on the third blocking pattern BM3 can fill the first recess RS1. The third bottom surface BS3 of the first conductive layer MEP1 can cover the second top surface TOS2 of the second lower interconnect LIL2. The third bottom surface BS3 of the first conductive layer MEP1 can be lower than the first top surface TOS1 of the second lower interconnect LIL2.

[0126] According to this embodiment, the second conductive layer MEP2 can be electrically connected to the second lower interconnect LIL2 through the first conductive layer MEP1. Because the resistivity of the first conductive layer MEP1 is lower than that of the third blocking pattern BM3, the contact resistance between the upper interconnect UIL and the lower interconnect LIL1 or LIL2 can be reduced.

[0127] Reference Figure 26 The second barrier layer BAP2 of the via portion VIP may have a fourth thickness T4 in the second direction D2. The fourth thickness T4 may be substantially equal to or greater than the second thickness T2. A portion of the second barrier layer BAP2 of the line portion LIP (e.g., the upper portion of the second barrier layer BAP2 of the line portion LIP) may have a fifth thickness T5 in the second direction D2. The fifth thickness T5 may be larger than the fourth thickness T4. In some embodiments, such as Figure 26 As shown, the second barrier layer BAP2 of the via portion VIP can have a uniform thickness in the second direction D2, and the second barrier layer BAP2 of the line portion LIP can have a thickness that varies in the second direction D2, increasing along the third direction D3.

[0128] The first conductive layer MEP1 of the via portion VIP may have a sixth thickness T6 in the second direction D2. The sixth thickness T6 may be substantially equal to or greater than the third thickness T3. A portion of the first conductive layer MEP1 of the line portion LIP (e.g., the upper portion of the first conductive layer MEP1 of the line portion LIP) may have a seventh thickness T7 in the second direction D2. The seventh thickness T7 may be larger than the sixth thickness T6. In some embodiments, such as Figure 26 As shown, the first conductive layer MEP1 of the via portion VIP can have a uniform thickness in the second direction D2, and the first conductive layer MEP1 of the line portion LIP can have a thickness that increases along the third direction D3 and varies in the second direction D2.

[0129] Reference Figure 27The second barrier layer BAP2 may be selectively formed only in the first recess RS1. For example, the top surface of the second barrier layer BAP2 may be located at the first horizontal level LV1. The second barrier layer BAP2 may not extend along the first barrier layer BAP1 in the third direction D3. The first conductive layer MEP1 may be in direct contact with the first barrier layer BAP1. The first conductive layer MEP1 may be in direct contact with the top surface of the second barrier layer BAP2.

[0130] Reference Figure 28 ,and Figure 3 In contrast, the first recess RS1 can be further extended into the second lower interconnect LIL2. The inner sidewall RIS of the first recess RS1 can have a protruding profile. The second barrier layer BAP2 can be disposed in the first recess RS1. Because the first recess RS1 is further extended, the contact area between the second barrier layer BAP2 and the second lower interconnect LIL2 can be further increased. As a result, the contact resistance between the upper interconnect UIL and the lower interconnect LIL1 or LIL2 can be reduced, thereby improving the electrical characteristics of the semiconductor device.

[0131] Reference Figure 29 The upper interconnect UIL can be formed using a single damascene process (or "single metal damascene process"). Specifically, the upper via UVI can be placed below the upper interconnect UIL. The upper via UVI can connect the upper interconnect UIL and the second lower interconnect LIL2 to each other.

[0132] The upper via UVI may include a fourth blocking pattern BM4 and a fourth conductive pattern FM4 located on the fourth blocking pattern BM4. The fourth blocking pattern BM4 may include a first blocking layer BAP1 and a second blocking layer BAP2. The fourth conductive pattern FM4 may include a first conductive layer MEP1 and a second conductive layer MEP2. The fourth blocking pattern BM4 and the fourth conductive pattern FM4 of the upper via UVI can be combined with... Figure 3 The via patterns of the UIL interconnects are basically the same.

[0133] The upper interconnect UIL on the upper via UVI may include a third barrier pattern BM3 and a third conductive pattern FM3. Unlike the upper via UVI, the second barrier layer BAP2 may be omitted in the third barrier pattern BM3.

[0134] Figure 30 These are semiconductor devices used to illustrate some embodiments of the concept according to the present invention. Figure 2A An enlarged sectional view of region "N". (Refer to...) Figure 30The first barrier pattern BM1 of the active contact AC may include a first barrier layer BAP1 and a second barrier layer BAP2. The second recess RS2 may be defined by a silicide pattern SC on the first source / drain pattern SD1. The second barrier layer BAP2 may be disposed in the second recess RS2 to directly cover (e.g., directly contact) the silicide pattern SC. The first barrier layer BAP1 may not be disposed in the second recess RS2. The first barrier layer BAP1 may be disposed between the first conductive pattern FM1 and the interlayer insulating layers 110 and 120, but may not contact the silicide pattern SC. Other features of the first barrier layer BAP1 and the second barrier layer BAP2 of the active contact AC may be the same as described above. Figure 3 The corresponding features of the first barrier layer BAP1 and the second barrier layer BAP2 are basically the same.

[0135] According to this embodiment, the active contact AC and the source / drain pattern SD1 or SD2 can be connected to each other through a second barrier layer BAP2 with relatively low resistivity. Furthermore, even though not shown in the figures, similar to the active contact AC, the gate contact GC and the gate electrode GE can also be connected to each other through the second barrier layer BAP2 with relatively low resistivity.

[0136] Figure 31A , Figure 31B , Figure 31C and Figure 31D These are semiconductor devices used to illustrate some embodiments of the concept according to the present invention, respectively along... Figure 1 The cross-sectional views are taken along lines A-A', B-B', C-C', and D-D'. In this embodiment, for ease of explanation, the details of the cross-sections are omitted. Figure 1 and Figures 2A to 2D The description of the same technical features as those in the embodiments is provided below. In other words, the following description will primarily focus on the technical features of this embodiment and those in the embodiments. Figure 1 and Figures 2A to 2D Differences between the embodiments.

[0137] Reference Figure 1 and Figures 31A to 31D A substrate 100 can be configured including a first active region PR and a second active region NR. A device isolation layer ST can be disposed on the substrate 100. The device isolation layer ST can define a first active pattern AP1 and a second active pattern AP2 in the upper portion of the substrate 100. The first active pattern AP1 and the second active pattern AP2 can be defined on the first active region PR and the second active region NR, respectively.

[0138] The first active pattern AP1 may include vertically stacked first channel patterns CH1. The stacked first channel patterns CH1 may be spaced apart from each other along a third direction D3. The stacked first channel patterns CH1 may be vertically stacked. The second active pattern AP2 may include vertically stacked second channel patterns CH2. The stacked second channel patterns CH2 may be spaced apart from each other along a third direction D3. The stacked second channel patterns CH2 may be vertically stacked. The first channel pattern CH1 and the second channel pattern CH2 may include, for example, silicon (Si), germanium (Ge), and / or silicon-germanium (SiGe).

[0139] The first active pattern AP1 may also include a first source / drain pattern SD1. A stacked first channel pattern CH1 may be disposed between a pair of adjacent first source / drain patterns SD1. The stacked first channel pattern CH1 can connect a pair of adjacent first source / drain patterns SD1.

[0140] The second active pattern AP2 may also include a second source / drain pattern SD2. A stacked second channel pattern CH2 may be disposed between a pair of adjacent second source / drain patterns SD2. The stacked second channel pattern CH2 may connect a pair of adjacent second source / drain patterns SD2.

[0141] The gate electrode GE may extend along a first direction D1 to intersect with the first channel pattern CH1 and the second channel pattern CH2. The gate electrode GE may be vertically stacked with the first channel pattern CH1 and the second channel pattern CH2. A pair of gate spacers GS may be respectively disposed on the opposite sidewalls of the gate electrode GE. A gate overlay pattern GP may be disposed on the gate electrode GE.

[0142] The gate electrode GE can be around each of the first channel pattern CH1 and the second channel pattern CH2 (see Figure 31D The gate electrode GE may surround the top surface, bottom surface, and two sidewalls of each of the first channel pattern CH1 and the second channel pattern CH2. The transistor according to this embodiment may be a 3D field-effect transistor (e.g., an MBCFET) in which the gate electrode GE three-dimensionally surrounds the channel patterns CH1 and CH2. In some embodiments, such as... Figure 31D As shown, the gate electrode GE can completely surround each of the first channel pattern CH1 and the second channel pattern CH2.

[0143] The gate dielectric pattern GI can be disposed between the gate electrode GE and each of the first channel pattern CH1 and the second channel pattern CH2. The gate dielectric pattern GI can surround each of the first channel pattern CH1 and the second channel pattern CH2.

[0144] An insulating pattern IP can be disposed on the second active region NR between the gate dielectric pattern GI and the second source / drain pattern SD2. The gate electrode GE can be spaced apart from the second source / drain pattern SD2 by the gate dielectric pattern GI and the insulating pattern IP. In some embodiments, the insulating pattern IP can be omitted on the first active region PR.

[0145] The first interlayer insulating layer 110 and the second interlayer insulating layer 120 can be disposed on the entire top surface of the substrate 100. An active contact AC can penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 to connect to the first source / drain pattern SD1 and the second source / drain pattern SD2. A gate contact GC can penetrate the second interlayer insulating layer 120 and the gate overlay pattern GP to connect to the gate electrode GE.

[0146] The third interlayer insulation layer 130 can be disposed on the second interlayer insulation layer 120. The fourth interlayer insulation layer 140 can be disposed on the third interlayer insulation layer 130. The first metal layer M1 can be disposed in the third interlayer insulation layer 130. The second metal layer M2 can be disposed in the fourth interlayer insulation layer 140. The first metal layer M1 and the second metal layer M2 can be disposed as described above. Figure 1 , Figures 2A to 2D and Figure 3 The descriptions are basically the same.

[0147] Figure 32 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention. Figure 33A , Figure 33B , Figure 33C and Figure 33D They are respectively along Figure 32 A sectional view taken from lines A-A', B-B', C-C', and D-D'.

[0148] Reference Figure 32 and Figures 33A to 33D The logic cell LC can be disposed on the substrate 100. The logic cell LC may include vertical field-effect transistors (hereinafter referred to as vertical transistors) constituting the logic device and interconnects connecting the vertical transistors.

[0149] The logic cell LC on the substrate 100 may include a first active region PR and a second active region NR. The first active region PR and the second active region NR may be defined by a trench TR formed in the upper portion of the substrate 100. The first active region PR and the second active region NR may be spaced apart from each other along a first direction D1.

[0150] The first lower epitaxial pattern SOP1 can be disposed on the first active region PR, and the second lower epitaxial pattern SOP2 can be disposed on the second active region NR. The first lower epitaxial pattern SOP1 can be superimposed on the first active region PR in a planar view, and the second lower epitaxial pattern SOP2 can be superimposed on the second active region NR in a planar view. The first lower epitaxial pattern SOP1 and the second lower epitaxial pattern SOP2 can be epitaxial patterns formed by, for example, a selective epitaxial growth (SEG) process. The first lower epitaxial pattern SOP1 can be disposed in the third recessed region RSR3 of the substrate 100, and the second lower epitaxial pattern SOP2 can be disposed in the fourth recessed region RSR4 of the substrate 100.

[0151] A first active pattern AP1 can be disposed on a first active region PR, and a second active pattern AP2 can be disposed on a second active region NR. Each of the first active pattern AP1 and the second active pattern AP2 can have a vertically protruding fin shape. When viewed in a plan view, each of the first active pattern AP1 and the second active pattern AP2 can have a strip shape extending along a first direction D1. The first active pattern AP1 can be arranged along a second direction D2, and the second active pattern AP2 can be arranged along a second direction D2. In some embodiments, such as Figure 32 As shown, the first active pattern AP1 can be spaced apart from each other along the second direction D2, and the second active pattern AP2 can be spaced apart from each other along the second direction D2.

[0152] Each of the first active patterns AP1 may include a first channel pattern CHP1 that protrudes vertically from the first lower epitaxial pattern SOP1 and a first upper epitaxial pattern DOP1 located on the first channel pattern CHP1. Each of the second active patterns AP2 may include a second channel pattern CHP2 that protrudes vertically from the second lower epitaxial pattern SOP2 and a second upper epitaxial pattern DOP2 located on the second channel pattern CHP2.

[0153] A device isolation layer ST can be disposed on the substrate 100 to fill the trench TR. The device isolation layer ST can cover the top surface of the first lower epitaxial pattern SOP1 and the top surface of the second lower epitaxial pattern SOP2. The first active pattern AP1 and the second active pattern AP2 can protrude vertically above the device isolation layer ST.

[0154] A plurality of gate electrodes GE extending parallel to each other along a first direction D1 can be disposed on a device isolation layer ST. The gate electrodes GE can be arranged along a second direction. In some embodiments, such as Figure 32As shown, the gate electrodes GE can be spaced apart from each other along the second direction D2. The gate electrodes GE can surround the first channel pattern CHP1 of the first active pattern AP1 and the second channel pattern CHP2 of the second active pattern AP2. For example, the first channel pattern CHP1 of the first active pattern AP1 can have first sidewalls SW1 to fourth sidewalls SW4. The first sidewalls SW1 and second sidewalls SW2 can be back-to-back and spaced apart from each other along the second direction D2, and the third sidewalls SW3 and fourth sidewalls SW4 can be back-to-back and spaced apart from each other along the first direction D1. The gate electrodes GE can be disposed on the first sidewalls SW1 to fourth sidewalls SW4. In other words, the gate electrodes GE can surround the first sidewalls SW1 to fourth sidewalls SW4. In some embodiments, the gate electrodes GE can surround the first channel pattern CHP1 and the second channel pattern CHP2.

[0155] A gate dielectric pattern GI can be disposed between each of the first channel pattern CHP1 and the second channel pattern CHP2 and the gate electrode GE. The gate dielectric pattern GI can cover the bottom surface of the gate electrode GE and the inner sidewall of the gate electrode GE. For example, the gate dielectric pattern GI can directly cover or directly contact the first sidewall SW1 to the fourth sidewall SW4 of the first channel pattern CHP1.

[0156] The first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 can protrude vertically above the gate electrode GE. The top surface of the gate electrode GE can be lower than the bottom surface of each of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. In other words, each of the first active pattern AP1 and the second active pattern AP2 can have a structure that protrudes vertically from the substrate 100 to penetrate the gate electrode GE.

[0157] The semiconductor device according to this embodiment may include a vertical transistor in which charge carriers (e.g., electrons) move along a third direction D3. For example, when the transistor is turned on by applying a voltage to the gate electrode GE, charge carriers can move from the lower epitaxial pattern SOP1 or SOP2 to the upper epitaxial pattern DOP1 or DOP2 through the channel pattern CHP1 or CHP2. The gate electrode GE according to this embodiment may completely surround the sidewalls SW1 to SW4 of the channel patterns CHP1 and CHP2. The transistor according to this embodiment may be a 3D field-effect transistor (e.g., a VFET (vertical field-effect transistor)) with a gate-around structure. Because the gate completely surrounds the channel, the semiconductor device conceived according to the present invention can have excellent electrical characteristics.

[0158] The spacer SPC covering the gate electrode GE and the first active pattern AP1 and the second active pattern AP2 can be disposed on the device isolation layer ST. The spacer SPC may include, for example, a silicon nitride layer or a silicon oxynitride layer. The spacer SPC may include a lower spacer LS, an upper spacer US, and a gate spacer GS located between the lower spacer LS and the upper spacer US.

[0159] The lower spacer LS can directly cover or contact the top surface of the device isolation layer ST. The gate electrode GE can be spaced from the device isolation layer ST along the third direction D3 via the lower spacer LS. The gate spacer GS can cover the top surface and outer sidewall of each of the gate electrodes GE. The upper spacer US can cover the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. However, the upper spacer US can also expose the top surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2, instead of covering them.

[0160] The first interlayer insulating layer 110 can be disposed on the spacer SPC. The top surface of the first interlayer insulating layer 110 can be substantially coplanar with the top surface of the first upper epitaxial pattern DOP1 and the top surface of the second upper epitaxial pattern DOP2. The second interlayer insulating layer 120, the third interlayer insulating layer 130 and the fourth interlayer insulating layer 140 can be sequentially stacked on the first interlayer insulating layer 110. The second interlayer insulating layer 120 can cover the top surface of the first upper epitaxial pattern DOP1 and the top surface of the second upper epitaxial pattern DOP2.

[0161] The first active contact AC1 can penetrate the second interlayer insulating layer 120 to connect to the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. The second active contact AC2 can sequentially penetrate the second interlayer insulating layer 120, the first interlayer insulating layer 110, the lower spacer LS, and the device isolation layer ST to connect to the first lower epitaxial pattern SOP1 and the second lower epitaxial pattern SOP2. The gate contact GC can sequentially penetrate the second interlayer insulating layer 120, the first interlayer insulating layer 110, and the gate spacer GS to connect to the gate electrode GE. The top surfaces of the gate contact GC, the first active contact AC1, and the second active contact AC2 can be substantially coplanar with the top surface of the second interlayer insulating layer 120.

[0162] Each of the first active contacts AC1 may extend along the second direction D2 and may be connected to at least one upper epitaxial pattern DOP1 or DOP2. Each of the second active contacts AC2 may be disposed below the first lower interconnect LIL1 and may be vertically stacked with the first lower interconnect LIL1. The second active contacts AC2 may have a strip shape extending along the second direction D2.

[0163] When viewed in a plan view, the gate contact GC can be positioned between the first active region PR and the second active region NR. In other words, the gate contact GC can be connected to the gate electrode GE located on the device isolation layer ST between the first active region PR and the second active region NR.

[0164] The first metal layer M1 can be disposed in the third interlayer insulating layer 130. The second metal layer M2 can be disposed in the fourth interlayer insulating layer 140. The first metal layer M1 and the second metal layer M2 can be disposed in accordance with the above reference. Figure 1 , Figures 2A to 2D and Figure 3 The descriptions are basically the same.

[0165] Figure 34 and Figure 35 This is for illustrating some embodiments of a semiconductor device according to the present invention. Figure 1 A cross-sectional view taken along line C-C'. In this embodiment, for ease of explanation, the details of the section view can be omitted. Figure 1 , Figures 2A to 2D and Figures 31A to 31D The description of the same technical features as those in the embodiments is provided below. In other words, the following description will primarily focus on the technical features of this embodiment and those in the embodiments. Figure 1 , Figures 2A to 2D and Figures 31A to 31D Differences between the embodiments.

[0166] Reference Figure 34 and Figure 35 The lowest level of the bottom surface of the active contact AC connected to the first source / drain pattern SD1 can be the third level LV3. The lowest level of the bottom surface of the active contact AC connected to the second source / drain pattern SD2 can be the fourth level LV4. Here, the third level LV3 and the fourth level LV4 can be different from each other. For example, the third level LV3 can be higher than the fourth level LV4.

[0167] The volume of the first source / drain pattern SD1 can differ from the volume of the second source / drain pattern SD2. For example, the volume of the first source / drain pattern SD1 can be larger than the volume of the second source / drain pattern SD2. Due to the volume difference between the epitaxial patterns, the recess levels of the epitaxial patterns can differ from each other in the process used to form the active contact AC. Therefore, the bottom surface of the active contact AC on the first source / drain pattern SD1 can be higher than the bottom surface of the active contact AC on the second source / drain pattern SD2.

[0168] Figure 36 This is for illustrating some embodiments of a semiconductor device according to the present invention. Figure 1A cross-sectional view taken along line C-C'. In this embodiment, for ease of explanation, the details of the view are omitted. Figure 1 , Figures 2A to 2D and Figure 3 The description of the same technical features as those in the embodiments is provided below. In other words, the following description will primarily focus on the technical features of this embodiment and those in the embodiments. Figure 1 , Figures 2A to 2D and Figure 3 Differences between the embodiments.

[0169] Reference Figure 36 The power transmission network (PON) can be disposed on the bottom surface 100B of the substrate 100. The PON may include a first back-side insulating layer 150 and a second back-side insulating layer 160 sequentially stacked on the bottom surface 100B of the substrate 100.

[0170] The power transmission network (PON) may further include a first back-side interconnect (BIL1) and a second back-side interconnect (BIL2). The first back-side interconnect (BIL1) may be disposed in a first back-side insulating layer 150, and the second back-side interconnect (BIL2) may be disposed in a second back-side insulating layer 160. A first back-side via (BVI1) may be disposed between the first back-side interconnect (BIL1) and a through-via (TVI), which will be described later, and a second back-side via (BVI2) may be disposed between the second back-side interconnect (BIL2) and the first back-side interconnect (BIL1).

[0171] A through-via TVI can extend from the bottom surface 100B of substrate 100 to the first lower interconnect LIL1. The bottom surface of the through-via TVI can be coplanar with the bottom surface 100B of substrate 100. The top surface of the through-via TVI can contact the bottom surface of the first lower interconnect LIL1. The first lower interconnect LIL1 can be connected to the power transmission network PON through the through-via TVI. The first back-side interconnect BIL1 and the second back-side interconnect BIL2 can form an interconnect network for applying power supply voltage (VDD) or ground voltage (VSS) to the first lower interconnect LIL1.

[0172] The through-hole (TVI) may include a fifth blocking pattern BM5 and a fifth conductive pattern FM5 located on the fifth blocking pattern BM5. The fifth blocking pattern BM5 may include a first blocking layer BAP1 and a second blocking layer BAP2. The fifth conductive pattern FM5 may include a first conductive layer MEP1 and a second conductive layer MEP2. The fifth blocking pattern BM5 and the fifth conductive pattern FM5 of the through-hole (TVI) can be combined with... Figure 3 The via patterns of the UIL interconnects are basically the same.

[0173] The fifth conductive pattern FM5 through the via TVI can be connected to the second conductive pattern FM2 of the first lower interconnect LIL1 via the second barrier layer BAP2, which has low resistivity. As a result, the contact resistance between the via TVI and the first lower interconnect LIL1 can be reduced, thereby improving the electrical characteristics of the semiconductor device.

[0174] In a semiconductor device according to embodiments of the present invention, an upper conductor (e.g., an interconnect, contact, or via) connected to a lower conductor may include a barrier pattern comprising a first barrier layer and a second barrier layer. The resistivity of the second barrier layer may be lower than that of the first barrier layer. The second barrier layer (instead of the first barrier layer) may be disposed between the lower and upper conductors to electrically connect them. As a result, according to some embodiments of the present invention, the contact resistance between the lower and upper conductors can be reduced, and the electrical characteristics of the semiconductor device can be improved.

[0175] Although the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive but illustrative. Consequently, the scope of the inventive concept will be determined by the widest permissible interpretation of the claims and their equivalents, and should not be constrained or limited by the foregoing description.

Claims

1. A semiconductor device comprising: a substrate; a first interlayer insulating layer on the substrate; a lower interconnect line in the first interlayer insulating layer; an etch stop layer on the first interlayer insulating layer and the lower interconnect line; a second interlayer insulating layer on the etch stop layer; and an upper interconnect line in the second interlayer insulating layer, the upper interconnect line including a via portion extending through the etch stop layer and contacting the lower interconnect line, wherein the via portion includes a barrier pattern and a conductive pattern on the barrier pattern, wherein the barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer and a second barrier layer between the conductive pattern and the lower interconnect line, wherein a resistivity of the first barrier layer is greater than a resistivity of the second barrier layer, wherein a concentration of nitrogen in the first barrier layer is greater than a concentration of nitrogen in the second barrier layer, and wherein an upper surface of the lower interconnect line includes a recess, the second barrier layer is in the recess and covers a bottom surface of the first barrier layer. the concentration of nitrogen in the first barrier layer is in a range of 10 at% to 60 at%, and 2. The semiconductor device according to claim 1, wherein wherein the concentration of nitrogen in the second barrier layer is less than 5 at%. the upper surface of the lower interconnect line includes a first portion covered by the etch stop layer and a second portion in contact with the via portion, and 3. The semiconductor device according to claim 1, wherein wherein the second portion is lower than the first portion with respect to the substrate. the second portion of the upper surface of the lower interconnect line defines the recess.

4. The semiconductor device according to claim 3, wherein the second barrier layer includes a second bottom surface, and 5. The semiconductor device according to claim 3, wherein wherein the second bottom surface covers at least 80% of the second portion of the upper surface of the lower interconnect line. the first barrier layer includes a first bottom surface spaced apart from the second portion of the upper surface of the lower interconnect line.

6. The semiconductor device according to claim 5, wherein the first barrier layer includes a tantalum nitride layer, a titanium nitride layer, and / or a manganese nitride layer, and 7. The semiconductor device according to claim 1, wherein wherein the second barrier layer includes tantalum, titanium, tungsten, nickel, cobalt, platinum, and / or graphene. the conductive pattern includes a first conductive layer on the barrier pattern and a second conductive layer on the first conductive layer, and 8. The semiconductor device according to claim 1, wherein wherein the first conductive layer and the second conductive layer include different metals and include copper, cobalt, ruthenium, tungsten, molybdenum, aluminum, silver, and / or gold. a thickness of the first barrier layer is greater than a thickness of the second barrier layer.

9. The semiconductor device according to claim 1, wherein ​

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