An ESD protection structure for LDMOS output

Abstract

This invention discloses an ESD protection structure for the output of an LDMOS device. An N-type deep well has a first N-well, a first P-well, and a second N-well arranged thereon. The first N-well includes a first N+ injection region and a first P+ injection region. The second N-well includes a second P+ injection region and a second N+ injection region. The first P-well includes multiple N+ injection regions and multiple P+ injection regions arranged alternately. The first N+ injection region and the first P+ injection region are connected to a power supply terminal. The second P+ injection region and the second N+ injection region are also connected to a power supply terminal. The multiple N+ injection regions and multiple P+ injection regions in the first P-well are connected in parallel to serve as a data output terminal. The data output terminal is connected to one end of a resistor R, and the other end of the resistor R is connected to the gate electrode. This invention connects the SCR device through a simple external auxiliary trigger circuit. When an ESD event occurs, the external circuit structure is turned on, and the conduction current of the external circuit triggers the SCR, thereby helping the SCR device turn on. This does not require changing the internal structure of the SCR device and reduces the SCR trigger voltage.

Description

Technical Field

[0001] The invention relates to an ESD protection structure, in particular to an ESD protection structure for an LDMOS output terminal. Background Art

[0002] Electrostatic discharge (ESD) is the instantaneous process in which a large amount of static charge is injected into the integrated circuit from the outside when the pin of an integrated circuit is floating. The whole process takes about 100ns. When the electrostatic discharge of the integrated circuit occurs, a high voltage of hundreds or even thousands of volts will be generated, which will break down the gate oxide layer of the input stage of the integrated circuit. With the advancement of integrated circuit technology, the characteristic size of MOS tubes is getting smaller and smaller, and the thickness of the gate oxide layer is getting thinner and thinner. Under this trend, it is very important to use high-performance ESD protection devices to discharge static charges to protect the gate oxide layer.

[0003] As one of the most efficient ESD protection devices, silicon controlled rectifiers (SCRs) are widely used in power devices. Since their holding voltage is very low, they can withstand very high ESD currents. Therefore, SCRs naturally have high ESD robustness. Compared with other ESD protection devices, such as diodes, MOS tubes, BJTs, etc., SCR devices have the strongest ESD protection capability per unit area.

[0004] However, on the one hand, since general SCR devices are unidirectional ESD protection devices ( Figure 1 As shown in the figure, the ESD protection in the other direction is completed by a parasitic diode or a diode in parallel. Using an additional diode for ESD protection in the other direction will increase the layout area. In some circuits where the input port needs to withstand negative voltage, if the IO voltage is lower than -0.7V and the GND voltage is 0V, when a diode is used for reverse protection, the diode will be turned on during normal operation, resulting in leakage. At this time, a bidirectional SCR structure must be used for protection.

[0005] On the other hand, a common SCR device has a defect that the trigger voltage is too high. The trigger voltage of a simple SCR is equivalent to the reverse breakdown voltage of the PN junction formed by the N-well and P-well, which is generally between a dozen volts and several dozen volts. Such a high breakdown voltage cannot provide effective ESD protection for internal circuit components because the internal components have been damaged by the ESD pulse voltage before the SCR is turned on. At this time, the trigger voltage of the SCR structure must be reduced.

[0006] Whether the SCR trigger voltage can be effectively reduced is related to whether it can be applied in the field of ESD protection. Many studies have been done on this. Traditionally, the method of reducing the SCR trigger voltage is to change the internal structure of the SCR. By changing the device structure of the SCR, a parasitic device is generated inside it. Under ESD conditions, the parasitic device is turned on first, and the turning on of the parasitic device then promotes or triggers the SCR to turn on. Generally, a heavily doped area is added at the connection between the N well and the P well, so that the heavily doped area is connected across the N well and the P well. However, due to the change in the SCR structure, the base width of the NPN and PNP transistors inside the SCR must be kept at a certain large value to accommodate the changed device structure. Due to the increase in the base width, the SCR will turn on slower, and the voltage overshoot will cause damage to the internal circuit. Summary of the invention

[0007] The purpose of the present invention is to overcome the defects of the prior art and provide an ESD protection structure for the output end of LDMOS. The external auxiliary trigger structure not only reduces the trigger voltage, but also shares a part of the ESD discharge current for the SCR structure, thereby improving the ESD protection capability of the device.

[0008] The object of the present invention is achieved as follows: An ESD protection structure for an LDMOS output terminal comprises, in sequence, a Si layer, a buried oxide layer, a P-type substrate and an N-type deep well on the P-type substrate, wherein a first N-well, a first P-well and a second N-well are arranged in sequence on the N-type deep well; the first N-well comprises a first N+ injection region and a first P+ injection region; the second N-well comprises a second P+ injection region and a second N+ injection region; the first P-well comprises a plurality of N+ injection regions and a plurality of P+ injection regions arranged at intervals;

[0009] The first N+ injection region and the first P+ injection region are connected to the power supply terminal; the second P+ injection region and the second N+ injection region are connected to the power supply terminal; the multiple N+ injection regions and the multiple P+ injection regions in the first P well are connected in parallel to each other as a data output terminal; the data output terminal is connected to one end of a resistor R, and the other end of the resistor R is connected to a gate electrode.

[0010] As a further limitation of the present invention, an SCR structure is formed between the power supply terminal and the data output terminal, and the SCR structure includes a first P+ injection region, a first N well, a first P well, and an N+ injection region in the first P well.

[0011] As a further limitation of the present invention, the SCR structure includes a second P+ implantation region, a second N-well, a first P-well, and an N+ implantation region within the first P-well.

[0012] As a further limitation of the present invention, a diode structure is formed between the data output terminal and the power supply terminal, and the diode structure includes a P+ injection region in the first P well, a first P well, a first N well and a first N+ injection region.

[0013] As a further limitation of the present invention, the diode structure includes a P+ implantation region within the first P well, a first P well, a second N well, and a second N+ implantation region.

[0014] As a further limitation of the present invention, the first P well includes six N+ injection regions and five P+ injection regions arranged at intervals.

[0015] As a further limitation of the present invention, a deep trench isolation layer is provided on the outside of the first N-well and the outside of the second N-well reaching the buried oxide layer.

[0016] Compared with the prior art, the present invention adopts the above technical solution, and has the following beneficial effects: a diode is parasitized on the SCR structure, and the ESD protection capability from the data output port (DOUT) to the power supply terminal (VDD) is bidirectionally protected, which reduces the trigger voltage of the SCR structure and more effectively protects the internal circuit; the width of the first P well (PX region) in the middle can be used to further adjust the maintenance voltage of the SCR path, and the external auxiliary trigger structure reduces the trigger voltage while also sharing a part of the ESD discharge current for the SCR structure, thereby improving the ESD protection capability of the device; at the same time, the data output terminal (DOUT) triggers the parasitic channel to open through the resistor R to reduce the parasitic SCR opening voltage from the power supply terminal VDD to the data output terminal DOUT. The layout of each injection area is fixed, which ensures that the parasitic resistance of the SCR path is stable, and the ESD current discharge is more uniform. For the output LDMOS ESD protection of SOI power integrated circuits, this protection device is used to avoid the disadvantage of weak protection capability from the data output terminal (DOUT) to the power supply terminal (VDD), and improve the ESD protection capability of the device; the SCR device is connected through a simple external auxiliary trigger circuit. When an ESD event occurs, the external circuit structure is turned on, and the conduction current of the external circuit triggers the SCR, thereby helping the SCR device to turn on. There is no need to change the internal structure of the SCR device, and the SCR trigger voltage is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of a unidirectional SCR ESD protection structure in the prior art.

[0018] Figure 2 A schematic diagram of the structure of the present invention. DETAILED DESCRIPTION

[0019] like Figure 2An ESD protection structure for an LDMOS output terminal is shown, which includes a Si layer, a buried oxide layer (BOX), a P-type substrate (P-sub) and an N-type deep well (DNW) on the P-type substrate (P-sub) in sequence, and a first N-well (NX), a first P-well (PX) and a second N-well (NX) are arranged in sequence on the N-type deep well (DNW); the first N-well (NX) includes a first N+ injection region and a first P+ injection region; the second N-well (NX) includes a second P+ injection region and a second N+ injection region; the first P-well includes a plurality of N+ injection regions and a plurality of P+ injection regions arranged at intervals; the first P-well (PX) includes six N+ injection regions and five P+ injection regions arranged at intervals.

[0020] The first N+ injection region and the first P+ injection region are connected to the power supply terminal (VDD); the second P+ injection region and the second N+ injection region are connected to the power supply terminal (VDD); multiple N+ injection regions and multiple P+ injection regions in the first P well are connected in parallel to each other as a data output terminal (DOUT); the data output terminal (DOUT) is connected to one end of a resistor R, and the other end of the resistor R is connected to a gate electrode; used to trigger the opening of the internal transistor of the SCR, the resistor used in this embodiment is 5K ohms,

[0021] An SCR structure is formed between the power supply terminal (VDD) and the data output terminal (DOUT), and the SCR structure includes a first P+ injection region, a first N-well (NX), a first P-well (PX), and an N+ injection region in the first P-well (PX). The SCR structure includes a second P+ injection region, a second N-well, a first P-well, and an N+ injection region in the first P-well.

[0022] A diode structure is formed between the data output terminal (DOUT) and the power supply terminal (VDD), and the diode structure includes a P+ injection region in the first P well (PX), a first P well (PX), a first N well (NX), and a first N+ injection region. The diode structure includes a P+ injection region in the first P well (PX), a first P well, a second N well (NX), and a second N+ injection region. A deep trench isolation layer (TR) is provided outside the first N well (NX) and outside the second N well (NX) to reach the buried oxide layer (BOX).

[0023] The present invention adopts this protection device for the output LDMOS ESD protection of SOI power integrated circuit, avoids the disadvantage of weak protection capability from the data output terminal (DOUT) to the power supply terminal (VDD), and improves the ESD protection capability of the device; connects the SCR device through a simple external auxiliary trigger circuit, when an ESD event occurs, the external circuit structure is turned on, and the conduction current of the external circuit triggers the SCR, thereby helping the SCR device to turn on, without changing the internal structure of the SCR device, and reducing the SCR trigger voltage; the width of the middle PX area is used to further adjust the holding voltage of the SCR path, and the layout of each injection area is fixed to ensure that the parasitic resistance of the SCR path is stable, so that the ESD current discharge is more uniform.

[0024] The present invention is not limited to the above-mentioned embodiments. On the basis of the technical solution disclosed in the present invention, technicians in this field can make some substitutions and deformations to some technical features therein according to the disclosed technical content without creative labor, and these substitutions and deformations are all within the protection scope of the present invention.

Claims

1. An ESD protection structure for an LDMOS output terminal, comprising, in sequence, a Si layer, a buried oxide layer, a P-type substrate, and an N-type deep well on the P-type substrate, characterized in that: The N-type deep well is provided with a first N-well, a first P-well and a second N-well in sequence; the first N-well includes a first N+ injection region and a first P+ injection region; the second N-well includes a second P+ injection region and a second N+ injection region; The first P well includes a plurality of N+ injection regions and a plurality of P+ injection regions arranged at intervals; The first N+ implantation region and the first P+ implantation region are connected to a power supply terminal; The second P+ implantation region and the second N+ implantation region are connected to a power supply terminal; The plurality of N+ injection regions and the plurality of P+ injection regions in the first P well are connected in parallel to each other as data output terminals; The data output terminal is connected to one end of a resistor R, and the other end of the resistor R is connected to a gate electrode; A diode structure is formed between the data output terminal and the power supply terminal, and the diode structure includes a P+ injection region in the first P well, a first P well, a first N well and a first N+ injection region; The diode structure includes a P+ implant region within a first P well, a first P well, a second N well, and a second N+ implant region.

2. An ESD protection structure for an LDMOS output terminal according to claim 1, characterized in that: An SCR structure is formed between the power supply terminal and the data output terminal, and the SCR structure includes a first P+ injection region, a first N well, a first P well, and an N+ injection region in the first P well.

3. An ESD protection structure for an LDMOS output terminal according to claim 2, characterized in that: The SCR structure includes a second P+ implantation region, a second N-well, a first P-well, and an N+ implantation region in the first P-well.

4. The ESD protection structure for an LDMOS output terminal according to claim 1, characterized in that: The first P well includes six N+ implantation regions and five P+ implantation regions which are arranged at intervals.

5. The ESD protection structure for an LDMOS output terminal according to claim 1, characterized in that: A deep trench isolation layer is disposed on the outer side of the first N well and the outer side of the second N well reaching the buried oxide layer.

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