Semiconductor device and method of forming the same

Abstract

Disclosed are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, active regions, an insulating structure, and a plurality of first conductive lines. The active regions are defined in the substrate in parallel and separated from each other. Each of the active regions includes an active fin and active end portions disposed on both sides of the active fin. The active fin and the active end portions include different materials, respectively. The insulating structure is disposed in the substrate and surrounds the active regions. The insulating structure includes a first insulating layer and a plurality of second insulating layers. The second insulating layers are disposed between adjacent active regions and surrounded by the first insulating layer, respectively. The plurality of first conductive lines are formed on the substrate and across the active regions. With the arrangement, the extension of the active regions can be improved, and the subsequently formed memory contact plug structures can be directly and stably contacted with the active regions.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device including active regions and an insulating structure and a method of forming the same. BACKGROUND

[0002] With the miniaturization of semiconductor devices and the increasing complexity of integrated circuits, the size of components is continuously reduced and the structure is continuously changed. Therefore, maintaining the performance of small-size semiconductor components is the main goal of the industry. In the semiconductor manufacturing process, a plurality of active regions are usually defined on a substrate as the basis, and then the required components are formed on the active regions. Generally, the active regions are formed on the substrate by photolithography and etching processes, but under the requirement of size miniaturization, the width of the active regions is gradually reduced, and the spacing between the active regions is gradually reduced, so that the manufacturing process also faces many limitations and challenges, which cannot meet the product demand. SUMMARY

[0003] One purpose of the present application is to provide a semiconductor device and a method of forming the same, wherein the active region includes an active fin and active end portions disposed on both sides of the active fin and including different materials. In this way, the extension range of the active region can be improved to ensure that the storage contact plug structure (SNC) can be in direct and stable contact with the active region. With this arrangement, the storage contact plug structure can have more optimized structural stability, thereby improving the element performance of the semiconductor device of the present application.

[0004] To achieve the above purpose, one embodiment of the present application provides a semiconductor device, comprising a substrate, active regions, an insulating structure, and a plurality of first conductive lines. The active regions are defined in the substrate in parallel and separated from each other, each of the active regions includes an active fin and active end portions disposed on both sides of the active fin, and the active fin and the active end portions include different materials, respectively. The insulating structure is disposed in the substrate and surrounds the active regions. The plurality of first conductive lines are formed on the substrate and cross the active regions.

[0005] To achieve the above purpose, one embodiment of the present application provides a method of forming a semiconductor device, comprising the following steps. First, a substrate is provided. Then, a plurality of active regions and an insulating structure are formed in the substrate, the insulating structure surrounds the active regions, wherein each of the active regions includes an active fin and active end portions disposed on both sides of the active fin, and the active fin and the active end portions include different materials, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1 to 7A cross-sectional view of a semiconductor device according to a preferred embodiment of the present application.

[0007] Figure 1 A top view of a semiconductor device according to the present application after forming an active cell;

[0008] Figure 2 A top view of a semiconductor device according to the present application after forming an active cell; Figure 1 A cross-sectional view along the line A-A'.

[0009] Figure 3 A top view of a semiconductor device according to the present application after forming an opening;

[0010] Figure 4 A top view of a semiconductor device according to the present application after forming an opening; Figure 3 A cross-sectional view along the line A-A'.

[0011] Figure 5 A cross-sectional view of a semiconductor device according to the present application after performing an epitaxial process.

[0012] Figure 6 A top view of a semiconductor device according to the present application after forming an insulating layer; and

[0013] Figure 7 A top view of a semiconductor device according to the present application after forming an insulating layer; and Figure 6 A cross-sectional view along the line A-A'.

[0014] Figure 8 A cross-sectional view of a semiconductor device according to another preferred embodiment of the present application after performing an epitaxial process.

[0015] Figure 9 A cross-sectional view of a semiconductor device according to another preferred embodiment of the present application after performing an epitaxial process.

[0016] Figure 10 A cross-sectional view of a semiconductor device according to a preferred embodiment of the present application.

[0017] Figures 11 to 12 A cross-sectional view of a semiconductor device according to a preferred embodiment of the present application.

[0018] Figure 11 A cross-sectional view of a semiconductor device according to the present application after forming an insulating layer; and

[0019] Figure 12 A cross-sectional view of a semiconductor device according to the present application after performing an etching process.

[0020] Figures 13 to 15 A cross-sectional view of a semiconductor device according to a preferred embodiment of the present application.

[0021] Figure 13A cross-sectional view of the semiconductor device of the present application after forming an active cell;

[0022] Figure 14 A cross-sectional view of the semiconductor device of the present application after forming an active cell; Figure 13 A cross-sectional view along the tangent line A-A';

[0023] Figure 15 A cross-sectional view of the semiconductor device of the present application after forming an active cell;

[0024] Wherein, the reference signs are explained as follows:

[0025] 100 substrate

[0026] 101 mask pattern

[0027] 101a surface

[0028] 102 shallow trench

[0029] 110 active cell

[0030] 110a top surface

[0031] 110b sidewall

[0032] 111 end portion

[0033] 113, 117, 213, 413 active end portion

[0034] 115, 415 active fin

[0035] 120 first insulating layer

[0036] 120a, 120b, 120c top surface

[0037] 130, 430 mask layer

[0038] 131, 431 opening

[0039] 140 second insulating layer

[0040] 140a top surface

[0041] 150, 150a, 450 active region

[0042] 160 insulating structure

[0043] 300, 500 semiconductor device

[0044] 320 insulating layer

[0045] 320a top surface

[0046] 321 opening

[0047] 410 active segment

[0048] 420 first insulating layer

[0049] 430 mask layer

[0050] 440 second insulating layer

[0051] 440a top surface

[0052] 540 first wire

[0053] 541 dielectric layer

[0054] 543 gate dielectric layer

[0055] 545 gate

[0056] 547 cap layer

[0057] 560 second wire

[0058] 560a contact

[0059] 561 semiconductor layer

[0060] 563 barrier layer

[0061] 565 conductive layer

[0062] 567 cap layer

[0063] 570 spacer

[0064] 571 first spacer

[0065] 573 second spacer

[0066] 575 third spacer

[0067] 580 dielectric layer

[0068] 590 plug

[0069] D1, x, y direction

[0070] g interval

[0071] h1, h2 height difference

[0072] L1, L2, L3 length DETAILED DESCRIPTION

[0073] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings. Those skilled in the art can, without departing from the spirit of the invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0074] Please refer to the following first. Figures 1 to 7 The illustration shows a schematic diagram of the fabrication process of the semiconductor device 300 in the first preferred embodiment of the present invention, wherein... Figure 1 , Figure 3 as well as Figure 6 These are top views of the semiconductor device 300 at different stages of its fabrication. Figure 2 , Figure 4 , Figure 5 ,as well as Figure 7 This is a cross-sectional schematic diagram of the semiconductor device 300 at different formation stages. First, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), or a silicon-on-insulator (SOI) substrate. At least one first insulating layer 120 is disposed within the substrate 100 to define a plurality of active area units 110. Each active area unit 110 extends parallel to and spaced apart from each other along a direction D1, and is alternately arranged, wherein the direction D1, for example, intersects and is not perpendicular to the y-direction or x-direction. Figure 1 As shown. In one embodiment, each active unit 110 has, for example, the same length L1 in direction D1, and adjacent active units 110 may also have the same spacing g.

[0075] In one embodiment, the formation of the active unit 110 can be achieved by, but is not limited to, the patterning fabrication process described below. For example, a mask layer (not shown) is first formed on a substrate 100, the mask layer including a plurality of mask patterns 101 for defining the active unit 110 and exposing a portion of the substrate 100. An etching process is then performed using the mask layer to remove the portion of the substrate 100 to form at least one shallow trench 102. An insulating material (not shown), such as silicon oxide, silicon nitride, or silicon oxynitride, is then filled into the shallow trench 102 to form a first insulating layer 120 with its top surface 120 aligned with the surface 101a of the mask layer, thereby defining the active unit 110. Figure 1 as well as Figure 2The active unit 110 can be formed by a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, but is not limited thereto.

[0076] As shown in FIG. 1A, a mask layer 130 is formed on the substrate 100 under the premise of retaining the mask pattern 101, and includes a plurality of openings 131 respectively exposing the first insulating layer 120 and the end portion 111 of the active unit 110 located between adjacent active units 110. Figure 3 As shown in FIG. 1A, a mask layer 130 is formed on the substrate 100 under the premise of retaining the mask pattern 101, and includes a plurality of openings 131 respectively exposing the first insulating layer 120 and the end portion 111 of the active unit 110 located between adjacent active units 110. Figure 4 As shown in FIG. 1A, a mask layer 130 is formed on the substrate 100 under the premise of retaining the mask pattern 101, and includes a plurality of openings 131 respectively exposing the first insulating layer 120 and the end portion 111 of the active unit 110 located between adjacent active units 110. Figure 3 As shown in FIG. 1A, a mask layer 130 is formed on the substrate 100 under the premise of retaining the mask pattern 101, and includes a plurality of openings 131 respectively exposing the first insulating layer 120 and the end portion 111 of the active unit 110 located between adjacent active units 110. Figure 3 As shown in FIG. 1A, a mask layer 130 is formed on the substrate 100 under the premise of retaining the mask pattern 101, and includes a plurality of openings 131 respectively exposing the first insulating layer 120 and the end portion 111 of the active unit 110 located between adjacent active units 110. Figure 4 As shown in FIG. 1A, a mask layer 130 is formed on the substrate 100 under the premise of retaining the mask pattern 101, and includes a plurality of openings 131 respectively exposing the first insulating layer 120 and the end portion 111 of the active unit 110 located between adjacent active units 110.

[0077] As shown in FIG. 1A, a mask layer 130 is formed on the substrate 100 under the premise of retaining the mask pattern 101, and includes a plurality of openings 131 respectively exposing the first insulating layer 120 and the end portion 111 of the active unit 110 located between adjacent active units 110. Figure 5 As shown in FIG. 1A, a mask layer 130 is formed on the substrate 100 under the premise of retaining the mask pattern 101, and includes a plurality of openings 131 respectively exposing the first insulating layer 120 and the end portion 111 of the active unit 110 located between adjacent active units 110. Figure 5 As shown in FIG. 1A, a mask layer 130 is formed on the substrate 100 under the premise of retaining the mask pattern 101, and includes a plurality of openings 131 respectively exposing the first insulating layer 120 and the end portion 111 of the active unit 110 located between adjacent active units 110. Figure 6 As shown in FIG. 1A, a mask layer 130 is formed on the substrate 100 under the premise of retaining the mask pattern 101, and includes a plurality of openings 131 respectively exposing the first insulating layer 120 and the end portion 111 of the active unit 110 located between adjacent active units 110. Figure 6 As shown in FIG. 1A, a mask layer 130 is formed on the substrate 100 under the premise of retaining the mask pattern 101, and includes a plurality of openings 131 respectively exposing the first insulating layer 120 and the end portion 111 of the active unit 110 located between adjacent active units 110. Figure 5The cross-sectional view shown shows the exposed top surface 110a and part of the sidewall 110b of the end 111 of the active unit 110, which can also be L-shaped, but is not limited to this. On the other hand, the remaining unreacted active units 110 form active fins 115, so that the active end 113 and the active fins 115 can together constitute multiple active regions 150 within the substrate 100. It should be noted that the active end 113 may include an epitaxial material different from that of the substrate 100. For example, when the substrate 100 is, for example, a silicon substrate, the active end 113 may include silicon germanium, but is not limited to this. Thus, the top surface of the active end 113 may be significantly slightly higher than the top surface of the active fins 115 and the top surface 140a of the second insulating layer 140, and has a height difference h1, such as Figure 7 As shown. On the other hand, the active end 113 may also have a different surface roughness than the substrate 100 (active fin 115). For example, when the substrate 100 is, for example, a silicon substrate, its surface roughness is smaller, while the surface roughness of the active end 113 (e.g., including silicon germanium) is larger. However, the specific difference in roughness may also vary depending on the material, and is not limited to the above. Then, the mask layer 130 and the mask pattern 101 are completely removed.

[0078] Please refer to Figure 6 as well as Figure 7 As shown, a second insulating layer 140 is formed above the first insulating layer 120 of the aforementioned portion, such that the top surface 140a of the second insulating layer 140 is flush with the top surface (i.e., top surface 110a) of the active fin 115, as... Figure 7 As shown. Thus, the first insulating layer 120 and the second insulating layer 140 together constitute an insulating structure 160 within the substrate 100, surrounding the active region 150. The second insulating layer 140 is disposed between adjacent active regions 150 and surrounded by the first insulating layer 120, as shown. Figure 6 As shown. With this configuration, the insulation structure 160 can further isolate the adjacent active region 150 and achieve a better insulation effect.

[0079] Thus, the semiconductor device 300 of the first preferred embodiment of the present invention is completed. The semiconductor device 300 has a plurality of active regions 150 and an insulating structure 160 surrounding the active regions 150. The active regions 150 include active fins 115 of different materials and active ends 113 disposed on both sides of the active fins 115, thereby obtaining a relatively extended length L2 in the direction D1. In this way, when other elements are subsequently formed on the active regions 150, a more stable contact and conductivity effect can be provided through the extended length of the active ends 113 and the epitaxial material.

[0080] However, those skilled in the art should easily understand that, in order to meet the actual product requirements, the semiconductor device and the manufacturing process thereof of the present application can also have other forms or can be achieved by other means, and are not limited to the foregoing. For example, in an embodiment, when the selective epitaxial growth manufacturing process is performed, the range formed by the epitaxial material can be selectively increased to form the active end portion 117 with a relatively large thickness. In this way, the top surface of the active end portion 117 can be significantly higher than the top surface (i.e., the top surface 110a) of the active fin 115 and the top surface 140a of the second insulating layer 140, and has a relatively large height difference h2, as shown in Figure 8 . Under this arrangement, the active region 150a (including the active end portion 117 and the active fin 115) can not only have a further extended length L3 in the direction D1, but the height difference h2 between the active fin 115 and the active end portion 117 can also further increase the contact area with the subsequently formed storage contact plug structure, thereby optimizing the overall structure. Alternatively, in another embodiment, the mask pattern 101 remaining above the end portion 111 of the active cell 110 can also be removed when the etching manufacturing process is performed through the mask layer 130, and part of the exposed first insulating layer 120 is removed, and only the top surface of the end portion 111 of the active cell 110 is exposed, that is, after the etching manufacturing process, part of the top surface 120c of the first insulating layer 120 can be flush with the top surface 110a of the active cell 110 but the sidewall 110b of the end portion 111 of the active cell 110 is not exposed, as shown in Figure 9 . In this way, when the selective epitaxial growth manufacturing process is subsequently performed, the active end portion 213 is only formed on the top surface 110a of the end portion 111 of the active cell 110, so that the active end portion 213 of the present embodiment can appear as a character in a cross-sectional view, as shown in Figure 9 . Thus, through the arrangement of the foregoing two embodiments, the extension range of the active region can also be effectively improved, and it is ensured that the subsequently formed storage contact plug structure can be in direct and stable contact with the active region.

[0081] In addition, those skilled in the art should easily understand that, in order to meet the actual product requirements, the semiconductor device and the manufacturing method thereof of the present application can also have other forms, and are not limited to the foregoing. Further embodiments or variations of the method of the semiconductor device of the present application will be described below. For simplicity of description, the following description mainly focuses on the differences between the embodiments, and the same parts will not be repeated. In addition, the same components in each embodiment of the present application are denoted by the same reference numerals for mutual reference between the embodiments.

[0082] Please refer to Figure 10As shown, a cross-sectional view of a semiconductor device 500 in a preferred embodiment of the present application is illustrated. The semiconductor device 500 in this embodiment is substantially the same as the semiconductor device 300 in the aforementioned first embodiment, including the substrate 100, the active region 150 (including the active fin 115 and the active end 113), the insulating structure 160 (including the insulating layer 120 and the second insulating layer 140), and the like, and thus will not be described again. The main difference between this embodiment and the aforementioned first embodiment is that the semiconductor device 500 in this embodiment additionally includes a plurality of first conductive lines 540 formed in the substrate 100 and a plurality of second conductive lines 560 and a plurality of plugs 590 formed on the substrate 100.

[0083] In detail, the first conductive lines 540 are, for example, parallel to each other and extend along the y direction, across the active region 150 and through the first insulating layer 120 and the second insulating layer 140. In an embodiment, a plurality of trenches (not shown) parallel to each other and spaced apart from each other are first formed in the substrate 100 and extend along the y direction. Then, a dielectric layer 541 covering the entire surface of the trenches, a gate dielectric layer 543 covering the lower half of the surface of the trenches, a gate 545 filling the lower half of the trenches, and a cap layer 547 filling the upper half of the trenches are sequentially formed. In this way, the surface of the cap layer 547 can be flush with the top surface (i.e., the top surface 110a) of the active fin 115, as shown in Figure 10 As shown, the first conductive lines 540 in the substrate 100 can serve as buried word lines (WL) 540 of the semiconductor device 500 and are interleaved with the active fin 115 of the active region 150 to receive or transmit voltage signals of each memory cell (not shown). Although the extension direction of the trenches or the first conductive lines 540 is not specifically shown in the drawings of this embodiment, those skilled in the art should easily understand that, if viewed from a top view, the first conductive lines 540 extending in the y direction should be interleaved with the active region 150 and pass through the insulating structure 160 (including the insulating layer 120 and the second insulating layer 140).

[0084] On the other hand, the second conductive lines 560 are, for example, parallel to each other and extend along the x direction, across the active region 150, and can be vertically interleaved with the first conductive lines 540 in a projection direction (not shown). The second conductive lines 560 and the plugs 590 are alternately arranged in the dielectric layer 580 above the substrate 100, and adjacent plugs 590 and second conductive lines 560 are isolated from each other by a spacer 570, as shown in Figure 10The gap wall 570, for example, includes a first gap wall 571 (e.g., including silicon nitride), a second gap wall 573 (e.g., including silicon oxide), and a third gap wall 575 (e.g., including silicon nitride) stacked in sequence on the sidewall of the second conductive line 560, but the disclosure is not limited thereto. The second conductive line 560, for example, includes a semiconductor layer (e.g., including polysilicon) 561, a barrier layer (e.g., including titanium and / or titanium nitride) 563, a conductive layer (e.g., including tungsten, aluminum, or copper) 565, and a cap layer (e.g., including silicon oxide, silicon nitride, or silicon oxynitride) 567 stacked in sequence, but the disclosure is not limited thereto. It is noted that a bit line contact (BLC) 560a is also formed under the second conductive line 560 and can further extend into the active fin 115 of the substrate 100 and between two adjacent first conductive lines 540 and two adjacent active end portions 113. In the embodiment, the bit line contact 560a, for example, is integrally formed with the semiconductor layer 561 of the second conductive line 560 and directly contacts the active fin 115, but the disclosure is not limited thereto. The plug 590 can simultaneously contact the active fin 115, the active end portion 113, and the cap layer 547 of the first conductive line 540, thereby forming a more stable storage node contact (SNC) structure. It is also noted that when the thickness of the active end portion 113 is significantly higher than that of the active fin 115, the bottom of the plug 590 can also have a corresponding height difference h1, so that the plug 590 can be more stably arranged.

[0085] Thus, the semiconductor device 500 of the embodiment, for example, can serve as a dynamic random access memory (DRAM) device including at least one transistor component (not shown) and at least one capacitor component (not shown) as the smallest constituent unit (memory cell) in a dynamic random access memory array and receiving voltage information from the second conductive line 560 (bit line) and the first conductive line 540 (word line). The active region 150 of the semiconductor device 500 also includes the active fin 115 having different materials and the active end portions 113 arranged on both sides of the active fin 115, so that the plug 590 can be more stably arranged on the active fin 115, the active end portion 113, and the interface therebetween, thereby forming a more stable contact and conductive effect. With the arrangement, the semiconductor device 500 of the embodiment can facilitate more optimized structure and component performance.

[0086] Please refer to Figures 11 to 12The diagram illustrates the fabrication process of a semiconductor device in a second embodiment of the present invention. The fabrication process of the semiconductor device in this embodiment is largely the same as that in the first embodiment described above, and will not be repeated here. The main difference between this embodiment and the first embodiment lies in that the insulating layer 320 is directly used as a mask layer, and etching and selective epitaxial growth processes are performed sequentially.

[0087] In detail, this embodiment involves defining a plurality of active cells 110 on the substrate 100, then removing the mask pattern (not shown), and then forming an insulating layer 320 to further surround and cover all the active cells 110. In other words, the top surface 320a of the insulating layer 320 is higher than the top surface 110a of the active cells 110, such as... Figure 11 As shown.

[0088] Next, a mask layer (not shown) is formed on the substrate 100, which includes a plurality of openings (not shown) that are respectively etched through the mask layer to form a plurality of corresponding openings 321 in the insulating layer 320, exposing the top surface 110a and sidewall 110b of the end 111 of each active unit 110, as shown. Figure 12 As shown in the first embodiment above. Subsequently, the process can proceed as described in the first embodiment above. Figures 5 to 7 As shown, the selective epitaxial growth process is performed while retaining the insulating mask 321 to form the fabrication process described above. Figures 6 to 7 The active end 113 shown, or formed as... Figure 8 The active end 117 is shown, but not limited to this. Then, a planarization process (not shown) is performed to remove the insulating layer 320 above the active unit 110, retaining only the insulating layer 320 on the top surface 320a below the top surface 110a of the active unit 110, which can surround the active unit 110 to form an insulating structure. Thus, the aforementioned active end 113 or active end 117 effectively improves the extension range of the active region, ensuring that the subsequently formed storage contact plug structure can directly and stably contact the active region.

[0089] Please refer to Figures 13 to 15 The diagram illustrates the fabrication process of a semiconductor device according to a third embodiment of the present invention. The fabrication process of the semiconductor device in this embodiment is largely the same as that in the first embodiment described above, and the similarities will not be repeated here. The main difference between the fabrication process in this embodiment and that in the first embodiment is that the active segment 410 is formed using a self-aligned double patterning fabrication process or a self-aligned reverse patterning fabrication process.

[0090] For details, please refer to Figure 13 as well asFigure 14 As shown, firstly, a plurality of active segments 410 are formed in the substrate 100 using the self-aligned dual patterning process or the self-aligned reverse patterning process. Each active segment 410 extends parallel to each other along direction D1 and is surrounded by a first insulating layer 420. Next, a mask layer 430 is formed on the substrate 100, which includes a plurality of openings 431 to partially expose the underlying active segments 410. Then, an etching process is performed through the mask layer 430 to partially remove the active segments 410 exposed from each opening 431, and shallow trenches 102 are formed in the substrate 100, thereby truncating each active segment 410 into the following shapes: Figure 1 The diagram shows multiple active units 110. Furthermore, after the aforementioned etching process, another etching process, such as a wet etching process, can be performed to partially remove the first insulating layer 420 surrounding the active units 110, particularly the first insulating layer 420 adjacent to the ends 111 of the active units 110, thereby forming a structure similar to... Figure 3 The structural pattern shown.

[0091] Subsequently, a selective epitaxial growth process can be performed while retaining the mask layer 430 to form active ends 413 on both sides of the active unit 110, while the remaining active units 110 form active fins 415, constituting the active region 450, as shown below. Figure 15 As shown. It should be noted that in this embodiment, if a top view (not shown, similar) is used... Figure 6 From the top view shown, the active end 413 should be formed on the side of each active unit 110 extending in the y direction, and on the portion of the side adjacent to at least one side extending in the D1 direction, thus presenting an L-shape; while Figure 15 In the cross-sectional view shown, the active end 413 is formed on the exposed surfaces on both sides of the active unit 110 (i.e., Figure 15 The shallow trench 102 shown can be U-shaped on its sidewalls and bottom surface. Then, after forming at the active end 413, a second insulating layer 440 is formed within the shallow trench 102. The top surface 440a of the second insulating layer 440 can be lower than the top surface 110a of the active unit 110, such as... Figure 15 As shown, or in another embodiment, it can be flush with the top surface 110a of the active unit 110. Thus, the remaining first insulating layer 420 and second insulating layer 440 can together constitute the insulating structure of this embodiment. Therefore, the active end 413 can also be formed through the manufacturing process of this embodiment, which can also effectively improve the extension range of the active region 450, ensuring that the subsequently formed storage contact plug structure can make direct and stable contact with the active region.

[0092] Overall, the semiconductor device of the present application is formed with an active region having a composite material. The active region in the semiconductor device includes active fins having different materials and active end portions disposed on both sides of the active fins. The active end portions are formed by a selective epitaxial growth process, so that the active region can have an overall extended length. In this way, the extension range of the active region can be effectively improved, the contact area between the active region and the plug structure can be increased, and the subsequently formed storage contact plug structure can be directly and stably contacted with the active region.

[0093] The above description is merely preferred embodiments of the present application, but not for limiting the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that, include: Substrate; Multiple active regions are defined within the substrate, parallel to and spaced apart from each other. Each active region includes an active fin and active ends disposed on both sides of the active fin. The active fin and the active ends are made of different materials. An insulating structure is disposed within the substrate, surrounding the active regions. Multiple first wires are formed on the substrate and span the active region; Multiple plugs are disposed on the substrate, and the plugs simultaneously contact the active fin and the active end; Multiple second wires are disposed on the substrate and intersect with the active region. The second wires directly contact the active fins and are alternately disposed with the plugs. A spacer wall is disposed on the substrate and located between the second wire and the plug.

2. The semiconductor device according to claim 1, characterized in that, The active fins and the active end caps each have different roughness.

3. The semiconductor device according to claim 1, characterized in that, The active end includes an epitaxial material.

4. The semiconductor device according to claim 1 or 3, characterized in that, There is a height difference between the active end and the active fin.

5. The semiconductor device according to claim 1, characterized in that, The insulation structure includes a first insulation layer and a plurality of second insulation layers, wherein the second insulation layers are respectively disposed between adjacent active regions and surrounded by the first insulation layer.

6. The semiconductor device according to claim 5, characterized in that, The plurality of first wires are disposed within the substrate and intersect with the active region, and the first wires pass through both the first insulating layer and the second insulating layer.

7. The semiconductor device according to claim 1, characterized in that, The top surface of the active fin that contacts the plug is lower than the top surface of the active end that contacts the plug.

8. The semiconductor device according to claim 1, characterized in that, Also includes: Multiple contacts are disposed below the second conductor, and the contacts are located between adjacent active ends.

9. A method for forming a semiconductor device, characterized in that, include: Provide substrate; as well as Multiple active regions and an insulating structure are formed within the substrate, with the insulating structure surrounding the active regions. Each active region includes an active fin and an active end disposed on both sides of the active fin. The active fin and the active end are respectively made of different materials. Multiple plugs are formed on the substrate, and the plugs simultaneously contact the active fins and the active end. Multiple first conductive lines are formed within the substrate and intersect with the active region; A plurality of second conductive lines are formed on the substrate and interspersed with the active region. The second conductive lines directly contact the active fins and are alternately arranged with the plugs. A gap wall is formed on the substrate, the gap wall being located between the second wire and the plug.

10. A method for forming a semiconductor device according to claim 9, characterized in that, Also includes: A plurality of active units are defined within the substrate, the active units extending in one direction parallel to and spaced apart from each other; An insulating layer is formed that surrounds and covers all of the active units; A plurality of openings are formed within the insulating layer, each opening exposing the end of each of the active units; and A planarization process is performed to remove the insulating layer above the active unit, so that the remaining insulating layer forms the insulating structure.

11. A method for forming a semiconductor device according to claim 10, characterized in that, Also includes: A selective epitaxial fabrication process is performed before the planarization process to form the active end at the end of the active unit, and the remaining active units form the active fins.

12. The method for forming a semiconductor device according to claim 9, characterized in that, Also includes: A plurality of active units are defined within the substrate, the active units extending in one direction parallel to and spaced apart from each other; A first insulating layer is formed, the first insulating layer surrounds all the active units, and the top surface of the first insulating layer is flush with the top surface of the active units; A mask layer is formed to cover the first insulating layer and the substrate, the mask layer including a plurality of openings; An etching process is performed through the mask layer to partially remove the first insulating layer and expose the ends of each of the active units; as well as A second insulating layer is formed on the remaining first insulating layer to form the insulating structure. The second insulating layer is disposed between adjacent active regions and surrounded by the first insulating layer.

13. The method for forming a semiconductor device according to claim 12, characterized in that, Also includes: A selective epitaxial fabrication process is performed before the formation of the second insulating layer, forming the active end at the end of the active unit, and the remaining active units form the active fins.

14. The method for forming a semiconductor device according to claim 9, characterized in that, Also includes: A plurality of active segments are formed within the substrate, the active segments extending parallel to and spaced apart from each other along a direction and surrounded by a first insulating layer; a mask layer is formed on the substrate, the mask layer including a plurality of openings to partially expose the active segments below; An etching process is performed through the mask layer to sever the active segment, forming multiple active units; and A selective epitaxial fabrication process is performed to form the active ends on both sides of the active unit.

15. A method for forming a semiconductor device according to claim 14, characterized in that, The active end is U-shaped.

16. The method for forming a semiconductor device according to claim 14, characterized in that, Also includes: After the active end is formed, a second insulating layer is formed, wherein the first insulating layer and the second insulating layer together serve as the insulating structure.

17. The method for forming a semiconductor device according to claim 14, characterized in that, Also includes: After the etching process, a wet etching process is performed to partially remove the first insulating layer surrounding the active unit, followed by the selective epitaxial process.

18. A method for forming a semiconductor device according to claim 17, characterized in that, The active end is L-shaped in a top view.

19. A method for forming a semiconductor device according to claim 9, characterized in that, The top surface of the active fin that contacts the plug is lower than the top surface of the active end that contacts the plug.

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