Semiconductor memory device and method for manufacturing the same

Abstract

Disclosed are a semiconductor memory device and a method for manufacturing the semiconductor memory device. The semiconductor memory device includes: a bit line overlapping a peripheral circuit layer; an interlayer insulating layer and a conductive pattern alternately stacked along a first direction on the bit line; a vertical channel connected to the bit line, the vertical channel penetrating the interlayer insulating layer and the conductive pattern, the vertical channel protruding further in the first direction than the stacked interlayer insulating layer and the conductive pattern; a connection pattern contacting a portion of each vertical channel that protrudes further in the first direction than the stacked interlayer insulating layer and the conductive pattern, the connection pattern connecting the vertical channels; a source channel contacting the connection pattern, the source channel extending in the first direction; and a source select line surrounding the source channel.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method for manufacturing the same. Background Art

[0002] A semiconductor memory device includes memory cells capable of storing data. A three-dimensional semiconductor memory device includes memory cells arranged three-dimensionally, making it possible to increase the number of memory cells per unit area of ​​a substrate.

[0003] In order to improve the integration density of a three-dimensional semiconductor device, the number of stacked memory cells may be increased. Summary of the Invention

[0004] A semiconductor memory device according to an embodiment of the present disclosure may include: a bit line overlapping with a peripheral circuit layer; an interlayer insulating layer and a conductive pattern alternately stacked along a first direction on the bit line; a vertical channel connected to the bit line, the vertical channel penetrating the interlayer insulating layer and the conductive pattern, the vertical channel protruding further in the first direction than the stacked interlayer insulating layer and the conductive pattern; a connecting pattern contacting a portion of each vertical channel protruding further in the first direction than the stacked interlayer insulating layer and the conductive pattern, the connecting pattern connecting the vertical channels; a source channel contacting the connecting pattern, the source channel extending in the first direction; and a source select line surrounding the source channel.

[0005] A semiconductor memory device according to an embodiment of the present disclosure may include: a word line, which includes a first region, a second region and a third region between the first region and the second region; a first vertical channel, which runs through the first region of the word line, and the first vertical channel extends in a first direction; a first connection pattern, which overlaps with the first region of the word line to be spaced apart from the word line in the first direction, and the first connection pattern is in contact with a sidewall of the first vertical channel; a first source channel, which contacts the first connection pattern, and the first source channel extends in the first direction; and a first source selection line, which overlaps with the first region of the word line to be spaced apart from the first connection pattern in the first direction, and the first source selection line surrounds the first source channel.

[0006] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor memory device may include: forming a source selection gate layer on a sacrificial substrate; forming a first source channel passing through the source selection gate layer, the first source channel being in contact with the sacrificial substrate; forming a preliminary connection structure connected to the first source channel; forming a unit stack structure including a first vertical channel and a conductive pattern, wherein the first vertical channel is in contact with the preliminary connection structure and extends in a first direction, and wherein the conductive pattern surrounds the first vertical channel and is stacked spaced apart from each other in the first direction; forming a bit line connected to the first vertical channel; forming a first bonding structure on the bit line; forming a peripheral circuit layer including a peripheral circuit and a second bonding structure overlapping with the peripheral circuit; bonding the first bonding structure and the second bonding structure to each other; removing the sacrificial substrate to expose the first source channel; and forming a source slit insulation layer passing through the source selection gate layer and the preliminary connection structure, the source selection gate layer and the preliminary connection structure overlapping with the peripheral circuit layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, this element can be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the text, like reference numerals refer to like elements.

[0008] Figure 1 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2 is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figures 3A to 3D is a plan view illustrating source select lines, word lines, drain select lines, and bit lines of a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 4A and Figure 4B is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figures 5A to 5C is an enlarged cross-sectional view illustrating a vertical channel and a source channel according to an embodiment of the present disclosure.

[0013] 6A to 6D is a cross-sectional view illustrating a process of forming a source channel according to an embodiment of the present disclosure.

[0014] 7A to 7D is a cross-sectional view illustrating a process of forming a preliminary connection structure according to an embodiment of the present disclosure.

[0015] Figure 8A and Figure 8B is a cross-sectional view illustrating a process of forming a conductive pattern according to an embodiment of the present disclosure.

[0016] Figure 9 is a cross-sectional view illustrating a process of forming a drain selection line according to an embodiment of the present disclosure.

[0017] Figure 10 is a cross-sectional view illustrating a process of forming a bit line according to an embodiment of the present disclosure.

[0018] Figure 11 is a cross-sectional view illustrating a process of forming a first bonding structure according to an embodiment of the present disclosure.

[0019] Figure 12 is a cross-sectional view illustrating a bonding process according to an embodiment of the present disclosure.

[0020] Figure 13A and Figure 13B is a cross-sectional view illustrating a process of forming a source selection line and a connection pattern according to an embodiment of the present disclosure.

[0021] Figure 14 is a cross-sectional view illustrating a process of forming a source layer according to an embodiment of the present disclosure.

[0022] Figure 15A and Figure 15B is a cross-sectional view illustrating a process of forming a preliminary connection structure according to an embodiment of the present disclosure.

[0023] Figure 16 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0024] Figure 17 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments of the concepts of the present disclosure. Embodiments of the concepts of the present disclosure can be implemented in various forms, and they should not be construed as limited to the specific embodiments set forth herein.

[0026] Hereinafter, the terms "first" and "second" are used to distinguish one component from another component, and are not meant to imply a specific number or order of the components. These terms can be used to describe various components, but these components are not limited by these terms.

[0027] Embodiments provide a semiconductor memory device and a method of manufacturing the semiconductor memory device that can improve the stability of a manufacturing process.

[0028] Figure 1 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0029] The semiconductor memory device may include a plurality of memory blocks BLK. Each memory block BLK may include a plurality of memory cell strings MS1 and MS2.

[0030] Memory cell strings MS1 and MS2 may be connected to a common source line CSL via connection patterns CP1 and CP2 and source select transistors SST. Source select transistors SST may be connected in parallel to the common source line CSL. Source select transistors SST may be connected to memory cell strings MS1 and MS2 via connection patterns CP1 and CP2. Memory cell strings MS1 and MS2 may be connected to bit lines BL via drain select transistors DST. Each of memory cell strings MS1 and MS2 may include a plurality of memory cells MC connected in series.

[0031] Gates of the source select transistors SST may be connected to source select lines SSL1 and SSL2 . A plurality of source select transistors SST commonly connected to any one of the source select lines SSL1 and SSL2 may be commonly connected to any one of the connection patterns CP1 and CP2 .

[0032] Each of the connection patterns CP1 and CP2 may electrically connect a plurality of memory cell strings. Connection between each of the connection patterns CP1 and CP2 and the common source line CSL may be controlled by a signal applied to source selection lines SSL1 and SSL2.

[0033] A gate of the drain select transistor DST may be connected to drain select lines DSL1 and DSL2 . The memory cell string MS1 or MS2 may be respectively connected to the drain select transistor DST commonly connected to each of the drain select lines DSL1 and DSL2 .

[0034] Gates of a plurality of memory cells MC may be connected to a plurality of word lines WL. The word lines WL may be disposed at different heights, and gates of memory cells MC disposed at the same height may be connected to the same word line WL.

[0035] Memory cell strings MS1 and MS2 selected by each word line WL may be divided into memory cell string groups that may be individually selected by drain select lines DSL1 and DSL2 .

[0036] To minimize read disturbance, the number of memory cell strings selected by each of the source select lines SSL1 and SSL2 may be smaller than the number of memory cell strings selected by each word line WL. In an embodiment, the memory cell strings that can be individually selected by the source select lines SSL1 and SSL2 may be the same as the memory cell strings that can be individually selected by the drain select lines DSL1 and DSL2.

[0037] Hereinafter, the present disclosure will be described mainly based on an embodiment in which a memory block BLK includes a first source select line SSL1 and a second source select line SSL2 isolated from each other and includes a first drain select line DSL1 and a second drain select line DSL2 isolated from each other. However, the present disclosure is not limited thereto, and the memory block BLK may include three or more source select lines isolated from each other and three or more drain select lines isolated from each other.

[0038] Memory cell strings MS1 and MS2 may include a first memory cell string group including a first memory cell string and a second memory cell string group including a second memory cell string MS2. The first memory cell string MS1 may be connected in parallel to the first connection pattern CP1.

[0039] The second memory cell string MS2 may be connected in parallel to the second connection pattern.

[0040] The first memory cell string MS1 may be connected to the common source line CSL under the control of a source select transistor SST connected to a first source select line SSL1, and may be connected to the bit lines BL under the control of a drain select transistor DST connected to a first drain select line DSL1. The second memory cell string MS2 may be connected to the common source line CSL under the control of a source select transistor SST connected to a second source select line SSL2, and may be connected to the bit lines BL under the control of a drain select transistor DST connected to a second drain select line DSL2.

[0041] The drain select transistors DST may be connected to the first memory cell string MS1 and the second memory cell string MS2, respectively. Each of the first connection pattern CP1 and the second connection pattern CP2 may be connected to two or more source select transistors SST. The number of source select transistors SST connected to the first connection pattern CP1 may be less than the number of first memory cell strings MS1 connected to the first connection pattern CP1. Similarly, the number of source select transistors SST connected to the second connection pattern CP2 may be less than the number of second memory cell strings MS2 connected to the second connection pattern CP2. A pair of first memory cell strings MS1 and second memory cell strings MS2 may be connected to each bit line BL.

[0042] Figure 2 is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure. In the following figures, a first direction D1, a second direction D2, and a third direction D3 may correspond to directions facing an X-axis, a Y-axis, and a Z-axis, respectively, which are orthogonal to each other in an XYZ Cartesian coordinate system. As used herein, a cross direction refers to a different direction. In some embodiments, a cross direction refers to an orthogonal direction.

[0043] The semiconductor memory device may include gate stack structures GST[A] and GST[B] that are isolated from each other. The gate stack structures GST[A] and GST[B] may be isolated from each other by first and second slits SI1 and SI2 that are connected to each other. Figure 2 A first gate stacked structure GST[A] and a second gate stacked structure GST[B] of a semiconductor memory device are illustrated. Each of the first gate stacked structure GST[A] and the second gate stacked structure GST[B] may constitute a memory block.

[0044] The first gate stack structure GST[A] may include a first drain select line DSL1[A], a second drain select line DSL2[A], a plurality of word lines WL[A], a plurality of first vertical channels VC1[A], a plurality of second vertical channels VC2[A], a first connection pattern CP1[A], a second connection pattern CP2[A], a first source select line SSL1[A], a second source select line SSL2[A], a first source channel SC1[A], and a second source channel SC2[A].

[0045] The word lines WL[A] may be stacked spaced apart from each other in the first direction D1. Each word line WL[A] may include a first region R1, a second region R2, and a third region R3 between the first region R1 and the second region R2.

[0046] Each of the first region R1 and the second region R2 may extend in the second direction D2 and the third direction D3. A width of the third region R3 in the third direction D3 may be defined as narrower than a width of each of the first region R1 and the second region R2 in the third direction D3. The third region R3 may extend in the second direction D2.

[0047] The first vertical channel VC1[A] may extend in the first direction D1 to penetrate the first region R1 of each word line WL[A]. The second vertical channel VC2[A] may extend in the first direction D1 to penetrate the second region R2 of each word line WL[A]. In other words, each word line WL[A] may extend to surround the first vertical channel VC1[A] and the second vertical channel VC2[A].

[0048] The first connection pattern CP1[A] may be spaced apart from the word lines WL[A] in the first direction D1 and overlap the first region R1 of each word line WL[A]. The first connection pattern CP1[A] may connect the first vertical channel VC1[A].

[0049] The second connection pattern CP2[A] may be spaced apart from the word lines WL[A] in the first direction D1 and overlap the second region R2 of each word line WL[A]. The second connection pattern CP2[A] may connect the second vertical channels VC2[A].

[0050] The first source select line SSL1[A] may be spaced apart from the first connection pattern CP1[A] in the first direction D1 and overlap the first region R1 of each word line WL[A]. The first source channel SC1[A] may contact the first connection pattern CP1[A] and extend in the first direction D1 to penetrate the first source select line SSL1[A].

[0051] The second source select line SSL2[A] may be spaced apart from the second connection pattern CP2[A] in the first direction D1 and overlap the second region R2 of each word line WL[A]. The second source channel SC2[A] may contact the second connection pattern CP2[A] and extend in the first direction D1 to penetrate the second source select line SSL2[A].

[0052] The first connection pattern CP1[A] may be isolated from the second connection pattern CP2[A] by a source slit SS. The source slit SS may be disposed between the first connection pattern CP1[A] and the second connection pattern CP2[A]. The source slit SS may extend between the first source select line SSL1[A] and the second source select line SSL2[A]. The first source select line SSL1[A] may be isolated from the second source select line SSL2[A] by the source slit SS. The source slit SS may overlap the third region R3 of each word line WL[A].

[0053] The first drain select line DSL1[A] may overlap the first source select line SSL1[A] with the word line WL[A] interposed therebetween. The first drain select line DSL1[A] may extend to surround the first vertical channel VC1[A].

[0054] The second drain select line DSL2[A] may overlap the second source select line SSL2[A] with the word line WL[A] interposed therebetween. The second drain select line DSL2[A] may extend to surround the second vertical channel VC2[A].

[0055] The first drain select line DSL1[A] may be isolated from the second drain select line DSL2[A] by a drain slit SD. The drain slit SD may be disposed between the first drain select line DSL1[A] and the second drain select line DSL2[A]. The drain slit SD may overlap the third region R3 of each word line WL[A] and be disposed between the first vertical channel VC1[A] and the second vertical channel VC2[A].

[0056] Similar to the first gate stack structure GST[A], the second gate stack structure GST[B] may include a first drain selection line DSL1[B], a second drain selection line DSL2[B], a plurality of word lines WL[B], a plurality of first vertical channels VC1[B], a plurality of second vertical channels VC2[B], a first connection pattern CP1[B], a second connection pattern CP2[B], a first source selection line SSL1[B], a second source selection line SSL2[B], a first source channel SC1[B] and a second source channel SC2[B].

[0057] The word line WL[A] of the first gate stack structure GST[A] can be isolated from the word line WL[B] of the second gate stack structure GST[B] by a first slit SI1. The first drain select line DSL1[A] and the second drain select line DSL2[A] of the first gate stack structure GST[A] can be isolated from the first drain select line DSL1[B] and the second drain select line DSL2[B] of the second gate stack structure GST[B] by a first slit SI1. The first source select line SSL1[A] and the second source select line SSL2[A] of the first gate stack structure GST[A] can be isolated from the first source select line SSL1[B] and the second source select line SSL2[B] of the second gate stack structure GST[B] by a second slit SI2.

[0058] According to the above structure, the width WW of each word line WL[A] and WL[B] can be formed to be wider than the width WD of each drain selection line DSL1[A], DSL2[A], DSL1[B] and DSL2[B], the width WS of each source selection line SSL1[A], SSL2[A], SSL1[B] and SSL2[B], and the width WC of each connection pattern CP1[A], CP2[A], CP1[B] and CP2[B].

[0059] The first and second source channels SC1 [A] and SC2 [A] of the first gate stack structure GST [A] and the first and second source channels SC1 [B] and SC2 [B] of the second gate stack structure GST [B] may be connected to a common source line CSL.

[0060] Figures 3A to 3D is a plan view illustrating source select lines, word lines, drain select lines, and bit lines of a semiconductor memory device according to an embodiment of the present disclosure.

[0061] Figure 3A It is an example Figure 2 The first source selection line SSL1[A] and the second source selection line SSL2[A] of the first gate stack structure GST[A] are shown. Figure 2 FIG. 1 is a plan view of an embodiment of a first source select line SSL1 [B] of a second gate stack structure GST [B].

[0062] Reference Figure 3A , the source slit SS may extend in the second direction D2. The second slit SI2 may extend in the second direction D2. The second slit SI2 and the source slit SS may have various shapes, such as a wavy shape or a straight line shape.

[0063] Source select lines SSL1[A], SSL2[A], and SSL1[B] may surround source channels SC1[A], SC2[A], and SC1[B], respectively. Sidewalls of each of the source channels SC1[A], SC2[A], and SC1[B] may be surrounded by a gate insulating layer GI. In other words, each of the source select lines SSL1[A], SSL2[A], and SSL1[B] may surround source channels SC1[A], SC2[A], or SC1[B] with the gate insulating layer GI interposed between the source select lines and the source channels.

[0064] Figure 3B It is an example Figure 2 The word line WL[A] of the first gate stack structure GST[A] and Figure 2 FIG. 1 is a plan view of an embodiment of a word line WL[B] of the second gate stack structure GST[B] shown in FIG.

[0065] Reference Figure 3B , the first slit SI1 may extend in the second direction D2. The first slit SI1 may have various shapes, such as a wavy shape or a straight line shape.

[0066] Word lines WL[A] and WL[B] may surround vertical channels VC1[A], VC2[A], and VC1[B]. Sidewalls of each of vertical channels VC1[A], VC2[A], and VC1[B] may be surrounded by a memory layer ML. In other words, word lines WL[A] and word lines WL[B] may each surround vertical channels VC1[A], VC2[A], or VC1[B], with the memory layer ML interposed between the word lines and the vertical channels.

[0067] A width WB of each of the source channels SC1 [A], SC2 [A], and SC1 [B] may be formed to be wider than a width WA of each of the vertical channels VC1 [A], VC2 [A], and VC1 [B].

[0068] The source channels SC1[A], SC2[A] and SC1[B] can be connected via Figure 2 The connection patterns CP1[A], CP2[A], and CP1[B] shown are connected to the vertical channels VC1[A], VC2[A], and VC1[B]. Therefore, in the present disclosure, the arrangement freedom of the source channels SC1[A], SC2[A], and SC1[B] can be improved. Specifically, even if the source channels SC1[A], SC2[A], and SC1[B] do not overlap with the vertical channels VC1[A], VC2[A], and VC1[B], the source channels SC1[A], SC2[A], and SC1[B] can be connected to the vertical channels VC1[A], VC2[A], and VC1[B]. In an embodiment, the central areas of some of the vertical channels VC1[A], VC2[A], and VC1[B] do not overlap with the central areas of the source channels SC1[A], SC2[A], and SC1[B], but may be offset from the central areas of the source channels SC1[A], SC2[A], and SC1[B].

[0069] In an embodiment, some of the vertical channels VC1[A], VC2[A], and VC1[B] may not overlap with the source channels SC1[A], SC2[A], and SC1[B]. In an embodiment, two or more of the vertical channels VC1[A], VC2[A], and VC1[B] may overlap with some of the source channels SC1[A], SC2[A], and SC1[B].

[0070] Figure 3C It is an example Figure 2 The first drain selection line DSL1[A] and the second drain selection line DSL2[A] of the first gate stack structure GST[A] are shown. Figure 2 FIG. 1 is a plan view of an embodiment of a first drain select line DSL1 [B] of a second gate stack structure GST [B].

[0071] Reference Figure 3C , the drain slit SD may extend in the second direction D2. The drain slit SD may have various shapes, such as a wavy shape or a straight line shape.

[0072] The vertical channels VC1[A], VC2[A], and VC1[B] may extend to penetrate the drain select lines DSL1[A], DSL2[A], and DSL1[B]. A memory layer ML may extend between each of the vertical channels VC1[A], VC2[A], and VC1[B] and each of the drain select lines DSL1[A], DSL2[A], and DSL1[B].

[0073] Figure 3D is a plan view illustrating a bit line according to an embodiment of the present disclosure.

[0074] Reference Figure 3D Each bit line BL can be connected to the vertical channels VC1[A], VC2[A] and VC1[B] via a contact plug CT. The vertical channels VC1[A], VC2[A] and VC1[B] connected to one bit line BL can be formed by Figure 3C The different drain select lines DSL1[A], DSL2[A] and DSL1[B] are shown to control respectively.

[0075] Figure 4A and Figure 4B is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure. Figure 4A and Figure 4B Each of the examples along Figure 3D The cross-sectional structure of the semiconductor memory device is shown along line AA′.

[0076] Reference Figure 4A and Figure 4B Each semiconductor memory device may include source selection lines SSL1[A], SSL2[A], and SSL1[B] disposed between the bit line BL and the common source line CSL. The source selection lines SSL1[A], SSL2[A], and SSL1[B] may be disposed at substantially the same height.

[0077] The multilayer structure 50 may be located between the height at which the source select lines SSL1[A], SSL2[A], and SSL1[B] are provided and the height at which the bit lines BL are provided. The multilayer structure 50 may include interlayer insulating layers 51 and conductive patterns 53 alternately stacked in a first direction D1. The conductive patterns 53 of the multilayer structure 50 may function as word lines WL[A] and WL[B] and drain select lines DSL1[A], DSL2[A], DSL1[B], and DSL2[B]. In an embodiment, the conductive patterns 53 may include conductive patterns 53B adjacent to the bit lines BL and spaced apart from each other in the direction in which the bit lines BL extend. Among the conductive patterns 53, the conductive patterns 53B may function as drain select lines, while the other conductive patterns may function as word lines.

[0078] The connection patterns CP1[A], CP2[A], and CP1[B] may be disposed between a height at which the source selection lines SSL1[A], SSL2[A], and SSL1[B] are disposed and a height at which the multilayer structure 50 is disposed. The connection patterns CP1[A], CP2[A], and CP1[B] may be disposed at substantially the same height.

[0079] The source select lines SSL1[A], SSL2[A], and SSL1[B] may be disposed between a first insulating layer 23 and a second insulating layer 21. The first insulating layer 23 may extend to cover surfaces of the source select lines SSL1[A], SSL2[A], and SSL1[B] facing the common source line CSL. The second insulating layer 21 may extend to cover surfaces of the source select lines SSL1[A], SSL2[A], and SSL1[B] facing the connection patterns CP1[A], CP2[A], and CP1[B].

[0080] The source selection lines SSL1[A], SSL2[A], and SSL1[B] may be spaced apart from the connection patterns CP1[A], CP2[A], and CP1[B] in the first direction D1 by the second insulating layer 21. The source selection lines SSL1[A], SSL2[A], and SSL1[B] may be insulated from the connection patterns CP1[A], CP2[A], and CP1[B] by the second insulating layer 21.

[0081] Source select lines SSL1[A], SSL2[A], and SSL1[B] may be penetrated by source channels SC1[A] and SC2[A]. Source channels SC1[A] and SC2[A] may extend through the second insulating layer 21 and contact connection patterns CP1[A] and CP2[A]. Source channels SC1[A] and SC2[A] may penetrate the first insulating layer 23 and protrude further than the first insulating layer 23 in the first direction D1. A gate insulating layer GI may be disposed between the second insulating layer 21 and the first insulating layer 23 and surround the sidewalls of each of the source channels SC1[A] and SC2[A].

[0082] Source channels SC1[A] and SC2[A] may be connected to a common source line CSL. In an embodiment, the common source line CSL may include a first source layer SL1 and a second source layer SL2, which are stacked spaced apart from each other in a first direction D1. Each of the first source layer SL1 and the second source layer SL2 may extend to overlap with the source select lines SSL1[A], SSL2[A], and SSL1[B]. Each of the first source layer SL1 and the second source layer SL2 may include various conductive materials. The first source layer SL1 may include a conductive material that can provide an ohmic contact. In an embodiment, the first source layer SL1 may include tungsten silicide. The second source layer SL2 may include a conductive material having a lower resistivity than the first source layer SL1. The first source layer SL1 and the second source layer SL2 may be connected to each other via a source contact plug SCT.

[0083] Each of the source channels SC1[A] and SC2[A] may include a source core insulating layer 27, a source channel layer 25, and a doped semiconductor pattern 29. The source channel layer 25 may extend along the inner wall of the gate insulating layer GI and be formed in a tubular shape. The source core insulating layer 27 and the doped semiconductor pattern 29 may fill the central region of each of the source channels SC1[A] and SC2[A] defined by the tubular source channel layer 25.

[0084] The source core insulating layer 27 may make contact with the first source layer SL1 . The doped semiconductor pattern 29 may make contact with any one of the connection patterns CP1 [A] and CP2 [A] corresponding to the doped semiconductor pattern 29 .

[0085] The doped semiconductor pattern 29 may be disposed between any one of the connection patterns CP1 [A] and CP2 [A] and the source core insulating layer 27 .

[0086] The source channel layer 25 may extend to surround the sidewalls of the source core insulating layer 27 and the sidewalls of the doped semiconductor pattern 29. The source channel layer 25 may penetrate the first insulating layer 23 and the second insulating layer 21 and contact any one of the connection patterns CP1[A] and CP2[A] and the first source layer SL1. The source channel layer 25 may include a semiconductor layer material. In an embodiment, the source channel layer 25 may include silicon. The source channel layer 25 and the source core insulating layer 27 may extend into the interior of the first source layer SL1.

[0087] Source channels SC1[A] and SC2[A] may be connected to vertical channels VC1[A] and VC2[A] via connection patterns CP1[A] and CP2[A]. Each of connection patterns CP1[A], CP2[A], and CP1[B] may include a channel contact layer 33. Each of vertical channels VC1[A], VC2[A], and VC1[B] may include a sidewall SW in contact with the channel contact layer 33.

[0088] The channel contact layer 33 may include a first surface SU1 and a second surface SU2 facing opposite directions. Hereinafter, a surface of the channel contact layer 33 facing the source select lines SSL1[A], SSL2[A], and SSL1[B] is designated as the first surface SU1, and a surface of the channel contact layer 33 facing the bit line BL is designated as the second surface SU2.

[0089] Reference Figure 4A According to an embodiment, each of the connection patterns CP1[A], CP2[A], and CP1[B] may further include a first conductive layer 31 and a second conductive layer 35. The first conductive layer 31 may extend along the first surface SU1 of the channel contact layer 33. The second conductive layer 35 may extend along the second surface SU2 of the channel contact layer 33.

[0090] Each of the vertical channels VC1[A], VC2[A], and VC1[B] may protrude further in the first direction D1 than the multilayer structure 50. In an embodiment, each of the vertical channels VC1[A], VC2[A], and VC1[B] may penetrate the second conductive layer 35 and the channel contact layer 33 and extend to the inside of the first conductive layer 31. Therefore, each of the vertical channels VC1[A], VC2[A], and VC1[B] may include a portion surrounded by the first conductive layer 31 and a portion surrounded by the second conductive layer 35.

[0091] The channel contact layer 33 may penetrate the memory layer ML between the first conductive layer 31 and the second conductive layer 35. Therefore, the memory layer ML may be isolated into the first memory pattern ML1 and the second memory pattern ML2 by the channel contact layer 33.

[0092] The first memory pattern ML1 may extend between each of the vertical channels VC1[A], VC2[A], and VC1[B] and the multilayer structure 50 along the sidewalls of the interlayer insulating layer 51 and the sidewalls of the conductive pattern 53. The first memory pattern ML1 may extend between each of the vertical channels VC1[A], VC2[A], and VC1[B] and the second conductive layer 35. The second memory pattern ML2 may be disposed between each of the vertical channels VC1[A], VC2[A], and VC1[B] and the first conductive layer 31.

[0093] In the above, each of the first conductive layer 31, the channel contact layer 33, and the second conductive layer 35 may include a doped semiconductor layer. In an embodiment, each of the first conductive layer 31, the channel contact layer 33, and the second conductive layer 35 may include doped silicon.

[0094] Reference Figure 4B According to an embodiment, each of the connection patterns CP1 [A], CP2 [A], and CP1 [B] may further include a conductive layer 31 ′ extending along the first surface SU1 of the channel contact layer 33 .

[0095] Each of the vertical channels VC1[A], VC2[A], and VC1[B] may penetrate the channel contact layer 33 and extend to the inside of the conductive layer 31 ′. Therefore, each of the vertical channels VC1[A], VC2[A], and VC1[B] may include a portion surrounded by the conductive layer 31 ′.

[0096] The channel contact layer 33 may penetrate the memory layer ML between the conductive layer 31 ′ and the multilayer structure 50 . Therefore, the memory layer ML may be isolated into a first memory pattern ML1 ′ and a second memory pattern ML2 ′ by the channel contact layer 33 .

[0097] The first memory pattern ML1′ may surround a portion of each of the vertical channels VC1[A], VC2[A], and VC1[B] penetrating the multilayer structure 50. The second memory pattern ML2′ may be disposed between each of the vertical channels VC1[A], VC2[A], and VC1[B] and the conductive layer 31′.

[0098] In the above, the channel contact layer 33 may include a doped semiconductor layer. The conductive layer 31' may include a conductive material that can provide an ohmic contact. In an embodiment, the conductive layer 31' may include tungsten silicide.

[0099] Return to reference Figure 4A and Figure 4B Each of the vertical channels VC1[A], VC2[A], and VC1[B] may include a core insulating layer 43, a channel layer 41, and a doped semiconductor pattern 45. The core insulating layer 43 may extend in the first direction D1 to penetrate the interlayer insulating layer 51 and the conductive pattern 53. The core insulating layer 43 may overlap the doped semiconductor pattern 45.

[0100] The channel layer 41 may surround the sidewalls of the core insulating layer 43. The channel layer 41 may extend between the core insulating layer 43 and the first conductive layer 31 or between the core insulating layer 43 and the conductive layer 31′ to close the end of the core insulating layer 43 facing the first source layer SL1. The channel layer 41 may extend to surround the sidewalls of the doped semiconductor pattern 45. The sidewall SW in contact with the channel contact layer 33 may be a partial sidewall of the channel layer 41, and the channel contact layer 33 may be in direct contact with the channel layer 41. The channel layer 41 may include a semiconductor material. In an embodiment, the channel layer 41 may include silicon.

[0101] Vertical channels VC1[A], VC2[A], and VC1[B] may be connected to bit lines BL. Bit lines BL may be connected to vertical channels VC1[A], VC2[A], and VC1[B] via contact plugs CT. Contact plugs CT may penetrate insulating layers 61 and 63 disposed between bit lines BL and multilayer structure 50 and contact vertical channels VC1[A], VC2[A], and VC1[B]. Bit lines BL may extend to overlap source select lines SSL1[A], SSL2[A], and SSL1[B], with multilayer structure 50 interposed between the bit lines and the source select lines.

[0102] In an embodiment, a third insulating layer 61 and a fourth insulating layer 63 may be disposed between the bit line BL and the multilayer structure 50. The fourth insulating layer 63 may fill the first slit SI1 and extend to overlap the third insulating layer 61.

[0103] The drain slit SD may penetrate the third insulating layer 61 and the fourth insulating layer 63. The drain slit SD may be filled with a drain slit insulating layer 65. The drain slit SD and the drain slit insulating layer 65 may extend between the conductive patterns 53B serving as drain selection lines.

[0104] The source slits SS and the second slits SI2 may be filled with first and second source slit insulating layers 81A and 81B, respectively. The first and second source slit insulating layers 81A and 81B may extend between the source selection lines SSL1[A], SSL2[A], and SSL1[B] and between the connection patterns CP1[A], CP2[A], and CP1[B].

[0105] The multilayer structure 50 may overlap with the peripheral circuit layer 10, with the bit line BL interposed between the multilayer structure 50 and the peripheral circuit layer 10. The bit line BL may be connected to the first bonding pad 75 via the first interconnect structure 73. The first interconnect structure 73 and the first bonding pad 75 may be buried in the first insulating structure 71. The peripheral circuit layer 10 may overlap with the bit line BL, with the first interconnect structure 73 and the first bonding pad 75 interposed between the peripheral circuit layer 10 and the bit line BL.

[0106] Peripheral circuit layer 10 may include: substrate 1 including an active area separated by isolation layer 3; peripheral circuit 5 for controlling operations of a memory block, such as programming, reading, or erasing; second interconnect structure 7 connected to peripheral circuit 5; and second bonding pads 15 connected to second interconnect structure 7. Peripheral circuit 5, second interconnect structure 7, and second bonding pads 15 may be buried in second insulating structure 9 provided on substrate 1. Peripheral circuit 5 may include a page buffer circuit for controlling bit lines BL. Second bonding pads 15 may be bonded to first bonding pads 75. Second insulating structure 9 may be bonded to first insulating structure 71.

[0107] Figures 5A to 5C is an enlarged cross-sectional view illustrating a vertical channel and a source channel according to an embodiment of the present disclosure.

[0108] Reference Figure 5A , the vertical channel VC may be surrounded by the conductive pattern 53, and the memory layer ML is interposed between the vertical channel VC and the conductive pattern 53. The memory layer ML may include a tunnel insulating layer TI, a data storage layer DS, and a blocking insulating layer BI.

[0109] The tunnel insulating layer TI may extend along the surface of the channel layer 41 of the vertical channel VC. The tunnel insulating layer TI may include an insulating material through which charges can tunnel. In an embodiment, the tunnel insulating layer TI may include a silicon oxide layer.

[0110] The data storage layer DS may extend along the surface of the tunnel insulating layer TI. The data storage layer DS may include a material layer capable of storing data. In an embodiment, the data storage layer DS may include a nitride layer capable of storing data changed by using Fowler-Nordheim tunneling.

[0111] The blocking insulating layer BI may extend along a surface of the data storage layer DS. The blocking insulating layer BI may include an oxide layer.

[0112] Reference Figure 5B , the vertical channel VC may be surrounded by the channel contact layer 33 of the connection pattern CP. The channel layer 41 of the vertical channel VC may be in contact with the channel contact layer 33 .

[0113] Reference Figure 5A and Figure 5B , the core insulating layer 43 of the vertical channel VC may fill the central region of the vertical channel VC and be surrounded by the channel layer 41 .

[0114] Reference Figure 5C, the source channel SC may be surrounded by the source select line SSL, and a gate insulating layer GI is interposed between the source channel SC and the source select line SSL.

[0115] The source channel SC may include a source channel layer 25. The region surrounded by the source channel layer 25 may be defined as a central region CR of the source channel SC. Figure 4A and Figure 4B The source core insulating layer 27 and the doped semiconductor pattern 29 shown in FIG. 2 fill the central region CR of the source channel SC.

[0116] The gate insulating layer GI may include an oxide of the source select line SSL. In an embodiment, the gate insulating layer GI may include silicon oxide.

[0117] 6A to 6D is a cross-sectional view illustrating a process of forming a source channel according to an embodiment of the present disclosure.

[0118] Reference Figure 6A , a source selection gate layer 107 may be formed on the sacrificial substrate 101. Although not shown in the drawings, the sacrificial substrate 101 may be in contact with an electrostatic chuck (ESC) of a semiconductor manufacturing device. The sacrificial substrate 101 may be a silicon substrate.

[0119] Before forming the source select gate layer 107, an etch stop layer 103 may be formed on the sacrificial substrate 101. The etch stop layer 103 may include a material having an etch selectivity with respect to the sacrificial substrate 101. In an embodiment, the etch stop layer 103 may include a nitride layer.

[0120] Before forming the source select gate layer 107, a first insulating layer 105 may be formed on the etch stop layer 103. After forming the source select gate layer 107, a second insulating layer 109 may be formed on the source select gate layer 107. The source select gate layer 107 may include various conductive materials. In an embodiment, the source select gate layer 107 may include doped silicon.

[0121] Subsequently, a first channel hole 111 may be formed, which penetrates the source select gate layer 107 and exposes the sacrificial substrate 101. The first channel hole 111 may extend to penetrate the etch stop layer 103, the first insulating layer 105, and the second insulating layer 109.

[0122] Reference Figure 6B, a gate insulating layer 113A may be formed on the sidewall of the source select gate layer 107 exposed by the first channel hole 111. In an embodiment, the gate insulating layer 113A may be formed by an oxidation process. When a portion of the sidewall of the source select gate layer 107 including silicon is oxidized, the gate insulating layer 113A may extend into the inside of the first channel hole 111.

[0123] The dummy insulating layer 113B may be formed by oxidizing a portion of the sacrificial substrate 101 when oxidizing the source select gate layer 107 .

[0124] Reference Figure 6C , an etch barrier pattern 115 may be formed. The etch barrier pattern 115 may have an overhanging structure. The etch barrier pattern 115 may extend onto the sidewalls of the first channel holes 111 to cover the gate insulating layer 113A and leave the bottom surface of each first channel hole 111 open. An opening 117 having an upper end and a lower end may be defined by the overhanging structure of the etch barrier pattern 115. The upper end of the opening 117 may have a first width W1, and the lower end of the opening 117 may have a second width W2 that is wider than the first width W1.

[0125] The process of forming the etch barrier pattern 115 may include a process of depositing an amorphous carbon layer through a deposition process having low step coverage and a process of removing a portion of the amorphous carbon layer to expose a bottom surface of each first channel hole 111 .

[0126] Subsequently, the etch barrier pattern 115 may be removed through the opening 117 defined by the etch barrier pattern 115. Figure 6B The dummy insulating layer 113B is shown. Subsequently, the etching barrier pattern 115 may be selectively removed to expose the gate insulating layer 113A.

[0127] Reference Figure 6D , source channels 120A and 120B may be formed to contact the sacrificial substrate 101. The source channels 120A and 120B may respectively fill the first channel holes 111. Each of the source channels 120A and 120B may be spaced apart from the source select gate layer 107 by a gate insulating layer 113A.

[0128] The process of forming source channels 120A and 120B may include forming a source channel layer 121 on the surface of each first channel hole 111 and filling the central region of each first channel hole 111 opened by the source channel layer 121 with a source core insulating layer 123 and a doped semiconductor pattern 125. The source channel layer 121 may be formed by growing silicon from a sacrificial substrate 101 through an epitaxial process or by depositing a silicon layer. The source core insulating layer 123 may fill a portion of each first channel hole 111 on the source channel layer 121. The doped semiconductor pattern 125 may include at least one of n-type impurities and p-type impurities.

[0129] The surface of each of the source channels 120A and 120B may be planarized by a planarization process such as a chemical mechanical polishing process. The source channels 120A and 120B may be connected to an ESC (not shown) supporting the sacrificial substrate 101 .

[0130] 7A to 7D is a cross-sectional view illustrating a process of forming a preliminary connection structure according to an embodiment of the present disclosure.

[0131] Reference Figure 7A A first stacked structure 130A extending to cover the source channels 120A and 120B may be formed on the second insulating layer 109. The first stacked structure 130A may include a first conductive layer 131, a first protective layer 133, a sacrificial layer 135, a second protective layer 137, and a second conductive layer 139 sequentially stacked on the second insulating layer 109. Each of the first conductive layer 131, the first protective layer 133, the sacrificial layer 135, the second protective layer 137, and the second conductive layer 139 may extend to overlap with the source channels 120A and 120B. The first conductive layer 131, the second conductive layer 139, and the sacrificial layer 135 may include silicon, and the first protective layer 133 and the second protective layer 137 may include oxide layers.

[0132] Subsequently, a second stacked structure 140 may be formed on the first stacked structure 130A. The second stacked structure 140 may include first material layers 141 and second material layers 143 alternately stacked on the first stacked structure 130A. In an embodiment, the first material layer 141 may be made of Figure 4A and Figure 4B The interlayer insulating layer 51 shown is made of insulating material, and the second material layer 143 can be made of Figure 4A and Figure 4B The conductive pattern 53 shown is made of a conductive material. In another embodiment, the first material layer 141 can be made of a conductive material for Figure 4A and Figure 4BThe interlayer insulating layer 51 is made of an insulating material, and the second material layer 143 may be made of a sacrificial insulating material having an etching selectivity with respect to the first material layer 141. In an embodiment, the sacrificial insulating material may include a silicon nitride layer.

[0133] Subsequently, a second channel hole 145 may be formed. The second channel hole 145 may penetrate the second stack structure 140 and extend into the first stack structure 130A. The second channel hole 145 may penetrate the second conductive layer 139, the second protective layer 137, the sacrificial layer 135, and the first protective layer 133 of the first stack structure 130A. The second channel hole 145 may have a bottom surface disposed inside the first conductive layer 131.

[0134] During the etching process of the first stack structure 130A and the second stack structure 140 performed to form the second channel hole 145, a ground voltage from an ESC (not shown) of a semiconductor manufacturing device may be applied to the sacrificial substrate 101. The thickness of the first protective layer 133 and the second protective layer 137 may be formed to be thin enough not to hinder the movement of charges. In an embodiment, the thickness of the first protective layer 133 and the second protective layer 137 may be formed to be Therefore, during the etching process of the first stack structure 130A and the second stack structure 140, charges accumulated in the first conductive layer 131, the sacrificial layer 135, and the second conductive layer 139 of the first stack structure 130A may be released through the sacrificial substrate 101 via the source channels 120A and 120B.

[0135] According to an embodiment of the present disclosure, charges accumulated in the first stack structure 130A during the etching process of the first and second stack structures 130A and 140 are discharged through the source channels 120A and 120B contacting the sacrificial substrate 101. Therefore, according to an embodiment of the present disclosure, the arc phenomenon can be alleviated or prevented.

[0136] Continuously, a memory layer 151 may be formed on the surface of each second channel hole 145. The memory layer 151 may include Figure 5A The blocking insulating layer BI, the data storage layer DS and the tunnel insulating layer TI are shown in FIG.

[0137] Subsequently, a vertical channel 150 filling the second channel hole 145 may be formed on the memory layer 151. The process of forming the vertical channel 150 may include forming a channel layer 153 on the surface of the memory layer 151 and filling the central area of ​​each second channel hole 145 opened by the channel layer 153 with a core insulating layer 155 and a doped semiconductor pattern 157. The channel layer 153 may include a semiconductor layer. In an embodiment, the channel layer 153 may include undoped silicon. In an embodiment, a portion of the channel layer 153 surrounding the doped semiconductor pattern 157 may include impurities identical to those of the doped semiconductor pattern 157. In an embodiment, the doped semiconductor pattern 157 may include n-type doped silicon.

[0138] Reference Figure 7B , a third insulating layer 161 may be formed on the second stack structure 140 penetrated by the vertical channel 150. Subsequently, a first slit 163 may be formed. The first slit 163 may penetrate the third insulating layer 161 and the second stack structure 140. The first slit 163 may penetrate the second conductive layer 139 and the second protective layer 137 of the first stack structure 130A to expose the sacrificial layer 135 of the first stack structure 130A.

[0139] Subsequently, a sidewall protective layer 165 may be formed on the sidewalls of the first slit 163. The sidewall protective layer 165 may include a material having an etch selectivity with respect to the sacrificial layer 135. In an embodiment, the sidewall protective layer 165 may include at least one of an oxide layer and a nitride layer.

[0140] Reference Figure 7C , a first opening 167 may be formed. The first opening 167 may expose a sidewall of each vertical channel 150 .

[0141] The process of forming the first opening 167 may include removing the first slit 163 Figure 7B The process of removing the sacrificial layer 135 and the process of removing a portion of the memory layer 151 to expose the channel layer 153 are shown. When removing the sacrificial layer 135, the first conductive layer 131 and the second conductive layer 139 may be formed by Figure 7B The first protective layer 133 and the second protective layer 137 shown in FIG. A portion of the memory layer 151 may be removed through the region where the sacrificial layer 135 is removed. When removing a portion of the memory layer 151, Figure 7B A first protective layer 133 and a second protective layer 137 are shown.

[0142] After the channel layer 153 is exposed through the first opening 167 , the Figure 7B Sidewall protection layer 165 is shown.

[0143] The memory layer 151 may be isolated into a first memory pattern 151A and a second memory pattern 151B by the first opening 167 .

[0144] Reference Figure 7D , a channel contact layer 169 may be formed. The channel contact layer 169 may be filled Figure 7C The first opening 167 is shown and contacts the channel layer 153. The channel contact layer 169 may include a doped semiconductor layer. In an embodiment, the channel contact layer 169 may include doped silicon.

[0145] By reference 7A to 7D The process described above can form a preliminary connection structure 130B. Preliminary connection structure 130B can connect channel layer 153 to source channels 120A and 120B. Preliminary connection structure 130B may include a channel contact layer 169, a first conductive layer 131, and a second conductive layer 139. Channel contact layer 169 may contact channel layer 153. First conductive layer 131 may contact the bottom surface of channel contact layer 169 and contact source channels 120A and 120B. Second conductive layer 139 may contact the top surface of channel contact layer 169 and may be penetrated by first slit 163.

[0146] In an embodiment where the first material layer 141 is made of an insulating material and the second material layer 143 is made of a conductive material, the Figure 9 In the embodiment where the first material layer 141 is made of an insulating material and the second material layer 143 is made of a sacrificial insulating material, the Figure 8A and Figure 8B The process shown is then performed Figure 9 The process shown in .

[0147] Figure 8A and Figure 8B is a cross-sectional view illustrating a process of forming a conductive pattern according to an embodiment of the present disclosure.

[0148] Reference Figure 8A , can be selectively removed through the first slit 163 Figure 7D The second material layer 143 is shown to define a second opening 171 between the first material layers 141. The first memory pattern 151A may be exposed through the second opening 171.

[0149] Reference Figure 8B , can be filled with conductive pattern 173 Figure 8AThe second opening 171 is shown in FIG. The conductive pattern 173 may extend to surround each vertical channel 150 with the first memory pattern 151A interposed therebetween. The conductive patterns 173 may be spaced apart from each other by the first material layer 141 in the extending direction of the vertical channel 150 .

[0150] pass 7A to 7D The process shown and Figure 8A and Figure 8B The process shown can form a preliminary connection structure 130B and a unit stack structure 170. The unit stack structure 170 can include a vertical channel 150 and a conductive pattern 173. The vertical channel 150 can contact the preliminary connection structure 130B. The conductive pattern 173 can surround the vertical channel 150 and be stacked spaced apart from each other.

[0151] As reference Figure 8A and Figure 8B As described above, the conductive pattern 173 may be used instead of the second material layer to form the unit stack structure 170. Although not shown in the drawings, the conductive pattern 173 may be used to form the unit stack structure 170. Figure 7B Before the sidewall protection layer 165 shown in FIG, a process of replacing the second material layer with a conductive pattern 173 is performed.

[0152] Figure 9 is a cross-sectional view illustrating a process of forming a drain selection line according to an embodiment of the present disclosure.

[0153] Reference Figure 9 , a fourth insulating layer 177 may be formed. The fourth insulating layer 177 may fill the first slit 163 and extend over the third insulating layer 161. Subsequently, a drain slit insulating layer 179 may be formed. The drain slit insulating layer 179 may isolate at least one of the conductive patterns 173 into drain select lines 173DSL1, 173DSL2, and 173DSL. In an embodiment, the drain slit insulating layer 179 may penetrate the third insulating layer 161 and the fourth insulating layer 177 and extend to penetrate the uppermost conductive pattern 173T among the conductive patterns 173. The conductive pattern 173 overlapping the drain slit insulating layer 179 may be retained as a word line.

[0154] The vertical channel 150 may include a first vertical channel 150A and a second vertical channel 150B. The drain slit insulating layer 179 may penetrate the uppermost conductive pattern 173T between the first vertical channel 150A and the second vertical channel 150B to isolate the uppermost conductive pattern 173T into a first drain select line 173DSL1 surrounding the first vertical channel 150A and a second drain select line 173DSL2 surrounding the second vertical channel 150B.

[0155] Figure 10is a cross-sectional view illustrating a process of forming a bit line according to an embodiment of the present disclosure.

[0156] Reference Figure 10 , a contact plug 180 may be formed penetrating the third insulating layer 161 and the fourth insulating layer 177. Subsequently, a bit line 181 connected to the contact plug 180 may be formed. The bit line 181 may be connected to the vertical channel 150 via the contact plug 180. The bit line 181 may be connected to a pair of first and second vertical channels 150A and 150B.

[0157] Figure 10 Only the contact plug 180 connected to one bit line 181 is illustrated. Although not shown in the figure, Figure 10 Another pair of the first vertical channel 150A and the second vertical channel 150B among the vertical channels 150 shown in FIG. 1 , which are not connected to the contact plug 180 , may be connected to another bit line via other contact plugs.

[0158] Figure 11 is a cross-sectional view illustrating a process of forming a first bonding structure according to an embodiment of the present disclosure.

[0159] Reference Figure 11 , a first bonding structure 189 may be formed on the bit line 181. The first bonding structure 189 may include a first insulating structure 183 and a first bonding pad 187. The first interconnect structure 185 may be buried in the first insulating structure 183. In an embodiment, the first interconnect structure 185 may be connected to the bit line 181. The first insulating structure 183 may include a multi-layer insulating layer having two or more layers. The first bonding pad 187 may be connected to the bit line 181 via the first interconnect structure 185. The first bonding pad 187 may include metal.

[0160] Figure 12 is a cross-sectional view illustrating a bonding process according to an embodiment of the present disclosure.

[0161] Reference Figure 12 Before performing the bonding process, a peripheral circuit layer 200 may be provided. The peripheral circuit layer 200 may include: a substrate 201 including an isolation layer 203 and a peripheral circuit 205; a second interconnect structure 209 connected to the peripheral circuit 205; and a second bonding structure 210.

[0162] The second bonding structure 210 may include a second insulating structure 207 and a second bonding pad 211. The second insulating structure 207 may be provided on the substrate 201 to cover the peripheral circuit 205. The second interconnect structure 209 may be buried in the second insulating structure 207. The second insulating structure 207 may include a multi-layer insulating layer having two or more layers. The second bonding pad 211 may be connected to the peripheral circuit 205 via the second interconnect structure 209. The second bonding pad 211 may include metal.

[0163] The first bonding structure 189 may be disposed to face the second bonding structure 210. The first bonding structure 189 and the second bonding structure 210 may be bonded to each other. The first bonding pad 187 may be bonded to the second bonding pad 211. The first insulating structure 183 may be bonded to the second insulating structure 207.

[0164] Figure 13A and Figure 13B is a cross-sectional view illustrating a process of forming a source selection line and a connection pattern according to an embodiment of the present disclosure.

[0165] Reference Figure 13A , you can remove Figure 12 In an embodiment, the sacrificial substrate 101 may be removed by using at least one of a chemical mechanical polishing process using a slurry having an etching selectivity with respect to the etch stop layer 103 and a wet etching process using an etchant having an etching selectivity with respect to the etch stop layer 103 .

[0166] The source channels 120A and 120B may be exposed because the sacrificial substrate 101 is removed. When the sacrificial substrate 101 is removed, a portion of the source channel layer 121 may be removed. Therefore, the source core insulating layer 123 of each source channel 120A and 120B may be exposed.

[0167] Reference Figure 13B , source slits 191A and second slits 191B may be formed. Source slits 191A and second slits 191B may penetrate the source select gate layer 107 and the preliminary connection structure 130B. The source select gate layer 107 and the preliminary connection structure 130B may overlap with the peripheral circuit layer 200, with the cell stack structure 170 interposed between the preliminary connection structure 130B and the peripheral circuit layer 200. Each of the source slits 191A and second slits 191B may penetrate the etch stop layer 103, the first insulating layer 105, the second insulating layer 109, the source select gate layer 107, and the preliminary connection structure 130B.

[0168] The source select gate layer 107 may be isolated into source select lines 107SSL1, 107SSL2, and 107SSL by the source slits 191A and the second slits 191B. The preliminary connection structure 130B may be isolated into connection patterns 130CP1, 130CP2, and 130CP by the source slits 191A and the second slits 191B.

[0169] The second slit 191B may overlap the first slit 163. The second slit 191B may extend to penetrate the first conductive layer 131 and the channel contact layer 169 of the preliminary connection structure 130B and extend to the inside of the first slit 163.

[0170] The source channels 120A and 120B may include a first source channel 120A and a second source channel 120B. A source slit 191A may penetrate the source select gate layer 107 between the first source channel 120A and the second source channel 120B. The source select gate layer 107 may be isolated by the source slit 191A into a first source select line 107SSL1 surrounding the first source channel 120A and a second source select line 107SSL2 surrounding the second source channel 120B.

[0171] The source slit 191A may extend between the first vertical channel 150A and the second vertical channel 150B. The preliminary connection structure 130B may be isolated by the source slit 191A into a first connection pattern 130CP1 surrounding the first vertical channel 150A and a second connection pattern 130CP2 surrounding the second vertical channel 150B.

[0172] Figure 14 is a cross-sectional view illustrating a process of forming a source layer according to an embodiment of the present disclosure.

[0173] Reference Figure 14 Before forming the source layer 195, the source slit insulating layer 193 may be filled with the source slit insulating layer 193. Figure 13B After removing each of the source slits 191A and the second slits 191B shown Figure 13B The etch stop layer 103 is shown in FIG.

[0174] Subsequently, a source layer 195 connected to the first source channel 120A and the second source channel 120B may be formed, with the first source channel 120A and the second source channel 120B remaining protruded further than the first insulating layer 105. The source layer 195 may extend over the bit line 181 to overlap the first source channel 120A and the second source channel 120B between the source layer 195 and the bit line 181. Although not shown in the drawings, the source layer 195 may be isolated in units of planes.

[0175] Subsequently, the process for forming Figure 4A 1 and 2. Subsequent processes of the source contact plug SCT and the second source layer SL2 are shown in FIG.

[0176] Figure 15A and Figure 15B is a cross-sectional view illustrating a process of forming a preliminary connection structure according to an embodiment of the present disclosure.

[0177] Reference Figure 15A Before forming the preliminary connection structure, source channels 220A and 220B may be formed. Source channels 220A and 220B may contact the sacrificial substrate 201. Source channels 220A and 220B may extend through the etch stop layer 203, the first insulating layer 205, the source select gate layer 207, and the second insulating layer 209 stacked on the sacrificial substrate 201. The sidewalls of each of the source channels 220A and 220B may be surrounded by a gate insulating layer 213A. The gate insulating layer 213A may be provided between each of the source channels 220A and 220B and the source select gate layer 207.

[0178] You can use reference 6A to 6D The process described above forms the sacrificial substrate 201, the etch stop layer 203, the first insulating layer 205, the source select gate layer 207, the second insulating layer 209, the source channels 220A and 220B, and the gate insulating layer 213A.

[0179] Subsequently, a first stacked structure 230A may be formed on the second insulating layer 209. The first stacked structure 230A may include a conductive layer 231 extending to cover the source channels 220A and 220B, and a sacrificial layer 235 stacked on the conductive layer 231. The conductive layer 231 may be capable of withstanding heat generated in subsequent processes and may include a conductive material that can provide an ohmic contact. In an embodiment, the conductive layer 231 may include tungsten silicide. The sacrificial layer 235 may include a material having an etch selectivity relative to the conductive layer 231. In an embodiment, the sacrificial layer 235 may include silicon.

[0180] Subsequently, a second stacked structure 240 may be formed on the first stacked structure 230A. The second stacked structure 240 may be formed as shown in FIG. Figure 7A The depicted structure includes first material layers 241 and second material layers 243 alternately stacked on the first stack structure 230A.

[0181] Subsequently, a memory layer 251 and a vertical channel 250 may be formed. The memory layer 251 and the vertical channel 250 may penetrate the second stack structure 240 and extend into the conductive layer 231 of the first stack structure 230A. Figure 7AThe memory layer 251 and the vertical channel 250 are formed by the process described above. The vertical channel 250 can be formed as shown in FIG. Figure 7A The depicted structure includes a channel layer 253 , a core insulating layer 256 , and a doped semiconductor pattern 257 .

[0182] Then, as reference Figure 7B As described, the third insulating layer 261 may be formed on the second stack structure 240, and the first slits 263 may be formed through the third insulating layer 261 and the second stack structure 240. The first slits 263 may expose the sacrificial layer 235 of the first stack structure 230A.

[0183] Subsequently, a sidewall protective layer 265 may be formed on the sidewalls of the first slit 263. The sidewall protective layer 265 may include a material having an etch selectivity with respect to the sacrificial layer 235. In an embodiment, the sidewall protective layer 265 may include at least one of an oxide layer and a nitride layer.

[0184] Reference Figure 15B , and reference Figure 7C Similar to what is described, Figure 15A In the state where the second stack structure 240 shown in FIG is protected by the sidewall protection layer 265, the sacrificial layer 235 and a portion of the memory layer 251 are removed. Therefore, the memory layer can be separated into the first memory pattern 251A and the second memory pattern 251B, and the channel layer 253 can be exposed between the first memory pattern 251A and the second memory pattern 251B.

[0185] Then, with reference Figure 7C Similar to the description, a channel contact layer 269 may be formed. The channel contact layer 269 may be disposed between the first memory pattern 251A and the second memory pattern 251B and contact the channel layer 253. The channel contact layer 269 may fill the region where the sacrificial layer is removed.

[0186] By reference Figure 15A and Figure 15B The described process can form a preliminary connection structure 230B that can connect the channel layer 253 to the source channels 220A and 220B.

[0187] Then, you can execute the reference Figure 8A and Figure 8B The formation process of the conductive pattern 273 described in Figure 9 The formation process of the drain selection line described in Figure 10 The process of forming the bit line described in Figure 11 The formation process of the first bonding structure described, referring to Figure 12 The described bonding process, reference Figure 13A and Figure 13B The process for forming the source selection line and the connection pattern described, and the reference Figure 14 The process for forming the source layer described in the following is then performed. Figure 4A 1 and 2. Subsequent processes of the source contact plug SCT and the second source layer SL2 are shown in FIG.

[0188] Figure 16 is a block diagram illustrating a configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0189] Reference Figure 16 , the memory system 1100 includes a memory device 1120 and a memory controller 1110 .

[0190] The memory device 1120 may include: a vertical channel connected to a bit line, the vertical channel extending through a drain select line and a word line; a connection pattern in contact with the vertical channel; a source channel connected to the vertical channel via the connection pattern; and a source select line surrounding the source channel.

[0191] The memory device 1120 may be a multi-chip package configured with a plurality of flash memory chips.

[0192] The memory controller 1110 controls the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as an operating memory for the CPU 1112, which performs overall control operations for data exchange with the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 detects and corrects errors included in data read from the memory device 1120. The memory interface 1115 interfaces with the memory device 1120. The memory controller 1110 may also include a read-only memory (ROM) or the like for storing code data used for interfacing with the host.

[0193] Figure 17 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0194] Reference Figure 17 , the computing system 1200 may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0195] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include a vertical channel connected to a bit line, the vertical channel penetrating a drain select line and a word line, a connection pattern contacting the vertical channel, a source channel connected to the vertical channel via the connection pattern, and a source select line surrounding the source channel.

[0196] According to the present disclosure, charges generated during the manufacturing process of a semiconductor memory device can be released through a source channel in contact with a sacrificial substrate, thereby reducing or preventing arcing. Therefore, the stability of the manufacturing process of the semiconductor memory device can be improved.

[0197] According to the present disclosure, after removing the sacrificial substrate, an etching process for defining source selection lines and connection patterns is performed, thereby reducing the difficulty level of the manufacturing process of the semiconductor memory device.

[0198] According to the present disclosure, the vertical channel and the source channel are electrically connected to each other through the connection pattern, thereby forming a current flow path between the bit line connected to the vertical channel and the common source line connected to the source channel.

[0199] CROSS-REFERENCE TO RELATED APPLICATIONS

[0200] This application claims the benefit of Korean Patent Application No. 10-2020-0110578 filed on August 31, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a bit line, the bit line overlapping the peripheral circuit layer; a source layer, the source layer being located above the bit line; interlayer insulating layers and conductive patterns, the interlayer insulating layers and the conductive patterns being alternately stacked along a first direction between the bit line and the source layer; a vertical channel connected to the bit line, the vertical channel penetrating the interlayer insulating layer and the conductive pattern, the vertical channel protruding further than the stacked interlayer insulating layer and the conductive pattern in the first direction; a connecting pattern contacting a portion of each of the vertical channels that protrudes further than the stacked interlayer insulating layer and the conductive pattern in the first direction, the connecting pattern connecting the vertical channels; a source channel, the source channel being in contact with the connection pattern, the source channel extending in the first direction to contact the source layer; as well as A source select line surrounds the source channel and is spaced apart from the connection pattern and the source layer, such that the source layer is electrically connected to the connection pattern via the source channel depending on a signal applied to the source select line.

2. The semiconductor memory device according to claim 1, wherein At least one of the vertical channels does not overlap with the source channel.

3. The semiconductor memory device according to claim 1, wherein The width of the source channel is wider than the width of each of the vertical channels.

4. The semiconductor memory device according to claim 1, wherein The conductive pattern includes: a drain select line adjacent to the bit line; and a word line disposed between the drain select line and the connection pattern, and The word line has a width wider than that of each of the drain select line, the source select line, and the connection pattern.

5. The semiconductor memory device according to claim 1, wherein The connection pattern includes: a channel contact layer, the channel contact layer being in contact with the vertical channels, the channel contact layer surrounding a sidewall of each of the vertical channels; and A first conductive layer extends along a first surface of the channel contact layer facing the source selection line, and surrounds each of the vertical channels.

6. The semiconductor memory device according to claim 5, wherein The connection pattern further includes a second conductive layer extending along a second surface of the channel contact layer, the second surface facing a direction opposite to the first surface of the channel contact layer, the second conductive layer surrounding each of the vertical channels.

7. The semiconductor memory device according to claim 6, wherein Each of the first conductive layer and the second conductive layer includes a doped silicon layer.

8. The semiconductor memory device according to claim 5, wherein The first conductive layer includes tungsten silicide.

9. The semiconductor memory device according to claim 5, wherein The channel contact layer includes doped silicon.

10. The semiconductor memory device according to claim 5, further comprising: a first memory pattern surrounding a portion of each of the vertical channels penetrating the stacked interlayer insulating layer and the conductive pattern; as well as A second memory pattern is disposed between each of the vertical channels and the first conductive layer, and the second memory pattern is spaced apart from the first memory pattern by the channel contact layer.

11. The semiconductor memory device according to claim 1, wherein The source layer overlaps the connection pattern, and the source channel is interposed between the source layer and the connection pattern.

12. The semiconductor memory device according to claim 11, wherein The source channel includes: a source core insulating layer, the source core insulating layer being in contact with the source layer; a doped semiconductor pattern disposed between the source core insulating layer and the connection pattern, the doped semiconductor pattern being in contact with the connection pattern; and A source channel layer surrounds a sidewall of the source core insulating layer and a sidewall of the doped semiconductor pattern, and extends to contact the source layer and the connection pattern.

13. A semiconductor memory device, comprising: source layer; a word line located above the source layer, the word line including a first region, a second region, and a third region between the first region and the second region; a first vertical channel, the first vertical channel penetrating the first region of the word line, the first vertical channel extending in a first direction; a first connection pattern disposed between the source layer and the word line, the first connection pattern overlapping the first region of the word line to be spaced apart from the word line in the first direction, and contacting a sidewall of the first vertical channel; a first source channel, the first source channel being in contact with the first connection pattern and the source layer, and extending in the first direction; as well as a first source select line overlapping the first region of the word line and spaced apart from the first connection pattern in the first direction, the first source select line surrounding the first source channel; The first source channel is disposed closer to the source layer than the first vertical channel, and is connected to the first vertical channel via the first connection pattern.

14. The semiconductor memory device according to claim 13, further comprising: a second vertical channel, the second vertical channel penetrating the second region of the word line, the second vertical channel extending in the first direction; a second connection pattern overlapping the second region of the word line to be spaced apart from the word line in the first direction, the second connection pattern contacting a sidewall of the second vertical channel; a second source channel, the second source channel being in contact with the second connection pattern and extending in the first direction; as well as A second source select line overlaps the second region of the word line to be spaced apart from the second connection pattern in the first direction, the second source select line surrounding the second source channel.

15. The semiconductor memory device according to claim 14 , further comprising a source slit insulating layer overlapping the third region of the word line, the source slit insulating layer being disposed between the first connection pattern and the second connection pattern, in, The source slit insulating layer extends between the first source select line and the second source select line.

16. The semiconductor memory device according to claim 14, further comprising: a gate insulating layer, the gate insulating layer being respectively disposed between the first source selection line and the first source channel and between the second source selection line and the second source channel; as well as Memory patterns are disposed between the first vertical channel and the word line and between the second vertical channel and the word line, respectively.

17. The semiconductor memory device according to claim 14, wherein The source layer is spaced apart from the first source selection line and the second source selection line in the first direction and overlaps with the first source selection line and the second source selection line, and Wherein, the first source channel and the second source channel extend into the source layer.

18. The semiconductor memory device according to claim 14, further comprising: a first drain select line, the first drain select line overlapping the first source select line, the word line being interposed between the first drain select line and the first source select line, and the first drain select line surrounding the first vertical channel; as well as A second drain select line overlaps the second source select line, the word line is interposed between the second drain select line and the second source select line, and the second drain select line surrounds the second vertical channel.

19. The semiconductor memory device according to claim 18, further comprising a drain slit insulating layer overlapping the third region of the word line, the drain slit insulating layer being disposed between the first drain select line and the second drain select line.

20. The semiconductor memory device according to claim 18, further comprising: a bit line overlapping the first source select line and the second source select line, and the first drain select line, the second drain select line, and the word line being interposed between the bit line and the first source select line and the second source select line; as well as A contact plug extends from the first vertical channel and the second vertical channel toward the bit line.

21. The semiconductor memory device according to claim 20, further comprising: a peripheral circuit layer, the peripheral circuit layer overlapping the first drain select line and the second drain select line, the bit line being interposed between the peripheral circuit layer and the first drain select line and the second drain select line, the peripheral circuit layer including a page buffer circuit; a first interconnect structure connected to the bit line between the page buffer circuit and the bit line; a second interconnect structure connected to the page buffer circuit between the page buffer circuit and the bit line; a first bonding pad in contact with the first interconnect structure between the first interconnect structure and the second interconnect structure; as well as A second bonding pad is in contact with the second interconnect structure between the first interconnect structure and the second interconnect structure, and is bonded to the first bonding pad.

22. The semiconductor memory device according to claim 13, wherein The first connection pattern includes: a channel contact layer surrounding a sidewall of the first vertical channel; and a first conductive layer, the first conductive layer being disposed between the channel contact layer and the first source selection line, the first conductive layer being in contact with the channel contact layer, and Wherein, the first vertical channel extends into the first conductive layer.

23. The semiconductor memory device according to claim 22, wherein The first connection pattern further includes a second conductive layer disposed between the channel contact layer and the word line, and the second conductive layer contacts the channel contact layer.

24. The semiconductor memory device according to claim 22, further comprising: a first memory pattern disposed between the first vertical channel and the word line; as well as A second memory pattern is disposed between the first conductive layer and the first vertical channel, and the second memory pattern is spaced apart from the first memory pattern by the channel contact layer.

25. The semiconductor memory device according to claim 13, wherein The first source channel has a width wider than that of the first vertical channel.

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