Mirror bit sonos flash memory cell

Abstract

The application discloses a mirror bit SONOS flash memory cell, which comprises a selection transistor and a storage transistor. The selection transistor is an enhancement mode MOS transistor and has a first threshold voltage. The storage transistor is a depletion mode SONOS storage transistor and has a second threshold voltage in a state without stored charge. The selection transistor and the storage transistor share a source region and a drain region which are heavily doped with a first conductive type. A channel doping layer which is lightly doped with the first conductive type is formed between the source region and the drain region. A first gate structure of the selection transistor and a second gate structure of the storage transistor are arranged on the channel doping layer. A first gate conductive material layer of the first gate structure has a first work function, and a second gate conductive material layer of the second gate structure has a second work function. The first threshold voltage is adjusted by the first work function, and the second threshold voltage is adjusted by the second work function. The application can simplify the forming process of the channel doping layer of the selection transistor and the storage transistor, and is beneficial to the reduction of the channel length of the whole selection transistor, the whole storage transistor and the whole cell.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit, and in particular to a Mirror-Bit SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) Flash memory cell. BACKGROUND

[0002] The Mirror-Bit SONOS Flash memory cell is generally composed of an enhanced NMOS select transistor and two symmetrically left and right depletion-mode N-type SONOS memory devices, i.e. depletion-mode memory.

[0003] In order to obtain the depletion-mode memory, N-type impurities are ion implanted in the P well to adjust the initial threshold voltage of the memory to a negative value.

[0004] The 1.5T Mirror-Bit SONOS Flash memory cell adopts a structure in which the memory channel and the select transistor channel are closely connected, and the select transistor does not have a separate source region and drain region. The channel of the entire memory cell is very short, and it is very difficult to perform separate threshold voltage adjustment ion implantation for the memory channel. This further limits the size reduction of the SONOS Flash memory cell. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a Mirror-Bit SONOS Flash memory cell that can simplify the formation process of the channel doping layer of the select transistor and the memory transistor, and facilitate the size reduction of the channel length of the entire select transistor, memory transistor and cell.

[0006] To solve the above technical problem, the present application provides a Mirror-Bit SONOS Flash memory cell, which comprises a select transistor and a memory transistor. The select transistor is an enhanced MOS transistor and has a first threshold voltage. The memory transistor is a depletion-mode SONOS memory transistor and has a second threshold voltage in a state without stored charge.

[0007] The select transistor and the memory transistor share a first conductive type heavily doped source region and drain region formed on a semiconductor substrate. A first conductive type lightly doped channel doping layer is formed on the surface of the semiconductor substrate between the source region and the drain region.

[0008] A first gate structure of the select transistor and a second gate structure of the memory transistor are arranged on the channel doping layer. The first gate structure and the second gate structure segmentally control the channel doping layer.

[0009] The first gate structure is composed of a first gate dielectric layer and a first gate conductive material layer.

[0010] The second gate structure is formed by stacking a second gate storage medium layer and a second gate conductive material layer; the second gate storage medium layer adopts an ONO layer.

[0011] The first gate conductive material layer has a first work function, and the second gate conductive material layer has a second work function.

[0012] The channel doping layer has the same doping process structure between the source region and the drain region, so as to facilitate the reduction of channel length.

[0013] The difference between the first threshold voltage and the second threshold voltage is set by the difference between the first work function and the second work function, the first threshold voltage of the selection tube is adjusted by the first work function, and the selection tube is an enhancement mode MOS transistor, and the second threshold voltage of the storage tube is adjusted by the second work function, and the storage tube is a depletion mode SONOS storage transistor.

[0014] Further improvement is that a well region of a second conductivity type is also formed on the semiconductor substrate, and the source region, the drain region and the channel doping layer are all formed in the well region.

[0015] Further improvement is that the semiconductor substrate comprises a silicon substrate.

[0016] Further improvement is that the storage tube and the selection tube are both N-type devices, the first conductivity type is N-type, and the second conductivity type is P-type.

[0017] The first work function is close to the valence band top of the semiconductor material of the semiconductor substrate.

[0018] The second work function is close to the conduction band bottom of the semiconductor material of the semiconductor substrate.

[0019] Further improvement is that the first gate conductive material layer adopts a first polysilicon gate, and the first polysilicon gate has P-type heavy doping and thus has the first work function.

[0020] Further improvement is that the second gate conductive material layer adopts a second polysilicon gate, and the second polysilicon gate has N-type heavy doping and thus has the second work function.

[0021] Further improvement is that the storage tube and the selection tube are both P-type devices, the first conductivity type is P-type, and the second conductivity type is N-type.

[0022] The first work function is close to the conduction band bottom of the semiconductor material of the semiconductor substrate.

[0023] The second work function is close to the valence band top of the semiconductor material of the semiconductor substrate.

[0024] Further improvement is that the first gate conductive material layer adopts a first polysilicon gate with N-type heavy doping and thus with the first work function.

[0025] Further improvement is that the second gate conductive material layer adopts a second polysilicon gate with P-type heavy doping and thus with the second work function.

[0026] Further improvement is that the mirror bit SONOS flash memory cell is of 1.5T structure.

[0027] Further improvement is that two second gate structures are arranged on the channel doping layer and symmetrically arranged on two sides of the first gate structure.

[0028] Further improvement is that the two second gate structures are self-aligned on two sides of the first gate structure.

[0029] Further improvement is that a first side wall is self-aligned on two sides of the first gate structure; and the inner side of each second gate structure and the side of the corresponding first gate structure are isolated by the corresponding first side wall.

[0030] Further improvement is that the outer side of each second gate structure is self-aligned with a second side wall.

[0031] The source region and the drain region are self-aligned with the corresponding second side wall.

[0032] Further improvement is that two first-conductive-type lightly-doped drain regions are self-aligned in the semiconductor substrate on the outer side of the two second gate structures.

[0033] Further improvement is that the lightly-doped drain regions are formed by first-conductive-type light doping ion implantation after the formation of the second gate structure on the outer side.

[0034] Alternatively, the lightly-doped drain regions are directly formed by extending the channel doping layer to the outer side of the second gate structure.

[0035] The process conditions of the channel doping layer of the select transistor and the storage transistor are set to be the same, and the threshold voltages of the two are adjusted by the work functions of the corresponding gate conductive material layers, so that the channel doping layer between the source region and the drain region is kept to be the same process structure under the condition of ensuring that the select transistor and the storage transistor are respectively of the enhancement type and the depletion type, thus avoiding the need of photolithography definition and alignment between different regions for forming the channel doping layer with different process structures, and the forming process of the channel doping layer of the select transistor and the storage transistor can be simplified, thereby facilitating the reduction of the channel length of the whole select transistor, the whole storage transistor and the whole unit, and the chip integration can be improved.

[0036] In addition, the process structure of the channel doping layer of the present application can also save the photolithography process, and thus the process cost can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0037] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0038] Figure 1 is a structure schematic diagram of the mirror bit SONOS flash memory unit of the embodiment of the present application;

[0039] Figures 2A-2I is a structure schematic diagram in each step of the manufacturing method of the mirror bit SONOS flash memory unit of the embodiment of the present application. DETAILED DESCRIPTION

[0040] As shown in Figure 1 is a structure schematic diagram of the mirror bit SONOS flash memory unit of the embodiment of the present application; the mirror bit SONOS flash memory unit of the embodiment of the present application comprises a select transistor and a storage transistor, the select transistor is an enhancement type MOS transistor and has a first threshold voltage, and the storage transistor is a depletion type SONOS storage transistor and has a second threshold voltage in the state of not storing charges.

[0041] The select transistor and the storage transistor share the first conductive type heavily doped source region and drain region formed on the semiconductor substrate 101, and the first conductive type lightly doped channel doping layer 103 is formed on the surface of the semiconductor substrate 101 between the source region and the drain region. In the embodiment of the present application, the source region and the drain region are in a symmetrical structure and are both composed of the first conductive type heavily doped region corresponding to the mark 110.

[0042] The first gate structure of the select transistor and the second gate structure of the storage transistor are arranged on the channel doping layer 103. The first gate structure and the second gate structure segmentally control the channel doping layer 103.

[0043] The first gate structure is formed by stacking a first gate dielectric layer 104 and a first gate conductive material layer 105.

[0044] The second gate structure is formed by stacking a second gate storage dielectric layer 106 and a second gate conductive material layer 107; the second gate storage dielectric layer 106 adopts an ONO layer, which includes a bottom oxide layer 106a, an intermediate nitride layer 106b and a top oxide layer 106c.

[0045] The first gate conductive material layer 105 has a first work function, and the second gate conductive material layer 107 has a second work function.

[0046] The channel doping layer 103 has the same doping process structure between the source region and the drain region, so as to facilitate the reduction of channel length.

[0047] The difference between the first threshold voltage and the second threshold voltage is set by the difference between the first work function and the second work function; the first threshold voltage of the select transistor is adjusted by the first work function, and the select transistor is an enhancement-mode MOS transistor; the second threshold voltage of the storage transistor is adjusted by the second work function, and the storage transistor is a depletion-mode SONOS storage transistor.

[0048] In the embodiment of the present application, a well region 102 of a second conductive type is further formed on the semiconductor substrate 101, and the source region, the drain region and the channel doping layer 103 are all formed in the well region 102.

[0049] The semiconductor substrate 101 includes a silicon substrate.

[0050] The storage transistor and the select transistor are both N-type devices, the first conductive type is N-type, and the second conductive type is P-type. The first work function is close to the valence band top of the semiconductor material of the semiconductor substrate 101. The second work function is close to the conduction band bottom of the semiconductor material of the semiconductor substrate 101. Preferably, the first gate conductive material layer 105 adopts a first polysilicon gate, which has P-type heavy doping and thus has the first work function. The second gate conductive material layer 107 adopts a second polysilicon gate, which has N-type heavy doping and thus has the second work function.

[0051] In other embodiments, the storage tube and the selection tube are both P-type devices, the first conductivity type is P-type, and the second conductivity type is N-type. The first work function is close to the conduction band bottom of the semiconductor material of the semiconductor substrate 101. The second work function is close to the valence band top of the semiconductor material of the semiconductor substrate 101. Preferably, the first gate conductive material layer 105 adopts a first polysilicon gate, which is heavily doped with N-type and thus has the first work function. The second gate conductive material layer 107 adopts a second polysilicon gate, which is heavily doped with P-type and thus has the second work function.

[0052] In the field of semiconductor technology, the threshold voltage of a MOS transistor and the type of a device, i.e., depletion type and enhancement type, are one-to-one corresponding. For an N-type device, the threshold voltage of a depletion type MOS transistor is less than 0V, so that the device is turned on when the gate-source voltage of the device is 0V. When the device needs to be turned off, a negative voltage needs to be applied to the gate, so that the gate-source voltage is negative and the absolute value is greater than the threshold voltage, so that the carriers, i.e., electrons, in the channel region are depleted, and the device is turned off. Conversely, the threshold voltage of an enhancement type MOS transistor is greater than 0V, so that the device is turned off when the gate-source voltage is 0V. If the device needs to be turned on, a positive voltage needs to be applied to the gate, so that the gate-source voltage is greater than the threshold voltage, so that the carriers are attracted into the channel, and the device is turned on.

[0053] According to the working principle, when the selection tube and the storage tube are both N-type devices, the first threshold voltage is positive, so that the selection tube is an enhancement type MOS transistor, and the first threshold voltage being positive and the selection tube being an enhancement type MOS transistor are one-to-one corresponding. The second threshold voltage is negative, so that the storage tube is a depletion type SONOS storage transistor, and the second threshold voltage being negative and the storage tube being a depletion type SONOS storage transistor are also one-to-one corresponding. Under the condition that the selection tube is a depletion type, the specific size of the first threshold voltage can be set according to actual needs, and under the condition that the storage tube is a depletion type SONOS storage transistor, the specific size of the second threshold voltage can be set according to actual needs.

[0054] In the embodiment of the application, the mirror bit SONOS flash memory cell is a 1.5T type structure.

[0055] The two second gate structures are arranged on the channel doped layer 103 and symmetrically arranged on both sides of the first gate structure.

[0056] Two second gate structures are self-aligned and formed on both sides of the first gate structure. Preferably, first sidewalls 202 are self-aligned and formed on both sides of the first gate structure; the inner side surface of each second gate structure and the corresponding side surface of the first gate structure are isolated by the corresponding first sidewalls 202. A hard mask layer 201 is also formed on top of the first gate conductive material layer 105, and the top of the hard mask layer 201 is opened to expose the top surface of the first gate conductive material layer 105.

[0057] The outer surfaces of both second gate structures are self-aligned to form second sidewalls 109. Preferably, the second sidewalls 109 are formed by stacking silicon oxide sidewalls and silicon nitride sidewalls.

[0058] The source region and the drain region are self-aligned with the corresponding second sidewall 109.

[0059] Two lightly doped drain regions 108 of a first conductivity type are self-aligned and formed in the semiconductor substrate 101 on the outer sides of the two second gate structures. The lightly doped drain regions 108 are formed on the outer sides of the second gate structures via lightly doped ion implantation of the first conductivity type. In other embodiments, the lightly doped drain regions 108 can also be formed directly by extending the channel doped layer 103 outwards from the outer side of the second gate structure.

[0060] Unlike existing technologies that require different doping of the channel doping layer 103 to adjust the select transistor and memory transistor in a mirrored SONOS flash memory cell to enhancement-mode and depletion-mode structures respectively, this embodiment of the invention sets the process conditions of the trench doping layer of the select transistor and memory transistor to be the same. The threshold voltage of the two transistors is adjusted by the work function of the corresponding gate conductive material layer. In this way, while ensuring that the select transistor and memory transistor are enhancement-mode and depletion-mode structures respectively, the channel doping layer 103 between the source and drain regions is kept to have the same process structure. This avoids the need for photolithography definition and alignment between different regions when forming channel doping layers 103 with different process structures. Therefore, this embodiment of the invention simplifies the formation process of the channel doping layer 103 of the select transistor and memory transistor, which is beneficial to reducing the channel length of the entire select transistor, memory transistor and the entire cell, thereby improving chip integration.

[0061] In addition, since the process structure of the channel doped layer 103 in this embodiment of the invention can save on photolithography, it can also reduce process costs.

[0062] like Figures 2A to 2I The diagram shown is a structural schematic of each step in the manufacturing method of the mirror-bit SONOS flash memory cell according to an embodiment of the present invention. The manufacturing method of the mirror-bit SONOS flash memory cell according to an embodiment of the present invention includes the following steps:

[0063] like Figure 2A As shown, the semiconductor substrate 101 is provided.

[0064] A well region 102 of a second conductivity type is formed on the semiconductor substrate 101.

[0065] Subsequently, ion implantation is performed to form a lightly doped channel layer 103 of the first conductivity type.

[0066] like Figure 2B As shown, the first gate dielectric layer 104 forms the first gate structure of the selector transistor.

[0067] like Figure 2C As shown, a first gate conductive material layer 105 is formed, and the first gate conductive material layer and the first gate dielectric layer 104 are patterned and etched to form the first gate structure formed by the first gate dielectric layer 104 and the first gate conductive material layer 105 stacked together.

[0068] In patterned etching, a hard mask layer 201 is also formed on the top surface of the first gate conductive material layer 105, followed by photolithography definition and then etching.

[0069] The first gate structure controls the channel doped layer 103 it covers, i.e., controls the channel's on and off states. The threshold voltage for the channel's on and off states controlled by the first gate structure is a first threshold voltage. The first gate conductive material layer 105 has a first work function, which adjusts the first threshold voltage of the select transistor and makes the select transistor an enhancement-mode MOS transistor.

[0070] When both the memory transistor and the select transistor in the mirrored SONOS flash memory cell are N-type devices, the first conductivity type is N-type and the second conductivity type is P-type. The first work function is close to the valence band top of the semiconductor material of the semiconductor substrate 101. Preferably, the first gate conductive material layer 105 is a first polysilicon gate, which is heavily P-type doped and thus has the first work function. In other embodiments, when both the memory transistor and the select transistor in the mirrored SONOS flash memory cell are P-type devices, the first conductivity type is P-type and the second conductivity type is N-type. The first work function is close to the conduction band bottom of the semiconductor material of the semiconductor substrate 101. Preferably, the first gate conductive material layer 105 is a first polysilicon gate, which is heavily N-type doped and thus has the first work function.

[0071] like Figure 2D As shown, a first sidewall 202 is formed on the side of the first gate structure.

[0072] As shown in FIG. 1C, a second gate storage medium layer 106 is formed to form the second gate structure. The second gate storage medium layer 106 is an ONO layer, which includes a bottom oxide layer 106a, a middle nitride layer 106b, and a top oxide layer 106c. Figure 2E

[0073] As shown in FIG. 1D, a second gate conductive material layer 107 is formed to form the second gate structure of the storage tube self-aligned on both sides of the first gate structure. The second gate conductive material layer 107 has a second work function. The second threshold voltage of the storage tube is adjusted by the second work function, and the storage tube is a depletion-mode SONOS storage transistor. Figure 2F

[0074] When the storage tube is an N-type device, the second work function is close to the conduction band bottom of the semiconductor material of the semiconductor substrate 101. Preferably, the second gate conductive material layer 107 is a second polysilicon gate with N-type heavy doping and thus has the second work function. In other embodiments, the storage tube can be a P-type device, and the second work function is close to the valence band top of the semiconductor material of the semiconductor substrate 101. Preferably, the second gate conductive material layer 107 is a second polysilicon gate with P-type heavy doping and thus has the second work function.

[0075] Figure 2G As shown in FIG. 1E, a light doping drain implantation (LDD implantation) is performed to form two first-conductivity-type light doping drain regions 108 in the semiconductor substrate 101 outside the two second gate structures. In other embodiments, the light doping drain region 108 can be formed directly by extending the channel doping layer 103 outside the outer side of the second gate structure.

[0076] Figure 2H As shown in FIG. 1F, a second side wall 109 is formed self-aligned on the outer side of the two second gate structures. Preferably, the second side wall 109 is formed by stacking a silicon oxide side wall and a silicon nitride side wall.

[0077] Figure 2I As shown in FIG. 1G, a first-conductivity-type heavy doping ion implantation is performed to form a source region and a drain region composed of two first-conductivity-type heavy doping regions corresponding to two marks 110 self-aligned outside the two second side walls 109.

[0078] Figure 1 As shown in FIG. 1H, the hard mask layer 201 on the top of the first gate conductive material layer 105 is opened, and a contact hole will be formed on the top of the first gate conductive material layer 105 later to finally realize the lead-out of the first gate conductive material layer 105. ​​​​​​

[0079] The application has been described in detail by specific embodiments above, but these do not constitute limitation of the application. Many variations and improvements can be made by those skilled in the art without departing from the principles of the application, and these should also be considered as within the protection scope of the application.

Claims

1. A mirror bit SONOS flash memory cell, comprising: The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell.

2. The mirror bit SONOS flash memory cell of claim 1, wherein: The application relates to a mirror bit SONOS flash memory cell.

3. The mirror bit SONOS flash memory cell of claim 2, wherein: The application relates to a mirror bit SONOS flash memory cell.

4. The mirror bit SONOS flash memory cell of claim 2, wherein: The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell.

5. The mirror bit SONOS flash memory cell of claim 4, wherein: The application relates to a mirror bit SONOS flash memory cell.

6. The mirror bit SONOS flash memory cell of claim 4, wherein: The application relates to a mirror bit SONOS flash memory cell.

7. The mirrored SONOS flash memory cell as described in claim 2, characterized in that: The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell.

8. The mirror bit SONOS flash memory cell of claim 7, wherein: The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. The application relates to a mirror bit SONOS flash memory cell. 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10. The mirrored SONOS flash memory cell as described in claim 1, characterized in that: Two second gate structures are self-aligned formed on two sides of the first gate structure.

11. The mirrored SONOS flash memory cell as described in claim 10, characterized in that: First side walls are self-aligned formed on two sides of the first gate structure; and the inner side surface of each second gate structure and the side surface of the corresponding first gate structure are isolated by the corresponding first side wall.

12. The mirror bit SONOS flash memory cell of claim 11, wherein: The outer side surfaces of the two second gate structures are self-aligned formed with second side walls. The source region and the drain region are self-aligned with the second side walls.

13. The mirrored SONOS flash memory cell as described in claim 12, characterized in that: Two first-conductive-type lightly doped drain regions are self-aligned formed in the semiconductor substrate on the outer side surfaces of the two second gate structures.

14. The mirrored SONOS flash memory cell as described in claim 13, characterized in that: The lightly doped drain regions are formed by first-conductive-type ion implantation after the outer side surfaces of the second gate structures are formed. Alternatively, the lightly doped drain regions are directly formed by extending the channel doping layer to the outer side surfaces of the second gate structures.

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