Preparation method of array substrate and array substrate

Abstract

The present application discloses a method for manufacturing an array substrate and an array substrate. The array substrate includes an oxide semiconductor layer, a gate electrode, and a metal oxide insulating layer formed between the oxide semiconductor layer and the gate electrode, and the metal oxide insulating layer is in contact with the oxide semiconductor layer. Wherein, after the step of forming the metal oxide insulating layer, the method for manufacturing the array substrate includes the following step: performing a laser irradiation treatment on the metal oxide insulating layer. The present application improves the mobility of the oxide TFT.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a method for manufacturing an array substrate and an array substrate. Background Art

[0002] In the field of active matrix flat panel displays, it mainly includes active matrix liquid crystal displays (AMLCD) and active matrix organic light-emitting diodes (AMOLED). Among them, thin film transistors, as pixel switches in display products, play an irreplaceable role. Since high resolution, large size, and flexible display have become new directions for the development of display technologies, higher requirements have been put forward for the performance of thin film transistors.

[0003] Oxide thin film transistors (TFT) are particularly prominent in large size, high resolution, and flexible displays due to their amorphous structure, higher mobility than a-Si, and lower cost. In order to improve the stability of oxide TFTs, TFTs with an etch stop layer (ESL) structure are widely used. This structure can effectively reduce the influence of external environmental factors and etch damage to the source and drain electrodes on the back channel. However, the array manufacturing method of the ESL structure requires more photomask steps and significantly increases the TFT size and parasitic capacitance. The TFT with a back channel etch (BCE) structure does not require an etch stop layer, and the channel can be significantly reduced compared to the ESL structure. Therefore, it has a relatively lower production cost and technical advantages compared to the ESL structure. However, the back channel is extremely vulnerable to the influence of post-processes, resulting in poor device performance. Therefore, its process requirements are relatively high, and it is generally used in LCDs. For top-gate structure TFTs, the overlap between the source and drain electrodes and the gate is small, and the parasitic capacitance is small. However, the number of photomasks is large and the cost is high, and it is widely used in AMOLEDs. With the continuous improvement of display requirements, that is, the popularization of high resolution and high refresh rate, higher requirements have been put forward for the mobility of TFTs. Currently, the mobility of oxide TFTs available for mass production is relatively low. Therefore, improving the mobility of oxide TFTs has become a technical problem to be solved urgently. Summary of the Invention

[0004] Embodiments of the present application provide a method for manufacturing an array substrate and an array substrate to improve the mobility of oxide TFTs.

[0005] An embodiment of the present application provides a method for preparing an array substrate, wherein the array substrate comprises an oxide semiconductor layer, a gate, and a metal oxide insulating layer formed between the oxide semiconductor layer and the gate, wherein the metal oxide insulating layer is in contact with the oxide semiconductor layer, wherein after the step of forming the metal oxide insulating layer, the method for preparing the array substrate comprises the following steps:

[0006] The metal oxide insulating layer is irradiated with laser.

[0007] Optionally, in some embodiments of the present application, in the step of laser irradiating the metal oxide insulating layer, the laser intensity in the laser irradiation is positively correlated with the oxygen vacancy content in the metal oxide insulating layer.

[0008] Optionally, in some embodiments of the present application, after the step of subjecting the metal oxide insulating layer to laser irradiation, the oxygen vacancy content in the metal oxide insulating layer is greater than 23%.

[0009] Optionally, in some embodiments of the present application, the material of the metal oxide insulating layer includes Ta 2 O 5 、ZrO 2 , HfO 2 、TiO 2 、Al 2 O 3 、SrO 2 and La 2 O 3 One or more of .

[0010] Optionally, in some embodiments of the present application, the material of the metal oxide insulating layer is Ta 2 O 5 .

[0011] Optionally, in some embodiments of the present application, the thickness of the metal oxide insulating layer is 20nm-50nm.

[0012] An embodiment of the present application further provides an array substrate, which is manufactured using the method for manufacturing an array substrate as described in any of the aforementioned embodiments.

[0013] Optionally, in some embodiments of the present application, the array substrate further includes a gate insulating layer, which is disposed on a side of the metal oxide insulating layer close to the gate, and the material of the gate insulating layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0014] Optionally, in some embodiments of the present application, the array substrate further includes a substrate, the gate is located on the side of the oxide semiconductor layer close to the substrate, and the array substrate further includes:

[0015] A source-drain metal layer disposed on the side of the oxide semiconductor layer away from the metal oxide insulating layer, the source-drain metal layer including a source electrode and a drain electrode;

[0016] A first passivation layer disposed on the side of the source-drain metal layer away from the oxide semiconductor layer;

[0017] An organic insulating layer disposed on the side of the first passivation layer away from the source-drain metal layer;

[0018] A common electrode disposed on the side of the organic insulating layer away from the first passivation layer;

[0019] A second passivation layer disposed on the side of the common electrode away from the organic insulating layer; and

[0020] A pixel electrode disposed on the side of the second passivation layer away from the common electrode;

[0021] Wherein, a contact hole is formed in the array substrate, the contact hole sequentially penetrates through the second passivation layer, the organic insulating layer, and the first passivation layer, and exposes the drain electrode, and the pixel electrode is connected to the drain electrode in the contact hole.

[0022] Optionally, in some embodiments of the present application, the array substrate further includes a substrate, the gate is located on the side of the oxide semiconductor layer away from the substrate, and the array substrate further includes:

[0023] A light-shielding layer disposed on the side of the oxide semiconductor layer close to the substrate;

[0024] A buffer layer disposed between the light-shielding layer and the oxide semiconductor layer;

[0025] An interlayer dielectric layer disposed on the side of the gate away from the gate insulating layer;

[0026] A source-drain metal layer disposed on the side of the interlayer dielectric layer away from the gate, the source-drain metal layer including a source electrode and a drain electrode;

[0027] A passivation layer disposed on the side of the source-drain metal layer away from the interlayer dielectric layer, a contact hole is formed in the passivation layer, and the contact hole exposes the drain electrode; and

[0028] A pixel electrode disposed on the side of the passivation layer away from the source-drain metal layer, the pixel electrode is connected to the drain electrode in the contact hole.

[0029] Compared with the method for preparing an array substrate in the prior art, in the method for preparing an array substrate provided in the present application, the array substrate includes an oxide semiconductor layer, a gate electrode, and a metal oxide insulating layer formed between the oxide semiconductor layer and the gate electrode. The metal oxide insulating layer is in contact with the oxide semiconductor layer. In the present application, after the step of forming the metal oxide insulating layer, the metal oxide insulating layer is irradiated with a laser, so as to be able to regulate the content of oxygen vacancies in the metal oxide insulating layer. Under a positive gate bias, the number of oxygen vacancies at the contact interface between the metal oxide insulating layer and the oxide semiconductor layer is increased, thereby improving the mobility of the thin film transistor. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. The drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0031] Figure 1 is a schematic flow chart of the method for preparing an array substrate provided in the present application.

[0032] Figure 2 is a schematic flow chart of the method for preparing an array substrate provided in Example 1 of the present application

[0033] Figure 3 is a schematic structural diagram of the array substrate prepared in Example 1 of the present application.

[0034] Figure 4 is a schematic flow chart of the method for preparing an array substrate provided in Example 2 of the present application.

[0035] Figure 5 is a schematic structural diagram of the array substrate prepared in Example 2 of the present application.

[0036] Figure 6 is a schematic structural diagram of the array substrate provided in the first embodiment of the present application.

[0037] Figure 7 is a schematic structural diagram of the array substrate provided in the second embodiment of the present application. Detailed Description of the Embodiments

[0038] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; and "inner" and "outer" refer to the outline of the device.

[0039] The embodiment of the present application provides a method for preparing an array substrate and an array substrate. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0040] Please refer to Figure 1 , the present application provides a method for preparing an array substrate. The array substrate includes an oxide semiconductor layer, a gate electrode, and a metal oxide insulating layer formed between the oxide semiconductor layer and the gate electrode. The metal oxide insulating layer is in contact with the oxide semiconductor layer. Among them, after the step of forming the metal oxide insulating layer, the method for preparing the array substrate includes the following steps:

[0041] B1: Perform laser irradiation on the metal oxide insulating layer.

[0042] Thus, by performing laser irradiation on the metal oxide insulating layer after the step of forming the metal oxide insulating layer, the present application can further regulate the content of oxygen vacancies in the metal oxide insulating layer. Under positive bias gate voltage, the number of oxygen vacancies at the contact interface between the metal oxide insulating layer and the oxide semiconductor layer increases, thereby improving the mobility of the thin film transistor.

[0043] The following will elaborate on the method for preparing the array substrate provided by the present application through specific embodiments.

[0044] Please refer to Figure 2 and Figure 3 , the first example of the present application provides a method for preparing an array substrate 100 with a bottom-gate structure, which includes the following steps:

[0045] B11: Provide a substrate 10.

[0046] Among them, the substrate 10 can be a rigid substrate, such as a glass substrate; or, the substrate 10 can also be a flexible substrate, such as a polyimide substrate. The present application does not specifically limit the material of the substrate 10.

[0047] B12: On one side of the substrate 10, a gate 111, a gate insulating layer 12, and a metal oxide insulating layer 13 are sequentially formed.

[0048] First, a gate metal layer 11 is formed on one side of the substrate 10 by physical vapor deposition, and the gate metal layer 11 is patterned to form the gate 111. Among them, the material of the gate 111 may include one or more of copper, aluminum, molybdenum, and titanium. It should be noted that while forming the gate 111, a signal trace 112 may also be formed, and the signal trace 112 may be a scan line.

[0049] Second, a gate insulating layer 12 is formed on the side of the gate 111 away from the substrate 10 by chemical vapor deposition. Among them, the material of the gate insulating layer 12 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0050] Finally, a metal oxide insulating layer 13 is formed on the side of the gate insulating layer 12 away from the gate 111 by physical vapor deposition. Among them, the thickness of the metal oxide insulating layer 13 is 20 nm - 50 nm, such as 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. Within the above thickness range, the uniformity of the oxygen vacancy distribution in the metal oxide insulating layer 13 after subsequent laser irradiation can be improved.

[0051] Specifically, the material of the metal oxide insulating layer 13 may include Ta 2 O 5 、ZrO 2 、HfO 2 、TiO 2 、Al 2 O 3 、SrO 2 and La 2 O 3 One or more of them. Since the above metal oxides all have a high dielectric constant, when the above materials are used, the metal oxide insulating layer 13 has good dielectric properties.

[0052] B13: Laser irradiate the metal oxide insulating layer 13.

[0053] After forming the metal oxide insulating layer 13, the metal oxide insulating layer 13 is laser irradiated by femtosecond laser technology. By controlling the laser intensity and laser irradiation time during the laser irradiation, the content of oxygen vacancies in the metal oxide insulating layer 13 can be controlled.

[0054] In this embodiment, the material of the metal oxide insulating layer 13 may be Ta 2 O 5 . Since Ta2 O 5 Can effectively reduce the driving voltage and power consumption of the device. Therefore, by using a laser to generate local thermal effects on Ta 2 O 5 And the excellent processing speed of the laser, precise control of the performance of Ta 2 O 5 Can be achieved. Specifically, by selecting lasers with different wavelengths, the content of oxygen vacancies in Ta 2 O 5 thin films can be effectively regulated, and then the carrier concentration can be adjusted.

[0055] In this embodiment, when the laser irradiation time is fixed, the laser intensity in the laser irradiation is positively correlated with the content of oxygen vacancies in the metal oxide insulating layer 13. Among them, after the step of laser irradiating the metal oxide insulating layer 13, the content of oxygen vacancies in the metal oxide insulating layer 13 is greater than 23%.

[0056] Specifically, when the material of the metal oxide insulating layer 13 is Ta 2 O 5 Under laser irradiation, the metal oxide insulating layer 13 includes chemical bonds such as Ta-O and C=O and oxygen vacancies Vo 2+ . Please refer to Table 1. Table 1 shows the changes in the content of Ta-O, C=O, and oxygen vacancies Vo 2 under no laser irradiation and under different laser intensity irradiations (laser intensities are 263 mJ / cm 2 309 mJ / cm 2 and 358 mJ / cm 2+ ) when the laser irradiation time is fixed:

[0057] Table 1

[0058]

[0059] As can be seen from the above table:

[0060] 1. Compared with the case of no laser irradiation, under laser irradiation, the content of oxygen vacancies in the metal oxide insulating layer 13 increases significantly. Specifically, the content of oxygen vacancies under no laser irradiation is only 22.35%. When laser irradiation is used, the content of oxygen vacancies is significantly greater than 22.35%, and when the laser irradiation intensity is 358 mJ / cm 2 , the content of oxygen vacancies can reach 34.02%.

[0061] 2. Under laser irradiation, as the laser intensity increases, the content of oxygen vacancies in the metal oxide insulating layer 13 also increases.

[0062] Therefore, in this embodiment, by laser irradiating the metal oxide insulating layer 13 after film formation and increasing the intensity of the laser irradiation, the oxygen vacancy content in the metal oxide insulating layer 13 can be significantly increased, thereby increasing the carrier concentration and improving the mobility of the oxide TFT.

[0063] It should be noted that this embodiment only schematically exemplifies the relationship between the laser irradiation intensity and the oxygen vacancy content in the metal oxide insulating layer 13 to prove that by regulating the laser irradiation intensity, the regulation of the oxygen vacancy content in the metal oxide insulating layer 13 can be achieved. In the actual process, the corresponding laser intensity can be set according to the actual application situation to achieve the regulation of the oxygen vacancy content.

[0064] B14: An oxide semiconductor layer 14, a source-drain metal layer 15, a first passivation layer 16, an organic insulating layer 17, a common electrode 18, a second passivation layer 19, and a pixel electrode 20 are sequentially formed on the side of the metal oxide insulating layer 13 away from the gate insulating layer 12. Among them, the source-drain metal layer 15 includes a source electrode 151 and a drain electrode 152. A contact hole 10A is formed in the second passivation layer 19, and the contact hole 10A sequentially penetrates the second passivation layer 19, the organic insulating layer 17, and the first passivation layer 16 and exposes the drain electrode 152. The pixel electrode 20 is connected to the drain electrode 152 in the contact hole 10A.

[0065] Among them, the oxide semiconductor layer 14 is formed by a physical vapor deposition process. The material of the oxide semiconductor layer 14 may include one or more of IGZO, IZO, IGZTO, IGTO, and IZTO.

[0066] Since the metal oxide insulating layer 13 has a high oxygen vacancy content, after the oxide semiconductor layer 14 is formed, the number of oxygen vacancies at the contact interface between the oxide semiconductor layer 14 and the metal oxide insulating layer 13 will increase. After the TFT is formed, the on-state current and mobility of the TFT can be improved.

[0067] It should be noted that in this embodiment, a gate insulating layer 12 and a metal oxide insulating layer 13 are provided between the gate 111 and the oxide semiconductor layer 14; in some embodiments, only the metal oxide insulating layer 13 may be provided between the gate 111 and the oxide semiconductor layer 14. In this case, the setting of the gate insulating layer 12 can be omitted, thereby reducing one process and being beneficial to saving process costs.

[0068] Among them, the source-drain metal layer 15 is formed on the oxide semiconductor layer 14 by a physical vapor deposition process, and the source-drain metal layer 15 is patterned to form a source electrode 151 and a drain electrode 152. Specifically, the material of the source-drain metal layer 15 may include one or more of copper, aluminum, molybdenum, and titanium.

[0069] It should be noted that in this embodiment, while forming the source electrode 151 and the drain electrode 152, a connection pad 153 can also be formed. The connection pad 153 is used to realize the conduction between signals of different layers. For example, in this embodiment, the connection pad 153 can be used to connect the signal trace 112 and the signal electrode 21. Among them, the signal electrode 21 is disposed on the same layer as the pixel electrode 20 and is used to transmit voltage to the signal trace 112.

[0070] Among them, both the first passivation layer 16 and the second passivation layer 19 can be formed by chemical vapor deposition process. The first passivation layer 16 and the second passivation layer 19 are made of the same material, which can include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0071] The organic insulating layer 17 can be formed by coating. The material of the organic insulating layer 17 can be a resin-based transparent insulating material.

[0072] Both the common electrode 18 and the pixel electrode 20 can be formed by physical vapor deposition process and then patterned. The common electrode 18 and the pixel electrode 20 are made of the same material, which can include indium tin oxide.

[0073] It should be noted that a first via hole (not shown in the figure) and a second via hole (not shown in the figure) are also formed in the array substrate 100. The first via hole sequentially penetrates through the metal oxide insulating layer 13 and the gate insulating layer 12 and exposes the signal trace 112. The second via hole sequentially penetrates through the second passivation layer 19, the organic insulating layer 17, and the first passivation layer 16 and exposes the connection pad 153. The signal electrode 21 is connected to the signal trace 112 through the connection pad 153.

[0074] Please refer to Figure 4 and Figure 5 together. Embodiment 2 of the present application provides a method for manufacturing an array substrate 100 with a top-gate structure, which includes the following steps:

[0075] B21: Provide a substrate 10.

[0076] Among them, the substrate 10 can be a rigid substrate, such as a glass substrate; or, the substrate 10 can also be a flexible substrate, such as a polyimide substrate. The present application does not make specific limitations on the material of the substrate 10.

[0077] B22: Sequentially form a light-shielding layer 22, a buffer layer 23, an oxide semiconductor layer 14, and a metal oxide insulating layer 13 on one side of the substrate 10.

[0078] First, form the light-shielding layer 22 by physical vapor deposition process. The material of the light-shielding layer 22 can include one or more of copper, aluminum, molybdenum, and titanium.

[0079] Secondly, a buffer layer 23 is formed on the side of the light-shielding layer 22 away from the substrate 10 by a chemical vapor deposition process. The material of the buffer layer 23 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0080] Next, an oxide semiconductor layer 14 is formed on the side of the buffer layer 23 away from the light-shielding layer 22 by a physical vapor deposition process. The material of the oxide semiconductor layer 14 may include one or more of IGZO, IZO, IGZTO, IGTO, and IZTO.

[0081] Finally, a metal oxide insulating layer 13 is formed on the side of the oxide semiconductor layer 14 away from the buffer layer 23 by a physical vapor deposition process. The thickness of the metal oxide insulating layer 13 is 20 nm - 50 nm, such as 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. Within the above thickness range, the uniformity of the oxygen vacancy distribution in the metal oxide insulating layer 13 after subsequent laser irradiation can be improved.

[0082] Specifically, the material of the metal oxide insulating layer 13 may include Ta 2 O 5 , ZrO 2 , HfO 2 , TiO 2 , Al 2 O 3 , SrO 2 and La 2 O 3 or more of them. Since the above metal oxides all have a high dielectric constant, when the above materials are used, the metal oxide insulating layer 13 has good dielectric properties.

[0083] B23: Laser irradiate the metal oxide insulating layer 13.

[0084] After forming the metal oxide insulating layer 13, the metal oxide insulating layer 13 is laser irradiated by a femtosecond laser technology. By controlling the laser intensity and laser irradiation time during the laser irradiation, the content of oxygen vacancies in the metal oxide insulating layer 13 can be controlled.

[0085] In this embodiment, the material of the metal oxide insulating layer 13 may be Ta 2 O 5 . Since Ta 2 O 5 can effectively reduce the driving voltage and power consumption of the device, therefore, by using the local thermal effect generated by the laser on Ta 2 O 5 and the excellent processing speed of the laser, it is possible to achieve Ta 2 O5 Precise control of performance. Specifically, by selecting lasers with different wavelengths, the content of oxygen vacancies in the Ta 2 O 5 thin film can be effectively regulated, thereby adjusting the carrier concentration.

[0086] In this embodiment, when the laser irradiation time is fixed, the laser intensity during laser irradiation is positively correlated with the content of oxygen vacancies in the metal oxide insulating layer 13. Among them, after the step of laser irradiating the metal oxide insulating layer 13, the content of oxygen vacancies in the metal oxide insulating layer 13 is greater than 23%.

[0087] Specifically, when the material of the metal oxide insulating layer 13 is Ta 2 O 5 , under laser irradiation, the metal oxide insulating layer 13 includes chemical bonds such as Ta-O and C=O as well as oxygen vacancies Vo 2+ . Please refer to Table 1. Table 1 shows the changes in the content of Ta-O, C=O, and oxygen vacancies Vo 2 under no laser irradiation and under different laser intensity irradiations (laser intensities are 263 mJ / cm 2 309 mJ / cm 2 and 358 mJ / cm 2+ respectively) when the laser irradiation time is fixed:

[0088] Table 1

[0089]

[0090] As can be seen from the above table:

[0091] 1. Compared with the case of no laser irradiation, under laser irradiation, the content of oxygen vacancies in the metal oxide insulating layer 13 increases significantly. Specifically, the content of oxygen vacancies under no laser irradiation is only 22.35%. When laser irradiation is used, the content of oxygen vacancies is significantly greater than 22.35%, and when the laser irradiation intensity is 358 mJ / cm 2 , the content of oxygen vacancies can reach 34.02%.

[0092] 2. Under laser irradiation, as the laser intensity increases, the content of oxygen vacancies in the metal oxide insulating layer 13 also increases.

[0093] Therefore, in this embodiment, by laser irradiating the metal oxide insulating layer 13 after film formation and increasing the intensity of laser irradiation, the content of oxygen vacancies in the metal oxide insulating layer 13 can be significantly increased, and thus the carrier concentration can be increased.

[0094] It should be noted that this embodiment only schematically illustrates the relationship between the laser irradiation intensity and the oxygen vacancy content in the metal oxide insulating layer 13, so as to prove that by regulating the laser irradiation intensity, the regulation of the oxygen vacancy content in the metal oxide insulating layer 13 can be achieved. In the actual process, the corresponding laser intensity can be set according to the actual application situation to achieve the regulation of the oxygen vacancy content.

[0095] B24: A gate insulating layer 12, a gate 111, an interlayer dielectric layer 24, a source-drain metal layer 15, a passivation layer 25, and a pixel electrode 20 are sequentially formed on the side of the metal oxide insulating layer 13 away from the oxide semiconductor layer 14. Among them, the source-drain metal layer 15 includes a source electrode 151 and a drain electrode 152. A contact hole 10A is formed in the passivation layer 25, and the pixel electrode 20 is connected to the drain electrode 152 through the contact hole 10A.

[0096] Among them, the formation methods and materials of the above film structures can all refer to the prior art and will not be elaborated here.

[0097] It should be noted that in this embodiment, a metal oxide insulating layer 13 and a gate insulating layer 12 are provided between the oxide semiconductor layer 14 and the gate 111; in some embodiments, only the metal oxide insulating layer 13 can be provided between the oxide semiconductor layer 14 and the gate 111. In this case, the setting of the gate insulating layer 12 can be omitted, and thus one process can be reduced, which is beneficial to saving the process cost.

[0098] Please refer to Figure 6 , the first embodiment of the present application provides an array substrate 100. The array substrate 100 provided by the first embodiment includes a substrate 10, a gate 111, a gate insulating layer 12, a metal oxide insulating layer 13, an oxide semiconductor layer 14, a source-drain metal layer 15, a first passivation layer 16, an organic insulating layer 17, a common electrode 18, a second passivation layer 19, and a pixel electrode 20.

[0099] Among them, the gate 111 is disposed on one side of the substrate 10. The gate insulating layer 12 is disposed on the side of the gate 111 away from the substrate 10. The metal oxide insulating layer 13 is disposed on the side of the gate insulating layer 12 away from the gate 111. The oxide semiconductor layer 14 is disposed on the side of the metal oxide insulating layer 13 away from the gate insulating layer 12. The source-drain metal layer 15 is disposed on the side of the oxide semiconductor layer 14 away from the metal oxide insulating layer 13, and the source-drain metal layer 15 includes a source electrode 151 and a drain electrode 152. The first passivation layer 16 is disposed on the side of the source-drain metal layer 15 away from the oxide semiconductor layer 14. The organic insulating layer 17 is disposed on the side of the first passivation layer 16 away from the source-drain metal layer 15. The common electrode 18 is disposed on the side of the organic insulating layer 17 away from the first passivation layer 16. The second passivation layer 19 is disposed on the side of the common electrode 18 away from the organic insulating layer 17. The pixel electrode 20 is disposed on the side of the second passivation layer 19 away from the common electrode 18. A contact hole 10A is formed in the array substrate 100. The contact hole 10A sequentially penetrates through the second passivation layer 19, the organic insulating layer 17, and the first passivation layer 16 and exposes the drain electrode 152. The pixel electrode 20 is connected to the drain electrode 152 within the contact hole 10A.

[0100] In addition, the array substrate 100 further includes a signal trace 112, a connection pad 153, and a signal electrode 21. The signal trace 112 is disposed on the same layer as the gate 111. The connection pad 153 is disposed on the same layer as the source electrode 151. The signal electrode 21 is disposed on the same layer as the pixel electrode 20. The signal electrode 21 is connected to the signal trace 112 through the connection pad 153.

[0101] It should be noted that the array substrate 100 in this embodiment can be obtained by using the preparation method of the array substrate 100 described in the foregoing Example 1. The related preparation method can refer to the description of Example 1 and will not be elaborated here.

[0102] Please refer to Figure 7 This application's second embodiment provides an array substrate 100. The array substrate 100 provided by the second embodiment includes a substrate 10, a light-shielding layer 22, a buffer layer 23, an oxide semiconductor layer 14, a metal oxide insulating layer 13, a gate insulating layer 12, a gate 111, an interlayer dielectric layer 24, a source-drain metal layer 15, a passivation layer 25, and a pixel electrode 20.

[0103] Among them, the light-shielding layer 22 is disposed on one side of the substrate 10. The buffer layer 23 is disposed on the side of the light-shielding layer 22 away from the substrate 10. The oxide semiconductor layer 14 is disposed on the side of the buffer layer 23 away from the light-shielding layer 22. The metal oxide insulating layer 13 is disposed on the side of the oxide semiconductor layer 14 away from the buffer layer 23. The gate insulating layer 12 is disposed on the side of the metal oxide insulating layer 13 away from the oxide semiconductor layer 14. The gate 111 is disposed on the side of the gate insulating layer 12 away from the metal oxide insulating layer 13. The interlayer dielectric layer 24 is disposed on the side of the gate 111 away from the gate insulating layer 12. The source-drain metal layer 15 is disposed on the side of the interlayer dielectric layer 24 away from the gate 111, and the source-drain metal layer 15 includes a source electrode 151 and a drain electrode 152. The passivation layer 25 is disposed on the side of the source-drain metal layer 15 away from the interlayer dielectric layer 24, and a contact hole 10A is formed in the passivation layer 25, and the contact hole 10A exposes the drain electrode 152. The pixel electrode 20 is disposed on the side of the passivation layer 25 away from the source-drain metal layer 15, and the pixel electrode 20 is connected to the drain electrode 152 within the contact hole 10A.

[0104] It should be noted that the array substrate 100 in this embodiment can be obtained by using the preparation method of the array substrate 100 described in the foregoing Example 2. The relevant preparation method can refer to the description of Example 2 and will not be elaborated herein.

[0105] The preparation method and the array substrate of an array substrate provided in the embodiments of the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A method for preparing an array substrate, characterized in that, the array substrate includes an oxide semiconductor layer, a gate electrode, and a metal oxide insulating layer formed between the oxide semiconductor layer and the gate electrode, the metal oxide insulating layer being in contact with the oxide semiconductor layer, wherein, after the step of forming the metal oxide insulating layer and before forming the oxide semiconductor layer, the method for preparing the array substrate includes the following steps: using femtosecond laser technology to irradiate the metal oxide insulating layer, and the oxygen vacancy content in the metal oxide insulating layer is greater than 23%.

2. The method for preparing an array substrate according to claim 1, characterized in that, in the step of irradiating the metal oxide insulating layer with laser, the laser intensity in the laser irradiation is positively correlated with the oxygen vacancy content in the metal oxide insulating layer.

3. The method for preparing an array substrate according to claim 1, characterized in that, The material of the metal oxide insulating layer includes Ta 2 O 5 、ZrO 2 , HfO 2 、TiO 2 、Al 2 O 3 、SrO 2 and La 2 O 3 One or more of .

4. The method for preparing an array substrate according to claim 3, characterized in that, The material of the metal oxide insulating layer is Ta 2 O 5 .

5. The method for preparing an array substrate according to claim 1, characterized in that, the thickness of the metal oxide insulating layer is 20nm - 50nm.

6. An array substrate, characterized in that, the array substrate is prepared by using the method for preparing an array substrate according to any one of claims 1 to 5.

7. The array substrate according to claim 6, characterized in that, the array substrate further includes a gate insulating layer, the gate insulating layer is disposed on a side of the metal oxide insulating layer close to the gate electrode, and the material of the gate insulating layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

8. The array substrate according to claim 7, characterized in that, the array substrate further includes a substrate, the gate electrode is located on a side of the oxide semiconductor layer close to the substrate, and the array substrate further includes: a source-drain metal layer disposed on a side of the oxide semiconductor layer away from the metal oxide insulating layer, the source-drain metal layer including a source electrode and a drain electrode; a first passivation layer disposed on a side of the source-drain metal layer away from the oxide semiconductor layer; an organic insulating layer disposed on a side of the first passivation layer away from the source-drain metal layer; a common electrode disposed on a side of the organic insulating layer away from the first passivation layer; a second passivation layer disposed on a side of the common electrode away from the organic insulating layer; and a pixel electrode disposed on a side of the second passivation layer away from the common electrode; wherein, a contact hole is formed in the array substrate, the contact hole sequentially penetrates through the second passivation layer, the organic insulating layer, and the first passivation layer, and exposes the drain electrode, and the pixel electrode is connected to the drain electrode in the contact hole.

9. The array substrate according to claim 7, characterized in that, the array substrate further includes a substrate, the gate electrode is located on a side of the oxide semiconductor layer away from the substrate, and the array substrate further includes: a light-shielding layer disposed on a side of the oxide semiconductor layer close to the substrate; A buffer layer, disposed between the light-shielding layer and the oxide semiconductor layer; An interlayer dielectric layer, disposed on a side of the gate away from the gate insulating layer; A source-drain metal layer, disposed on a side of the interlayer dielectric layer away from the gate, the source-drain metal layer including a source electrode and a drain electrode; A passivation layer, disposed on a side of the source-drain metal layer away from the interlayer dielectric layer, a contact hole being formed in the passivation layer, the contact hole exposing the drain electrode; and A pixel electrode, disposed on a side of the passivation layer away from the source-drain metal layer, the pixel electrode being connected to the drain electrode within the contact hole.

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