Array substrate and display panel

Abstract

The present invention provides an array substrate and a display panel. The array substrate includes a light-shielding layer, a semiconductor active layer, and a gate metal line. The semiconductor active layer is disposed above the light-shielding layer. Among them, the boundary of the light-shielding layer covered by the semiconductor active layer is not parallel to the extending direction of the gate metal line. By adjusting the design of the light-shielding layer, the boundary of the light-shielding layer covered by the semiconductor active layer is not parallel to the extending direction of the gate metal line, so as to ensure that when the semiconductor active layer is annealed by ELA, the scanning direction of ELA is not parallel to the boundary, alleviating the phenomenon of abnormal crystallization of the semiconductor active layer corresponding to the boundary.

Description

Technical Field

[0001] The present application relates to the field of displays, and in particular, to an array substrate and a display panel. Background Art

[0002] In the existing liquid crystal display (LCD) technology, a light-shielding layer is usually disposed below the channel region of a thin-film transistor to prevent the backlight from directly irradiating the channel region and affecting the performance of the thin-film transistor.

[0003] As Figures 1 to 3 shown, the light-shielding layer 11 is usually only disposed at a position corresponding to the channel region of the thin-film transistor, and a part of the boundary of the semiconductor active layer 12 covers the light-shielding layer 11. Due to the influence of the thickness of the light-shielding layer 11, at a position corresponding to the part of the boundary, a slope edge 13 is formed on the semiconductor active layer 12. The slope edge 13 is parallel to the direction of the gate metal line 14. When an excimer laser annealing (ELA) process is used to perform laser annealing on the amorphous silicon layer, the scanning direction of the ELA is the same as the extending direction of the gate metal line 14. The silicon oxide grains located at the slope edge 13 will exhibit abnormal crystallization, ultimately affecting the electrical performance of the thin-film transistor.

[0004] Therefore, there is a problem of abnormal crystallization of the semiconductor active layer in the existing display panel, which needs to be solved. Summary of the Invention

[0005] The present invention provides an array substrate and a display panel to alleviate the problem of abnormal crystallization of the semiconductor active layer in the existing display panel.

[0006] To solve the above problems, the technical solutions provided by the present invention are as follows:

[0007] The present invention provides an array substrate, which includes a light-shielding layer, a semiconductor active layer, and a gate metal line. The semiconductor active layer is disposed above the light-shielding layer;

[0008] Wherein, the boundary of the light-shielding layer covered by the semiconductor active layer is not parallel to the extending direction of the gate metal line.

[0009] Optionally, in some embodiments of the present invention, the boundary of the light-shielding layer covered by the semiconductor active layer is perpendicular to the extending direction of the gate metal line.

[0010] Optionally, in some embodiments of the present invention, the array substrate includes a plurality of thin film transistors, the active layer includes the active regions of the thin film transistors, the shape of the active region is n-type, including opposite first and second sides, and a third side connecting the first side and the second side; the active region includes a first channel region and a second channel region, the first channel region is located on the first side, and the second channel region is located on the second side.

[0011] Optionally, in some embodiments of the present invention, the light-shielding layer includes a first light-shielding portion and a second light-shielding portion, the first light-shielding portion is located under the first side, and the second light-shielding portion is located under the second side.

[0012] Optionally, in some embodiments of the present invention, the projection of the first side on the light-shielding layer falls within the region where the first light-shielding portion is located, and the projection of the second side on the light-shielding layer falls within the region where the second light-shielding portion is located.

[0013] Optionally, in some embodiments of the present invention, the first light-shielding portion and the second light-shielding portion are mirror images of each other.

[0014] Optionally, in some embodiments of the present invention, the light-shielding layer is located under the first side or the second side.

[0015] Optionally, in some embodiments of the present invention, the projection of the first side or the second side on the light-shielding layer falls within the region where the light-shielding layer is located.

[0016] Optionally, in some embodiments of the present invention, the shape of the light-shielding layer is I-shaped or L-shaped.

[0017] Correspondingly, the present invention further provides a display panel, which includes the array substrate according to any one of the embodiments of the present invention.

[0018] The present invention provides an array substrate and a display panel. The array substrate includes a light-shielding layer, a semiconductor active layer, and a gate metal line. The semiconductor active layer is disposed above the light-shielding layer. Wherein, the boundary of the light-shielding layer covered by the semiconductor active layer is not parallel to the extending direction of the gate metal line. By adjusting the design of the light-shielding layer, the boundary of the light-shielding layer covered by the semiconductor active layer is not parallel to the extending direction of the gate metal line, so as to ensure that when the semiconductor active layer is annealed by ELA, the scanning direction of ELA is not parallel to the boundary, alleviating the phenomenon of abnormal crystallization of the semiconductor active layer corresponding to the boundary. Description of the Drawings

[0019] The following will make the technical solutions and other beneficial effects of the present application obvious by describing the specific embodiments of the present application in detail in conjunction with the drawings.

[0020] Figure 1 is a top view structural schematic diagram of an existing array substrate;

[0021] Figure 2 is a cross-sectional structural schematic diagram of an existing array substrate;

[0022] Figure 3 is Figure 2 an enlarged schematic diagram of area 101 in

[0023] Figure 4 is a first top view structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0024] Figure 5 is a second top view structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0025] Figure 6 is a third top view structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0026] Figure 7 is a cross-sectional structural schematic diagram of an array substrate provided by an embodiment of the present invention. Detailed implementation manners

[0027] Next, in combination with the specific implementation manners of the present invention, the technical solutions in the implementation manners and / or embodiments of the present invention will be clearly and completely described. Obviously, the implementation manners and / or embodiments described below are only a part of the implementation manners and / or embodiments of the present invention, rather than all of the implementation manners and / or embodiments. Based on the implementation manners and / or embodiments in the present invention, all other implementation manners and / or embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] The directional terms mentioned in the present invention, such as [up], [down], [left], [right], [front], [rear], [inside], [outside], [side], etc., are only references to the directions in the attached drawings. Therefore, the directional terms used are for explaining and understanding the present invention, rather than for limiting the present invention. The terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features.

[0029] Aiming at the phenomenon of abnormal crystallization of the semiconductor active layer in the existing display panel, the present invention provides an array substrate and a display panel that can alleviate this problem.

[0030] In one embodiment, please refer to Figures 4 to 7 ,Figure 4 FIG. 1 shows a first top view structural schematic diagram of an array substrate provided by an embodiment of the present invention. Figure 5 FIG. 2 shows a second top view structural schematic diagram of an array substrate provided by an embodiment of the present invention. Figure 6 FIG. 3 shows a third top view structural schematic diagram of an array substrate provided by an embodiment of the present invention. Figure 7 FIG. 4 shows a cross-sectional structural schematic diagram of an array substrate provided by an embodiment of the present invention, specifically, a cross-sectional structural schematic diagram of the array substrate along the Figures 4 to 6 direction of BB' in FIG. As Figures 4 to 7 shown, the array substrate provided by an embodiment of the present invention includes a light-shielding layer 21, a semiconductor active layer 22, and a gate metal line 24. The semiconductor active layer 22 is disposed on the light-shielding layer 21.

[0031] Among them, a boundary 23 of the light-shielding layer 21 covered by the semiconductor active layer 22 is not parallel to an extending direction of the gate metal line 24.

[0032] Preferably, the boundary of the light-shielding layer 21 covered by the semiconductor active layer 22 is perpendicular to the extending direction of the gate metal line 24.

[0033] By adjusting the design of the light-shielding layer in the embodiment of the present invention, the boundary of the light-shielding layer covered by the semiconductor active layer is not parallel to the extending direction of the gate metal line, so as to ensure that when the semiconductor active layer is annealed by ELA, the scanning direction of ELA is not parallel to the boundary, and the phenomenon of abnormal crystallization of the semiconductor active layer corresponding to the boundary is alleviated.

[0034] Specifically, please refer to Figures 4 to 7 , the array substrate provided by an embodiment of the present invention includes a substrate 20, a light-shielding layer 21, a first insulating layer 26, a semiconductor active layer 22, a second insulating layer 27, a gate metal layer 24, a third insulating layer 28, and a source-drain layer 29 which are sequentially stacked. The semiconductor active layer 22, the second insulating layer 27, the gate metal layer 24, the third insulating layer 28, and the source-drain layer 29 together form a thin film transistor in the array substrate.

[0035] Among them, the semiconductor active layer 22 is patterned to form the active region 22 of the thin film transistor. When the thin film transistor is an N-type metal oxide semiconductor (N-Metal-Oxide-Semiconductor, abbreviated as NMOS), the active region 22 includes a channel region, lightly doped regions on both sides of the channel region, and a heavily doped region outside the channel region and the lightly doped regions; when the thin film transistor is a P-type metal oxide semiconductor (P-Metal-Oxide-Semiconductor, abbreviated as PMOS), the active region 22 includes a channel region and a heavily doped region outside the channel region. Before the ELA annealing process, the semiconductor active layer 22 is a single crystal silicon thin film. In one embodiment, as Figures 4 to 6 shown, the shape of the active region is n-type, including opposite first side 221 and second side 222, and a third side 223 connecting the first side 221 and the second side 222.

[0036] The gate metal layer 24 is patterned to form the gate and gate metal lines of the thin film transistor. The gate and the gate metal lines are connected. Generally, as Figures 4 to 6 shown, the gate is a local region on the gate metal line. The local region where the gate metal line 24 spatially overlaps with the semiconductor active layer 22 is the gate of the thin film transistor. Correspondingly, the local region where the semiconductor active layer spatially overlaps with the gate metal line 24 is the channel region of the thin film transistor. In one embodiment, as Figures 4 to 6 shown, the gate metal line extends in the horizontal direction and has two spatial overlaps with the semiconductor active layer 22. The active region includes two channel regions, a first channel region and a second channel region. The first channel region is located on the first side 221, and the second channel region is located on the second side 222.

[0037] The source-drain layer 29 is patterned to form at least two source-drain metal lines. The two source-drain metal lines are respectively connected to the heavily doped regions on both sides of the channel region of the active layer 22 through vias 25 penetrating the third insulating layer 28 and the second insulating layer 27 to form ohmic contacts. The metal lines connected to the heavily doped regions become the source and drain of the thin film transistor.

[0038] The second insulating layer 27 is located between the semiconductor active layer 22 and the gate metal layer 24, covering the semiconductor active layer 22, and serving to block the semiconductor active layer 22 from the upper gate metal layer 24. The third insulating layer 28 is located between the gate metal layer 24 and the source-drain layer 29, covering the gate metal layer 24, and serving to block the gate metal layer 24 from the source-drain layer 29.

[0039] The first insulating layer 26 is located between the semiconductor active layer 22 and the light-shielding layer 21, covering the light-shielding layer 21, and at the same time playing a role in preventing heavy metals from diffusing into the semiconductor active layer 22 and affecting the performance of the thin-film transistor.

[0040] The light-shielding layer 21 is formed on the substrate 20 and is used to block the light incident on the thin-film transistor from below the array substrate, mainly blocking the light incident on the channel region of the thin-film transistor, thereby avoiding the occurrence of photoinduced leakage in the thin-film transistor and affecting the electrical performance of the thin-film transistor. The material of the light-shielding layer 21 generally uses an opaque light-absorbing material, usually an opaque heavy metal material such as molybdenum.

[0041] In one embodiment, as Figure 4 and Figure 5 shown, the light-shielding layer 21 is patterned to form two light-shielding portions corresponding to one thin-film transistor, namely the first light-shielding portion 211 and the second light-shielding portion 212. The first light-shielding portion 211 is located below the first side 221 and is used to block the light below the first channel region. The second light-shielding portion 212 is located below the second side 222 and is used to block the light below the second channel region. The projection of the first side 221 on the light-shielding layer 21 falls within the region where the first light-shielding portion 211 is located, and the projection of the second side 222 on the light-shielding layer 21 falls within the region where the second light-shielding portion 212 is located. In this way, the boundary 23 of the light-shielding layer 21 covered by the semiconductor active layer 22 is perpendicular to the extending direction of the gate metal line 24.

[0042] In one implementation, as Figure 4 shown, the shapes of the first light-shielding portion 211 and the second light-shielding portion 212 are both I-shaped, and the first light-shielding portion 211 and the second light-shielding portion 212 are mirror images of each other. The third side 223 covers a part of the boundary on the right side of the first light-shielding portion 211 to form a corresponding first sloped side. The first sloped side is perpendicular to the gate metal line 24, and the first sloped side is perpendicular to the scanning direction of ELA in the ELA process, alleviating the phenomenon of abnormal crystallization of silicon oxide grains at the first sloped side during the ELA annealing process. Similarly, the third side 223 covers a part of the boundary on the left side of the second light-shielding portion 212 to form a corresponding second sloped side. The second sloped side is perpendicular to the gate metal line 24, and the second sloped side is perpendicular to the scanning direction of ELA in the ELA process, alleviating the phenomenon of abnormal crystallization of silicon oxide grains at the second sloped side during the ELA annealing process.

[0043] In another implementation, as Figure 5As shown, the shapes of the first light-shielding portion 211 and the second light-shielding portion 212 are both L-shaped, and the first light-shielding portion 211 and the second light-shielding portion 212 are mirror images of each other. Compared with the previous embodiment, in this embodiment, the reduction in the widths of the first light-shielding portion 211 and the second light-shielding portion 212 increases the aperture ratio of the display panel.

[0044] In other embodiments, the shapes of the first light-shielding portion 211 and the second light-shielding portion 212 can be any other shapes that meet the inventive concept of the embodiments of the present invention, and the shapes of the first light-shielding portion 211 and the second light-shielding portion 212 can be the same or different, which are not limited herein.

[0045] In one embodiment, as Figure 6 shown, the light-shielding layer 21 is patterned to form a light-shielding portion corresponding to one thin-film transistor. The light-shielding portion can be located under the first side 221 to block the light below the first channel region, or can be located under the second side 222 to block the light below the second channel region. The projection of the first side 221 or the second side 222 on the light-shielding layer 21 falls within the region where the light-shielding portion is located. In this way, the boundary 23 where the light-shielding layer 21 is covered by the semiconductor active layer 22 is perpendicular to the extending direction of the gate metal line 24. Similarly, the third side 223 covers a partial boundary of the light-shielding portion to form a corresponding sloped side, and the sloped side is perpendicular to the gate metal line 24 and perpendicular to the scanning direction of ELA in the ELA process, alleviating the phenomenon of abnormal crystallization of silicon oxide grains at the second sloped side during the ELA annealing process. The light-shielding portion can be I-shaped, L-shaped or any other shape that meets the inventive concept of the embodiments of the invention, which is not limited herein. Compared with the above embodiment, this embodiment only provides one light-shielding portion corresponding to one thin-film transistor, further increasing the aperture ratio of the display panel.

[0046] Correspondingly, the embodiments of the present invention further provide a display panel, and the display panel includes any one of the array substrates provided by the embodiments of the present invention. Therefore, the display panel has the technical features and beneficial effects of any one of the array substrates provided by the embodiments of the present invention. For details, please refer to the above embodiments related to the array substrate, which will not be elaborated herein.

[0047] In summary, the embodiment of the present invention provides an array substrate and a display panel. The array substrate includes a light-shielding layer, a semiconductor active layer, and a gate metal line. The semiconductor active layer is disposed above the light-shielding layer. Among them, the boundary of the light-shielding layer covered by the semiconductor active layer is not parallel to the extending direction of the gate metal line. By adjusting the design of the light-shielding layer, the boundary of the light-shielding layer covered by the semiconductor active layer is not parallel to the extending direction of the gate metal line, so as to ensure that when the semiconductor active layer is annealed by ELA, the scanning direction of ELA is not parallel to the boundary, alleviating the phenomenon of abnormal crystallization of the semiconductor active layer corresponding to the boundary.

[0048] The above has introduced the array substrate and the display panel provided by the embodiment of the present invention in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. An array substrate, characterized in that, It includes a light-shielding layer, a semiconductor active layer, and a gate metal wire. The semiconductor active layer is disposed above the light-shielding layer; The array substrate includes a plurality of thin-film transistors. The semiconductor active layer includes the active regions of the thin-film transistors. The shape of the active region is n-type, including opposite first and second sides, and a third side connecting the first side and the second side. The light-shielding layer includes a first light-shielding portion and a second light-shielding portion; Wherein, the boundary of the light-shielding layer covered by the semiconductor active layer is perpendicular to the extending direction of the gate metal wire. The third side covers a partial boundary on the right side of the first light-shielding portion to form a corresponding first sloped side, and the first sloped side is perpendicular to the gate metal wire. The third side covers a partial boundary on the left side of the second light-shielding portion to form a corresponding second sloped side, and the second sloped side is perpendicular to the gate metal wire.

2. The array substrate according to claim 1, wherein The active region includes a first channel region and a second channel region. The first channel region is located on the first side, and the second channel region is located on the second side.

3. The array substrate according to claim 2, wherein, The first light-shielding portion is located under the first side, and the second light-shielding portion is located under the second side.

4. The array substrate according to claim 3, characterized in that, The projection of the first side on the light-shielding layer falls within the region where the first light-shielding portion is located, and the projection of the second side on the light-shielding layer falls within the region where the second light-shielding portion is located.

5. The array substrate according to claim 4, wherein The first light-shielding portion and the second light-shielding portion are mirror images of each other.

6. The array substrate according to claim 2, wherein, The light-shielding layer is located under the first side or the second side.

7. The array substrate according to claim 6, wherein The projection of the first side or the second side on the light-shielding layer falls within the region where the light-shielding layer is located.

8. The array substrate according to any one of claims 1 to 7, characterized in that The shape of the light-shielding layer is I-shaped or L-shaped.

9. A display panel, characterized in that, It includes the array substrate according to any one of claims 1 to 8.

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