Image display element

Abstract

An image display element includes: a plurality of micro light emitting elements arranged in an array; and a semiconductor layer in which a drive circuit that supplies a current to cause each of the plurality of micro light emitting elements to emit light is provided, a transistor and a wiring layer that constitute the drive circuit are provided on a first surface of the semiconductor layer, the plurality of micro light emitting elements are provided on a second surface of the semiconductor layer opposite the first surface, and the transistor and the wiring layer are electrically connected to the micro light emitting elements through a through electrode that penetrates the semiconductor layer.

Description

Technical Field

[0001] This invention relates to an image display element comprising miniature light-emitting elements. Background Technology

[0002] Display elements in which multiple micro-light-emitting elements constituting pixels are arranged on a substrate (backplane) have been proposed. For example, in the technology disclosed in Japanese Patent Application Publication No. 2002-141492, a driving circuit is formed on a silicon substrate, and a micro-array of light-emitting diodes (LEDs) emitting ultraviolet light is arranged on the driving circuit.

[0003] Furthermore, the aforementioned technology discloses a microdisplay element that displays color images by providing a wavelength conversion layer on top of a light-emitting diode array to convert ultraviolet light into visible light in red, green, and blue. Alternatively, a method for full-color display is proposed using a monochrome display element with compound semiconductors emitting blue, green, and red light stacked on a driving circuit.

[0004] Such display elements are characterized by their small size, high brightness, and high durability. Therefore, they are expected to be used as display elements for glasses-like devices, head-up displays (HUDs), and the like. Summary of the Invention

[0005] The technical problem to be solved by the present invention

[0006] In high-resolution / high-brightness microdisplay elements used in eyeglass-type terminals, light-emitting elements emitting strong visible, near-ultraviolet, and ultraviolet light are stacked on a silicon substrate on which CMOS (Complementary Metal Oxide Semiconductor) circuitry is formed. Light leakage to the driving circuit substrate made of the silicon substrate is unavoidable. N-wells and P-wells, containing PMOS and NMOS transistors respectively, are disposed on the surface of the silicon substrate. Light reaching the silicon substrate surface is absorbed by the silicon, generating electron / hole pairs in the two wells. These electrons and holes flow into the source / drain of the transistors, becoming the transistor's leakage current. If this leakage current is large, the circuit cannot operate as designed.

[0007] To avoid the aforementioned problems, a light-shielding layer covering the transistor is considered. If a metallic light-shielding layer is used, a gap is required between the electrodes connected to the light-emitting element. Since the interlayer insulating film between the buried wirings is transparent, light reaches the transistor through the interlayer insulating film. Therefore, it is difficult to completely eliminate the light intrusion path. Using insulating materials for light shielding avoids this problem, but to completely prevent light intrusion, a very thick layer is required, necessitating very long wiring between the drive circuit board and the light-emitting element, resulting in other problems such as high resistance and thermal resistance.

[0008] The main objective of this invention is to achieve stable and high-precision control in high-resolution / high-brightness micro-display elements by preventing light from entering the vicinity of the transistors on the driving circuit board.

[0009] To address the aforementioned problems, an image display element according to one embodiment of the present invention includes: a plurality of micro light-emitting elements arranged in an array; and a semiconductor layer having a driving circuit disposed on each of the plurality of micro light-emitting elements for supplying current to cause it to emit light, a transistor constituting the driving circuit and a wiring layer disposed on a first surface of the semiconductor layer, the plurality of micro light-emitting elements disposed on a second surface of the semiconductor layer opposite to the first surface, and the transistor and the wiring layer being electrically connected to the micro light-emitting elements through through electrodes penetrating the semiconductor layer.

[0010] In high-resolution / high-brightness micro-display elements, by preventing light from entering the vicinity of the transistors that constitute the driving circuit, the control precision of image display can be improved, the display quality can be enhanced, and power consumption can be reduced. Attached Figure Description

[0011] Figure 1A This is a cross-sectional schematic diagram of an image display element according to the first embodiment of the present invention.

[0012] Figure 1B This is a top view schematic diagram of the image display element according to the first embodiment of the present invention.

[0013] Figure 2 This is a cross-sectional schematic diagram showing the connection between the micro light-emitting element and the semiconductor layer of the image display element according to the first embodiment of the present invention.

[0014] Figure 3 This is a cross-sectional schematic diagram of the peripheral portion of the transistor in the driving circuit of the image display element constituting the first embodiment of the present invention.

[0015] Figure 4 This is a cross-sectional schematic diagram relating to the connection between the micro light-emitting element and the semiconductor layer of the image display element according to the second embodiment of the present invention.

[0016] Figure 5 This is a cross-sectional schematic diagram of the peripheral portion of the transistor in the driving circuit of the image display element constituting the third embodiment of the present invention.

[0017] Figure 6 This is a cross-sectional schematic diagram relating to the connection between the micro light-emitting element and the semiconductor layer of the image display element according to the fourth embodiment of the present invention.

[0018] Figure 7 This is a cross-sectional schematic diagram relating to the connection between the micro light-emitting element and the semiconductor layer of the image display element according to the fifth embodiment of the present invention.

[0019] Figure 8 This is a cross-sectional schematic diagram relating to the connection between the micro light-emitting element and the semiconductor layer of the image display element according to the sixth embodiment of the present invention.

[0020] Figure 9 This is a cross-sectional schematic diagram of the peripheral portion of the transistor in the driving circuit of the image display element constituting the seventh embodiment of the present invention. Detailed Implementation

[0021] The following examples illustrate image display elements with multiple micro-light-emitting elements, referring to Figures 1 to 12. Figure 9 Embodiments of the present invention will be described. The image display element includes a plurality of micro-light-emitting elements and a driving circuit board 50. The driving circuit board 50 supplies current to the micro-light-emitting elements located in the pixel region 1 to control light emission. The micro-light-emitting elements are arranged in an array in the pixel region 1. The micro-light-emitting elements emit light to the side opposite to the driving circuit board 50. Unless otherwise specified, the surface of the micro-light-emitting element that emits light into the air is referred to as the light-emitting surface. Furthermore, in the description of the configuration of the image display element, unless otherwise specified, the light-emitting surface is referred to as the upper surface, the surface opposite to the light-emitting surface is referred to as the lower surface, and the surfaces other than the upper and lower surfaces are referred to as the side surfaces. Similarly, the direction of light emission is referred to as upward, and the opposite direction is referred to as downward. The direction perpendicular to the light-emitting surface and towards the air is also referred to as the front.

[0022] The electrode on the upper surface of the micro-light-emitting element is referred to as the first electrode, and the electrode on the lower surface is referred to as the second electrode. The conductive layer on the upper surface of the compound semiconductor constituting the micro-light-emitting element is referred to as the first conductive layer, and the conductive layer on the lower surface is referred to as the second conductive layer. Furthermore, the following description focuses on a micro-light-emitting element constructed using a compound semiconductor as the light-emitting part; however, light-emitting elements constructed from other materials such as organic LEDs and quantum dot LEDs can also be used as micro-light-emitting elements.

[0023] In the pixel region 1, the driving circuit board 50 houses a micro light emitting element driving circuit that controls the current supplied to each micro light emitting element. Row selection circuits that select each row of micro light emitting elements arranged in a two-dimensional matrix, column signal output circuits that output light emission signals to each column, image processing circuits that calculate light emission signals based on input signals, and input / output circuits are disposed outside the pixel region 1. The driving circuit board 50 is generally a silicon substrate (semiconductor substrate) with LSI (Large Scale Integration) formed on it. Since it can be manufactured using known techniques, its function and configuration will not be described in detail. Furthermore, in this embodiment, a MOS-FET (Field Effect Transistor) is exemplified as a transistor, but even a bipolar transistor can be configured in the same way.

[0024] Furthermore, there are no particular limitations on the shape of the micro-light-emitting elements when viewed from above. Micro-light-emitting elements can take various planar shapes such as rectangles, polygons, circles, and ellipses, but the maximum envisioned length is less than 10 μm. The image display element is envisioned to have more than 3,000 micro-light-emitting elements clustered in pixel area 1.

[0025] [First Implementation]

[0026] Figure 1A This is a cross-sectional schematic diagram of the image display element 200 according to the first embodiment of the present invention. Figure 1B This is a top-down view. Figure 1B The cross-sectional view of part 1A-1A' is Figure 1A , Figure 1B It is along Figure 1A The cross-sectional view taken from 1B-1B shows the portion where the through electrode 40 is configured. (See diagram 1B-1B.) Figure 1A , Figure 1B As shown, the image display element 200 includes: a pixel region 1 in which a plurality of micro-light-emitting elements 100 are arranged in a two-dimensional array, and a connection region 3 connecting the first electrode 30 of the micro-light-emitting elements 100. In this embodiment, the image display element 200 is a monochrome display element, and one micro-light-emitting element 100 constitutes a pixel 5. In this configuration, the upper surface of the micro-light-emitting element 100 is a light-emitting surface.

[0027] The micro-light-emitting element 100 includes a compound semiconductor layer 14, a P-electrode (second electrode) 23P, and an N-electrode (first electrode) 30. The compound semiconductor layer 14 includes: a light-emitting layer 12 that emits light; an N-type layer (first conductive layer) 11 that injects electrons into the light-emitting layer 12; and a P-type layer (second conductive layer) 13 that injects holes into the light-emitting layer 12. For example, in micro-light-emitting elements emitting light in the ultraviolet to red wavelength range, the compound semiconductor layer 14 is a nitride semiconductor (AlInGaN-based); in the case of emitting light in the yellow-green to red wavelength range, it is an AlInGaP-based semiconductor. In the red to infrared wavelength range, it is an AlGaAs-based or GaAs-based semiconductor. The compound semiconductor layer 14 can be not only an inorganic compound semiconductor but also an organic electroluminescent element or a quantum dot electroluminescent element.

[0028] In this configuration, the compound semiconductor layer 14 of the micro light-emitting element 100 is described with an N-type layer 11 disposed on the light-emitting side, but a configuration in which a P-type layer 13 is disposed on the light-emitting side can also be used. The N-type layer 11, the light-emitting layer 12, and the P-type layer 13 are typically not single layers but are optimized to contain multiple layers; however, since this is not directly related to the configuration of this patent, the detailed structure of each layer is not described. Figure 1A In this process, the compound semiconductor layer 14 is cut between adjacent micro-light-emitting elements 100, but the N-type layer 11 can also be connected.

[0029] The driving circuit substrate 50 is composed of a semiconductor layer 60 and a wiring layer 70, with the wiring layer 70 disposed on a first surface of the semiconductor layer 60. On a second surface of the semiconductor layer 60 opposite to the first surface, micro-light-emitting elements 100 are arranged in an array. The semiconductor layer 60 is, for example, made of monocrystalline silicon, but is not limited thereto. A transistor 80 constituting the driving circuit is disposed at the boundary between the wiring layer 70 and the semiconductor layer 60. The channel portion and the source / drain diffusion layers constituting the transistor 80 are contained on the semiconductor layer 60 side, and the wiring connecting the gate, the gate insulating film, and the transistor terminals is contained in the wiring layer 70. P-wells 61 and N-wells 64 for arranging transistors are disposed on the first surface side of the semiconductor layer 60, and a semiconductor layer body 63 is disposed inside it. The semiconductor layer body 63 is, for example, a monocrystalline silicon substrate or an epitaxial growth layer, typically P-type, but is not limited thereto.

[0030] A through electrode 40 is provided in the semiconductor layer 60. In the pixel region 1, the transistor 80 constituting the micro-light-emitting element driving circuit is connected to the P electrode 23P of the micro-light-emitting element 100 via the through electrode 40 and the electrode connection portion 20. An underfill 16 is used to fill the spaces between adjacent micro-light-emitting elements 100 and between the micro-light-emitting element 100 and the driving circuit substrate 50. The underfill can be an inorganic material or an organic material, preferably a light-shielding material. The underfill can also be omitted.

[0031] A connection element 110 is provided in the connection region 3 for connecting the N electrode 30 and the driving circuit substrate 50 via wiring (e.g., ground wiring). The connection element 110 includes a compound semiconductor layer 14 identical to the compound semiconductor layer 14 constituting the micro light-emitting element 100, and has N wiring 18 that is conductive to the N electrode 30. The N wiring 18 is connected to the wiring layer 70 via a through electrode 40 and an electrode connection portion 20. Furthermore, the through electrodes disposed in the connection region 3 may also have multiple shapes with the same shape as the through electrodes 40 disposed in the pixel region 1 arranged along the edge of the pixel region 1. Alternatively, they may be formed into shapes longer than the through electrode 40, as with the through electrode 40a. In the pixel region 1, the size of the through electrode 40 is limited because the through electrodes must be arranged at pixel pitch, but in the connection region 3, through electrodes 40a of any size can be arranged. The connection electrodes in the connection region 3 can be sized according to the through electrode size, such that the connection electrode 20a is disposed on the through electrode 40a.

[0032] Current is supplied from transistor 80 to P electrode 23P through through electrode 40 and electrode connection portion 20. Current is injected from P electrode 23P into light-emitting layer 12 through P-type layer 13, generating light emission. Current flowing from N-type layer 11 to N electrode 30 flows from N wiring 18 of connection element 110 through electrode connection portion 20 and through electrode 40 to ground wire of wiring layer 70. In this way, driving circuit board 50 controls the amount of light emitted by each micro light-emitting element 100 to display images.

[0033] like Figure 3 As shown, the wiring layer 70 consists of wiring portions (72, 73, 74, etc.) primarily made of aluminum and copper, and an interlayer insulating film 71 that insulates the wirings. The interlayer insulating film 71 uses a transparent insulating film such as silicon oxide; therefore, the light path cannot be completely blocked within the wiring layer 70. This is because interrupting the transparent insulating film to completely block the light path would cause a short circuit between the wirings. In the prior art, on the first surface side of the semiconductor layer 60, i.e. Figure 3A micro-light-emitting element 100 is disposed above the wiring layer 70. Therefore, it is unavoidable that a certain amount of light emitted by the micro-light-emitting element 100 leaks into the wiring layer 70 on the side opposite to the light emission direction and reaches the semiconductor layer 60. The light reaching the semiconductor layer 60 is absorbed near the diffusion layer constituting the source / drain of the transistor, generating leakage current.

[0034] In this configuration, the micro-light-emitting element 100 is disposed on the second surface of the semiconductor layer 60, i.e., the surface opposite to the wiring layer 70. Of the light emitted by the micro-light-emitting element 100, light leaking to the side of the semiconductor layer 60 opposite to the light emission direction is absorbed by the semiconductor layer 60 and does not reach the vicinity of the transistor 80. Therefore, leakage current in the transistor 80 can be prevented. The thickness of the semiconductor layer 60 is preferably about 2 μm to 20 μm. Since the absorption coefficient of silicon decreases with longer wavelengths, the longer the emission wavelength, the thicker the semiconductor layer 60 needs to be.

[0035] This configuration can be manufactured as follows. The side of the silicon substrate on which the driving circuit is formed, opposite to the side where the transistor 80 and wiring layer 70 are formed (the second side), is ground to achieve the necessary thickness. This allows the wiring layer 70 and semiconductor layer 60 to be realized. Next, an insulating film is formed inside a hole that opens from the second side of the semiconductor layer 60 to the first side of the semiconductor layer 60. The insulating film does not completely fill the hole, leaving space in the center of the hole. The insulating film at the bottom of the hole is removed, leaving only the insulating film on the sidewall of the hole. This forms a through-electrode protective film 41.

[0036] Next, the conductive portion 42 of the through electrode is formed by embedding a conductor in the space surrounded by the through electrode protective film 41. Known techniques can be utilized in these manufacturing processes. Thus, the through electrode 40 is formed, and the micro-light-emitting element 100 is attached via the electrode connection portion 20, thereby revealing the image display element 200. Further details are irrelevant to this invention and are therefore omitted.

[0037] The planar shape of the through electrode 40 can be any shape, such as circular, quadrilateral, or rectangular. The insulating film can be formed by methods such as CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) and can be made of any material. The conductor constituting the conductive part 42 of the through electrode can be either a metal or a semiconductor. As the through electrode 40 moves from the second surface of the semiconductor layer 60 toward the first surface, its horizontal dimension can either gradually decrease or remain constant.

[0038] exist Figure 2 The figure shows a cross-sectional view of the micro light-emitting element 100, its semiconductor layer 60, and the connecting portion. Figure 2This is a cross-sectional view of the second side of the semiconductor layer 60. Regarding the semiconductor layer 60, only a portion of the side connected to the micro-light-emitting element 100 (a portion of the semiconductor layer body 63) is depicted. The micro-light-emitting element 100 is segmented, and the side of the light-emitting layer 12 of the micro-light-emitting element 100 is covered by an insulating protective film 15. The P-electrode 23P is configured to contact the P-type layer 13 and can be made of a highly reflective metal material such as silver or aluminum, or multiple layers of different metal materials can be stacked. Alternatively, it can be a structure stacked from the P-type layer 13 side with a transparent conductive film, a dielectric multilayer film, or a metal film.

[0039] The N-electrode 30 is a transparent conductive film, such as an oxide semiconductor like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or a silver nanofiber film. In pixel region 1, the N-electrode 30 is in contact with the N-type layer 11. Figure 2 As shown, in connection region 3, N electrode 30 is connected to N-type layer 11 and electrically connected to N wiring 18 via N-type layer 11. N electrode 30 and N wiring 18 can also be directly connected.

[0040] The electrode connection portion 20 is a connection component such as a bump, paste, or anisotropic conductive film. It can be disposed on the P electrode 23P side and connected to the through electrode 40, disposed on the through electrode 40 side and connected to the P electrode 23P, or a portion of the electrode connection portion 20 can be disposed on both the P electrode 23P side and the through electrode 40 side and bonded together.

[0041] The through electrode 40 is composed of a through electrode conductive portion (conductor) 42 penetrating the semiconductor layer 60 and a through electrode protective film (insulating layer) 41 covering its periphery. Furthermore, a semiconductor layer protective film 43 is disposed on the bonding surface side of the semiconductor layer 60 where it is bonded to the micro-light-emitting element 100. The semiconductor layer protective film 43 prevents current from flowing between adjacent P electrodes 23P via the semiconductor layer 60. However, to enable the micro-light-emitting element 100 to emit light, the voltage applied to the electrode connection portion 20 can be omitted as long as the current does not flow between the electrode connection portion 20 and the semiconductor layer 60. The through electrode protective film 41 and the semiconductor layer protective film 43 are insulating films such as SiO2 and SiN, and are transparent. To suppress light transmission, their thickness is preferably 200 nm or less. Furthermore, to reduce light intrusion into the through electrode protective film 41, it is preferable that the surface of the through electrode 40 is completely covered by the electrode connection portion 20. That is, it is preferable that the surfaces of both the through electrode conductive portion 42 and the through electrode protective film 41 are covered by the electrode connection portion 20. In this structure, light can be prevented from penetrating into the semiconductor layer 60 through the through electrode protective film 41.

[0042] Figure 3An enlarged view of the peripheral portion of transistor 80 is shown. Figure 3 This is a cross-sectional view of the first side of semiconductor layer 60. Additionally, for easier observation, in... Figure 3 In, with Figure 1A Reverse the vertical direction. In Figure 3 Below the image, a miniature light-emitting element 100 is disposed. Regarding the semiconductor layer 60, only a portion of the transistor 80 side is depicted. In pixel region 1, an NMOS transistor supplying current to the miniature light-emitting element 100 via a through electrode 40 is illustrated. A source 82 and a drain 83 are disposed in a P-well 61, separated from other transistors by a channel element separation 85. Both the source 82 and drain 83 are N-diffusion layers. A gate 81 is disposed between the source 82 and drain 83, separated by a gate insulating film 84. The source 82 is connected to the through electrode 40. The wiring layer 70 is composed of a contact plug 72, a first layer wiring 73, a via plug 74, an interlayer insulating film 71, etc. Figure 3 In this diagram, only the first layer routing 73 is shown, omitting the routing of subsequent layers, but the routing layer has multiple layers. Furthermore, in... Figure 3 While the gate 81 and the first layer wiring 73 appear to be not connected anywhere, they are envisioned to be connected to other wiring on the inner side of the paper, near the front. Although not shown, a PMOS-FET is also configured in the N-well (second well) 64.

[0043] When a positive voltage is applied to the gate 81, the transistor 80 is turned on, and the current supplied from the first layer wiring 73 flows from the drain 83 to the source 82. The current flows from the source 82 through the through electrode 40 to the micro light-emitting element 100 located on the opposite side of the semiconductor layer 60.

[0044] In this configuration, Figure 3 In connection region 3, the through electrode 40, which is connected to the N electrode 30, is connected to the wiring (e.g., ground wiring) via the P-type diffusion layer 87. In this configuration, the through electrode 40 and the ground wire are connected without passing through the transistor 80, but they can also be connected via the transistor 80 using the same structure as pixel region 1. As shown in connection region 3, the power supply voltage is supplied to the N-well 64 from the power supply wiring via the connected N-type diffusion layer 86.

[0045] In this configuration, unlike conventional designs, by placing the micro-light-emitting element 100 on the surface of the semiconductor layer 60 opposite to the wiring layer 70, it is possible to prevent light emitted by the micro-light-emitting element 100 from intruding into the vicinity of the transistor 80 and causing leakage current in the transistor 80. Therefore, by improving the accuracy of circuit operation, image display accuracy can be improved. Moreover, in this configuration, since the semiconductor layer 60 is thinner, the thermal resistance caused by the semiconductor layer 60 is reduced, and the heat emitted by the micro-light-emitting element 100 can be quickly dissipated. This reduces the temperature rise of the micro-light-emitting element 100 and improves luminous efficiency.

[0046] [Second Implementation]

[0047] use Figure 4 The second embodiment will be described. In the image display element 200a of this configuration, only the configuration of the semiconductor layer 60a differs from that of the first embodiment. Otherwise, it is the same as the first embodiment. In the first embodiment, a semiconductor layer protective film 43 is disposed on the surface of the semiconductor layer 60 on the side where the micro light-emitting element 100 is disposed, but in this configuration, a protective diffusion layer 44 is provided.

[0048] In this configuration, a protective diffusion layer 44 is provided to prevent leakage current between the electrode connection portions 20 of adjacent micro-light-emitting elements 100. The protective diffusion layer 44 has a conductivity type opposite to that of the semiconductor layer body 63 (in this embodiment, it is an N-type conductive layer). The protective diffusion layer 44 surrounds the through-electrode 40 and is formed on the surface of the semiconductor layer 60a. The protective diffusion layer 44 is cut off in each adjacent through-electrode 40. In this configuration, the electrode connection portion 20 is in direct contact with the protective diffusion layer 44. That is, since the electrode connection portion 20 is in direct contact with silicon, light can be prevented from penetrating into the through-electrode protective film 41. Since NPN bonding can be performed between adjacent electrode connections on the surface of the semiconductor layer 60a, no leakage current is generated.

[0049] According to this configuration, the same effect as the first embodiment can also be achieved.

[0050] [Third Implementation Method]

[0051] use Figure 5The third embodiment will be described. In the image display element 200b of this configuration, only the configuration of the semiconductor layer 60b differs from that of the first embodiment. Otherwise, it is the same as the first embodiment. The difference in the image display element 200b compared to the first embodiment lies in the addition of a deep N-well (third well) 62 to the pixel region 1. In this configuration, a triple-well structure is used in the semiconductor layer 60b. In addition to the P-well (first well) 61 and N-well (second well) 64 that constitute the CMOS circuit, a deep N-well (third well) 62 is also provided, through which the P-well 61 is electrically separated from the semiconductor layer body 63 of the semiconductor layer 60b. When a power supply voltage is applied to the deep N-well 62, the junction between the P-well 61, which is maintained at ground level, and the deep N-well 62 is reverse biased, thereby generating a depletion layer. Through this depletion layer, carriers generated by light reaching the vicinity of the transistor 80 of the semiconductor layer 60b are captured, thereby preventing the generation of leakage current in the transistor. When the wavelength emitted by the micro-light-emitting element 100 is very long, or when infrared light can be incident on the image display element 200b, the semiconductor layer 60b cannot completely absorb the light unless it becomes very thick. However, the thicker the semiconductor layer 60b, the more difficult it is to fabricate the through electrode 40. Therefore, allowing a small amount of light intrusion can suppress leakage current through this triple-well structure. In addition, in conventional manufacturing methods, the semiconductor layer body 63 is the original silicon substrate, and in the case of an epitaxial layer, the triple-well structure is a subsequently fabricated well structure corresponding to the epitaxial layer.

[0052] exist Figure 5 In the connection region 3, the deep N-well 62 is connected to the N-well 64, and the power supply voltage is supplied from the power supply wiring through the N-type diffusion layer 86 connected to the N-well 64.

[0053] In this configuration, the same effect as in the first embodiment can also be achieved.

[0054] [Fourth Implementation Method]

[0055] use Figure 6 The fourth embodiment will be described. In the image display element 200c of this configuration, only the configuration of the micro light-emitting element 100c differs from that of the first embodiment. Otherwise, it is the same as the first embodiment. The micro light-emitting element 100c differs from the first embodiment in that it has a P-type layer 13 arranged in the light emission direction, does not have an electrode connection portion 20, and has a spacer wall 24 around it.

[0056] The micro-light-emitting element 100 of the first to third embodiments, once shaped, is bonded to the semiconductor layer 60 via the electrode connection portion 20, thus making it suitable for a manufacturing method of forming an image display element. For example, on a substrate on which a compound semiconductor layer 14 is grown, the compound semiconductor layer 14 is processed, a protective film 15 and a P-electrode 23P are formed, and then it is bonded to the semiconductor layer 60 via the electrode connection portion 20 to form an underfill 16. Afterward, the substrate is peeled off to form an N-electrode 30, thereby completing the image display element 200c. That is, the processing of the compound semiconductor layer 14, the formation of the protective film 15 or the P-electrode 23P, etc., are not performed on the semiconductor layer 60. The micro-light-emitting element 100c of this configuration is suitable for a manufacturing method in which these processes related to the manufacturing of the micro-light-emitting element 100c are performed on the semiconductor layer 60. The advantage of performing these processes on the semiconductor layer 60 is that precise alignment is not required when bonding the semiconductor layer 60 and the compound semiconductor layer 14.

[0057] like Figure 6 As shown, in the micro-light-emitting element 100c, an N-electrode 23N (second electrode) is disposed on the through electrode 40, and a compound semiconductor layer 14c is disposed thereon. The N-electrode 23N covers the entire through electrode 40 so that the through electrode protective film 41 is not exposed. The compound semiconductor layer 14c is stacked in the order of N-type layer 11, light-emitting layer 12, and P-type layer 13 from the N-electrode 23N side. Spacer walls 24 are provided between adjacent N-electrodes 23N. The spacer walls 24 are preferably conductive. The spacer walls 24 surround the outer periphery of the micro-light-emitting element 100c and are arranged in a grid pattern when viewed from above. The spacer walls 24 are preferably at least light-reflective on their sides. This can suppress light emission from the micro-light-emitting element 100c to the adjacent portion and prevent light crosstalk.

[0058] Furthermore, the sides of the spacer 24 are preferably inclined in a manner that opens toward the light emission direction. By reflecting light emitted in the horizontal direction toward the light emission direction, the light emission efficiency can be improved. Therefore, the spacer 24 can be constructed with a material that has a high reflectivity to visible light as the main component, such as silver or aluminum, or it can be a composite component in which these metallic materials are disposed at least on the surface and the interior is composed of inorganic or organic materials.

[0059] The compound semiconductor layer 14c is surrounded by a protective film 15c. The protective film 15c is an insulating film that is transparent to the light emitted by the micro-light-emitting element 100c. The surface of the P-type layer 13 of the compound semiconductor layer 14c is exposed from the protective film 15c, and the P-electrode 30c (the first electrode) contacts it. The P-electrode 30c is a transparent electrode. Figure 6In the process, the protective film 15c is buried at the same height as the surface of the P-type layer 13 of the compound semiconductor layer 14c, and has a flat surface, but it can also cover the N electrode 23N and the compound semiconductor layer 14c with a certain thickness.

[0060] In the connection region 3, the spacer wall 24 is in contact with the through electrode 40. That is, in Figure 6 In the configuration, the connecting element 110c consists of a spacer wall 24 and a P electrode 30c. However, the P electrode 30c can be omitted, or the spacer wall 24 can be configured with the same structure as the N electrode 23N and the compound semiconductor layer 14c in the pixel region 1, overlapping each other. The spacer wall 24 is continuously arranged from the pixel region 1 to the connecting region 3, reducing the wiring resistance on the first electrode side of the micro light-emitting element 100c. As a result, the P electrode 30c, which is a transparent electrode, can be made thinner, reducing light absorption by the P electrode 30c and improving light output.

[0061] In this configuration, the compound semiconductor layer 14c occupies a very narrow area within the micro-light-emitting element 100c. Therefore, as described above, if, in order to avoid precise alignment, the compound semiconductor layer 14c is integrally attached to the semiconductor layer 60 and then processed to obtain an effect as described above... Figure 6 The box-shaped compound semiconductor layer 14c shown results in the loss of compound semiconductor layer between the box-shaped portions of the compound semiconductor layer 14c. A large amount of compound semiconductor layer is wasted. To avoid such loss of compound semiconductor layer 14, a manufacturing method can be adopted that pre-processes the box-shaped compound semiconductor layer 14c by intercalation and transfer it onto the semiconductor layer 60. In this case, the loss of compound semiconductor layer 14c can be reduced and it can be utilized effectively, but precise alignment is required. Thus, in this configuration where the area occupied by compound semiconductor layer 14c in the micro-light-emitting element 100c is very narrow, the compound semiconductor layer can be utilized effectively.

[0062] In this configuration, it is preferable to use a metallic material for the N-electrode 23N and the spacer 24 to prevent light leakage from these portions into the semiconductor layer 60. However, since a gap inevitably forms between the N-electrode 23N and the spacer 24, light leaks into the semiconductor layer 60. The leaked light is absorbed by the semiconductor layer 60 and does not reach the transistor 80. Therefore, in this configuration, the same effect as in the first embodiment can be achieved.

[0063] [Fifth Implementation Method]

[0064] use Figure 7 The fifth embodiment will be described. The image display element 200d configured in this way is similar to that in the fourth embodiment, but differs from the fourth embodiment in that the surface portion of the semiconductor layer 60d is used in the configuration of the spacer wall 24d.

[0065] In the first to fourth embodiments, the surface of the semiconductor layer 60 on the side adjacent to the micro light-emitting element 100 is flat, but as Figure 7 As shown, the surface of the semiconductor layer 60d is recessed into a bathtub shape. A through electrode 40 is disposed at the bottom of the recess, and the protrusion forms the main body of the spacer wall 24d. A semiconductor layer protective film 43d is formed on the surface of the semiconductor layer 60d. The N electrode 23N is disposed at the bottom of the recess, covering the entire through electrode 40, which is the same as in the fourth embodiment. A spacer wall reflective layer 25 is disposed on the sidewall surface of the spacer wall 24d. The spacer wall reflective layer 25 is made of a thin film with high conductivity and high reflectivity to visible light. For example, it is a metal film mainly composed of silver and aluminum. In this configuration, the N electrode 23N and the spacer wall reflective layer 25 can be formed simultaneously using the same material, which has the advantage. The micro-light-emitting element 100d has a protective film 15d covering the compound semiconductor layer 14c and a P electrode 30d made of a transparent electrode, which is the same as in the fourth embodiment.

[0066] In connection region 3, similar to pixel region 1, a bump and recess are formed on the surface of semiconductor layer 60d, and a through electrode 40 is disposed at the bottom of the recess. The through electrode 40 is connected to the spacer reflective layer 25. The spacer reflective layer 25 is continuously connected from pixel region 1, forming a wiring on the first electrode side. Connection element 110d is composed of spacer 24d. Additionally, in... Figure 7 In the connection region 3, the configuration is such that the P electrode 30d is removed, but the P electrode 30d can also be configured in the same way as in the fourth embodiment.

[0067] In this configuration, the same effect as in the first embodiment can also be achieved.

[0068] [Sixth Implementation Method]

[0069] use Figure 8The sixth embodiment will be described. The configuration of the micro-light-emitting element in the image display element 200e of this embodiment is similar to that of the fourth embodiment, but differs in that it is a full-color display element. The display elements of the first to fifth embodiments are monochrome displays, directly emitting light emitted from the compound semiconductor layer 14 to the outside. In this configuration, the micro-light-emitting element is composed of an excitation light-emitting element 105 and wavelength conversion sections (blue wavelength conversion section 31, red wavelength conversion section 32, and green wavelength conversion section 33). The excitation light-emitting element 105 is, for example, composed of a nitride semiconductor layer 14e, an N-electrode (second electrode) 23N, and a P-electrode (first electrode) 30c, and emits ultraviolet, near-ultraviolet, or blue light as excitation light. The wavelength conversion section disposed on the light-emitting surface side of the excitation light-emitting element 105 absorbs the excitation light and emits down-converted long-wavelength light to the outside. The wavelength conversion section is configured to fill the bathtub-shaped area surrounded by the spacer wall 24. Figure 8 As shown, the blue micro-light-emitting element 100B has a blue wavelength conversion section 31 disposed on the excitation light-emitting element 105. The blue wavelength conversion section 31 absorbs the excitation light emitted by the excitation light-emitting element 105 and emits blue light. The blue wavelength conversion section 31 is, for example, a resin layer containing phosphor particles, quantum dot particles, dyes composed of fluorescent molecules, etc. The blue wavelength conversion section 31 is surrounded by a spacer wall 24 to prevent light leakage to the red micro-light-emitting element 100R, the green micro-light-emitting element 100G, or the blue micro-light-emitting element 100B belonging to other pixels. Furthermore, since the sidewalls of the spacer wall 24 are inclined in a manner that opens in the light emission direction, the light emission efficiency can be improved.

[0070] The red micro-light-emitting element 100R and the green micro-light-emitting element 100G are identical to the blue micro-light-emitting element 100B, except that the red wavelength conversion section 32 and the green wavelength conversion section 33 are made of the same materials. Furthermore, when the excitation light-emitting element 105 is configured to emit blue light, the blue wavelength conversion section 31 is not required. However, by using a transparent resin section instead of the blue wavelength conversion section 31, the light extraction efficiency can be improved.

[0071] In this configuration, not only the excitation light emitted by the excitation light emitting element 105 may penetrate into the vicinity of the transistor 80, but the down-converted blue, green, and red light may also penetrate into the vicinity of the transistor 80. In particular, since silicon has a low absorption coefficient for red light, by setting the thickness of the semiconductor layer 60 in a way that prevents the intrusion of red light, it is possible to prevent the intrusion of all light including the excitation light.

[0072] In this configuration, the same effects as in the first embodiment can be achieved. Furthermore, full-color display can be achieved using a single image display element.

[0073] [Seventh Implementation Method]

[0074] use Figure 9 The seventh embodiment will be described. The image display element 200f configured in this way differs from the image display element 200 of the first embodiment in that it has a connection electrode 45 on its first surface, such as a diffusion layer connecting the through electrode 40 and the transistor 80. Otherwise, it differs from the first embodiment.

[0075] Based on the formation of the through electrode 40, it is easy to form a large horizontal dimension. However, if the large through electrode 40 is to be directly connected to the transistor 80, a large diffusion layer needs to be formed on the first surface. This is not preferable when reducing the pixel area. Therefore, a connection electrode 45 is formed inside the semiconductor layer 60 from the diffusion layer of the source 82 of the transistor 80 formed on the first surface. By connecting the through electrode 40 and the connection electrode 45, the area of ​​the diffusion layer can be prevented from increasing. The connection electrode 45 can be formed as follows: A small-diameter hole is formed from the source 82 and the P-type diffusion layer 87 toward the interior of the semiconductor layer 60, and a connection electrode protective film 46 is formed inside the hole. An insulating film such as SiO2 is deposited by CVD, and a dry etching method is used to etch back the film so that the insulating film remains only on the sidewall of the hole. Then, a conductive material is buried in the space of the hole not covered by the connection electrode protective film 46 to form the connection electrode 45. The connecting electrode 45 is preferably in contact with the surface of the diffusion layer on the first side and is electrically connected to the source electrode 82 and the P-type diffusion layer 87.

[0076] The connecting electrode 45 can be formed to a defined area. By pre-forming the connecting electrode 45 on the first surface, a through electrode 40 with a large cross-sectional area in the horizontal direction can be used. Therefore, the through electrode 40 can be easily manufactured.

[0077] In this configuration, the same effect as in the first embodiment can also be achieved.

[0078] 〔Summarize〕

[0079] The first aspect of the image display element disclosed herein includes: a plurality of micro light-emitting elements arranged in an array; and a semiconductor layer having a driving circuit disposed on each of the plurality of micro light-emitting elements for supplying current to cause it to emit light, a transistor constituting the driving circuit and a wiring layer disposed on a first side of the semiconductor layer, the plurality of micro light-emitting elements disposed on a second side of the semiconductor layer opposite to the first side, the transistor and the wiring layer being electrically connected to the micro light-emitting elements through through electrodes penetrating the semiconductor layer.

[0080] According to the above configuration, by arranging a micro light-emitting element on the surface of the semiconductor layer opposite to the wiring layer, it is possible to prevent the light emitted by the micro light-emitting element from penetrating into the vicinity of the transistor and generating leakage current in the transistor.

[0081] The image display element of Embodiment 2 of this disclosure is configured such that, in Embodiment 1 above, the cross-section of the through electrode has an insulating layer disposed on the outer side and a conductor disposed on the inner side when viewed from above.

[0082] The image display element of Embodiment 3 of this disclosure is configured such that, in Embodiment 1 or 2 above, a through electrode is provided on each of the micro light-emitting elements.

[0083] The image display element of Embodiment 4 of this disclosure is configured such that, in any of the embodiments 1-3 described above, a through electrode covers the entire second surface via an electrode connection portion.

[0084] Based on the above structure, it is possible to prevent light from penetrating into the interior of the semiconductor layer.

[0085] The image display element of Embodiment 5 of this disclosure is configured such that, in any of Embodiments 1 to 3 above, on the second surface, a through electrode is entirely covered by an electrode of a micro light-emitting element.

[0086] Based on the above structure, it is possible to prevent light from penetrating into the interior of the semiconductor layer.

[0087] The image display element of Embodiment 6 of this disclosure is configured such that, in any of Embodiments 1 to 5 above, a through electrode is connected to an N-type diffusion layer or a P-type diffusion layer in the first surface.

[0088] The image display element of Embodiment 7 of this disclosure is configured such that, in any of Embodiments 1 to 6, the second side of the semiconductor layer, except for the through electrode portion, is covered by an insulating film.

[0089] Based on the above configuration, current can be prevented from flowing between adjacent electrodes through the semiconductor layer.

[0090] The image display element of Embodiment 8 of this disclosure is configured such that, in any of Embodiments 1-6 above, in the second surface of the semiconductor layer, the through electrode is covered by a diffusion layer with a conductivity type opposite to that of the main body of the semiconductor layer.

[0091] Based on the above configuration, leakage current between the electrode connections of adjacent micro light-emitting elements can be prevented.

[0092] The image display element of Embodiment 9 of this disclosure is configured such that, in any of Embodiments 1 to 8 above, in a pixel region where a plurality of micro light-emitting elements are disposed, a first well of a transistor is disposed on the first side of a semiconductor layer, and a third well with a conductivity type opposite to that of the first well is disposed on the second side of the first well.

[0093] The image display element of Embodiment 10 of this disclosure is configured such that, in Embodiment 9 above, the third well is connected to the wiring layer via a second well whose conductivity type is opposite to that of the first well.

[0094] Based on the above configuration, by capturing the charge carriers generated by light reaching the vicinity of the transistor in the semiconductor layer through the depletion layer, leakage current of the transistor can be prevented.

[0095] The image display element of Embodiment 11 of this disclosure is configured such that, in any one of Embodiments 1 to 10, the micro-light-emitting element has a first electrode on the light-emitting surface side of the micro-light-emitting element and a second electrode on the surface opposite to the light-emitting surface, the second electrode being connected to the through electrode, and the polarity of the second electrode being opposite to that of the first electrode.

[0096] The image display element of Embodiment 12 of this disclosure is configured such that, in Embodiment 11 above, a connection region is disposed outside a pixel region in which a plurality of micro light-emitting elements are disposed, and a connection element and a through electrode are disposed in the connection region. The connection element connects the first electrode of the plurality of micro light-emitting elements and the wiring layer, and the through electrode is connected to the connection element.

[0097] The image display element of Embodiment 13 of this disclosure is configured such that, in any one of Embodiments 1-12 above, the micro light-emitting element is composed of an excitation light-emitting element and a wavelength conversion unit.

[0098] Based on the above configuration, full-color display can be achieved using a single image display element.

[0099] The image display element of Embodiment 14 of this disclosure is configured such that, in any one of Embodiments 1 to 13, a micro light-emitting element is surrounded by a spacer wall, which is formed on the second side of the semiconductor layer.

[0100] According to the above configuration, by using a metallic material for at least a portion of the spacer wall, it is possible to prevent light leakage into the semiconductor layer.

[0101] The image display element of Embodiment 15 of this disclosure is configured such that, in Embodiment 14 above, the spacer includes a protrusion disposed on the second surface of the semiconductor layer and is formed by the semiconductor layer.

[0102] This disclosure is not limited to the embodiments described above, and various modifications can be made within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included within the technical scope of this invention. Moreover, new technical features can be formed by combining the technical means disclosed in each embodiment.

Claims

1. An image display element comprising: a plurality of micro light emitting elements arranged in an array; and a semiconductor layer in which a drive circuit for supplying a current to each of the plurality of micro light emitting elements to cause it to emit light is provided, a transistor and a wiring layer constituting the drive circuit are provided on a first surface of the semiconductor layer, the plurality of micro light emitting elements are provided on a second surface of the semiconductor layer opposite to the first surface, the transistor and the wiring layer are electrically connected to the micro light emitting elements through a through electrode that penetrates the semiconductor layer, the semiconductor layer absorbs light emitted from the micro light emitting elements, and the semiconductor layer is formed to a thickness such that the light does not reach the transistor constituting the drive circuit, on the first surface, the through electrode is directly connected to an N-type diffusion layer or a P-type diffusion layer.

2. An image display element comprising: a plurality of micro light emitting elements arranged in an array; and a semiconductor layer in which a drive circuit for supplying a current to each of the plurality of micro light emitting elements to cause it to emit light is provided, a transistor and a wiring layer constituting the drive circuit are provided on a first surface of the semiconductor layer, the plurality of micro light emitting elements are provided on a second surface of the semiconductor layer opposite to the first surface, the transistor and the wiring layer are electrically connected to the micro light emitting elements through a through electrode that penetrates the semiconductor layer, the semiconductor layer absorbs light emitted from the micro light emitting elements, and the semiconductor layer is formed to a thickness such that the light does not reach the transistor constituting the drive circuit, on the second surface of the semiconductor layer, a periphery of the through electrode is covered with a diffusion layer having a conduction type opposite to a conduction type of a main body of the semiconductor layer located inside the semiconductor layer, and the diffusion layer is in contact with the semiconductor layer on the second surface.

3. An image display element comprising: a plurality of micro light emitting elements arranged in an array; and a semiconductor layer in which a drive circuit for supplying a current to each of the plurality of micro light emitting elements to cause it to emit light is provided, a transistor and a wiring layer constituting the drive circuit are provided on a first surface of the semiconductor layer, the plurality of micro light emitting elements are provided on a second surface of the semiconductor layer opposite to the first surface, the transistor and the wiring layer are electrically connected to the micro light emitting elements through a through electrode that penetrates the semiconductor layer, the semiconductor layer absorbs light emitted from the micro light emitting elements, and the semiconductor layer is formed to a thickness such that the light does not reach the transistor constituting the drive circuit, in a pixel region in which the plurality of micro light emitting elements are provided, a first well in which the transistor is provided is provided on a first surface side of the semiconductor layer, and a third well having a conduction type opposite to the first well is provided on a second surface side of the first well.

4. The image display element according to claim 3, characterized in that, The third well is connected to the wiring layer via a second well, the conduction type of the second well being opposite to that of the first well.

5. An image display element comprising: a plurality of micro light emitting elements arranged in an array; and a semiconductor layer provided with a drive circuit for supplying a current to each of the plurality of micro light emitting elements to cause it to emit light, the image display element characterized in that a transistor and a wiring layer constituting the drive circuit are provided on a first surface of the semiconductor layer, the plurality of micro light emitting elements are provided on a second surface of the semiconductor layer opposite to the first surface, the transistor and the wiring layer are electrically connected to the micro light emitting elements through a through electrode that penetrates the semiconductor layer, the semiconductor layer absorbs light emitted from the micro light emitting elements, the semiconductor layer being formed to a thickness such that the light does not reach the transistor constituting the drive circuit, the micro light emitting element includes: a first electrode provided on the side of a light emission surface of the micro light emitting element; and a second electrode having a polarity opposite to that of the first electrode and provided on a surface opposite to the light emission surface, the second electrode being electrically connected to the through electrode.

6. The image display element according to claim 5, characterized in that a connection region in which a connection element and a through electrode are provided is provided outside a pixel region in which the plurality of micro light emitting elements are provided, the connection element connecting the first electrode of the plurality of micro light emitting elements and the wiring layer, the through electrode being connected to the connection element.

7. The image display element according to any one of claims 1, 2, 3, and 5, characterized in that the through electrode is provided corresponding to each of the micro light emitting elements.

8. The image display element according to any one of claims 1, 2, 3, and 5, characterized in that a cross section of the through electrode is provided with an insulating layer on the outside and an electrically conductive body on the inside when viewed from above.

9. The image display element according to any one of claims 1, 2, 3, and 5, characterized in that in the second surface, the through electrode is covered entirely by an electrode connection portion.

10. The image display element according to any one of claims 1, 2, 3, and 5, characterized in that in the second surface, the through electrode is covered entirely by one electrode of the micro light emitting element.

11. The image display element according to any one of claims 1, 2, 3, and 5, characterized in that the second surface of the semiconductor layer is covered by an insulating film except for the through electrode.

12. The image display element according to any one of claims 1, 2, 3, and 5, characterized in that the micro light emitting element is constituted by an excitation light emitting element and a wavelength conversion portion.

13. The image display element according to any one of claims 1, 2, 3, and 5, characterized in that the micro light emitting element is surrounded by a partition wall, the partition wall being formed on the second surface of the semiconductor layer.

14. The image display element according to claim 13, characterized in that ​ The partition wall includes a convex portion disposed on a second surface of the semiconductor layer and composed of the semiconductor layer.

15. The image display element according to claim 13, wherein The micro light emitting element is composed of an excitation light emitting element and a wavelength conversion portion disposed inside the partition wall.

Images