Charge / discharge switch circuit, charge / discharge control device, chip and battery management system

Abstract

This disclosure provides a charge / discharge switch circuit for controlling the charging current and / or discharging current of a battery / battery, comprising: a first MOS transistor, the gate of which receives a first control signal to be turned on and off, the first MOS transistor being a low-voltage MOS transistor; a second MOS transistor, the gate of which receives a second control signal to be turned on and off, the second MOS transistor being a high-voltage MOS transistor; and a switch, one end of which is connected to the gate of the second MOS transistor, and the other end of which is connected to the source of the second MOS transistor, so that when the first MOS transistor is off, the switch is turned on to turn off the second MOS transistor before or simultaneously with the first MOS transistor being off. A charge / discharge control device, a chip, and a battery management system are also provided.

Description

Technical Field

[0001] This disclosure relates to a charge / discharge switch circuit, a charge / discharge control device, a chip, and a battery management system. Background Technology

[0002] In battery systems, overcharging and over-discharging not only reduce battery life but can also lead to safety accidents such as explosions and fires in severe cases. Examples of such batteries include lithium-ion battery packs.

[0003] Figure 1 This illustrates a conventional overcurrent detection method based on existing technology.

[0004] During normal battery discharge, the voltage at the control signal OD and OC ports of the drive unit is typically around VDD, 5V, or 15V. The control signals OD and OC are connected to the gates (G) of the protection switches MOSFETs M1 and M2, respectively. At this time, M1 and M2 operate in the linear region, and the drain (D) and source (S) of M1 and M2 are equivalent to a single on-resistance with a resistance value of R. on .

[0005] Discharge current I dsg The current flows from terminal P- to terminal B-, with a higher voltage at terminal P-. When the voltage difference (I) between terminal P- and terminal B- is detected... dsg *R on When a certain threshold is reached, the voltage of the control signal OD changes from, for example, VDD to VB- (the voltage at the B- terminal), thereby turning off M1 and shutting off the discharge path. The control signal OC can remain at a potential such as VDD, and M2 can remain in the on state.

[0006] Similarly, during normal battery charging, the gate voltages of M1 and M2 are VDD. Current flows from terminal B- to terminal P-. The voltage at terminal P- is lower. When the voltage difference between terminal B- and terminal P- (I... chg *R on When a certain threshold is reached, the voltage of the control signal OC changes from, for example, VDD to VB-, turning off M2 and cutting off the charging path. The control signal OD can remain at a potential such as VDD, and M1 can remain in the on state.

[0007] exist Figure 1 In the circuit structure shown, during normal charging, the on-resistance R of M1 and M2 is... on Since M1 and M2 are connected in series in the circuit of the battery and external charger, the power loss P caused by the on-resistance of M1 and M2 during system charging is significant. Loss =I chg *[2*R on ] 2This power loss is directly converted into heat generation in the system. Therefore, the temperature rise during system charging due to the heat loss between M1 and M2 is ΔT = P. Loss / (C*m), where C is the specific heat coefficient of the system and m is the mass of the system.

[0008] The safe operating temperature of a lithium battery system is typically around 45°C. Therefore, in order to control the system temperature rise caused by heat dissipation due to the on-resistance of M1 and M2, the maximum value of the charging current I must be controlled. chg(max) =P Loss(max) / ([2*R on ] 2 This reduces the charging current, which will inevitably prolong the system's charging time.

[0009] Similarly, during the discharge process, the on-resistance R of M1 and M2 on The series connection between the battery and the load (R) Load In the circuit, the heat loss P caused by the on-resistance of M1 and M2 is... Loss =I dsg *[2*R on ] 2 This power loss reduces the battery's energy utilization efficiency and limits the maximum discharge current. The heat loss from M1 and M2 during system discharge results in a ΔT = P. Loss / (C*m), where C is the specific heat coefficient of the system and m is the mass of the system. The safe operating temperature of a lithium battery system is typically around 45℃. Therefore, in order to control the system temperature rise caused by the heat dissipation due to the on-resistance of M1 and M2, the maximum value of the charging current I must be controlled. dsg(max) =P Loss(max) / ([2*R on ] 2 This will limit the maximum current that the battery system can output. Summary of the Invention

[0010] To address one of the aforementioned technical problems, this disclosure provides a charge / discharge switch circuit, a charge / discharge control device, a chip, and a battery management system.

[0011] According to one aspect, a charge / discharge switch circuit for controlling the charging current and / or discharging current of a battery / cell includes:

[0012] The first MOS transistor receives a first control signal at its gate to turn on and off. The first MOS transistor is a low-voltage MOS transistor, and its source or drain is connected to the battery side.

[0013] A second MOS transistor, the gate of which receives a second control signal for turning on and off, is a high-voltage MOS transistor. The source or drain of the second MOS transistor is connected to an external load or external charger. The drain or source of the second MOS transistor is connected to the drain or source of the first MOS transistor.

[0014] A switch, one end of which is connected to the gate of the second MOS transistor and the other end of which is connected to the source of the second MOS transistor, so that when the first MOS transistor is turned off, the switch is turned on so that the second MOS transistor is turned off before the first MOS transistor is turned off or is turned off at the same time as the first MOS transistor is turned off.

[0015] According to at least one embodiment of the present disclosure, the first MOS transistor is a discharge MOS transistor and the first control signal is a discharge control signal, the second MOS transistor is a charge MOS transistor and the second control signal is a charge control signal, the source of the first MOS transistor is connected to the battery side, the source of the second MOS transistor is connected to the external load or external charger side, and the drain of the second MOS transistor is connected to the drain of the second MOS transistor.

[0016] According to at least one embodiment of the present disclosure, the first MOS transistor is a charging MOS transistor and the first control signal is a discharging control signal, the second MOS transistor is a discharging MOS transistor and the second control signal is a discharging control signal, the drain of the first MOS transistor is connected to the battery side, the drain of the second MOS transistor is connected to the external load or external charger side, and the source of the second MOS transistor is connected to the source of the second MOS transistor.

[0017] According to at least one embodiment of this disclosure, the battery side is the low-voltage side of the battery, the external load or external charger side is the low-voltage side of the external load or the low-voltage side of the external charger, or the battery side is the high-voltage side of the battery, and the external load or external charger side is the high-voltage side of the external load or the high-voltage side of the external charger.

[0018] According to at least one embodiment of the present disclosure, a high-voltage protection diode is connected between the source and drain of the first MOS transistor.

[0019] According to at least one embodiment of the present disclosure, the on-resistance of the first MOS transistor is less than the on-resistance of the second MOS transistor.

[0020] According to at least one embodiment of this disclosure, the first MOS transistor and the second MOS transistor are NMOS transistors.

[0021] According to at least one embodiment of this disclosure, a second resistor is further included, the switch is a switching NMOS transistor, one end of the second resistor is connected to the gate of the switching NMOS transistor and the other end of the second resistor is connected to the source of the switching NMOS transistor, the gate of the switching NMOS transistor is connected to a current signal, the drain of the switching NMOS transistor is connected to the gate of a second MOS transistor, and the source of the switching NMOS transistor is connected to the source of the second MOS transistor.

[0022] According to at least one embodiment of this disclosure, when it is necessary to turn off the second MOS transistor, the current signal is provided, causing the second MOS transistor to be quickly turned off by the voltage formed on the second resistor.

[0023] According to at least one embodiment of the present disclosure, a first resistor is further included, one end of which is connected to the gate of the second MOS transistor and the other end of which is connected to the source of the second MOS transistor.

[0024] According to at least one embodiment of this disclosure, a second high-voltage protection diode is further included. The switch is a switching NMOS transistor. The positive terminal of the second high-voltage protection diode is connected to the gate of the switching NMOS transistor, and the negative terminal of the second high-voltage protection diode is connected to the source of the switching NMOS transistor. The gate of the switching NMOS transistor is connected to a current signal. The drain of the switching NMOS transistor is connected to the gate of a second MOS transistor, and the source of the switching NMOS transistor is connected to the source of the second MOS transistor.

[0025] According to at least one embodiment of this disclosure, when it is necessary to turn off the second MOS transistor, the current signal is provided, causing the second MOS transistor to be quickly turned off by the voltage formed on the second high-voltage protection diode.

[0026] According to at least one embodiment of the present disclosure, a first high-voltage protection diode is further included, wherein the positive terminal of the first high-voltage protection diode is connected to the gate of the second MOS transistor and the negative terminal of the high-voltage protection diode is connected to the source of the second MOS transistor.

[0027] According to at least one embodiment of the present disclosure, the switch is an N-channel junction field-effect transistor, the gate of the N-channel junction field-effect transistor is connected to the source of the second MOS transistor, the drain of the N-channel junction field-effect transistor is connected to the gate of the second MOS transistor, and the source of the N-channel junction field-effect transistor is connected to the source of the second MOS transistor.

[0028] According to at least one embodiment of the present disclosure, when it is necessary to turn off the second MOS transistor, the N-channel junction field-effect transistor is quickly turned off so that the second MOS transistor is quickly turned off.

[0029] According to at least one embodiment of the present disclosure, a first resistor is further included, one end of which is connected to the gate of the second MOS transistor and the other end of which is connected to the source of the second MOS transistor.

[0030] According to at least one embodiment of the present disclosure, the switch is an N-channel junction field-effect transistor, the gate of the N-channel junction field-effect transistor is connected to the source of the second MOS transistor, the drain of the N-channel junction field-effect transistor is connected to the gate of the second MOS transistor, and the source of the N-channel junction field-effect transistor is connected to the source of the second MOS transistor.

[0031] According to at least one embodiment of the present disclosure, when it is necessary to turn off the second MOS transistor, the N-channel junction field-effect transistor is quickly turned off so that the second MOS transistor is quickly turned off.

[0032] According to at least one embodiment of the present disclosure, a first high-voltage protection diode is further included, wherein the positive terminal of the first high-voltage protection diode is connected to the gate of the second MOS transistor and the negative terminal of the high-voltage protection diode is connected to the source of the second MOS transistor.

[0033] According to another aspect, a charge / discharge control device is provided for controlling the charging current and / or discharging current of a battery / battery pack, comprising:

[0034] The charge / discharge switch circuit described above; and

[0035] A driving circuit, wherein the driving circuit is used to provide the first control signal and the second control signal.

[0036] According to another aspect, a charge / discharge control device is provided for controlling the charging current and / or discharging current of a battery / battery pack, comprising:

[0037] The charge / discharge switch circuit described above; and

[0038] A driving circuit, wherein the driving circuit is used to provide the first control signal, the second control signal, and the current signal.

[0039] According to at least one embodiment of this disclosure, it further includes:

[0040] A voltage acquisition unit and / or detection circuit, wherein the voltage acquisition unit is used to acquire the voltage of the battery / battery pack, and the detection circuit is used to detect the charging current and / or discharging current; and

[0041] A control logic circuit that provides control signals to the drive circuit based on signals from the voltage acquisition unit and / or detection circuit.

[0042] According to another aspect, a chip integrates a charge / discharge switch circuit as described above, or integrates a charge / discharge control device as described above.

[0043] According to another aspect, a battery management system is characterized by including the charge / discharge switch circuit as described above, or including the charge / discharge control device as described above, or including the chip as described above.

[0044] According to another aspect, an electrical device includes:

[0045] A battery / battery pack for powering other components in the electrical equipment; and

[0046] The charge / discharge switch circuit described above, or the charge / discharge control device described above, or the chip described above, or the battery management system described above. Attached Figure Description

[0047] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0048] Figure 1 A schematic diagram of prior art battery management is shown.

[0049] Figure 2 A schematic diagram of a high-voltage transistor is shown.

[0050] Figure 3 A schematic diagram of battery management is shown.

[0051] Figure 4 A schematic diagram of battery management is shown.

[0052] Figure 5 A schematic diagram of battery management is shown.

[0053] Figure 6 A schematic diagram of battery management is shown.

[0054] Figure 7 A schematic diagram of a battery management system according to one embodiment of the present disclosure is shown.

[0055] Figure 8 A schematic diagram of a battery management system according to one embodiment of the present disclosure is shown.

[0056] Figure 9 A schematic diagram of a battery management system according to one embodiment of the present disclosure is shown.

[0057] Figure 10 A schematic diagram of a battery management system according to one embodiment of the present disclosure is shown.

[0058] Figure 11 A schematic diagram of a battery management system according to one embodiment of the present disclosure is shown.

[0059] Figure 12 A schematic diagram of an electrical device according to one embodiment of the present disclosure is shown. Detailed Implementation

[0060] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0061] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0062] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0063] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0064] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0065] For descriptive purposes, this disclosure may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as “below” or “under” another component or feature would subsequently be positioned “above” said other component or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0066] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0067] In battery management application environments, Figure 1 In the circuit structure shown, transistors M1 and M2 must both be high-voltage MOSFETs. The basic structure of a high-voltage MOSFET is as follows: Figure 2 As shown, the corresponding high-voltage MOSFET on-resistance R DS,on It consists of six parts, namely,

[0068] R DS,on =R s,metal +R source +R channel +R drift +R drain +R d,metal .

[0069] Among them, R s,metal R is the source contact resistance. source R is the source neutral region drift resistance. channel , where R is the channel resistance. drift For the drift resistance in the lightly doped breakdown voltage region, R drain R is the drain neutral region drift resistance. d,metal This is the drain contact resistance.

[0070]

[0071]

[0072]

[0073] V GS V is the gate-source voltage. Th C is the threshold turn-on voltage of the NMOSFET. ox The unit capacitance of the gate oxide layer is μ. n，ch μ represents the electron mobility of the NMOSFET channel.n，drift N represents the electron mobility in the breakdown voltage drift region. drift d represents the migration rate of N-type impurities in the pressure-resistant drift region. drift L is the vertical depth of the channel in the pressure-resistant drift zone. drift W is the length of the channel in the direction of the pressure-resistant drift region. drift BV is the width of the breakdown voltage drift region perpendicular to the channel direction, BV is the drain-source breakdown voltage of the NMOSFET, and V is the voltage in volts (used to normalize BV, where BV / V is a dimensionless physical quantity).

[0074] High-voltage NMOSFETs (e.g., source-drain breakdown voltage greater than 10V) are equivalent to low-voltage NMOSFETs (e.g., source-drain breakdown voltage less than 5V). The device structure must employ a long, lightly doped drift area, and the higher the drain-source breakdown voltage, the higher the doping concentration of the drift area. drift The lower the value, the longer the drift region L. drift And the longer it gets.

[0075] Based on the formula for the voltage withstand drift region resistance above, it can be seen that the higher the voltage withstand, the greater the drift resistance R in the lightly doped voltage withstand region. drift The larger the value, the higher the on-resistance of the NMOSFET. Generally speaking, for high-voltage NMOSFETs, the drift region resistance is dominant.

[0076] In conventional protection switch circuit design, two high-voltage MOSFETs connected in series must be used.

[0077] To address the problems existing in the current technology, such as the power losses caused by the charging and discharging switches, which affect the performance of the battery system, it is necessary to reduce the series on-resistance of the MOSFET in the current path. Therefore, it is possible to use only... Figure 1 The MOSFETs M1 or M2 shown are connected in series in the current path, with one of the MOSFETs used as both a charging and discharging switch. Clearly, using a single MOSFET reduces the on-resistance by half and the power consumption by half. However, using a high-voltage MOSFET will cause the following problems.

[0078] The following explanation will focus on the case where a single MOSFET is used as both the charging and discharging switch.

[0079] Figure 3 The battery discharge process is illustrated. The example shown is where only M1 is used for the charge / discharge switch, omitting M2. Figure 3As shown, the source (S) of MOS transistor M1 is connected to the base (B-) of the battery, and the drain (D) of MOS transistor M1 is connected to the p-terminal of the external load. MOS transistor M1 has a parasitic diode D1. The gate (G) of MOS transistor M1 receives a control signal from the driving unit to turn it on and off. The source (S) of MOS transistor M1 is shorted to its substrate (Bulk, B-terminal). By using a single MOS transistor M1, the on-resistance R of the charge / discharge switch will obviously be reduced. on Reduced to half.

[0080] When the battery discharges to an external load, the direction of current flow in the circuit is: discharge current I dsg The current flows from terminal P- to terminal B-, and the voltage at terminal B- is higher than the voltage at terminal P-. When the voltage difference (I) between terminal P- and terminal B- is detected... dsg *R on When a certain threshold is reached, the voltage of the control signal of the gate of MOS transistor M1 changes from high level (e.g., VDD, the power supply voltage of the driving unit) to VP- (the voltage at the P- terminal), thereby turning off M1 and shutting off the discharge path.

[0081] Figure 4 The battery charging process is illustrated. The example shown is where only M1 is used for the charge / discharge switch, omitting M2. Figure 4 As shown, the source (S) of MOS transistor M1 is connected to the base (B-) of the battery, and the drain (D) of MOS transistor M1 is connected to the p-terminal of the external load. MOS transistor M1 has a parasitic diode D1. The gate (G) of MOS transistor M1 receives a control signal from the driving unit to turn it on and off. The source (S) of MOS transistor M1 is shorted to its substrate (Bulk, B-terminal). By using a single MOS transistor M1, the on-resistance R of the charge / discharge switch will obviously be reduced. on Reduced to half.

[0082] When a battery is charged via an external charger, the direction of current flow in the circuit is: charging current I chg The current flows from terminal B- to terminal P-, and the voltage at terminal P- is higher than the voltage at terminal B-. When the voltage difference (I) between terminal B- and terminal P- is detected... chg *R on When a certain threshold is reached, in order to turn off M1, the control signal voltage of the gate of MOS transistor M1 changes from high level (VDD, power supply voltage of the driving circuit) to VB-, that is, the gate G and the source S are short-circuited, VG = VS = VB-.

[0083] D1 is a natural parasitic diode of MOSFET M1. The positive terminal (anode, P-type doped) of parasitic diode D1 is the P-well (bulk) of MOSFET M1, and the negative terminal (cathode, N-type doped) of parasitic diode D1 is the drain D of MOSFET M1. Therefore, even if the voltage of the control signal of MOSFET M1's gate G is VB-, and MOSFET M1 is turned off (conductive channel not formed), the charging current still continues to flow through parasitic diode D1, continuing to charge the battery.

[0084] Therefore, due to the presence of the parasitic diode D1, MOSFET M1 still cannot completely turn off the charging current under overcurrent charging conditions.

[0085] The following explanation addresses the case where only M2 is used in the charge / discharge switch, while M1 is omitted.

[0086] Figure 5 An example is shown in the case of discharge, such as Figure 5 As shown, the drain (D) of MOS transistor M2 is connected to the B-terminal of the battery, and the source (S) of MOS transistor M2 is connected to the P-terminal of the external load. MOS transistor M2 has a parasitic diode D1. The gate (G) of MOS transistor M2 receives a control signal from the driving unit to turn it on and off. The source (S) of MOS transistor M2 is shorted to its substrate (Bulk, B-terminal). By using a single MOS transistor M2, the on-resistance R of the charge / discharge switch will obviously be reduced. on Reduced to half.

[0087] When the battery discharges to a load, the direction of current flow in the circuit is: discharge current I dsg The current flows from terminal P- to terminal B-, with a higher voltage at terminal B-. When the voltage difference (I) between terminals P- and B- is detected... dsg *R on When a certain threshold is reached, in order to shut off the discharge path, the voltage of the gate control signal of MOS transistor M2 changes from high level (VDD, the power supply voltage of the drive circuit) to VP-, and the gate G and source S are shorted, VG = VS = VP-. Although VG - VS = 0, and the conductive channel of M2 disappears, because the positive terminal of parasitic diode D1 is connected to the P-type substrate region (bulk) of MOS transistor M2 and is connected to the source S, i.e., the P- terminal, and the negative terminal of D1 is connected to the drain D of MOS transistor M2, the battery can still continue to discharge to the load through the parasitic diode D1 of MOS transistor M2, and the discharge path cannot be completely shut off.

[0088] Figure 6 An example is shown in the charging case, such as Figure 5As shown, the drain (D) of MOS transistor M2 is connected to the B-terminal of the battery, and the source (S) of MOS transistor M2 is connected to the P-terminal of the external load. MOS transistor M2 has a parasitic diode D1. The gate (G) of MOS transistor M2 receives a control signal from the driving unit to turn it on and off. The source (S) of MOS transistor M2 is shorted to its substrate (Bulk, B-terminal). By using a single MOS transistor M2, the on-resistance R of the charge / discharge switch will obviously be reduced. on Reduced to half.

[0089] When the battery is charged by an external charger, the direction of current flow in the circuit is: charging current I chg The current flows from terminal B to terminal P. The voltage at terminal P is higher. When the voltage difference (I) between terminal B and terminal P is detected... chg *R on When a certain threshold is reached, in order to turn off the MOS transistor M2, the voltage of the control signal of the MOS transistor M2 changes from high level (VDD, the power supply voltage of the driving circuit) to VB-, that is, the gate G and the source S are short-circuited, VG=VS=VB-, the conductive channel of the MOS transistor M2 disappears, and the MOS transistor M2 is turned off.

[0090] according to Figures 3 to 6 As can be seen from the explanation, although using MOS transistors M1 or M2 alone can reduce the on-resistance, it cannot completely shut off the current path when overcurrent occurs during charging or discharging.

[0091] To address the problems existing in the prior art, this disclosure provides the following technical solutions. In the embodiments of this disclosure, the MOS transistor is in the form of an NMOSFET; however, those skilled in the art should understand that a PMOSFET can also be used. When using a PMOSFET, the principle is the same as described above, and will not be repeated here for the sake of brevity.

[0092] In this disclosure, to reduce the on-resistance of the NMOS transistor in the current path, a combination of low-voltage and high-voltage NMOS transistors is used. For example, in the following description, the discharge control switch is replaced with a low-voltage NMOS transistor, while the charging control switch still uses a high-voltage NMOS transistor. Of course, based on the principles of this disclosure, those skilled in the art should understand that the charging control switch can also be replaced with a low-voltage NMOS transistor, while the discharge control switch still uses a high-voltage NMOS transistor.

[0093] This disclosure provides a charge / discharge switch circuit for controlling the charging current and / or discharging current of a battery / battery, comprising: a first MOS transistor, the gate of which receives a first control signal to turn on and off, the first MOS transistor being a low-voltage MOS transistor, and the source or drain of the first MOS transistor being connected to the battery side; a second MOS transistor, the gate of which receives a second control signal to turn on and off, the second MOS transistor being a high-voltage MOS transistor, the source or drain of the second MOS transistor being connected to an external load or an external charger side, and the drain or source of the second MOS transistor being connected to the drain or source of the second MOS transistor; and a switch, one end of which is connected to the gate of the second MOS transistor, and the other end of which is connected to the source of the second MOS transistor, such that when the first MOS transistor is off, the switch is turned on so that the second MOS transistor is turned off before or simultaneously with the first MOS transistor being turned off.

[0094] Furthermore, the first MOS transistor is a discharge MOS transistor and the first control signal is a discharge control signal; the second MOS transistor is a charge MOS transistor and the second control signal is a charge control signal; the source of the first MOS transistor is connected to the battery side; the source of the second MOS transistor is connected to the external load or external charger side; and the drain of the second MOS transistor is connected to the drain of the second MOS transistor.

[0095] Furthermore, the first MOS transistor is a charging MOS transistor and the first control signal is a discharging control signal, the second MOS transistor is a discharging MOS transistor and the second control signal is a discharging control signal, the drain of the first MOS transistor is connected to the battery side, the drain of the second MOS transistor is connected to the external load or external charger side, and the source of the second MOS transistor is connected to the source of the second MOS transistor.

[0096] Furthermore, the battery side is the low-voltage side of the battery, the external load or external charger side is the low-voltage side of the external load or the low-voltage side of the external charger, or the battery side is the high-voltage side of the battery, and the external load or external charger side is the high-voltage side of the external load or the high-voltage side of the external charger.

[0097] Furthermore, the on-resistance of the first MOS transistor is less than that of the second MOS transistor. Thus, for the first and second MOS transistors connected in series, since the on-resistance of the first MOS transistor is much smaller than that of the second MOS transistor, the on-resistance of their series circuit is significantly reduced, resulting in a significant reduction in power consumption. Additionally, when the first and second MOS transistors have the same dimensions, the on-resistance of the lower-voltage first MOS transistor is obviously much smaller than that of the higher-voltage second MOS transistor. Even when the dimensions are different, if the on-resistance of the first MOS transistor is made equal to that of the second MOS transistor, the manufacturing cost of the lower-voltage first MOS transistor is much lower than that of the higher-voltage second MOS transistor, effectively reducing system cost.

[0098] Furthermore, a high-voltage protection diode is connected between the source and drain of the first MOS transistor.

[0099] The technical solution of this disclosure will be described below with reference to specific examples.

[0100] <First Implementation Method>

[0101] like Figure 7 As shown, this embodiment provides a charge and discharge control device, which may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a drive unit 40, and a charge and discharge control switch 50.

[0102] VDD generator 10 can be connected to the highest voltage of the battery / battery pack in order to generate the voltage VDD required inside the charge / discharge control device based on the highest voltage.

[0103] The voltage acquisition unit 20 can be used to acquire the voltage of a battery / battery pack. In the case of a battery pack, the voltage acquisition unit 20 can be used to acquire the voltage of each battery cell.

[0104] The logic control circuit 30 can generate control signals based on the collected battery / battery pack voltage. Alternatively, the logic control circuit 30 can also generate control signals based on the charging current and discharging current.

[0105] The drive unit 40 provides the signal to drive the charge and discharge control switch 50 according to the control signal of the logic control circuit 30.

[0106] The charge / discharge control switch 50 controls the charging current and discharging current based on the received switch control signal.

[0107] The charge / discharge control switch 50 may include a first low-voltage NMOS transistor 100 used as a discharge switch, a high-voltage NMOS transistor 200 used as a charge switch, and a switching NMOS transistor 300.

[0108] The first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200 can be connected in series on the high-voltage side of the battery / battery pack or in series on the low-voltage side of the battery / battery pack, and there is no limitation on the order in which they are connected in series.

[0109] In this embodiment, the example is that a first low-voltage NMOS transistor 100 and a high-voltage NMOS transistor 200 are connected in series to the low-voltage side of the battery / battery pack, and the example is that the source S of the first low-voltage NMOS transistor 100 is connected to the low-voltage terminal of the battery / battery pack.

[0110] The gate of the first low-voltage NMOS transistor 100 receives a discharge control signal OD from the driving unit 40, and the gate of the high-voltage NMOS transistor 200 receives a charge control signal OC from the driving unit 40. The drain of the first low-voltage NMOS transistor 100 is connected to the drain of the high-voltage NMOS transistor 200. The first low-voltage NMOS transistor 100 has a first parasitic diode D1, and the high-voltage NMOS transistor 200 has a second parasitic diode D2.

[0111] The positive terminal of the first high-voltage protection diode 102 is connected to the source of the first low-voltage NMOS transistor 100, and the negative terminal of the first high-voltage protection diode 102 is connected to the drain of the first low-voltage NMOS transistor 100.

[0112] The drain of the switching NMOS transistor 300 is connected to the gate of the high-voltage NMOS transistor 200, and the source of the switching NMOS transistor 300 is connected to the source of the high-voltage NMOS transistor 200. A first resistor 302 is connected between the source and drain of the switching NMOS transistor 300.

[0113] The gate of the switching NMOS transistor 300 receives a current signal OB from the driving unit 40, and the gate of the switching NMOS transistor 300 is connected to the source of the high-voltage NMOS transistor 200 through a second resistor 304. The switching NMOS transistor 300 can be in a low-voltage form and can be made very small in size.

[0114] The source of the first low-voltage NMOS transistor 100 is connected to the low-voltage terminal B- of the battery / battery pack, while the source of the high-voltage NMOS transistor 200 is connected to the low-voltage terminal P- of an external load or charger. Those skilled in the art will also understand that connecting the source of the high-voltage NMOS transistor 200 to the low-voltage terminal B- of the battery / battery pack, and the source of the first low-voltage NMOS transistor 100 to the low-voltage terminal P- of an external load or charger, can achieve the same function. Similarly, connecting it to the high-voltage side of the battery / battery pack can also achieve the same function.

[0115] According to embodiments of this disclosure, the breakdown voltage of the first low-voltage NMOS transistor 100 can be 1.8 to 7V, i.e., V GS V GD V DS The voltage rating can range from 1.8 to 7V. The voltage rating of a high-voltage NMOS transistor 200 is related to the battery voltage, and is typically 1.5 to 2 times the sum of the voltages of each battery cell. For example, with 16 batteries, each cell typically has a voltage of 4.5V, so the voltage rating needs to be 4.5 * 16 * (1.5 to 2). For instance, its voltage rating should be greater than 108V, i.e., V... GS V GD V DS Greater than 108V. As described above, on-resistance is related to the withstand voltage; therefore, the on-resistance of the first low-voltage NMOS transistor 100 will be significantly less than that of the high-voltage NMOS transistor 200. The withstand voltage of the switching NMOS transistor 300 can be between 10 and 20V.

[0116] In this design, the first low-voltage NMOS transistor 100 is a low-voltage transistor. Therefore, when the first low-voltage NMOS transistor 100 is turned off, if the high-voltage NMOS transistor 200 cannot be turned off in time (e.g., before or simultaneously with the first low-voltage NMOS transistor 100), the high-voltage NMOS transistor 200 remains on, and the voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. Since the voltage at the P- terminal will rise to the P+ terminal value during the turn-off process of both the first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200, this means the voltage at the P- terminal will increase.

[0117] Since the high-voltage NMOS transistor 200 cannot be turned off in time, the rising voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. Since the first low-voltage NMOS transistor 100 is a low-voltage transistor, if a high voltage is applied to its drain, it will inevitably cause damage to the first low-voltage NMOS transistor 100.

[0118] In this embodiment, by setting a switch (in the form of a switching NMOS transistor 300), the high-voltage NMOS transistor 200 is turned off in a timely manner during the turn-off process (e.g., before or simultaneously with the first low-voltage NMOS transistor 100). This ensures that the rising voltage at the P-terminal is not applied to the drain of the first low-voltage NMOS transistor 100, but rather to the drain of the high-voltage NMOS transistor 200 (because the high-voltage NMOS transistor 200 is a high-voltage type transistor, the high voltage will not cause damage to the high-voltage NMOS transistor 200).

[0119] For a practical high-voltage NMOS transistor 200, there is a parasitic capacitance between its gate G and source S. Due to the presence of this parasitic capacitance, even at V... GS Even when the voltage is below the threshold voltage, the high-voltage NMOS transistor 200 cannot turn off quickly because the discharge of charge from the capacitor takes time. Therefore, even if the gate control signal voltage is below the threshold voltage, the high-voltage NMOS transistor 200 cannot turn off quickly. The parasitic capacitance of the high-voltage NMOS transistor 200 needs to be discharged through the circuit with the first resistor 302. In this situation, a turn-off delay of the high-voltage NMOS transistor 200 is inevitable.

[0120] In this embodiment, a switch connected in series between the gate and source of the high-voltage NMOS transistor 200 is used to quickly turn off the high-voltage NMOS transistor 200 when it needs to be turned off (so that the parasitic capacitance is discharged quickly).

[0121] When the high-voltage NMOS transistor 200 needs to be turned off, the drive voltage provides a current signal OB. The current OB flows through the second resistor 304, thus forming a voltage through the second resistor 304. This voltage is greater than the gate-source voltage V of the switching NMOS transistor 300. GS The switching NMOS transistor 300 quickly turns on, thus forming a path between the gate and source of the high-voltage NMOS transistor 200. This allows the parasitic capacitance between the gate and source of the high-voltage NMOS transistor 200 to discharge rapidly, thereby causing the high-voltage NMOS transistor 200 to turn off quickly. In this way, the rising P-terminal voltage is not applied to the drain of the first low-voltage NMOS transistor 100, and the first low-voltage NMOS transistor 100 will not be damaged.

[0122] Furthermore, the purpose of connecting a first high-voltage protection diode 102 in series between the source and drain of the first low-voltage NMOS transistor 100 is that when the first low-voltage NMOS transistor 100 is turned off, but the high-voltage NMOS transistor 200 is not turned off in time, a high voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. The first high-voltage protection diode 102 will then act as a protector, causing it to reverse-bias breakdown, thus preventing damage to the first low-voltage NMOS transistor 100. This is because the reverse breakdown of the first high-voltage protection diode 102 prevents the drain voltage of the first low-voltage NMOS transistor 100 from becoming excessively high.

[0123] With the configuration of this embodiment, the on-resistance value of the series NMOS transistor from the B-terminal to the P-terminal is:

[0124] R on =R DS,on (100)+R DS,on (200), where R on R is the sum of the on-resistances of the first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200. DS,on (100) is the on-resistance of the first low-voltage NMOS transistor 100, while R DS,on (200) is the on-resistance of the high-voltage NMOS transistor 200.

[0125] Furthermore, since the first low-voltage NMOS transistor 100 is a low-voltage NMOSFET, the physical structure of a low-voltage NMOSFET does not require a low-doped voltage drift region. In other words, for a low-voltage NMOSFET, R... DS,on (100)=R s,metal +R source +R channel +R drain +R d,metal .

[0126] Therefore, for NMOSFETs of the same physical size, R DS,on (100) is much smaller than R DS,on (200), then R on ≈R DS,on (200). Therefore, by using high and low voltage NMOSFETs in series, the on-resistance of the series MOSFETs can be reduced by half, thus reducing the heat loss caused by the on-resistance by half.

[0127] <Second Implementation Method>

[0128] like Figure 8As shown, this embodiment provides a charge and discharge control device, which may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a drive unit 40, and a charge and discharge control switch 50.

[0129] VDD generator 10 can be connected to the highest voltage of the battery / battery pack in order to generate the voltage VDD required inside the charge / discharge control device based on the highest voltage.

[0130] The voltage acquisition unit 20 can be used to acquire the voltage of a battery / battery pack. In the case of a battery pack, the voltage acquisition unit 20 can be used to acquire the voltage of each battery cell.

[0131] The logic control circuit 30 can generate control signals based on the collected battery / battery pack voltage. Alternatively, the logic control circuit 30 can also generate control signals based on the charging current and discharging current.

[0132] The drive unit 40 provides the signal to drive the charge and discharge control switch 50 according to the control signal of the logic control circuit 30.

[0133] The charge / discharge control switch 50 controls the charging current and discharging current based on the received switch control signal.

[0134] The charge / discharge control switch 50 may include a first low-voltage NMOS transistor 100 used as a discharge switch, a high-voltage NMOS transistor 200 used as a charge switch, and a switching NMOS transistor 300.

[0135] The first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200 can be connected in series on the high-voltage side of the battery / battery pack or in series on the low-voltage side of the battery / battery pack, and there is no limitation on the order in which they are connected in series.

[0136] In this embodiment, the example is that a first low-voltage NMOS transistor 100 and a high-voltage NMOS transistor 200 are connected in series to the low-voltage side of the battery / battery pack, and the example is that the source S of the first low-voltage NMOS transistor 100 is connected to the low-voltage terminal of the battery / battery pack.

[0137] The gate of the first low-voltage NMOS transistor 100 receives a discharge control signal OD from the driving unit 40, and the gate of the high-voltage NMOS transistor 200 receives a charge control signal OC from the driving unit 40. The drain of the first low-voltage NMOS transistor 100 is connected to the drain of the high-voltage NMOS transistor 200. The first low-voltage NMOS transistor 100 has a first parasitic diode D1, and the high-voltage NMOS transistor 200 has a second parasitic diode D2.

[0138] The positive terminal of the first high-voltage protection diode 102 is connected to the source of the first low-voltage NMOS transistor 100, and the negative terminal of the first high-voltage protection diode 102 is connected to the drain of the first low-voltage NMOS transistor 100.

[0139] The drain of the switching NMOS transistor 300 is connected to the gate of the high-voltage NMOS transistor 200, and the source of the switching NMOS transistor 300 is connected to the source of the high-voltage NMOS transistor 200. A second high-voltage protection diode 306 is connected between the source and drain of the switching NMOS transistor 300. The positive terminal of the second high-voltage protection diode 306 is connected to the source of the high-voltage NMOS transistor 200, and the negative terminal of the second high-voltage protection diode 306 is connected to the gate of the high-voltage NMOS transistor 200. Thus, when current flows through the positive and negative terminals of the second high-voltage protection diode 306, its breakdown voltage is 6.5–7.5V, ensuring that the gate-source voltage of the high-voltage NMOS transistor 200 is greater than the threshold turn-on voltage, thereby turning on the high-voltage NMOS transistor 200.

[0140] The gate of the switching NMOS transistor 300 receives a current signal OB from the driving unit 40, and the gate of the switching NMOS transistor 300 is connected to the source of the high-voltage NMOS transistor 200 through a third high-voltage protection diode 308. The positive terminal of the third high-voltage protection diode 308 is connected to the source of the high-voltage NMOS transistor 200, while the negative terminal of the third high-voltage protection diode 308 is connected to the source of the switching NMOS transistor 300. The switching NMOS transistor 300 can be a low-voltage diode and can be made very small.

[0141] The source of the first low-voltage NMOS transistor 100 is connected to the low-voltage terminal B- of the battery / battery pack, while the source of the high-voltage NMOS transistor 200 is connected to the low-voltage terminal P- of an external load or charger. Those skilled in the art will also understand that connecting the source of the high-voltage NMOS transistor 200 to the low-voltage terminal B- of the battery / battery pack, and the source of the first low-voltage NMOS transistor 100 to the low-voltage terminal P- of an external load or charger, can achieve the same function. Similarly, connecting it to the high-voltage side of the battery / battery pack can also achieve the same function.

[0142] According to embodiments of this disclosure, the breakdown voltage of the first low-voltage NMOS transistor 100 can be 1.8 to 7V, i.e., V GS V GD V DSThe voltage rating can range from 1.8 to 7V. The voltage rating of a high-voltage NMOS transistor 200 is related to the battery voltage, and is typically 1.5 to 2 times the sum of the voltages of each battery cell. For example, with 16 batteries, each cell typically has a voltage of 4.5V, so the voltage rating needs to be 4.5 * 16 * (1.5 to 2). For instance, its voltage rating should be greater than 108V, i.e., V... GS V GD V DS Greater than 108V. As described above, on-resistance is related to the withstand voltage; therefore, the on-resistance of the first low-voltage NMOS transistor 100 will be significantly less than that of the high-voltage NMOS transistor 200. The withstand voltage of the switching NMOS transistor 300 can be between 10 and 20V.

[0143] In this design, the first low-voltage NMOS transistor 100 is a low-voltage transistor. Therefore, when the first low-voltage NMOS transistor 100 is turned off, if the high-voltage NMOS transistor 200 cannot be turned off in time (e.g., before or simultaneously with the first low-voltage NMOS transistor 100), the high-voltage NMOS transistor 200 remains on, and the voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. Since the voltage at the P- terminal will rise to the P+ terminal value during the turn-off process of both the first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200, this means the voltage at the P- terminal will increase.

[0144] Since the high-voltage NMOS transistor 200 cannot be turned off in time, the rising voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. Since the first low-voltage NMOS transistor 100 is a low-voltage transistor, if a high voltage is applied to its drain, it will inevitably cause damage to the first low-voltage NMOS transistor 100.

[0145] In this embodiment, by setting a switch (in the form of a switching NMOS transistor 300), the high-voltage NMOS transistor 200 is turned off in a timely manner during the turn-off process (e.g., before or simultaneously with the first low-voltage NMOS transistor 100). This ensures that the rising voltage at the P-terminal is not applied to the drain of the first low-voltage NMOS transistor 100, but rather to the drain of the high-voltage NMOS transistor 200 (because the high-voltage NMOS transistor 200 is a high-voltage type transistor, the high voltage will not cause damage to the high-voltage NMOS transistor 200).

[0146] For a practical high-voltage NMOS transistor 200, there is a parasitic capacitance between its gate G and source S. Due to the presence of this parasitic capacitance, even at V... GSEven when the voltage is below the threshold voltage, the high-voltage NMOS transistor 200 cannot turn off quickly because the discharge of charge from the capacitor takes time. Therefore, even if the gate control signal voltage is below the threshold voltage, the high-voltage NMOS transistor 200 cannot turn off quickly. The parasitic capacitance of the high-voltage NMOS transistor 200 needs to be discharged through the circuitry of the second high-voltage protection diode 306. In this situation, a turn-off delay of the high-voltage NMOS transistor 200 is inevitable.

[0147] In this embodiment, a switch connected in series between the gate and source of the high-voltage NMOS transistor 200 is used to quickly turn off the high-voltage NMOS transistor 200 when it needs to be turned off (so that the parasitic capacitance is discharged quickly).

[0148] When the high-voltage NMOS transistor 200 needs to be turned off, the drive voltage provides a current signal OB. The current OB flows through the third high-voltage protection diode 308, which forms a voltage (its breakdown voltage is typically 6.5–7.5V when there is current flowing from its positive to its negative terminal). This voltage is greater than the gate-source voltage V of the switching NMOS transistor 300. GS The switching NMOS transistor 300 quickly turns on, thus forming a path between the gate and source of the high-voltage NMOS transistor 200. This allows the parasitic capacitance between the gate and source of the high-voltage NMOS transistor 200 to discharge rapidly, thereby causing the high-voltage NMOS transistor 200 to turn off quickly. In this way, the rising P-terminal voltage is not applied to the drain of the first low-voltage NMOS transistor 100, and the first low-voltage NMOS transistor 100 will not be damaged.

[0149] Furthermore, the purpose of connecting a first high-voltage protection diode 102 in series between the source and drain of the first low-voltage NMOS transistor 100 is that when the first low-voltage NMOS transistor 100 is turned off and the high-voltage NMOS transistor 200 is not turned off in time, the high voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. The first high-voltage protection diode 102 will play a protective role here. The high voltage will cause the first high-voltage protection diode 102 to break down in reverse, thereby avoiding damage to the first low-voltage NMOS transistor 100.

[0150] Thus, the on-resistance of the series NMOS transistor from the B-terminal to the P-terminal is:

[0151] R on =R DS,on (100)+R DS,on (200), where R onR is the sum of the on-resistances of the first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200. DS,on (100) is the on-resistance of the first low-voltage NMOS transistor 100, while R DS,on (200) is the on-resistance of the high-voltage NMOS transistor 200.

[0152] Furthermore, since the first low-voltage NMOS transistor 100 is a low-voltage NMOSFET, the physical structure of a low-voltage NMOSFET does not require a low-doped voltage drift region. In other words, for a low-voltage NMOSFET, R... DS,on (100)=R s,metal +R source +R channel +R drain +R d,metal .

[0153] Therefore, for NMOSFETs of the same physical size, R DS,on (100) is much smaller than R DS,on (200), then R on ≈R DS,on (200). Therefore, by using high and low voltage NMOSFETs in series, the on-resistance of the series MOSFETs can be reduced by half, thus reducing the heat loss caused by the on-resistance by half.

[0154] <Third Implementation Method>

[0155] like Figure 9 As shown, this embodiment provides a charge and discharge control device, which may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a drive unit 40, and a charge and discharge control switch 50.

[0156] VDD generator 10 can be connected to the highest voltage of the battery / battery pack in order to generate the voltage VDD required inside the charge / discharge control device based on the highest voltage.

[0157] The voltage acquisition unit 20 can be used to acquire the voltage of a battery / battery pack. In the case of a battery pack, the voltage acquisition unit 20 can be used to acquire the voltage of each battery cell.

[0158] The logic control circuit 30 can generate control signals based on the collected battery / battery pack voltage. Alternatively, the logic control circuit 30 can also generate control signals based on the charging current and discharging current.

[0159] The drive unit 40 provides the signal to drive the charge and discharge control switch 50 according to the control signal of the logic control circuit 30.

[0160] The charge / discharge control switch 50 controls the charging current and discharging current based on the received switch control signal.

[0161] The charge / discharge control switch 50 may include a first low-voltage NMOS transistor 100 used as a discharge switch, a high-voltage NMOS transistor 200 used as a charge switch, and a switching NMOS transistor 300.

[0162] The first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200 can be connected in series on the high-voltage side of the battery / battery pack or in series on the low-voltage side of the battery / battery pack, and there is no limitation on the order in which they are connected in series.

[0163] In this embodiment, the example is that a first low-voltage NMOS transistor 100 and a high-voltage NMOS transistor 200 are connected in series to the low-voltage side of the battery / battery pack, and the example is that the source S of the first low-voltage NMOS transistor 100 is connected to the low-voltage terminal of the battery / battery pack.

[0164] The gate of the first low-voltage NMOS transistor 100 receives a discharge control signal OD from the driving unit 40, and the gate of the high-voltage NMOS transistor 200 receives a charge control signal OC from the driving unit 40. The drain of the first low-voltage NMOS transistor 100 is connected to the drain of the high-voltage NMOS transistor 200. The first low-voltage NMOS transistor 100 has a first parasitic diode D1, and the high-voltage NMOS transistor 200 has a second parasitic diode D2.

[0165] The positive terminal of the first high-voltage protection diode 102 is connected to the source of the first low-voltage NMOS transistor 100, and the negative terminal of the first high-voltage protection diode 102 is connected to the drain of the first low-voltage NMOS transistor 100.

[0166] The drain of the N-channel junction field-effect transistor 400 is connected to the gate of the high-voltage NMOS transistor 200, and the source of the N-channel junction field-effect transistor 400 is connected to the source of the high-voltage NMOS transistor 200. A third resistor 404 is connected between the source and drain of the N-channel junction field-effect transistor 400. The gate of the N-channel junction field-effect transistor 400 is connected to the source of the high-voltage NMOS transistor 200. The N-channel junction field-effect transistor 400 is a low-voltage N-channel junction field-effect transistor.

[0167] The source of the first low-voltage NMOS transistor 100 is connected to the low-voltage terminal B- of the battery / battery pack, while the source of the high-voltage NMOS transistor 200 is connected to the low-voltage terminal P- of an external load or charger. Those skilled in the art will also understand that connecting the source of the high-voltage NMOS transistor 200 to the low-voltage terminal B- of the battery / battery pack, and the source of the first low-voltage NMOS transistor 100 to the low-voltage terminal P- of an external load or charger, can achieve the same function. Similarly, connecting it to the high-voltage side of the battery / battery pack can also achieve the same function.

[0168] According to embodiments of this disclosure, the breakdown voltage of the first low-voltage NMOS transistor 100 can be 1.8 to 7V, i.e., V GS V GD V DS The voltage rating can range from 1.8 to 7V. The voltage rating of a high-voltage NMOS transistor 200 is related to the battery voltage, and is typically 1.5 to 2 times the sum of the voltages of each battery cell. For example, with 16 batteries, each cell typically has a voltage of 4.5V, so the voltage rating needs to be 4.5 * 16 * (1.5 to 2). For instance, its voltage rating should be greater than 108V, i.e., V... GS V GD V DS Greater than 108V. As described above, on-resistance is related to the withstand voltage; therefore, the on-resistance of the first low-voltage NMOS transistor 100 will be significantly less than that of the high-voltage NMOS transistor 200. The withstand voltage of the N-channel junction field-effect transistor 400 can range from 10 to 20V.

[0169] In this design, the first low-voltage NMOS transistor 100 is a low-voltage transistor. Therefore, when the first low-voltage NMOS transistor 100 is turned off, if the high-voltage NMOS transistor 200 cannot be turned off in time (e.g., before or simultaneously with the first low-voltage NMOS transistor 100), the high-voltage NMOS transistor 200 remains on, and the voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. Since the voltage at the P- terminal will rise to the P+ terminal value during the turn-off process of both the first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200, this means the voltage at the P- terminal will increase.

[0170] Since the high-voltage NMOS transistor 200 cannot be turned off in time, the rising voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. Since the first low-voltage NMOS transistor 100 is a low-voltage transistor, if a high voltage is applied to its drain, it will inevitably cause damage to the first low-voltage NMOS transistor 100.

[0171] In this embodiment, by setting a switch (in the form of a switching NMOS transistor 300), the high-voltage NMOS transistor 200 is turned off in a timely manner during the turn-off process (e.g., before or simultaneously with the first low-voltage NMOS transistor 100). This ensures that the rising voltage at the P-terminal is not applied to the drain of the first low-voltage NMOS transistor 100, but rather to the drain of the high-voltage NMOS transistor 200 (because the high-voltage NMOS transistor 200 is a high-voltage type transistor, the high voltage will not cause damage to the high-voltage NMOS transistor 200).

[0172] For a practical high-voltage NMOS transistor 200, there is a parasitic capacitance between its gate G and source S. Due to the presence of this parasitic capacitance, even at V... GS Even when the voltage is below the threshold voltage, the high-voltage NMOS transistor 200 cannot turn off quickly because the discharge of charge from the capacitor takes time. Therefore, even if the gate control signal voltage is below the threshold voltage, the high-voltage NMOS transistor 200 cannot turn off quickly. The parasitic capacitance of the high-voltage NMOS transistor 200 needs to be discharged through a circuit with the third resistor 404. In this situation, a turn-off delay of the high-voltage NMOS transistor 200 is inevitable.

[0173] In this embodiment, a switch connected in series between the gate and source of the high-voltage NMOS transistor 200 is used to quickly turn off the high-voltage NMOS transistor 200 when it needs to be turned off (so that the parasitic capacitance is discharged quickly).

[0174] When the high-voltage NMOS transistor 200 needs to be turned off, the N-channel junction field-effect transistor 400 quickly turns on, forming a path between the gate and source of the high-voltage NMOS transistor 200. This allows the parasitic capacitance between the gate and source of the high-voltage NMOS transistor 200 to discharge rapidly, thus enabling the high-voltage NMOS transistor 200 to turn off quickly. In this way, the rising P-terminal voltage is not applied to the drain of the first low-voltage NMOS transistor 100, and the first low-voltage NMOS transistor 100 is not damaged.

[0175] Furthermore, the purpose of connecting a first high-voltage protection diode 102 in series between the source and drain of the first low-voltage NMOS transistor 100 is that when the first low-voltage NMOS transistor 100 is turned off and the high-voltage NMOS transistor 200 is not turned off in time, the high voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. The first high-voltage protection diode 102 will play a protective role here. The high voltage will cause the first high-voltage protection diode 102 to break down in reverse, thereby avoiding damage to the first low-voltage NMOS transistor 100.

[0176] Thus, the on-resistance of the series NMOS transistor from the B-terminal to the P-terminal is:

[0177] R on =R DS,on (100)+R DS,on (200), where R on R is the sum of the on-resistances of the first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200. DS,on (100) is the on-resistance of the first low-voltage NMOS transistor 100, while R DS,on (200) is the on-resistance of the high-voltage NMOS transistor 200.

[0178] Furthermore, since the first low-voltage NMOS transistor 100 is a low-voltage NMOSFET, the physical structure of a low-voltage NMOSFET does not require a low-doped voltage drift region. In other words, for a low-voltage NMOSFET, R... DS,on (100)=R s,metal +R source +R channel +R drain +R d,metal .

[0179] Therefore, for NMOSFETs of the same physical size, R DS,on (100) is much smaller than R DS,on (200), then R on ≈R DS,on (200). Therefore, by using high and low voltage NMOSFETs in series, the on-resistance of the series MOSFETs can be reduced by half, thus reducing the heat loss caused by the on-resistance by half.

[0180] <Fourth Implementation Method>

[0181] like Figure 10 As shown, this embodiment provides a charge and discharge control device, which may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a drive unit 40, and a charge and discharge control switch 50.

[0182] VDD generator 10 can be connected to the highest voltage of the battery / battery pack in order to generate the voltage VDD required inside the charge / discharge control device based on the highest voltage.

[0183] The voltage acquisition unit 20 can be used to acquire the voltage of a battery / battery pack. In the case of a battery pack, the voltage acquisition unit 20 can be used to acquire the voltage of each battery cell.

[0184] The logic control circuit 30 can generate control signals based on the collected battery / battery pack voltage. Alternatively, the logic control circuit 30 can also generate control signals based on the charging current and discharging current.

[0185] The drive unit 40 provides the signal to drive the charge and discharge control switch 50 according to the control signal of the logic control circuit 30.

[0186] The charge / discharge control switch 50 controls the charging current and discharging current based on the received switch control signal.

[0187] The charge / discharge control switch 50 may include a first low-voltage NMOS transistor 100 used as a discharge switch, a high-voltage NMOS transistor 200 used as a charge switch, and a switching NMOS transistor 300.

[0188] The first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200 can be connected in series on the high-voltage side of the battery / battery pack or in series on the low-voltage side of the battery / battery pack, and there is no limitation on the order in which they are connected in series.

[0189] In this embodiment, the example is that a first low-voltage NMOS transistor 100 and a high-voltage NMOS transistor 200 are connected in series to the low-voltage side of the battery / battery pack, and the example is that the source S of the first low-voltage NMOS transistor 100 is connected to the low-voltage terminal of the battery / battery pack.

[0190] The gate of the first low-voltage NMOS transistor 100 receives a discharge control signal OD from the driving unit 40, and the gate of the high-voltage NMOS transistor 200 receives a charge control signal OC from the driving unit 40. The drain of the first low-voltage NMOS transistor 100 is connected to the drain of the high-voltage NMOS transistor 200. The first low-voltage NMOS transistor 100 has a first parasitic diode D1, and the high-voltage NMOS transistor 200 has a second parasitic diode D2.

[0191] The positive terminal of the first high-voltage protection diode 102 is connected to the source of the first low-voltage NMOS transistor 100, and the negative terminal of the first high-voltage protection diode 102 is connected to the drain of the first low-voltage NMOS transistor 100.

[0192] The drain of the switching NMOS transistor 300 is connected to the gate of the high-voltage NMOS transistor 200, and the source of the switching NMOS transistor 300 is connected to the source of the high-voltage NMOS transistor 200. A fourth high-voltage protection diode 402 is connected between the source and drain of the switching NMOS transistor 300, wherein the positive terminal of the fourth high-voltage protection diode 402 is connected to the source of the high-voltage NMOS transistor 200, and the negative terminal of the fourth high-voltage protection diode 402 is connected to the gate of the high-voltage NMOS transistor 200.

[0193] The drain of the N-channel junction field-effect transistor 400 is connected to the gate of the high-voltage NMOS transistor 200, and the source of the N-channel junction field-effect transistor 400 is connected to the source of the high-voltage NMOS transistor 200. A third resistor 404 is connected between the source and drain of the N-channel junction field-effect transistor 400. The gate of the N-channel junction field-effect transistor 400 is connected to the source of the high-voltage NMOS transistor 200. The N-channel junction field-effect transistor 400 is a low-voltage N-channel junction field-effect transistor.

[0194] The source of the first low-voltage NMOS transistor 100 is connected to the low-voltage terminal B- of the battery / battery pack, while the source of the high-voltage NMOS transistor 200 is connected to the low-voltage terminal P- of an external load or charger. Those skilled in the art will also understand that connecting the source of the high-voltage NMOS transistor 200 to the low-voltage terminal B- of the battery / battery pack, and the source of the first low-voltage NMOS transistor 100 to the low-voltage terminal P- of an external load or charger, can achieve the same function. Similarly, connecting it to the high-voltage side of the battery / battery pack can also achieve the same function.

[0195] According to embodiments of this disclosure, the breakdown voltage of the first low-voltage NMOS transistor 100 can be 1.8 to 7V, i.e., V GS V GD V DS The voltage rating can range from 1.8 to 7V. The voltage rating of a high-voltage NMOS transistor 200 is related to the battery voltage, and is typically 1.5 to 2 times the sum of the voltages of each battery cell. For example, with 16 batteries, each cell typically has a voltage of 4.5V, so the voltage rating needs to be 4.5 * 16 * (1.5 to 2). For instance, its voltage rating should be greater than 108V, i.e., V... GS V GD V DS Greater than 108V. As described above, on-resistance is related to the withstand voltage; therefore, the on-resistance of the first low-voltage NMOS transistor 100 will be significantly less than that of the high-voltage NMOS transistor 200. The withstand voltage of the N-channel junction field-effect transistor 400 can range from 10 to 20V.

[0196] In this design, the first low-voltage NMOS transistor 100 is a low-voltage transistor. Therefore, when the first low-voltage NMOS transistor 100 is turned off, if the high-voltage NMOS transistor 200 cannot be turned off in time (e.g., before or simultaneously with the first low-voltage NMOS transistor 100), the high-voltage NMOS transistor 200 remains on, and the voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. Since the voltage at the P- terminal will rise to the P+ terminal value during the turn-off process of both the first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200, this means the voltage at the P- terminal will increase.

[0197] Since the high-voltage NMOS transistor 200 cannot be turned off in time, the rising voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. Since the first low-voltage NMOS transistor 100 is a low-voltage transistor, if a high voltage is applied to its drain, it will inevitably cause damage to the first low-voltage NMOS transistor 100.

[0198] In this embodiment, by setting a switch (in the form of a switching NMOS transistor 300), the high-voltage NMOS transistor 200 is turned off in a timely manner during the turn-off process (e.g., before or simultaneously with the first low-voltage NMOS transistor 100). This ensures that the rising voltage at the P-terminal is not applied to the drain of the first low-voltage NMOS transistor 100, but rather to the drain of the high-voltage NMOS transistor 200 (because the high-voltage NMOS transistor 200 is a high-voltage type transistor, the high voltage will not cause damage to the high-voltage NMOS transistor 200).

[0199] For a practical high-voltage NMOS transistor 200, there is a parasitic capacitance between its gate G and source S. Due to the presence of this parasitic capacitance, even at V... GS Even when the voltage is below the threshold voltage, the high-voltage NMOS transistor 200 cannot turn off quickly because the discharge of charge from the capacitor takes time. Therefore, even if the gate control signal voltage is below the threshold voltage, the high-voltage NMOS transistor 200 cannot turn off quickly. The parasitic capacitance of the high-voltage NMOS transistor 200 needs to be discharged through the circuit of the fourth high-voltage protection diode 402. In this situation, a turn-off delay of the high-voltage NMOS transistor 200 is inevitable.

[0200] In this embodiment, a switch connected in series between the gate and source of the high-voltage NMOS transistor 200 is used to quickly turn off the high-voltage NMOS transistor 200 when it needs to be turned off (so that the parasitic capacitance is discharged quickly).

[0201] When the high-voltage NMOS transistor 200 needs to be turned off, the N-channel junction field-effect transistor 400 quickly turns on, forming a path between the gate and source of the high-voltage NMOS transistor 200. This allows the parasitic capacitance between the gate and source of the high-voltage NMOS transistor 200 to discharge rapidly, thus enabling the high-voltage NMOS transistor 200 to turn off quickly. In this way, the rising P-terminal voltage is not applied to the drain of the first low-voltage NMOS transistor 100, and the first low-voltage NMOS transistor 100 is not damaged.

[0202] Furthermore, the purpose of connecting a first high-voltage protection diode 102 in series between the source and drain of the first low-voltage NMOS transistor 100 is that when the first low-voltage NMOS transistor 100 is turned off and the high-voltage NMOS transistor 200 is not turned off in time, the high voltage at the P- terminal will be applied to the drain of the first low-voltage NMOS transistor 100. The first high-voltage protection diode 102 will play a protective role here. The high voltage will cause the first high-voltage protection diode 102 to break down in reverse, thereby avoiding damage to the first low-voltage NMOS transistor 100.

[0203] Thus, the on-resistance of the series NMOS transistor from the B-terminal to the P-terminal is:

[0204] R on =R DS,on (100)+R DS,on (200), where R on R is the sum of the on-resistances of the first low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200. DS,on (100) is the on-resistance of the first low-voltage NMOS transistor 100, while R DS,on (200) is the on-resistance of the high-voltage NMOS transistor 200.

[0205] Furthermore, since the first low-voltage NMOS transistor 100 is a low-voltage NMOSFET, the physical structure of a low-voltage NMOSFET does not require a low-doped voltage drift region. In other words, for a low-voltage NMOSFET, R... DS,on (100)=R s,metal +R source +R channel +R drain +R d,metal .

[0206] Therefore, for NMOSFETs of the same physical size, R DS,on (100) is much smaller than R DS,on (200), then R on ≈R DS,on (200). Therefore, by using high and low voltage NMOSFETs in series, the on-resistance of the series MOSFETs can be reduced by half, thus reducing the heat loss caused by the on-resistance by half.

[0207] According to another embodiment of this disclosure, a chip is provided that integrates the charge / discharge control switch circuit described above, for example in... Figure 11 The portion shown by reference numeral 50 in the accompanying drawing. This chip can also integrate the charge / discharge control device described above, for example in... Figure 1 The portion shown in the accompanying drawing is marked with reference numeral 1000.

[0208] According to another embodiment of the present disclosure, the battery management system includes the charge / discharge control switch circuit as described above, or includes the charge / discharge control device as described above.

[0209] like Figure 12 As shown, this disclosure also provides an electrical device that may include a battery / battery pack for powering other components in the device; the device may also include the charge / discharge control switch circuit, charge / discharge control device, or chip as described above.

[0210] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0211] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0212] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A charge-discharge switching circuit for controlling a charge current and / or a discharge current of a battery / batteries, characterized by, comprises: a low-voltage MOS transistor, a gate of which receives a first control signal to be turned on and off, a source or a drain of which is connected to a battery side; a high-voltage MOS transistor, a gate of which receives a second control signal to be turned on and off, a source or a drain of which is connected to an external load or an external charger side, a drain or a source of which is connected to a drain or a source of the low-voltage MOS transistor; a switch, one end of which is connected to the gate of the high-voltage MOS transistor, the other end of which is connected to the source of the high-voltage MOS transistor, one end of which is further connected to one end of a first resistor or a negative terminal of a second high-voltage protection diode, the other end of which is further connected to the other end of the first resistor or a positive terminal of the second high-voltage protection diode, when the low-voltage MOS transistor is turned off, the switch is turned on to make the high-voltage MOS transistor turned off before or at the same time when the low-voltage MOS transistor is turned off, thereby making the parasitic capacitance of the high-voltage MOS transistor quickly discharged through the turned-on switch; a high-voltage protection diode is connected between the source and the drain of the low-voltage MOS transistor; the on-resistance of the low-voltage MOS transistor is smaller than the on-resistance of the high-voltage MOS transistor; the charge-discharge switching circuit further comprises a second resistor, the switch is a switch NMOS transistor, one end of the second resistor is connected to the gate of the switch NMOS transistor and the other end of the second resistor is connected to the source of the switch NMOS transistor, the gate of the switch NMOS transistor is connected to a current signal, the drain of the switch NMOS transistor is connected to the gate of the high-voltage MOS transistor, and the source of the switch NMOS transistor is connected to the source of the high-voltage MOS transistor; when the high-voltage MOS transistor needs to be turned off, the current signal is provided, and the voltage formed on the second resistor makes the high-voltage MOS transistor quickly turned off.

2. The charge and discharge switching circuit according to claim 1, wherein the low-voltage MOS transistor is a discharge MOS transistor and the first control signal is a discharge control signal, the high-voltage MOS transistor is a charge MOS transistor and the second control signal is a charge control signal, the source of the low-voltage MOS transistor is connected to the battery side, the source of the high-voltage MOS transistor is connected to the external load or the external charger side, and the drain of the low-voltage MOS transistor is connected to the drain of the high-voltage MOS transistor.

3. The charge-discharge switching circuit according to claim 1, wherein the battery side is a low-voltage side of a battery, and the external load or the external charger side is a low-voltage side of the external load or a low-voltage side of the external charger. ​ The battery side is the high-voltage side of the battery, and the external load or external charger side is the high-voltage side of the external load or the high-voltage side of the external charger.

4. The charge and discharge switching circuit according to claim 1, wherein The low-voltage MOS transistor and the high-voltage MOS transistor are NMOS transistors.

5. The charge and discharge switching circuit according to any one of claims 1 to 4, wherein A second high-voltage protection diode is further included, a gate of the NMOS transistor for switching is connected to a positive terminal of the second high-voltage protection diode, a source of the NMOS transistor for switching is connected to a negative terminal of the second high-voltage protection diode, a gate of the high-voltage MOS transistor is connected to a drain of the NMOS transistor for switching, and a source of the high-voltage MOS transistor is connected to the source of the NMOS transistor for switching.

6. The charge and discharge switching circuit according to claim 5, wherein When the high-voltage MOS transistor needs to be turned off, the current signal is provided, and a voltage formed on the second high-voltage protection diode makes the high-voltage MOS transistor be quickly turned off.

7. The charge and discharge switching circuit according to claim 5, wherein A first high-voltage protection diode is further included, a gate of the high-voltage MOS transistor is connected to a positive terminal of the first high-voltage protection diode, and a source of the high-voltage MOS transistor is connected to a negative terminal of the first high-voltage protection diode.

8. The charge and discharge switching circuit according to any one of claims 1 to 4, wherein The switch is an N-channel junction field effect transistor, a gate of the N-channel junction field effect transistor is connected to a source of the high-voltage MOS transistor, a drain of the N-channel junction field effect transistor is connected to a gate of the high-voltage MOS transistor, and a source of the N-channel junction field effect transistor is connected to a source of the high-voltage MOS transistor.

9. The charge and discharge switching circuit according to claim 8, wherein When the high-voltage MOS transistor needs to be turned off, the N-channel junction field effect transistor is quickly turned off so that the high-voltage MOS transistor is quickly turned off.

10. The charge and discharge switching circuit according to claim 8, wherein A first high-voltage protection diode is further included, a gate of the high-voltage MOS transistor is connected to a positive terminal of the first high-voltage protection diode, and a source of the high-voltage MOS transistor is connected to a negative terminal of the first high-voltage protection diode.

11. A charge / discharge control device for controlling a charge current and / or a discharge current of a battery / battery pack, characterized by, It comprises: The charge-discharge switching circuit according to any one of claims 1 to 10; and A driving circuit for providing the first control signal and the second control signal.

12. The charge and discharge control device according to Claim 11, wherein It further comprises: A voltage acquisition unit for acquiring the voltage of the battery / battery pack and / or a detection circuit for detecting the charging current and / or the discharging current; and A control logic circuit for providing a control signal to the driving circuit based on a signal from the voltage acquisition unit and / or the detection circuit.

13. A chip, characterized by The chip is integrated with the charge-discharge switching circuit according to any one of claims 1 to 10 or the charge-discharge control device according to claim 11 or 12.

14. A battery management system, characterized by, It comprises the charge-discharge switching circuit according to any one of claims 1 to 10 or the charge-discharge control device according to claim 11 or 12 or the chip according to claim 13.

15. An electrical device, characterized by It comprises: A battery / battery pack for powering other components in the electrical device; and The charge-discharge switching circuit according to any one of claims 1 to 10, or the charge-discharge control device according to claim 11 or 12, or the chip according to claim 13, or the battery management system according to claim 14.

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