Level shifting devices and methods

Abstract

Embodiments of this disclosure relate to level shifting devices and methods. An output potential level of two first levels is delivered based on an input level of two second levels. The output potential level is delivered at a first node that electrically connects a first transistor and a second transistor together between two second nodes where the first level is applied. A first DC voltage defining an upper limit of the control voltage of the first transistor is delivered by a first voltage generator powered by one of the second nodes. A second DC voltage defining an upper limit of the control voltage of the second transistor is delivered by a second voltage generator controlled by a value representing the first voltage and powered between the second nodes.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. 2008826, filed on August 31, 2020, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic devices, such as integrated circuits, and more particularly to logic level shifting or logic level conversion devices (level shifters). Background Technology

[0004] A logic level shifter is a circuit provided to receive logic input signals and deliver logic output signals representing those input signals. The logic output signals have potential levels that may differ from the potential levels of the input signals. The potential levels of a logic signal correspond to its respective logic state, such as 0 and 1 or low and high. In other words, the level of each logic signal in the input and output logic signals falls between two potential levels.

[0005] For one of the input levels, the level shifter sets the output potential to one of the output levels; for the other input level, the level shifter sets the output potential to the other output level. In other words, the level shifter selects the output potential level from two output levels different from the two input levels based on the level of the logic input signal.

[0006] There is a need to improve known logic level shifters and known logic level shifting methods. Summary of the Invention

[0007] The embodiments overcome all or some of the drawbacks of known logic level shifters.

[0008] The embodiments overcome all or part of the drawbacks of known logic level shifting methods.

[0009] An embodiment provides a method for delivering an output potential level of two first levels based on an input level of two second levels. The method includes: delivering an output level via a first node, the first node electrically connecting a first transistor and a second transistor in series between two second nodes to which the first level is applied; delivering a first DC voltage that defines an upper limit of a control voltage for the first transistor via a first voltage generator powered by one of the second nodes; and delivering a second DC voltage that defines an upper limit of a control voltage for the second transistor via a second voltage generator, the second voltage generator being controlled by a value representing the first voltage and powered between the second nodes.

[0010] An embodiment provides an apparatus configured to deliver an output potential level of one of two first levels based on an input level of one of two second levels. The apparatus includes: a first transistor and a second transistor connected together via a first output level delivery node and electrically connected in series between second nodes on which the first level is applied; a first voltage generator powered by one of the second nodes and configured to deliver a first DC voltage that defines an upper limit of a control voltage for the first transistor; and a second voltage generator controlled by a value representing the first voltage and configured to deliver a second DC voltage that defines an upper limit of a control voltage for the second transistor.

[0011] According to an embodiment: a first signal representing the desired state of a second transistor is referenced to the potential of one of the second nodes; and preferably, the first signal is generated from a second signal representing the desired state of a first transistor and is referenced to a reference potential of a second level.

[0012] According to an embodiment: the first generator includes a third transistor configured to conduct a first current for powering the first generator; and the second generator includes a fourth transistor forming a current mirror with the third transistor and configured to conduct a second current for powering the second generator.

[0013] According to an embodiment: a first generator includes a first element electrically connected in series with a third transistor between a second node in the second node and a third node for delivering a first voltage, the first element having a predetermined voltage drop when a first current flows through it, and the first element preferably including a diode; and a second generator includes a second element having a predetermined voltage drop when a second current flows through it, the second generator coupling a fourth node to another second node in the second node, and preferably including a fifth transistor and a diode electrically connected in series.

[0014] According to an embodiment: one or more transistor control circuits include, or each includes: a first additional transistor, a second additional transistor, and a third additional transistor, electrically connected in series in this order between one of the second nodes and an additional node applying a second level, the second additional transistor having its control terminal coupled to a node for delivering a first voltage; a connection node, located between the first and second additional transistors, coupled to a control terminal of a transistor controlled by a first circuit; and / or one or more second transistor control circuits include, or each includes: a fourth additional transistor, a fifth additional transistor, and a sixth additional transistor, electrically connected in this order between one of the second nodes and another second node, the fifth additional transistor having its control terminal coupled to a node for delivering a second voltage; and a connection node, located between the fifth and sixth additional transistors, coupled to a control terminal of a transistor controlled by a second circuit.

[0015] According to an embodiment, the circuit for controlling the first transistor is made of a first circuit or a first circuit of the first circuit, and / or the circuit for controlling the second transistor is formed of a second circuit or a second circuit of the second circuit.

[0016] According to an embodiment, the first signal controls a fourth additional transistor in the circuit used to control the second transistor.

[0017] According to an embodiment, the first signal is generated by another first signal in a first circuit, which has a third additional transistor controlled by a second signal.

[0018] According to an embodiment: a third additional transistor of the circuit for controlling the first transistor is controlled by a signal that is the inverted phase of the second signal; and / or a fourth additional transistor of the circuit for controlling the second transistor is controlled by a signal that is the inverted phase of the first signal.

[0019] According to an embodiment: the inverted signal, which is the first signal, is delivered by another first circuit in the first circuit, which controls its third additional transistor with the inverted signal, which is the second signal, and controls its first additional transistor with the other circuit or the first circuit; and the first additional transistor of the other first circuit in the first circuit is controlled by the yet another first circuit in the first circuit.

[0020] According to an embodiment, the fourth additional transistor of another second circuit in the second circuit is controlled by an inverted signal as the first signal, and the sixth transistor of the control circuit of the second switch is controlled by another second circuit in the second circuit.

[0021] According to an embodiment: another circuit in the second circuit controls its fourth additional transistor with a first signal, and controls its sixth additional transistor with another second circuit in the second circuit; and the sixth additional transistor of another second circuit in the second circuit is controlled by yet another second circuit in the second circuit.

[0022] According to an embodiment, the value of the first DC voltage is selected between a value lower than a voltage threshold for controlling the first transistor and a value higher than a voltage threshold, depending on the level of the enable / disable logic signal.

[0023] According to an embodiment, the output potential level control is preferably performed using an OLED type display screen. Attached Figure Description

[0024] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustration rather than limitation, with reference to the accompanying drawings, in which:

[0025] Figure 1 An example of a device that applies the embodiments described herein is illustrated schematically;

[0026] Figure 2 An embodiment of a level shifter is schematically illustrated;

[0027] Figure 3 schematically shown Figure 2 An example of a level shifter circuit;

[0028] Figure 4 Another embodiment of a level shifter is shown in part and schematically.

[0029] Figure 5 schematically shown Figure 4 Example of a shifter circuit; and

[0030] Figure 6 An embodiment of a device including a level shifter is illustrated schematically. Detailed Implementation

[0031] In the various figures, similar features have been designated by similar reference numerals. Specifically, common structural and / or functional features in the various embodiments may have the same reference numerals and may be arranged with the same structure, dimensions, and material properties.

[0032] For clarity, only steps and components useful for understanding the embodiments described herein are illustrated and described in detail. Specifically, the display screen, display screen control circuitry, digital module for generating display screen control signals, and power supply module are not described in detail, and the embodiments are compatible with such common components.

[0033] Unless otherwise indicated, when referring to two elements connected together, it means that there is no direct connection of any intermediate element other than a conductor; and when referring to two elements coupled together, it means that the two elements can be connected or that they can be coupled via one or more other elements.

[0034] In the following disclosure, unless otherwise specified, references to absolute positional modifiers (such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc.) or relative positional modifiers (such as the terms “above,” “below,” “higher,” “lower,” etc.) or orientation modifiers (such as “horizontal,” “vertical,” etc.) refer to the orientation shown in the accompanying drawings.

[0035] Unless otherwise specified, the expressions “about,” “roughly,” “substantially,” and “approximately” indicate within 10%, and preferably within 5%.

[0036] Unless otherwise specified, ordinal numbers (such as "first," "second," etc.) are used only to distinguish elements. Specifically, these adjectives do not limit the described devices and methods to a specific order of these elements.

[0037] Figure 1 An example of a device 100 applying the described embodiments is shown schematically.

[0038] In this example, device 100 is provided to display an image. Device 100 can be used in a motor vehicle to display various data, typically for the driver. A motor vehicle may include multiple devices, such as device 100.

[0039] Device 100 includes a display screen 110 for displaying images. Display screen 110 typically includes a pixel array 112, such as an organic light-emitting diode (OLED) array. For example, array 112 is produced by a printing method. As an example, array 112 has a resolution referred to as "4K resolution" or higher, i.e., 3,840 or more by 2,160 or more pixels.

[0040] Display screen 110 also includes control circuits 114 and 116 (DRV), which are typically configured to control the rows and columns of array 112, respectively. In the example shown, circuit 116 controls the scanning of rows of array 112.

[0041] Device 100 also includes a digital unit 120 (PU), which includes, for example, a sequential digital data processing unit, such as a microprocessor or microcontroller, and, for example, a memory containing programs. Digital unit 120 is configured (specifically programmed) to provide control circuitry 114 with control signals SI0 to be applied to display screen 110 and control signals SIi (SI1, SI2) for control circuitry 116. The number of signals SIi is equal to 2 in the illustrated example, and is typically equal to 4 or 8 in other examples. The control signals SIi may have a frequency of approximately 133 kHz.

[0042] Device 100 also includes a power supply module 130 (PWR). Power supply module 130 is powered by voltage VBAT, typically delivered by a battery (not shown). Power supply module 130 delivers a voltage for powering digital unit 120 between node VCC and node GND, to which a reference potential (such as ground) is applied. In other words, power supply module 130 applies a power potential to nodes VCC and GND, to which digital unit 120 is coupled (preferably connected).

[0043] Each control signal SIi takes a level between two potentials corresponding to the respective node VCC and GND. In other words, the potential level taken by each control signal SIi is equal to or substantially equal to the potentials of node VCC and GND outside the rising or falling edge of the signal. As an example, the voltage between node VCC and node GND is equal to or approximately 3.3V.

[0044] The power module 130 also delivers potentials on nodes VGH and VGL for powering the display screen 110. The potentials of nodes VGH and VGL differ from the potentials of the corresponding nodes VCC and GND. Typically, at least the potential of node VGH is greater than the potential of node VCC, for example, the potential of node VGH is greater than 20V (compared to the reference potential of node GND).

[0045] Device 100 also includes a group 140 or block of level shifters for receiving signals SIi. Group 140 is coupled (preferably connected) to control circuitry 116. More specifically, for each signal SIi in the signal SIi group, group 140 includes level shifters 142-i (142-1, 142-2, SHIFT) that couple control circuitry 116 to the output of digital unit 120, on which digital unit 120 delivers signal SIi. Each level shifter 142-i is coupled (preferably connected) to four nodes GND, VCC, VGH, and VGL.

[0046] For each signal SIi, level shifter 142-i provides the control circuit 116 with an output potential level corresponding to one of two levels of the potentials of nodes VGH and VGL, based on the level of the input signal SIi. In other words, each level shifter 142-i converts the relevant signal SIi into a signal SOi (SO1, SO2), taking the level of that signal between the levels of nodes VGH and VGL. The signal SIi thus has a level compatible with the level applied to the display screen 110 by the control circuit 116.

[0047] Although specific examples of level shifter applications have been described above, these examples are not limiting. The described embodiments are compatible with any application where logic signals are transmitted between two circuits using different corresponding potential levels.

[0048] Figure 2 An embodiment of a level shifter 200 (i.e., a logic level shifting device) is schematically illustrated. Figure 1 Each level shifter 142-i of device 100 can be replaced by level shifter 200. Level shifter 200 can receive... Figure 1 The device 100 has one input signal SIi to the signal SIi, and the delivery can be... Figure 1 The output signal SOi of device 100 is one of the output signals SOi.

[0049] Level shifter 200 includes two transistors 201 and 202 electrically connected in series between nodes VGH and VGL. The output signal SO is delivered by level shifter 200 at the connection node 210 between the two transistors 201 and 202.

[0050] Preferably, transistors 201 and 202 are field-effect transistors having corresponding P-type and N-type channels, with the P-channel transistor 201 located on one side of node VGH. As a variation, other types of transistors or field-effect transistors with other N or P conductivity types of channels are possible.

[0051] Level shifter 200 includes circuitry 220 for controlling the gates of transistors 201 and 202. More specifically, circuitry 220 is configured to apply inverted control signals to the respective transistors 201 and 202 at outputs 251 and 261 of circuitry 220. The inverted control signals mean that the control signals applied to transistors 201 and 202 cause the other transistor to turn off when one of transistors 201 and 202 is turned on. Transistors 201 and 202 can also be turned off simultaneously. When transistor 201 is turned on, the output level of level shifter 200 corresponds to the potential of node VGH. When transistor 202 is turned on, the output level of level shifter 200 corresponds to the potential of node VGL.

[0052] Circuit 220 receives a logic signal SGND representing the desired output level of level shifter 200. Therefore, the logic signal SGND represents the desired state of transistors 201 and / or 202. The logic signal SGND is referenced to the potential of node GND. Using a potential as a reference for the logic signal means that each of the two logic levels of the signal has a constant difference from this potential, where one of the differences can be 0. In the event of a change in this potential, the level of the logic signal therefore changes in the same way. Therefore, this potential acts as a reference potential for the level of the logic signal.

[0053] Level shifter 200 may include logic circuitry 225 (CTRL_IN) powered between node VCC and node GND. Logic circuitry 225 receives the input signal SI from level shifter 200. Logic circuitry 225 outputs signal SGND from signal SI. Logic circuitry 225 may include an inverter or buffer that receives signal SI and outputs signal SGND.

[0054] In the illustrated example, a portion 230 of circuit 220 includes a diode 236 and a transistor 233, preferably a P-channel field-effect transistor, electrically connected in series between node VGH and node 235. Diode 236 may include one of a field-effect transistor assembled from one or more diodes and / or multiple diodes connected in series and / or parallel. Transistor 233 is a diode assembly, i.e., it has drain and gate terminals coupled together (preferably connected together). Transistor 233 has a source terminal (S) facing node VGH. The cathode of diode 236 faces node VGH. Node 235 is coupled (preferably connected) to current source 232. For example, current source 232 couples circuit 220 to node GND.

[0055] In operation, current source 232 samples the current IB1 flowing through section 230 from node VGH. Section 230 then delivers a DC voltage V1 between node VGH and node 235. In other words, section 230 forms a voltage generator. As an example, the DC voltage V1 is in the range of 4.8V to 4.9V. As an example, the value of current IB1 is in the range of 1μA to 10μA, for example, equal to 2μA or approximately 2μA.

[0056] Preferably, the capacitor element CV1 is provided between node VGH and node 235, that is, in parallel with the series connection of transistor 233 and diode 236.

[0057] The examples shown are not limiting. In variations, diode 236 can be replaced by any element that has a predetermined voltage drop when current (such as current IB1) ​​flows through it. Such an element can include one or more components connected in series and / or parallel, such as resistors, transistors, diodes, or Zener diodes. Voltage generator 230 can also be replaced by any generator capable of generating voltage V1 between node VGH and node 235 and powered by current (such as current IB1) ​​supplied by node VGH. Preferably, such a generator is powered between node VGH and node GND, i.e., the current supplied by node VGH reaches node GND.

[0058] Circuit 220 includes a module 250 (CTRL_HS) for controlling transistor 201. Module 250 is therefore coupled (preferably connected) to the control terminal of transistor 201 (the gate terminal in the example of a field-effect transistor). Module 250 receives the signal SGND. Module 250 is coupled (preferably connected) to node GND. Module 250 is also coupled (preferably connected) to nodes VGH and 235.

[0059] In operation, module 250 receives voltage V1 and delivers a control voltage VGSP (not shown) to transistor 201 at node 251. Preferably, the control voltage VGSP of transistor 201 takes two values ​​to set transistor 201 to the corresponding on and off states, depending on the desired state of the transistor.

[0060] Module 250 is configured such that the control voltage VGSP of transistor 201 is always less than or equal to voltage V1 in absolute value. In other words, voltage V1 forms the upper limit of the control voltage VGSP of transistor 201. In other words, voltage V1 forms the upper limit of the absolute value |VGSP| of the control voltage VGSP.

[0061] Preferably, transistor 201 has a source terminal (S) located on one side of node VGH. A control voltage VGSP is then applied between the source terminal and the gate terminal of transistor 201. The turn-off value taken by the control voltage can be close to 0, i.e., module 250 applies a potential to the gate terminal of transistor 201 that is substantially equal to the potential of node VGH. The turn-on value taken by the control voltage can be equal to or less than a predetermined value of voltage V1, for example, having a constant difference from voltage V1.

[0062] It is desirable to limit the control voltage between the gate and source of transistor 201 to avoid damaging the transistor. For example, applying a control voltage close to the voltage between node VGH and node GND to transistor 201 may damage the transistor.

[0063] Preferably, a portion 240 of circuit 220 includes a diode 246 and a transistor 244, preferably a P-channel field-effect transistor, connected in series between node VGH and node 245. Transistor 244 is preferably assembled with transistor 233 as a current mirror and has a source terminal (S) located on one side of node VGH. Diode 246 has its cathode facing node VGH.

[0064] Preferably, transistor 244 has its control terminal coupled (preferably connected) to the control terminal and drain terminal of transistor 233 of voltage generator 230.

[0065] More preferably: diodes 236 and 246 are identical within manufacturing tolerances; diodes 236 and 246 are located between node VGH and the source terminals (S) of the corresponding transistors 233 and 244; within manufacturing tolerances, transistors 233 and 244 have a predetermined size ratio relative to each other, or more preferably, are identical.

[0066] In operation, current IB1 flows through transistor 233. Transistor 244 conducts current IB2 supplied by node VGH. The value of current IB2 has a ratio to the value of current IB1 that is equal to or substantially equal to the size ratio between transistor 244 and transistor 233. In other words, transistors 233 and 244 form a current mirror. The values ​​of currents IB1 and IB2 are preferably equal or substantially equal.

[0067] The examples of current mirrors shown are not limiting. A current mirror can be any current mirror capable of supplying current IB2 from current IB1. In another example, transistors 233 and 244 can be directly connected to node VGH. In yet another example, diodes 236 and 246 are replaced with two corresponding components capable of causing the same voltage drop when the corresponding currents IB1 and IB2 pass through.

[0068] Part 240 also includes a component 247 coupling node 245 to VGL. Component 247 includes a diode 248 electrically connected in series between node 245 and node VGL, and a diode-assembled transistor 249. Transistor 249 is preferably an N-channel field-effect transistor. Transistor 249 then has its source facing node VGL. Diode 248 has its cathode facing node VGL.

[0069] In operation, current IB2 flows through component 247. Component 247 causes a predetermined voltage drop when current IB2 flows. This voltage drop forms a DC voltage V2. In variations, component 247 can be replaced with any element that has a predetermined voltage drop when current (such as current IB2) flows.

[0070] DC voltage V2 is delivered at nodes 245 and VGL based on the current IB2 flowing between nodes VGH and VGL. In other words, section 240 forms a generator for voltage V2 powered by current IB2 between nodes VGH and VGL. As an example, DC voltage V2 is equal to or substantially equal to voltage V1.

[0071] Preferably, the capacitor element CV2 is disposed between node VGL and node 245, i.e., in parallel with component 247.

[0072] In the example shown, voltage generator 240 receives voltage V1 between node VGH and the control terminal of transistor 244. Therefore, voltage V1 controls voltage generator 240. This example is not limiting; voltage generator 240 can be replaced with any generator that: is capable of generating voltage V2 between node 245 and node VGL; is powered between node VGH and node VGL; and is controlled by voltage V1 or by any value representing voltage V1 (such as, for example, the value of current IB1).

[0073] Circuit 220 also includes a module 260 (CTRL_LS) for controlling transistor 202. Module 260 is coupled (preferably connected) to node 245 and VGL. In operation, module 260 receives voltage V2 and delivers a control voltage VGSN (not shown) to transistor 202 at node 261. Module 260 is configured such that voltage V2 forms an upper limit of the control voltage VGSN of transistor 202.

[0074] Preferably, transistor 202 has a source terminal (S) located on one side of node VGL. A control voltage VGSN is then applied between the source terminal and the gate terminal of transistor 202. The turn-off value taken by the control voltage can be close to 0, i.e., module 260 applies a potential to the gate terminal of transistor 201 that is substantially equal to the potential of node VGL. The turn-on value taken by the control voltage can be equal to or less than a predetermined value of voltage V2, for example, having a constant difference from voltage V2. This avoids the risk of damaging transistor 202.

[0075] Instead of generator 240, it is conceivable to provide another generator to supply voltage V2 between node VGL and node GND. For example, if the potential of node VGL is greater than the potential of node GND, this other generator could be designed to resemble voltage generator 230. If the potential of node VGL is less than the potential of node GND, this other generator could be provided, differing from voltage generator 230 in that the N and P conduction types (specifically, the cathode and anode of a diode) are interchanged.

[0076] In comparison, the fact that a generator 240, powered between nodes VGH and VGL and controlled by a voltage representing voltage V1, allows for the delivery of a DC voltage V2 to limit the control voltage VGSN of transistor 202 using a similar generator 240 when the potential of node VGL is greater than, substantially equal to, or less than the potential of node GND. Specifically, the same level shifter 200 can be used for the potential value of node VGL, which can be positive or negative (relative to the reference potential of node GND). As an example, the potential of node VGL can take any value between -10V and 13V. Furthermore, this allows the potential of node VGL to change during operation, and specifically, to change its sign, which is desirable in some applications (specifically, as shown in the image).

[0077] Module 260 receives a signal SVGH representing the desired state of transistor 202. The signal SVGH is preferably referenced to a potential relative to node VGH. Module 260 is then coupled (preferably connected) to node VGH. Preferably, the signal SVGH is delivered by module 250, more preferably from signal SGND. As a variation, circuitry 220 may be provided to deliver the signal SVGH, which is preferably referenced to a potential relative to node VGH or VGL.

[0078] Figure 3 schematically shown Figure 2 An embodiment of circuit 220 for level shifter 200. More specifically, this example includes the above-described circuitry. Figure 2The components described. These components will not be described further. Specific examples of modules 250 and 260 of circuit 220 are detailed. Outputs 251 and 261 of circuit 220 are coupled (preferably connected) to corresponding transistors 201 and 202. Figure 2 ) control terminals.

[0079] Module 250 includes circuits 310, 330, and 340. Each circuit 310, 330, and 340 includes the following components electrically connected in series in this order between node VGH and node GND: first corresponding transistors 311, 331, and 341; second corresponding transistors 312, 332, and 342; and third corresponding transistors 313, 333, and 343. The second transistors 312, 332, and 342 each couple (preferably connect) a control terminal to node 235 for delivering DC voltage V1.

[0080] Preferably, the first transistors 311, 331, 341 and the second transistors 312, 332, 342 are P-channel field-effect transistors and have their source terminals located on one side of node VGH. Preferably, the third transistors 313, 333 and 343 are N-channel field-effect transistors and have their source terminals located on one side of node GND.

[0081] Each of circuits 310, 330, and 340 generates a transistor control signal; in other words, it forms a transistor control circuit. Each of circuits 310, 330, and 340 has a transistor control output formed by a connection node between a first transistor (311, 331, and 341, respectively) and a second transistor (312, 332, and 342, respectively).

[0082] More specifically, circuit 310 controls transistor 201 ( Figure 2 Circuit 330 controls transistors 311 and 341, and circuit 340 controls transistor 331.

[0083] Preferably, each of circuits 310, 330, and 340 includes a Zener diode (318, 338, and 348, respectively) and a resistive element (such as a resistor, 319, 339, and 349, respectively) connected in series between its transistor control output and node VGH. Zener diodes 318, 338, and 348 have their cathodes facing node VGH.

[0084] In each of circuits 310, 330, and 340, the first transistor (311, 331, and 341, respectively) and the third transistor (313, 333, and 343, respectively) are inverted. Circuits 310, 330, and 340 are powered between node VGH and node GND; in other words, the charging / discharging current of the gates of the transistors controlled by these circuits is provided by nodes VGH and GND.

[0085] When the third transistors (313, 333, and 343, respectively) are in the ON state, the second transistors (312, 332, and 342, respectively) maintain the potential of the connection node between the first transistors (311, 331, and 341, respectively) and the second transistors (312, 332, and 342, respectively) at a value greater than the potential of node 235, which is, for example, equal to the potential of node 235 plus the threshold turn-on voltage of the second transistors (312, 332, and 342, respectively). Therefore, the transistor control voltage delivered by each of the circuits 310, 330, and 340 is limited by voltage V1.

[0086] In each of circuits 310, 330, and 340, Zener diodes 318, 338, and 348 are used to prevent the control provided by the circuitry when the first transistor (311, 331, and 341, respectively) and the second transistor (312, 332, and 342, respectively) are in the off state from being floating. The values ​​of Zener diodes 318, 338, and 348 are selected such that when the Zener diodes are turned on, the transistor control voltage delivered by the associated circuits 310, 330, or 340 is sufficient to turn on the associated controlled transistor (i.e., greater than the transistor's control voltage threshold) and limits that control voltage to a value less than the control voltage threshold allowed by the controlled transistor (i.e., clamps it) without degradation. The examples shown are not limiting, and Zener diodes 318, 338, and 348, as well as resistors 319, 339, and 349, can be omitted or replaced with any element capable of preventing the outputs of circuits 310, 330, and 340 from floating.

[0087] The third transistor 333 in circuit 330 is controlled by signal SGND. The third transistor 313 in circuit 310 is controlled by signal SGND1.

[0088] Signal SGND1 is the inverse of signal SGND and is referenced to the potential of node GND. Signal SGND1 can be derived from... Figure 3 The inverter, not shown, is delivered with reference to the potential of node GND and the received signal SGND. The third transistor 343 of circuit 340 is controlled by signal SGND1.

[0089] In the example shown, circuits 330 and 340 control the state of the first transistor 311 of circuit 301 to control transistor 201. Figure 2 This state is the inverse of the state of the third transistor 313, which is controlled by the signal SGND1. This example is not limiting, and circuits 330 and 340 can be replaced by any circuit configured to provide the first transistor 311 with a control signal in the inverse state of the third transistor 313.

[0090] In the example shown, circuit 340 controls the first transistor 331 of circuit 330 to an inverted state as the state of the third transistor 333 imposed on circuit 330 by signal SGND. This example is not limiting, and circuit 340 can be replaced with any circuit configured to control the first transistor 331 of circuit 330 to an inverted state as the state of the third transistor 333.

[0091] In the example shown, circuit 330 controls the first transistor 341 of circuit 340 to be in the inverse state of the third transistor 343, which is imposed on circuit 340 by signal SGND1. Advantageously, the first transistors 331 and 341 of circuits 330 and 340 form a latch that allows for the stable delivery of control signals to transistor 201.

[0092] Preferably, the signal SVGH delivered by module 250 is a transistor control signal delivered by circuit 330, or is obtained from the transistor control signal.

[0093] In the example shown, module 250 further delivers a signal SVGH1, which is the inverse of signal SVGH. Signal SVGH1 is referenced to the potential of node VGH. Preferably, signal SVGH1 delivered by module 250 is a transistor control signal delivered by circuit 340, or is obtained from such transistor control signal.

[0094] The control transistor 201 has been described above. Figure 2 A specific example of module 250. This example is not limiting, and module 250 can be formed by any circuit capable of controlling transistor 201 to a desired state represented by signal SGND and limiting the control voltage VGSP of transistor 201 to less than voltage V1. Figure 2 The value of ). Preferably, module 250 is powered between node VGH and node GND.

[0095] Module 260 includes circuits 320, 350, and 360. Each circuit 320, 350, and 360 includes the following components electrically connected in series in this order between nodes VGH and VGL: fourth corresponding transistors 324, 354, and 364; fifth corresponding transistors 325, 355, and 365; and sixth corresponding transistors 326, 356, and 366. The fifth transistors 325, 355, and 365 each have their control terminals coupled (preferably connected) to node 245 for providing DC voltage V2.

[0096] Preferably, the fifth transistors 325, 355, 365 and the sixth transistors 326, 356, 366 are N-channel field-effect transistors and have their source terminals located on one side of node VGL. Preferably, the fourth transistors 324, 354 and 364 are P-channel field-effect transistors and have their source terminals located on one side of node VGH.

[0097] Each of circuits 320, 350, and 360 generates a transistor control signal. Each of circuits 320, 350, and 360 has a transistor control output formed by a connection node between a fifth transistor (325, 355, and 365, respectively) and a sixth transistor (326, 356, and 366, respectively).

[0098] More specifically, circuit 320 controls transistor 202 ( Figure 2 Circuit 350 controls transistors 326 and 366, and circuit 360 controls transistor 356.

[0099] Preferably, each of circuits 320, 350, and 360 includes a Zener diode (328, 358, and 368, respectively) and a resistive element (329, 359, and 369, respectively) connected in series between its transistor control output and node VGL. Zener diodes 328, 358, and 368 have their anodes facing node VGL.

[0100] In each of circuits 320, 350, and 360, the fourth transistor (324, 354, and 364, respectively) and the sixth transistor (326, 356, and 366, respectively) are inverted. Circuits 320, 350, and 360 are powered between nodes VGH and VGL.

[0101] When the fourth transistor (324, 354, and 364, respectively) is in the ON state, the fifth transistor (325, 355, and 365, respectively) maintains the potential of the connection node between the fifth transistor (325, 355, and 365, respectively) and the sixth transistor (326, 356, and 366, respectively) at a value less than the potential of node 245, which is, for example, equal to the potential of node 245 minus the threshold ON voltage of the fifth transistor (325, 355, and 365, respectively). Therefore, the transistor control voltage delivered by each of the circuits 320, 350, and 360 is limited by voltage V2.

[0102] In each of circuits 320, 350, and 360, Zener diodes 328, 358, and 368 are used to prevent the control signals delivered by the circuits from being floating when the fifth transistor (325, 355, and 365, respectively) and the sixth transistor (326, 356, and 366, respectively) are in the off state. The values ​​of Zener diodes 328, 358, and 368 are selected such that the transistor control voltage delivered by circuits 320, 350, or 360 when the Zener diode is turned on is sufficient to turn on the relevant controlled transistor, and limits that control voltage to a value less than a threshold value that can be allowed by the controlled transistor (i.e., clamps it) without degradation.

[0103] The examples shown are not limiting; Zener diodes 328, 358, and 368, as well as resistors 329, 359, and 369, can be omitted or replaced with any components that can prevent the output of circuits 320, 350, and 360 from floating.

[0104] The fourth transistor 354 of circuit 350 is controlled by signal SVGH1. The fourth transistor 324 of circuit 320 is controlled by signal SVGH. The fourth transistor 364 of circuit 360 is controlled by signal SVGH.

[0105] In the example shown, circuits 350 and 360 control the state of the sixth transistor 326 of circuit 320 to control transistor 202. Figure 2 This state is the inverse of the state of the fourth transistor 324, which is controlled by the signal SVGH. This example is not limiting, and circuits 350 and 360 can be replaced by any circuit configured to deliver control to the sixth transistor 326 to achieve a state that is the inverse of the state of the fourth transistor 324.

[0106] In the example shown, circuit 360 controls the sixth transistor 356 of circuit 350 to an inverted state as the state of the fourth transistor 354 of circuit 350 imposed by signal SVGH1. This example is not limiting, and circuit 360 can be replaced by any circuit configured to control the sixth transistor 356 of circuit 350 to an inverted state as the state of the fourth transistor 354.

[0107] In the example shown, circuit 350 controls the sixth transistor 366 of circuit 360 to an inverted state as the state of the fourth transistor 364 of circuit 360 imposed by the signal SVGH. The advantage is that the sixth transistors 356 and 366 of circuits 350 and 360 form a latch.

[0108] Although in the example shown, signal SVGH1 is output by module 250, signal SVGH1 can be generated in module 260 by any adapter circuit, for example, the circuit being powered between power nodes VGH and VGL of module 260.

[0109] A specific example of module 260 used to control transistor 202 has been described above. Figure 2 This example is not limiting, and module 260 can be formed by any circuit capable of controlling transistor 202 to a desired state represented by signal SVGH and limiting the control voltage VGSN of transistor 202 to less than voltage V2. Figure 2 The value of ). Preferably, module 260 is powered between node VGH and node VGL.

[0110] Figure 4 Another embodiment of the level shifter 400 is shown partially and schematically. The level shifter 400 can be used instead of... Figure 1 The device 100 includes a level shifter 142-i. The level shifter 400 comprises... Figure 2 The same elements as the level shifter 200, and specifically, may include about Figure 3 Modules 250 and 260 are described. These components will no longer be described; only the differences will be highlighted.

[0111] Level shifter 400 and Figure 2 The difference between the level shifter 200 and the previous one is that logic circuit 225 is replaced by logic circuit 425. Logic circuit 425 and... Figure 2 The difference between logic circuit 225 and level shifter 200 is that, in addition to delivering signal SGND from signal SI, logic circuit 425 also outputs a disable signal DIS. The disable signal can be obtained from the enable signal EN. In level shifter 400, this is replaced by... Figure 1 In the case of one of the shifters 142-i in device 100, the enable signal EN can be generated by digital unit 120 ( Figure 1 )deliver.

[0112] In the level shifter 400, node 235 is not directly connected to current source 232, but is coupled to current source via transistor 452, preferably an N-channel field-effect transistor. Transistor 452 has a drain terminal (D) facing node 235. Transistor 452 is controlled by inverter 453 that receives a disable signal DIS.

[0113] Preferably, the source terminal (S) of transistor 452 forms a connection node 454 between transistor 452 and current source 232. Node 454 and GND are coupled together by transistor 456 (preferably an N-channel field-effect transistor), which has a source terminal (S) on one side of node GND. Transistor 456 is controlled by a disable signal DIS.

[0114] Preferably, the level shifter 400 further includes a diode 458 and a resistor element 450, which are electrically connected in series between node 454 and node GND, in other words, in parallel with transistor 456.

[0115] During operation, transistor 452 is turned on when the disable signal DIS is low. Current IB1 flows, which provides a voltage sufficient for DC voltages V1 and V2 to control the on / off states of transistors 201 and 202 according to the desired state indicated by signal SI, as controlled by modules 250 and 260. DC voltages V1 and V2 then have values ​​greater than the on-voltage threshold of the corresponding switches 201 and 202.

[0116] When the disable signal is high, transistor 452 is turned off and voltages V1 and V2 are 0. Therefore, the control voltages of transistors 201 and 202 are limited to 0; in other words, transistors 201 and 202 are simultaneously turned off and the output of level shifter 400 is in a floating potential state. This floating potential state is called the high impedance state.

[0117] In image display methods (such as by Figure 1 In the device implementation of the type of device in the middle, where level shifter 142-i is replaced by level shifter 400, therefore display screen 110 ( Figure 1 The steps to disable the control terminal can be advantageously provided.

[0118] The example shown is not limiting, and the level shifter 400 may include any circuitry configured to set DC voltages V1 and V2 to values ​​less than the turn-on voltage thresholds of the respective transistors 201 and 202, other than transistors 452 and 456, inverter 453, diode 458, and resistor 459. Specifically, the circuitry is capable of selecting the value of voltage V1 between two values, less than and greater than the control voltage threshold VGSP of transistor 201, based on the level of signal DIS or signal EN.

[0119] Figure 5 schematically shown Figure 4 An example of the logic circuit 425 of the level shifter 400. More specifically, the logic circuit 425 shown corresponds to the signal SGND1 ( Figure 3 The example delivered to module 250. Besides... Figure 4 In addition to the signals SGND and DIS shown, logic circuit 425 also outputs signal SGND1. Furthermore, logic circuit 425 includes active components such as inverters and logic gates. These components are powered between node VCC and node GND. Figure 5 These nodes are not shown in the diagram.

[0120] Logic circuit 425 includes: inverter 510, which receives signal EN and delivers signal DIS; inverter 520, which receives signal DIS; AND gate 530, having an input coupled (preferably connected) to the output of inverter 520; inverter 550, having its input coupled (preferably connected) to the output of AND gate 530 and delivering signal SGND; and inverters 540 and 542, connected in series to form a buffer circuit. The input of inverter 540 is coupled (preferably connected) to the output of AND gate 530, and the output of inverter 542 delivers signal SGND1.

[0121] Figure 6 An embodiment of a device 600 including a level shifter is illustrated schematically.

[0122] Equipment 600 includes and Figure 1 The components of device 100 are the same as or similar to those in the device. These components will not be described in detail again; only the differences will be highlighted.

[0123] Equipment 600 and Figure 1The difference between device 100 and control device 600 is that control device 600 includes two display screens 110A (OLEDA) and 110B (OLEDB) instead of display screen 110, each of which includes corresponding pixel arrays 112A and 112B, corresponding control circuits 114A and 114B, and another corresponding control circuit 116A and 116B; power module 130 delivers different potentials on two nodes VGHA and VHGB instead of the potential of node VGH, and delivers different potentials on two nodes VGLA and VGLB instead of the potential of node VGL; digital unit 120 delivers signal SIiA (SI1A and SI2A) to control circuit 116A and signal SIiB (SI1B and SI2B) to control circuit 116B instead of signal SIi; and digital unit 120 is coupled (preferably connected) to control circuits 114A and 114B.

[0124] Display screens 110A and 110B can be display screen 110 ( Figure 1 The types of arrays 112A and 112B correspond to array 112, and control circuits 114A and 114B correspond to control circuit 114. Figure 1 ), and other control circuits 116A and 116B correspond to control circuit 116 ( Figure 1 Preferably, display screens 110A and 110B differ from each other in that display screen 110A is powered between nodes VGHA and VGLA, which have potentials different from those of nodes VGHB and VGLB, which apply the power supply potential to display screen 110B. For example, one of potentials VGLA and VGLB is positive, and the other of the potentials of nodes VGLA and VGLB is negative.

[0125] According to this embodiment, a component 640 is provided comprising a plurality of level shifters, all of which are identical (within manufacturing tolerances). In the example shown, component 604 includes four level shifters 200A-1, 200A-2, 200B-1, and 200B-2. The level shifters are... Figure 2 The level shifter 200 is similar to or the same as the level shifter 200. Level shifters 200A-1, 200A-2, 200B-1, and 200B-2 (SHIFT) can also be similar to... Figure 4 The level shifter 400 is similar or identical, and an additional link (not shown) is then set between the digital unit 120 and the level shifter 400 to transmit enable / disable signals.

[0126] Preferably, component 640 is a monolithic integrated circuit, i.e., located inside and on top of the same semiconductor wafer portion. Preferably, component 640 is located within an integrated circuit package. An integrated circuit package means that the package (preferably compact) has connection areas or connection pins from the integrated circuit to other electronic circuitry outside the package (e.g., with a printed circuit board PCB).

[0127] Level shifters 200A-1 and 200A-2 are coupled (preferably connected) to nodes VCC, VGHA, and VGLA. Level shifters 200A-1 and 200A-2 form a level shifter group, thereby delivering control signals to control circuit 116A. Level shifters 200B-1 and 200B-2 are coupled (preferably connected) to nodes VCC, VGHB, and VGLB. Level shifters 200B-1 and 200B-2 form a level shifter group, thereby delivering control signals to control circuit 116B.

[0128] Although an example has been shown of component 640 comprising four identical level shifters forming two groups respectively associated with two display screens, multiple display screens with more than two can be provided. It is further possible to provide more than two level shifters per group (i.e., per display screen), for example, four or eight level shifters per display screen.

[0129] The advantage of device 600 is that it can connect to various display screens powered between different high and low potentials from the same component 640, and for the same component, the low potential can have different symbols for two different display screens.

[0130] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will readily conceive of by those skilled in the art. Specifically, although the embodiment has a potential greater than that of node VGL and greater than that of node GND, other embodiments can be obtained by inverting the sign of the potential (referenced to the potential of node GND), by swapping the N and P conduction types of the transistor channels, and by swapping the anode and cathode of the diodes, further inverting the direction of current flow during operation.

[0131] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art. Specifically, the selection of each transistor (more specifically, the maximum drain-source voltage that the transistor can block) can be accomplished in a conventional manner based on the voltage / current level that the transistor must block in the operation described above.

Claims

1. A circuit configured to deliver an output potential level of two first levels based on an input level of two second levels, comprising: A first transistor and a second transistor are connected at a first node, the first node being configured to deliver the output potential level, wherein the first transistor and the second transistor are electrically connected in series between the second node on which the two first levels are applied. A first voltage generator, powered by one of the second nodes, is configured to deliver a first DC voltage, which defines an upper limit of a control voltage applied to the control terminal of the first transistor by a first transistor control circuit. as well as A second voltage generator is powered between the second nodes. The second voltage generator is controlled by a value representing the first DC voltage and is configured to deliver a second DC voltage, which limits an upper limit of the control voltage applied to the control terminal of the second transistor by the second transistor control circuit. in: A first signal is input to the second transistor control circuit and indicates the desired state of the second transistor, the first signal being referenced to the potential of one of the second nodes; as well as The first signal is generated from the second signal, which is input to the first transistor control circuit and represents the desired state of the first transistor. The second signal is referenced to the reference potentials of the two second levels.

2. The circuit according to claim 1, wherein: The first voltage generator includes a third transistor configured to conduct a first current for powering the first voltage generator; and The second voltage generator includes a fourth transistor that forms a current mirror with the third transistor, and the fourth transistor is configured to conduct a second current for powering the second voltage generator.

3. The circuit according to claim 2, wherein: The first voltage generator includes a first element electrically connected in series with the third transistor between one of the second nodes and the third node, the third node delivering the first DC voltage, and the first element having a predetermined voltage drop in response to the passage of the first current; and The second voltage generator includes a second element that couples a fourth node to another second node in the second node, and the second element has a predetermined voltage drop in response to the passage of the second current.

4. The circuit of claim 3, wherein the first element is a diode, and the second element is a fifth transistor and a diode connected in series.

5. The circuit according to claim 1, wherein the first transistor control circuit comprises: A first additional transistor, a second additional transistor, and a third additional transistor are connected in series sequentially between one of the second nodes and an additional node to which one of the two second levels is applied, wherein the second additional transistor has its control terminal coupled to the node associated with the first DC voltage. as well as A connection node is located between the first additional transistor and the second additional transistor, the node being coupled to provide the control voltage applied to the control terminal of the first transistor.

6. The circuit according to claim 5, wherein the second transistor control circuit comprises: A fourth, a fifth, and a sixth additional transistor are electrically connected in series sequentially between one of the second nodes and the other of the second nodes, wherein the fifth additional transistor has its control terminal coupled to the node associated with the second DC voltage. as well as A connection node, located between the fifth and sixth additional transistors, is coupled to provide the control voltage applied to the control terminal of the second transistor.

7. The circuit according to claim 6, wherein: The first signal is applied to the control terminal of the fourth additional transistor; and The second signal is applied to the control terminal of the third additional transistor.

8. The circuit of claim 6, wherein the second transistor control circuit further comprises: The seventh, eighth, and ninth additional transistors are electrically connected in series sequentially between one of the second nodes and the other of the second nodes, and the eighth additional transistor has its control terminal coupled to the node associated with the second DC voltage. as well as A connection node is located between the eighth additional transistor and the ninth additional transistor, the node being coupled to provide a control voltage applied to the control terminal of the sixth additional transistor.

9. The circuit according to claim 8, wherein: A first complementary signal is input to the second transistor control circuit and represents the desired state of the second transistor, and the first signal and the first complementary signal are referenced to the potential of one of the second nodes, wherein the first signal is applied to the control terminal of the fourth additional transistor, and the first complementary signal is applied to the control terminal of the seventh additional transistor; and The second signal is applied to the control terminal of the third additional transistor.

10. The circuit of claim 8, wherein the ninth additional transistor is part of a latching circuit.

11. The circuit of claim 6, wherein the first transistor control circuit further comprises: The tenth, eleventh, and twelfth additional transistors are connected in series sequentially between one of the second nodes and the additional node to which one of the two second levels is applied, and the eleventh additional transistor has its control terminal coupled to the node associated with the first DC voltage. as well as A connection node, located between the tenth additional transistor and the eleventh additional transistor, is coupled to provide the control voltage applied to the control terminal of the first additional transistor.

12. The circuit according to claim 11, wherein: The first signal is applied to the control terminal of the fourth additional transistor; and The first signal is generated from the second signal and the second complementary signal. The second signal and the second complementary signal are input to the first transistor control circuit. The second complementary signal is referenced to the reference potentials of the two second levels. The second signal is applied to the control terminal of the third additional transistor, and the second complementary signal is applied to the control terminal of the twelfth additional transistor.

13. The circuit of claim 11, wherein the tenth additional transistor is part of a latching circuit.

14. The circuit of claim 1, wherein the value of the first DC voltage is selected based on the level of a logic enable / disable signal between a value below and above a voltage threshold for the control terminal of the first transistor.

15. The circuit according to claim 1, wherein the output potential level controls the display screen.

16. A method for delivering an output potential level of two first levels based on an input level of two second levels, comprising: The output potential level is delivered through a first node, which connects a first transistor and a second transistor in series between two second nodes that apply the two first levels. A first DC voltage is delivered by a first voltage generator powered by one of the second nodes, the first DC voltage defining an upper limit on the control voltage of the first transistor; A second DC voltage is delivered via a second voltage generator, which is controlled by a value representing the first voltage and is powered between the second nodes, and the second DC voltage defines an upper limit for the control voltage of the second transistor; Receive a first signal indicating the desired state of the second transistor, the first signal being referenced to the potential of the one of the second nodes; as well as The first signal is generated from a second signal representing the desired state of the first transistor, the second signal being referenced to the reference potentials of the two second levels.

17. The method of claim 16, further comprising: Conducting a first current to power the first voltage generator; as well as The first current is mirrored to conduct a second current used to power the second voltage generator.

18. The method of claim 17, further comprising: A predetermined voltage drop is generated in response to the passage of the first current to produce the first DC voltage; In response to the passage of the second current, a predetermined voltage drop is generated to produce the second DC voltage.

19. The method of claim 16, wherein the value of the first DC voltage is selected based on the level of a logic enable / disable signal between a value below a voltage threshold for the control terminal of the first transistor and a value above the voltage threshold.

20. The method of claim 16, further comprising: The output potential level is used to control the display screen.

21. A circuit, comprising A current mirror circuit includes a first transistor and a second transistor, the first transistor being coupled between a high power supply potential node and a first intermediate node, the second transistor being coupled between the high power supply potential node and the second intermediate node, and the second transistor having a control terminal coupled to the first transistor and a control terminal of the first intermediate node. A current source is coupled between the first intermediate node and the ground node; A first capacitor is coupled between the high power potential node and the first intermediate node and is configured to provide a first voltage; A third transistor is coupled between the second intermediate node and the low power potential node, and the third transistor has a control terminal coupled to the second intermediate node. A second capacitor is coupled between the second intermediate node and the low power potential node and is configured to provide a second voltage; A first output transistor and a second output transistor are connected at an output node, wherein the first transistor and the second transistor are electrically connected in series between the high power supply potential node and the low power supply potential node. A first driving circuit, powered by the first voltage, is configured to generate a first control signal applied to the control terminal of the first output transistor; as well as The second driving circuit, powered by the second voltage, is configured to generate a second control signal applied to the control terminal of the second output transistor.

22. The circuit of claim 21, wherein the first driving circuit is powered between the high power potential node and the ground node, and wherein the second driving circuit is powered between the high power potential node and the low power potential node.

23. The circuit of claim 21, wherein the first capacitor is connected in parallel with the series connection of the first transistor and the first diode, and wherein the second capacitor is connected in parallel with the series connection of the second transistor and the second diode.

24. The circuit of claim 21, wherein the first driving circuit is configured to receive a third control signal referenced between a power supply voltage node and the ground node, the first driving circuit shifting the third control signal relative to the first voltage level to generate the first control signal.

25. The circuit of claim 24, wherein the second driving circuit further outputs a fourth control signal in response to the third control signal, and wherein the second driving circuit is configured to receive the fourth control signal, the second driving circuit shifting the fourth control signal relative to the second voltage level to generate the second control signal.

26. The circuit of claim 21, wherein the first driving circuit comprises: A first additional transistor, a second additional transistor, and a third additional transistor are connected in series sequentially between the high power potential node and the ground node, wherein the control terminal of the second additional transistor is coupled to the first intermediate node. as well as An interconnect node is located between the first additional transistor and the second additional transistor, and the first control signal is output at the interconnect node.

27. The circuit of claim 26, wherein the first driving circuit further comprises a latching circuit responsive to an input signal and having an output configured to generate a latching signal applied to a control terminal of the first additional transistor, and wherein the input signal is applied to a control terminal of the third additional transistor.

28. The circuit of claim 21, wherein the second driving circuit comprises: The fourth, fifth, and sixth additional transistors are connected in series sequentially between the high power potential node and the low power potential node, wherein the control terminal of the fifth additional transistor is coupled to the second intermediate node. as well as An interconnect node is located between the fifth additional transistor and the sixth additional transistor, and the second control signal is output at the interconnect node.

29. The circuit of claim 28, wherein the second driving circuit further comprises a latching circuit responsive to an input signal and having an output configured to generate a latching signal applied to a control terminal of the sixth additional transistor, and wherein the input signal is applied to a control terminal of the fourth additional transistor.

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