A parity check circuit and method

Abstract

The present invention discloses a parity check circuit and method. The parity check circuit includes a state setting module, a first operation module, a shift module, a second operation module and a third operation module; the first input end of the first operation module is connected to a data signal; the state setting module is used to output a state signal to the first operation module, the first operation module is used to perform a logic operation on the data signal and the first signal output by the shift module, perform a logic operation on the state signal and the first signal, and output a second signal; the shift module is used to shift the second signal and output the first signal; the second operation module is used to perform a logic operation on the first signal and the control signal, and output a third signal; the third operation module is used to perform a logic operation on the third signal and the second signal, and output a data signal and a parity check bit. The parity check circuit of the present invention can output the original data signal and the parity check bit, and does not require a microcontroller, which is conducive to reducing costs.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of data transmission, and in particular to a parity check circuit and method. Background Art

[0002] During data communication, data may inevitably be interfered by external factors during transmission from the sender to the receiver. Therefore, during the communication process, especially wireless communication, it is necessary for the receiver to determine whether the received data is the data sent by the sender.

[0003] In this regard, the usual practice is that after sending data information, the sender sends a check bit related to the data information, such as a parity check bit. After receiving the data information and the check bit, the receiver determines whether the received check bit has the same correlation with the received data, thereby determining whether the received data is sent by the sender.

[0004] However, the existing parity check circuit needs to implement the parity check algorithm through a microcontroller, which is costly, and the existing parity check circuit can only output the check bit. Summary of the invention

[0005] The present invention provides a parity check circuit and method, which can output data signals and parity check bits without requiring a microcontroller, thus helping to reduce costs.

[0006] In a first aspect, an embodiment of the present invention provides a parity check circuit, the parity check circuit comprising: a state setting module, a data module, a first operation module, a shift module, a second operation module and a third operation module;

[0007] The first input terminal of the first operation module is connected to the data signal;

[0008] The output end of the state setting module is electrically connected to the first input end of the first operation module, the second input end of the first operation module is electrically connected to the output end of the shift module, and the output end of the first operation module is electrically connected to the input end of the shift module. The state setting module is used to output a state signal to the first operation module after the data signal is sent. The first operation module is used to perform a logic operation on the data signal and a first signal output by the shift module, and perform a logic operation on the state signal and the first signal, and output a second signal. The shift module is used to shift the second signal and output the first signal.

[0009] The first input end of the second operation module is electrically connected to the output end of the shift module, the second input end of the second operation module is connected to the control signal, and the second operation module is used to perform a logic operation on the first signal and the control signal, and output a third signal;

[0010] The first input end of the third operation module is electrically connected to the output end of the second operation module, and the second input end of the third operation module is electrically connected to the output end of the first operation module. The third operation module is used to perform logical operations on the third signal and the second signal, and output the data signal and the parity bit.

[0011] Optionally, the parity check circuit further includes: a clock module;

[0012] The clock module is electrically connected to a clock terminal of the shift module. The clock module is used to output a clock signal. The shift module is used to output the first signal in response to the clock signal of the clock module.

[0013] Optionally, the parity check circuit further includes: a control module;

[0014] The control module is electrically connected to the second input end of the second operation module, and the control module is used to output the control signal.

[0015] Optionally, the first operation module includes a first XOR operation unit;

[0016] The first input end of the first XOR operation unit is the first input end of the first operation module, the second input end of the first XOR operation unit is the second input end of the first operation module, the output end of the first XOR operation unit is the output end of the first operation module, and the first XOR operation unit is used to perform a logical XOR operation on the data signal and the first signal output by the shift module, and perform a logical XOR operation on the state signal and the first signal, and output a second signal.

[0017] Optionally, the second operation module includes a logic and operation unit;

[0018] The first input end of the logic and operation unit is the first input end of the second operation module, the second input end of the logic and operation unit is the second input end of the second operation module, the output end of the logic and operation unit is the output end of the second operation module, and the logic and operation unit is used to perform a logic and operation on the first signal and the control signal, and output a third signal.

[0019] Optionally, the third operation module includes a second XOR operation unit;

[0020] The first input end of the second XOR operation unit is the first input end of the third operation module, the second input end of the second XOR operation unit is the second input end of the third operation module, the output end of the second XOR operation unit is the output end of the third operation module, and the second XOR operation unit performs a logic operation on the third signal and the second signal, and outputs the data signal and the parity bit.

[0021] Optionally, the shift module includes a shift register;

[0022] The input end of the shift register is the input end of the shift module, the output end of the shift register is the output end of the shift module, and the shift register is used to output the first signal according to the second signal.

[0023] Optionally, the shift register comprises a flip-flop.

[0024] Optionally, the parity check circuit further comprises a resistor;

[0025] The output terminal of the state setting module is electrically connected to the first input terminal of the first operation module through the resistor.

[0026] In a second aspect, an embodiment of the present invention further provides a parity check method, the parity check method comprising:

[0027] The first operation module receives the data signal, and the state setting module sends a state signal to the first operation module;

[0028] The first operation module performs a logic operation on the data signal and the first signal output by the shift module, and performs a logic operation on the state signal and the first signal, and outputs a second signal;

[0029] The shift module shifts the second signal to output a first signal;

[0030] The second operation module performs a logic operation on the first signal and the control signal, and outputs a third signal;

[0031] The third operation module performs a logic operation on the third signal and the second signal, and outputs the data signal and a parity bit.

[0032] In the present invention, the parity check circuit includes a state setting module, a first operation module, a shift module, a second operation module and a third operation module. The external data module can send a data signal. The first operation module performs a logic operation on the data signal and the first signal output by the shift module, and uses the result of the logic operation as the second signal. After the first operation module outputs the second signal, the shift module can output the first signal according to the second signal. The second operation module performs a logic operation on the first signal and the control signal, and outputs the result of the logic operation as the third signal. The third operation module performs a logic operation on the third signal and the second signal, and outputs the data signal. After the data signal is sent, the state setting module outputs the state signal to the first operation module, the first operation module performs a logic operation on the state signal and the first signal, and outputs the second signal; the shift module shifts the second signal and outputs the first signal; the second operation module performs a logic operation on the first signal and the control signal, and outputs the third signal; the third operation module performs a logic operation on the third signal and the second signal, and outputs a parity check bit, the parity check bit, for example, indicates whether the number of 1s in the data signal is an odd number or an even number, so that the received data signal can be judged whether it is accurate according to the parity check bit, so that the data signal and the parity check bit can be output, and only three operation modules and one shift module are needed to realize the parity check, and there is no need to use a microcontroller for algorithm processing, so as to achieve the effect of reducing costs. The present invention solves the problem that the existing parity check circuit needs to realize the parity check algorithm through a microcontroller, which is costly, and the existing parity check circuit can only output the check bit, and realizes that the parity check circuit can output the data signal and the parity check bit, and no microcontroller is required, so as to achieve the effect of reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a structural schematic diagram of a parity check circuit provided by an embodiment of the present invention;

[0034] Figure 2 is a structural schematic diagram of another parity check circuit provided by an embodiment of the present invention;

[0035] Figure 3 is a timing diagram corresponding to a parity check circuit provided by an embodiment of the present invention;

[0036] Figure 4 is a timing diagram corresponding to another parity check circuit provided by an embodiment of the present invention;

[0037] Figure 5 is a timing diagram corresponding to another parity check circuit provided by an embodiment of the present invention;

[0038] Figure 6 is a timing diagram corresponding to another parity check circuit provided by an embodiment of the present invention;

[0039] Figure 7 The present invention provides a flowchart of a parity check method. DETAILED DESCRIPTION

[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0041] Figure 1 is a schematic diagram of a parity check circuit provided by an embodiment of the present invention, see Figure 1 The parity check circuit includes: a state setting module 110, a first operation module 130, a shift module 140, a second operation module 150 and a third operation module 160; the first input end of the first operation module 130 is connected to the data signal Data; the output end of the state setting module 110 is electrically connected to the first input end of the first operation module 130, the second input end of the first operation module 130 is electrically connected to the output end of the shift module 140, and the output end of the first operation module 130 is electrically connected to the input end of the shift module 140. The state setting module 110 is used to output the state signal A to the first operation module 130 after the data signal Data is sent. The first operation module 130 is used to perform a logic operation on the data signal and the first signal B1 output by the shift module 140, and to perform a logic operation on the state signal. The state signal A performs a logic operation on the first signal B1, and outputs the second signal B2; the shift module 140 is used to shift the second signal and output the first signal B1; the first input end of the second operation module 150 is electrically connected to the output end of the shift module 140, and the second input end of the second operation module 150 is connected to the control signal. The second operation module 150 is used to perform a logic operation on the first signal B1 and the control signal C, and output the third signal B3; the first input end of the third operation module 160 is electrically connected to the output end of the second operation module 150, and the second input end of the third operation module 160 is electrically connected to the output end of the first operation module 130. The third operation module 160 is used to perform a logic operation on the third signal B3 and the second signal B2, and output the data signal Data and the parity bit E.

[0042] Among them, the external data module can send a data signal Data, the first operation module 130 performs a logic operation on the data signal Data and the first signal B1 output by the shift module 140, and uses the result of the logic operation as the second signal B2, wherein the first signal B1 is output by the shift module 140 according to the second signal B2 output by the first operation module 130, and when the first operation module 130 has not yet output the second signal B2, the first signal B1 output by the shift module 140 can be defaulted to 0, and after the first operation module 130 outputs the second signal B2, the shift module 140 can output the first signal B1 according to the second signal B2 as the input signal for the next operation of the first operation module 130. The second operation module 150 then performs a logic operation on the first signal B1 and the control signal C, and outputs the result of the logic operation as the third signal B3, and the third operation module 160 performs a logic operation on the third signal B3 and the second signal B2, and outputs the data signal Data.

[0043] After the data signal Data is sent, the output end of the external data module is in a high impedance state, and the state setting module 110 can output the state signal A to the first operation module 130, wherein the state signal A can be a high level signal 1 or a low level signal 0. The first operation module 130 performs a logic operation on the state signal A and the first signal B1, and outputs the second signal B2; the shift module 140 shifts the second signal B2 and outputs the first signal B1; the second operation module 150 performs a logic operation on the first signal B1 and the control signal C, and outputs the third signal B3; the third operation module 16 0 performs a logical operation on the third signal B3 and the second signal B2, and outputs a parity bit E, where the parity bit E, for example, indicates whether the number of 1s in the data signal Data is an odd number or an even number, and the parity bit E is, for example, 0 or 1, 0 indicates that the number of 1s in the data signal Data is an even number, and 1 indicates that the number of 1s in the data signal Data is an odd number; or, 0 indicates that the number of 1s in the data signal Data is an odd number, and 1 indicates that the number of 1s in the data signal Data is an even number, so that whether the received data signal Data is accurate can be judged according to the parity bit E.

[0044] Exemplarily, the data signal Data is, for example, 8 bits, and the data signal Data is serial data, then the operation of the parity check circuit is: (1) After the first operation module 130 receives the first bit D1 of the data signal Data, it performs a logic operation on the first bit D1 of the data signal Data and the first bit B11 of the first signal B1. At this time, the first bit B11 of the first signal B1 is 0 by default. After the logic operation, the first bit B21 of the second signal B2 is obtained. The shift module 140 outputs the second bit B12 of the first signal B1 according to the first bit B21 of the second signal B2 as the input signal for the next operation of the first operation module 130. The second operation module 150 then replaces the first bit B11 of the first signal B1 with the first bit B21 of the first signal B2. 1 performs a logic operation on the first bit C1 of the control signal C to obtain the first bit B31 of the third signal B3, and the third operation module 160 performs a logic operation on the first bit B31 of the third signal B3 and the first bit B21 of the second signal B2 to output the first bit D1 of the data signal Data; (2) the first operation module 130 performs a logic operation on the second bit D2 of the data signal Data and the second bit B12 of the first signal B1, that is, the first operation module 130 performs a logic operation on the second bit D2 of the data signal Data and the second bit B12 of the first signal B1 to obtain the second bit B22 of the second signal B2, and the shift module 140 outputs the third bit B22 of the first signal B1 according to the second bit B22 of the second signal B2 13, the second operation module 150 performs a logic operation on the second bit B12 of the first signal B1 and the second bit C2 of the control signal C to obtain the second bit B32 of the third signal B3, and the third operation module 160 performs a logic operation on the second bit B32 of the third signal B3 and the second bit B22 of the second signal B2 to output the second bit D2 of the data signal Data; (3) and so on, until the third operation module 160 performs a logic operation on the eighth bit B38 of the third signal B3 and the eighth bit D28 of the second signal B2 to output the eighth bit D8 of the data signal Data, and the data signal Data is sent; (4) After the data signal Data is sent, the state setting module 110 can output the state signals A to The first operation module 130 operates the state signal A and the ninth bit B19 of the first signal B1 to obtain the ninth bit B29 of the second signal B2. The second operation module 150 performs a logic operation on the ninth bit B19 of the first signal B1 and the ninth bit C9 of the control signal C to obtain the ninth bit B39 of the third signal B3. The third operation module 160 performs a logic operation on the ninth bit B39 of the third signal B3 and the ninth bit B29 of the second signal B2 to obtain the parity bit E, thereby outputting the data signal Data and the parity bit E. Only three operation modules and one shift module are required to realize the parity check, and there is no need to use a microcontroller for algorithm processing, thereby achieving the effect of reducing costs.

[0045] The technical solution of this embodiment is that the parity check circuit includes a state setting module, a first operation module, a shift module, a second operation module and a third operation module. The external data module can send a data signal. The first operation module performs a logic operation on the data signal and the first signal output by the shift module, and uses the result of the logic operation as the second signal. After the first operation module outputs the second signal, the shift module can output the first signal according to the second signal as the input signal for the next operation of the first operation module. The second operation module then performs a logic operation on the first signal and the control signal, and outputs the result of the logic operation as the third signal. The third operation module performs a logic operation on the third signal and the second signal, and outputs a data signal. After the data signal is sent, the state setting module outputs the state signal to the first operation module, the first operation module performs a logical operation on the state signal and the first signal, and outputs the second signal; the shift module shifts the second signal and outputs the first signal; the second operation module performs a logical operation on the first signal and the control signal, and outputs the third signal; the third operation module performs a logical operation on the third signal and the second signal, and outputs a parity check bit, the parity check bit, for example, indicates whether the number of 1s in the data signal is an odd number or an even number, so that the received data signal can be judged whether it is accurate according to the parity check bit, so that the data signal and the parity check bit can be output, and only three operation modules and one shift module are needed to realize the parity check, and there is no need to use a microcontroller for algorithm processing, so as to achieve the effect of reducing costs. The technical solution of this embodiment solves the problem that the existing parity check circuit needs to implement the parity check algorithm through a microcontroller, which is costly, and the existing parity check circuit can only output the check bit, and realizes that the parity check circuit can output the data signal and the parity check bit, and no microcontroller is required, so as to achieve the effect of reducing costs.

[0046] On the basis of the above implementation plan, Figure 2 is a schematic diagram of the structure of another parity check circuit provided by an embodiment of the present invention. Figure 2 The parity check circuit also includes a clock module 170; the clock module 170 is electrically connected to the clock end of the shift module 140, the clock module 170 is used to output a clock signal CLK, and the shift module 140 is used to output a first signal B1 in response to the clock signal CLK of the clock module 170.

[0047] Specifically, the clock module 170 can generate a clock signal CLK, and the shift module 140 can work in response to the clock signal of the clock module 170, thereby outputting the first signal B1. The clock signal CLK includes a rising edge and a falling edge, and the shift module 140 operates at the rising edge of the clock signal CLK, thereby outputting the first signal B1.

[0048] Alternatively, see Figure 2The parity check circuit further includes a control module 180; the control module 180 is electrically connected to the second input terminal of the second operation module 150, and the control module 180 is used to output a control signal C.

[0049] Specifically, the control module 180 can output the control signal C, so that the second operation module 150 can perform a logic operation on the first signal B1 output by the shift module 140 and the control signal C, thereby obtaining the third signal B3. When the external data module sends the data signal Data, the control signal C is, for example, a high-level signal 1, and when the state setting module 110 sends the state signal A, the control signal C is, for example, a low-level signal 0.

[0050] Alternatively, see Figure 2 The first operation module 130 includes a first XOR operation unit 131; the first input end of the first XOR operation unit 131 is the first input end of the first operation module 130, the second input end of the first XOR operation unit 131 is the second input end of the first operation module 130, the output end of the first XOR operation unit 131 is the output end of the first operation module 130, and the first XOR operation unit 131 is used to perform a logical XOR operation on the data signal Data and the first signal B1 output by the shift module 140, and perform a logical XOR operation on the state signal A and the first signal B1, and output the second signal B2.

[0051] Specifically, the first XOR operation unit 131 can perform a logical XOR operation on the data signal Data and the first signal B1 output by the shift module 140. The logical XOR operation means that if the two input values ​​are different, the XOR result is 1, and if the two input values ​​are the same, the XOR result is 0. For example, if the first bit D1 of the data signal Data is 0 and the first bit B11 of the first signal B1 is 0, the first bit B21 of the second signal B2 output by the first XOR operation unit 131 is 0; for example, if the first bit D1 of the data signal Data is 1 and the first bit B11 of the first signal B1 is 0, the first bit B21 of the second signal B2 output by the first XOR operation unit 131 is 1. In addition, the first XOR operation unit 131 can also perform a logical XOR operation on the state signal A and the first signal B1, thereby outputting the second signal B2.

[0052] Alternatively, see Figure 2 The second operation module 150 includes a logic AND operation unit 151; the first input end of the logic AND operation unit 151 is the first input end of the second operation module 150, the second input end of the logic AND operation unit 151 is the second input end of the second operation module 150, the output end of the logic AND operation unit 151 is the output end of the second operation module 150, and the logic AND operation unit 151 is used to perform a logic AND operation on the first signal B1 and the control signal C, and output a third signal B3.

[0053] Specifically, the logic AND operation unit 151 can perform a logic AND operation on the first signal B1 and the control signal C. The logic AND operation means that if the two input values ​​are different, the result is 0, and if the two input values ​​are the same, the result is 1. For example, if the first bit B11 of the first signal B1 is 0 and the first bit C1 of the control signal C is 1, the first bit B31 of the third signal B3 output by the logic AND operation unit 151 is 0; for example, if the second bit B12 of the first signal B1 is 1 and the second bit C2 of the control signal C is 1, the second bit B32 of the third signal B3 output by the logic AND operation unit 151 is 1, so that the third signal B3 can be output.

[0054] Alternatively, see Figure 2 The third operation module 160 includes a second XOR operation unit 161; the first input end of the second XOR operation unit 161 is the first input end of the third operation module 160, the second input end of the second XOR operation unit 161 is the second input end of the third operation module 160, the output end of the second XOR operation unit 161 is the output end of the third operation module 160, the second XOR operation unit 161 performs a logic operation on the third signal B3 and the second signal B2, and outputs the data signal Data and the parity bit E.

[0055] Specifically, the second XOR operation unit 161 can perform an XOR operation on the third signal B3 and the second signal B2. For example, when the first bit B31 of the third signal B3 is 0 and the first bit B21 of the second signal B2 is 1, the second XOR operation unit 161 outputs the first bit D1 of the data signal Data as 1; for example, when the ninth bit B39 of the third signal B3 is 0 and the ninth bit B29 of the second signal B2 is 0, the second XOR operation unit 161 outputs the parity bit E as 0.

[0056] Alternatively, see Figure 2 The shift module 140 includes a shift register 141; the input end of the shift register 141 is the input end of the shift module 140, the output end of the shift register 141 is the output end of the shift module 140, and the shift register 141 is used to output the first signal B1 according to the second signal B2.

[0057] Specifically, the data in the shift register 141 can be shifted right or left bit by bit in sequence under the action of the clock pulse. The data can be input and output in parallel, or input and output in series, or input and output in parallel. Preferably, the shift register 141 can shift the second signal B2 output by the first operation module 130 right by one bit. For example, when the second signal B2 is 00100110, the first signal B1 output by the shift register 141 is 00010011.

[0058] Alternatively, see Figure 2 , the shift register 141 includes a trigger 1411.

[0059] Specifically, the shift register 141 includes a trigger 1411, which is, for example, a D trigger, that is, the value output by the trigger 1411 is the same as the input value, that is, when the first bit B21 of the second signal B2 output by the first operation module 130 is 0, the second bit of the first signal B1 output by the shift register 141 is also 0. It should be noted that when the shift register 141 outputs the first bit B11 of the first signal B1, the first operation module 130 has not yet output the second signal B2, so the first bit B11 of the first signal B1 output by the shift register 141 is 0 by default.

[0060] Alternatively, see Figure 2 The parity check circuit further includes a resistor R1; the output end of the state setting module 110 is electrically connected to the first input end of the first operation module 130 through the resistor R1.

[0061] Specifically, the resistor R1 can be a pull-up resistor or a pull-down resistor. When the state signal A output by the state setting module 110 is a high-level signal 1, the resistor R1 is a pull-up resistor. When the state signal A output by the state setting module 110 is a low-level signal 0, the resistor R1 is a pull-down resistor, thereby outputting the state signal A to the first operation module 130. When the external data module completes sending the data signal Data, the first input terminal of the first operation module 130 will be set to a high impedance state. At this time, the state setting module 1210 can output the state signal A to the first operation module 130 through the resistor R1. The representation of the parity check bit E is related to the value of the state signal A. Table 1 is the relationship between the parity check bit and the number of 1s in the state signal and the data signal. Referring to Table 1, when the state signal A is 0, the parity check bit E is 1, indicating that the number of 1s in the data signal Data is an odd number, and the parity check bit 0 indicates that the number of 1s in the data signal Data is an even number; when the state signal A is 1, the parity check bit E is 1, indicating that the number of 1s in the data signal Data is an even number, and the parity check bit E is 0, indicating that the number of 1s in the data signal Data is an odd number. Thus, it can be achieved that no matter whether the state signal A is set to a high level signal or a low level signal, the parity check bit E can indicate whether the number of 1s in the data signal Data is an odd number or an even number.

[0062] Table 1 Relationship between the parity bit and the number of 1s in the status signal and data signal

[0063] Status signal A The number of 1s in the data signal Data Parity bit E 0 Odd number 1 0 Even number 0 1 Odd number 0 1 Even number 1

[0064] For example, Figure 3is a timing diagram corresponding to a parity check circuit provided by an embodiment of the present invention, see Figure 2 and Figure 3 , the data signal Data is 00101101, the state signal A is 0, the first terminal input of the first operation module 130 is 0, and the second terminal input is 0. After the first XOR operation unit 131 performs XOR operation, the first bit B21 of the second signal B2 output is 0. When the clock signal CLK is at a rising edge, the second bit B11 of the first signal B1 output by the trigger 1411 is 0, so as to serve as the input of the next operation of the first XOR operation unit 131; the logic AND operation unit 151 performs XOR operation on the first bit B11 of the first signal B1 and the first bit C1 of the control signal C. After the row logical AND operation, the first bit B31 of the output third signal B3 is 0, and the second XOR operation unit 161 performs an XOR operation on the first bit B31 of the third signal B3 and the first bit B21 of the second signal B2, and the output is 0, and so on. Finally, the result output by the second XOR operation unit 161 is 001011010, that is, the output data signal 00101101, and the parity bit is 0. Because the status signal A is 0, the parity bit is 0, indicating that the number of 1s in the data signal Data is an even number, and the result of the parity bit is consistent with the situation of the data signal.

[0065] Figure 4 is a timing diagram corresponding to another parity check circuit provided by an embodiment of the present invention, see Figure 2 and Figure 4 , the data signal Data is 00111011, the state signal A is 0, after the first XOR operation unit 131, the trigger 1411, the logic AND operation unit 151 and the second XOR operation unit 161, the second XOR operation unit 161 outputs 001110111, that is, the data signal 00111011 is output, and the parity bit is 1. Because the state signal A is 0, the parity bit is 1, indicating that the number of 1s in the data signal Data is an odd number, and the result of the parity bit is consistent with the situation of the data signal.

[0066] Figure 5 is a timing diagram corresponding to another parity check circuit provided by an embodiment of the present invention, see Figure 2 and Figure 5 , the data signal Data is 00101101, the state signal A is 1, after the first XOR operation unit 131, the trigger 1411, the logic AND operation unit 151 and the second XOR operation unit 161, the second XOR operation unit 161 outputs 001011011, that is, the data signal 00101101 is output, and the parity bit is 1. Because the state signal A is 1, the parity bit is 1, indicating that the number of 1s in the data signal Data is an even number, and the result of the parity bit is consistent with the situation of the data signal.

[0067] Figure 6 is a timing diagram corresponding to another parity check circuit provided by an embodiment of the present invention, see Figure 2 and Figure 6 , the data signal Data is 00111011, the state signal A is 1, after the first XOR operation unit 131, the trigger 1411, the logic AND operation unit 151 and the second XOR operation unit 161, the second XOR operation unit 161 outputs 001110110, that is, the data signal 00111011 is output, and the parity bit is 0. Because the state signal A is 1, the parity bit is 0, indicating that the number of 1s in the data signal Data is an odd number, and the result of the parity bit is consistent with the situation of the data signal.

[0068] Figure 7 is a flowchart of a parity check method provided by an embodiment of the present invention, see Figure 7 , parity check methods include:

[0069] S710: The first operation module receives a data signal, and the state setting module sends a state signal to the first operation module.

[0070] Specifically, the external data module can send a data signal Data to the first operation module 130. After the data signal Data is sent, the output end of the external data module is in a high-impedance state, and the state setting module 110 can output a state signal A to the first operation module 130, wherein the state signal A can be a high-level signal 1 or a low-level signal 0.

[0071] S720: The first operation module performs a logic operation on the data signal and the first signal output by the shift module, performs a logic operation on the state signal and the first signal, and outputs a second signal.

[0072] Specifically, the first operation module 130 performs a logical operation based on the data signal Data and the first signal B1 output by the shift module 140, and uses the result of the logical operation as the second signal B2, wherein the first signal B1 is output by the shift module 140 based on the second signal B2 output by the first operation module 130. When the first operation module 130 has not yet output the second signal B2, the first signal B1 output by the shift module 140 defaults to 0. After the first operation module 130 outputs the second signal B2, the shift module 140 can output the first signal B1 based on the second signal B2.

[0073] S730. The shift module shifts the second signal to output the first signal.

[0074] Specifically, after the first operation module 130 outputs the second signal B2, the shift module 140 may shift the second signal B2, for example, shift it one bit to the right, and output the shift result as the first signal B1.

[0075] S740: The second operation module performs a logic operation on the first signal and the control signal, and outputs a third signal.

[0076] Specifically, the second operation module 150 performs a logic operation on the first signal B1 and the control signal C, and outputs the result of the logic operation as the third signal B3, wherein when the external data module sends the data signal Data, the control signal C is, for example, a high-level signal 1, and when the state setting module 110 sends the state signal A, the control signal C is, for example, a low-level signal 0.

[0077] S750: The third operation module performs a logic operation on the third signal and the second signal, and outputs a data signal and a parity bit.

[0078] Specifically, the third operation module 160 performs a logical operation on the third signal B3 and the second signal B2, and outputs the data signal Data and a parity check bit E, where the parity check bit E indicates, for example, whether the number of 1s in the data signal Data is an odd number or an even number, and the parity check bit E is, for example, 0 or 1, 0 indicating that the number of 1s in the data signal Data is an even number, and 1 indicating that the number of 1s in the data signal Data is an odd number; or, 0 indicating that the number of 1s in the data signal Data is an odd number, and 1 indicating that the number of 1s in the data signal Data is an even number, so that whether the received data signal Data is accurate can be determined based on the parity check bit E, and only three operation modules and one shift module are required to implement parity check, and there is no need to use a microcontroller for algorithm processing, thereby achieving the effect of reducing costs.

[0079] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A parity check circuit, characterized in that: include: A state setting module, a first operation module, a shift module, a second operation module and a third operation module; The first input terminal of the first operation module is connected to the data signal; The output end of the state setting module is electrically connected to the first input end of the first operation module, the second input end of the first operation module is electrically connected to the output end of the shift module, and the output end of the first operation module is electrically connected to the input end of the shift module. The state setting module is used to output a state signal to the first operation module after the data signal is sent. The first operation module is used to perform a logic operation on the data signal and a first signal output by the shift module, and perform a logic operation on the state signal and the first signal, and output a second signal. The shift module is used to shift the second signal and output the first signal. The first input end of the second operation module is electrically connected to the output end of the shift module, the second input end of the second operation module is connected to the control signal, and the second operation module is used to perform a logic operation on the first signal and the control signal, and output a third signal; The first input end of the third operation module is electrically connected to the output end of the second operation module, and the second input end of the third operation module is electrically connected to the output end of the first operation module. The third operation module is used to perform logical operations on the third signal and the second signal, and output the data signal and the parity bit.

2. The parity check circuit according to claim 1, characterized in that: Also includes: Clock module; The clock module is electrically connected to a clock terminal of the shift module. The clock module is used to output a clock signal. The shift module is used to output the first signal in response to the clock signal of the clock module.

3. The parity check circuit according to claim 1, characterized in that: Also includes: Control module; The control module is electrically connected to the second input end of the second operation module, and the control module is used to output the control signal.

4. The parity check circuit according to claim 1, characterized in that: The first operation module includes a first XOR operation unit; The first input end of the first XOR operation unit is the first input end of the first operation module, the second input end of the first XOR operation unit is the second input end of the first operation module, the output end of the first XOR operation unit is the output end of the first operation module, and the first XOR operation unit is used to perform a logical XOR operation on the data signal and the first signal output by the shift module, and perform a logical XOR operation on the state signal and the first signal, and output a second signal.

5. The parity check circuit according to claim 1, characterized in that: The second operation module includes a logic and operation unit; The first input end of the logic and operation unit is the first input end of the second operation module, the second input end of the logic and operation unit is the second input end of the second operation module, the output end of the logic and operation unit is the output end of the second operation module, and the logic and operation unit is used to perform a logic and operation on the first signal and the control signal, and output a third signal.

6. The parity check circuit according to claim 1, characterized in that: The third operation module includes a second XOR operation unit; The first input end of the second XOR operation unit is the first input end of the third operation module, the second input end of the second XOR operation unit is the second input end of the third operation module, the output end of the second XOR operation unit is the output end of the third operation module, and the second XOR operation unit performs a logic operation on the third signal and the second signal, and outputs the data signal and the parity bit.

7. The parity check circuit according to any one of claims 1 to 6, characterized in that: The shift module includes a shift register; The input end of the shift register is the input end of the shift module, the output end of the shift register is the output end of the shift module, and the shift register is used to output the first signal according to the second signal.

8. The parity check circuit according to claim 7, characterized in that: The shift register includes a flip-flop.

9. The parity check circuit according to claim 1, characterized in that: It also includes resistors; The output terminal of the state setting module is electrically connected to the first input terminal of the first operation module through the resistor.

10. A parity check method, characterized in that: include: The first operation module receives the data signal, and the state setting module sends a state signal to the first operation module; The first operation module performs a logic operation on the data signal and the first signal output by the shift module, and performs a logic operation on the state signal and the first signal, and outputs a second signal; The shift module shifts the second signal to output a first signal; The second operation module performs a logic operation on the first signal and the control signal, and outputs a third signal; The third operation module performs a logic operation on the third signal and the second signal, and outputs the data signal and a parity bit.

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