Data transmission method, system, and chip

Abstract

The present application provides a data transmission method, system, and chip. The data transmission method includes: receiving an intra-chip bus write access request; wherein the intra-chip bus write access request includes: valid data; obtaining configuration information of an encapsulation header; encapsulating the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and sending the first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit design, and in particular to data transmission methods, systems, and chips. Background Art

[0002] Currently, the most widely used and mature interface for inter-chip data transmission (or direct inter-chip data access) is the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express) interface. However, the PCIE interface only supports point-to-point access, has an inflexible topology, and can only support data transmission between chips on a board. It is mainly used in X86 computer systems. In addition, the PCIE interface operates at a high frequency, is complex to implement and debug, and has limited single-channel bandwidth.

[0003] With the increasing application of Ethernet technology and the increasing bandwidth of Ethernet transmission, the Ethernetization of chip interfaces is becoming increasingly evident. Using Ethernet packets for inter-chip data transmission will be a significant trend and offer significant advantages. Inter-chip data transmission based on Ethernet packets can leverage the flexible routing characteristics of Ethernet packets and build flexible topologies using independent switching chips on or between boards or embedded switching accelerators. Traditional inter-chip data transmission methods based on Ethernet packets are overly complex to implement, increasing chip design complexity, requiring more chips, increasing chip area, and power consumption, thereby increasing chip cost. Summary of the Invention

[0004] Embodiments of the present application provide a data transmission method, system, and chip.

[0005] In a first aspect, an embodiment of the present application provides a data transmission method, applied to a first chip, the method comprising:

[0006] receiving an on-chip bus write access request, wherein the on-chip bus write access request includes: valid data;

[0007] Get the configuration information of the encapsulation header;

[0008] The valid data is encapsulated into a first Ethernet packet according to the configuration information of the encapsulation header, and the first Ethernet packet is sent; wherein the first Ethernet packet includes: an encapsulation header and valid data.

[0009] In a second aspect, an embodiment of the present application provides a data transmission method, applied to a second chip, the method comprising:

[0010] Receive a first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data;

[0011] When the encapsulation header includes: a custom header, and the custom header includes: a valid data length and an access address, obtaining the valid data length and the access address from the first Ethernet packet; wherein the access address is an address of the valid data in the memory of the second chip;

[0012] Valid data is obtained from the first Ethernet packet according to the valid data length, and the obtained valid data is written into the access address.

[0013] In a third aspect, an embodiment of the present application provides a chip, comprising: at least one Ethernet transmission module; each Ethernet transmission module comprises: an on-chip bus write access request receiving submodule, a configuration information acquisition submodule, and an Ethernet packet encapsulation and transmission submodule;

[0014] The on-chip bus write access request receiving submodule is configured to receive an on-chip bus write access request; wherein the on-chip bus write access request includes: valid data;

[0015] Configuration information acquisition submodule, used to obtain the configuration information of the encapsulation header;

[0016] The Ethernet packet encapsulation and sending submodule is used to encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data.

[0017] In a fourth aspect, an embodiment of the present application provides a chip, comprising: at least one Ethernet receiving module; each Ethernet receiving module comprises: an Ethernet packet receiving submodule and a data writing submodule;

[0018] The Ethernet packet receiving submodule is configured to receive a first Ethernet packet, wherein the first Ethernet packet includes an encapsulation header and valid data.

[0019] The data writing submodule is used to obtain the valid data length and access address from the first Ethernet packet when the encapsulation header includes: a custom header, and the custom header includes: a valid data length and an access address; wherein the access address is the address of the valid data in the memory of the second chip; obtain valid data from the first Ethernet packet according to the valid data length, and write the obtained valid data into the address range.

[0020] In a fifth aspect, an embodiment of the present application provides a chip, comprising: at least one Ethernet sending module of any one of the above-mentioned types, and at least one Ethernet receiving module of any one of the above-mentioned types.

[0021] In a sixth aspect, an embodiment of the present application provides a data transmission system, including:

[0022] The first chip is configured to receive an intra-chip bus write access request, wherein the intra-chip bus write access request includes valid data; obtain configuration information of an encapsulation header; encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein the first Ethernet packet includes the encapsulation header and the valid data;

[0023] The third chip is used to receive the first Ethernet packet, write the first Ethernet packet into a randomly allocated address in the memory, classify the first Ethernet packet, and then queue it into a queue designated by the central processing unit.

[0024] In a seventh aspect, an embodiment of the present application provides a data transmission system, including:

[0025] The first chip is configured to receive an intra-chip bus write access request, wherein the intra-chip bus write access request includes valid data, valid data length, and an access address, wherein the access address is an address of the valid data in a memory of the second chip; obtain configuration information of an encapsulation header; encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein the first Ethernet packet includes an encapsulation header and valid data; the encapsulation header includes a custom header, and the custom header includes the valid data length and the access address;

[0026] The second chip is used to receive a first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data; when the encapsulation header includes: a custom header, and the custom header includes: a valid data length and an access address, obtain the valid data length and the access address from the first Ethernet packet; obtain valid data from the first Ethernet packet according to the valid data length, and write the obtained valid data into the range address.

[0027] The data transmission method provided in the embodiment of the present application directly encapsulates the valid data into a first Ethernet packet and sends it out when valid data needs to be sent, without having to first write the valid data into a double data rate (DDR), thereby effectively reducing the bandwidth of the DDR; the central processing unit (CPU) is not required to participate in the transmission of valid data, that is, no additional CPU core resources are required; thereby reducing the complexity of chip design, effectively reducing the chip area and power consumption, and thus reducing the chip cost.

[0028] The data transmission method provided in the embodiment of the present application directly obtains valid data from the first Ethernet packet and writes it into the corresponding access address when receiving the first Ethernet packet, without parsing and classifying the first Ethernet packet. The implementation logic is relatively simple, thereby reducing the complexity of chip design, effectively reducing the chip area and power consumption, and thus reducing the cost of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a block diagram of the traditional inter-chip data transmission system;

[0030] Figure 2 A flowchart of a data transmission method provided in one embodiment of the present application;

[0031] Figure 3 A flowchart of a data transmission method provided in another embodiment of the present application;

[0032] Figure 4 A block diagram of a chip according to another embodiment of the present application;

[0033] Figure 5 A block diagram of the chip provided in another embodiment of the present application;

[0034] Figure 6 A block diagram of a data transmission system according to another embodiment of the present application;

[0035] Figure 7 A block diagram of the composition of a data transmission system provided in another embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the technical solution of the present application, the data transmission method, system, and chip provided in the present application are described in detail below with reference to the accompanying drawings.

[0037] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the scope of this application to those skilled in the art.

[0038] In the absence of conflict, the various embodiments of the present application and the various features therein may be combined with each other.

[0039] As used herein, the term "and / or" includes any and all combinations of at least one of the associated listed items.

[0040] The terms used herein are used only to describe specific embodiments and are not intended to limit this application. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of at least one other feature, whole, step, operation, element, component, and / or group thereof is not excluded.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0042] Figure 1 This is a block diagram of the traditional inter-chip data transmission system. Figure 1 As shown, the data processed by the subsystem (SUBSYS) of chip 1 needs to be transferred to the memory (MEM, MEMory) of chip 2. The process is as follows:

[0043] The SUBSYS of chip 1 writes the processed data into the Double Data Rate (DDR) according to the instructions of the Central Processing Unit (CPU). The Ethernet packet transmission accelerator (ETH_TX_ACC) reads the data to be sent from the corresponding address of the DDR according to the instructions of the CPU, encapsulates the read data into an Ethernet packet, and sends it to chip 2.

[0044] Chip 2 receives the Ethernet packet sent by chip 1. The Ethernet packet receiving accelerator (ETH_RX_ACC) writes the received message to a randomly assigned address in the memory, parses and classifies the message, and puts it into the queue specified by the CPU. The CPU takes the message queue identifier (ID, Identity) from the queue and reads the message for processing based on the message queue ID.

[0045] The following problems exist in the process of data transmission between the chips:

[0046] (1) Assuming that the data transmission traffic demand is 50Gbps, the chip 1 needs to reserve 125Gbps (Gbit per second) of DDR bandwidth for the data transmission channel (evaluated based on 40% DDR utilization). Assuming that the frequency of a DDR controller is 3200 MHz and the data bit width is 32 bits, at least one more DDR controller must be designed ( Figure 1 This will undoubtedly increase the complexity of chip design, increase chip area, and increase chip power consumption, thereby increasing the cost of chip application (for example, the larger the chip area, the higher the tape-out cost; the greater the chip power consumption, the more heat dissipation devices are required, and additional DDR particles are required).

[0047] (2) During the data transmission process, chip 1 requires the full participation of the CPU. That is, the CPU needs to issue a send command to ETH_TX_ACC and construct the description or message header structure required for message transmission. Considering the large amount of data flow, at least one CPU core is required to complete this task. Therefore, the design of chip 1 needs to reserve a CPU core for this data transmission channel. The introduction of an additional CPU core increases the complexity of chip design, the chip area, and the chip power consumption, which in turn increases the chip cost.

[0048] (3) After receiving the message, chip 2 needs ETH_RX_ACC to parse and classify the message, which will introduce complex logic, increase the complexity of chip design, increase the chip area, and increase the chip power consumption, thereby increasing the chip cost.

[0049] Figure 2 A flowchart of a data transmission method provided in one embodiment of the present application.

[0050] First, refer to Figure 2 An embodiment of the present application provides a data transmission method, which is applied to a first chip. It should be noted that the first chip refers to a chip that requires inter-chip data transmission, and can be any type of chip, such as a baseband processing chip, a CPU chip, etc.

[0051] The method includes:

[0052] Step 200: Receive an intra-chip bus write access request; wherein the intra-chip bus write access request includes valid data.

[0053] In some exemplary embodiments, the on-chip bus write access request can be initiated by any other data processing module in the first chip (for example, the SUBSYS mentioned above) after processing the data. The valid data is the data obtained after processing the data and needs to be transmitted to the second chip.

[0054] It should be noted that after processing the data, the data processing module generally initiates multiple on-chip bus write access requests for the processed data. That is to say, the valid data in each on-chip bus write access request initiated is only a small part of the processed data. The data processing module can periodically initiate on-chip bus write access requests. After receiving the on-chip bus write access request, if there is no time to process the on-chip bus write access request, the on-chip bus write access request can be temporarily stored in the random access memory (RAM). Since the valid data in the on-chip bus write access request is only a small part of the processed data, temporarily storing the on-chip bus write access request in the RAM does not take up too much storage space, that is, there is no need to reserve too much storage space for data transmission.

[0055] It should be noted that the size of valid data in each initiated on-chip bus write access request can be set arbitrarily according to actual conditions, and generally can be set to an integer multiple of the bus bit width.

[0056] In some exemplary embodiments, since most current mainstream chip designs are based on the Advanced RISC Machine (ARM) core and the on-chip interconnection uses the Advanced eXtensible Interface (AXI) bus, an on-chip bus write access request can be initiated through the AXI bus, thereby combining the AXI bus with Ethernet transmission technology to achieve efficient, simple and flexible direct data transmission.

[0057] It should be noted that with technological development, if the on-chip interconnect uses other types of buses (non-AXI buses), on-chip bus write access requests can also be initiated through other types of buses. The embodiments of this application do not limit the specific type of bus used to receive write access requests, and the specific bus type is not used to limit the scope of protection of the embodiments of this application.

[0058] In some exemplary embodiments, the on-chip bus write access request includes only valid data.

[0059] In some other exemplary embodiments, the intra-chip bus write access request includes: valid data, valid data length and access address; wherein the access address is the address of the valid data in the memory of the second chip, such as an AXI bus write access request.

[0060] It should be noted that if the on-chip bus write access request does not include the valid data length and access address, the receiving chip needs to use the existing receiving chip to realize the reception of the first Ethernet packet. If the second chip proposed in the embodiment of the present application is used to implement it, the writing of valid data cannot be realized. This is because there is no valid data length and access address in the first Ethernet packet, so the second chip cannot know where the valid data should be written in the memory; if the write access request includes the valid data length and access address, then the receiving chip can use the second chip proposed in the embodiment of the present application to implement it.

[0061] Step 201: Obtain configuration information of the encapsulation header.

[0062] In some exemplary embodiments, if the write access request includes a valid data length and an access address, the encapsulation header includes: a custom header, and the custom header includes: a valid data length DATA_LEN and an access address DST_ADDR; if the write access request does not include a valid data length DATA_LEN and an access address DST_ADDR, the encapsulation header also does not include a custom header.

[0063] In some exemplary embodiments, the custom header further includes a reserved field RESERVE, which can be used to adjust the length of the custom header or fill in other information that requires attention.

[0064] It should be noted that the specific positions of the valid data length DATA_LEN and the access address DST_ADDR in the custom header can be set arbitrarily, and the bit width occupied in the custom header can also be set arbitrarily.

[0065] In some exemplary embodiments, the packaging header further includes at least one of the following:

[0066] Ethernet header, Internet Protocol (IP) header, User Datagram Protocol (UDP) header, Transmission Control Protocol (TCP) header.

[0067] In some exemplary embodiments, the IP may be Internet Protocol Version 4 (IPV4) or Internet Protocol Version 6 (IPV6).

[0068] In some example embodiments, the configuration information of the package header may be acquired from the CPU of the first chip.

[0069] In some exemplary embodiments, the custom header can be carried on any layer. For example, the custom header can be carried on L2 (i.e., data link layer), L3 (i.e., network layer), or L4 (i.e., transport layer).

[0070] Specifically, if the custom header is carried in L2, the format of the encapsulation header is: Ethernet header + custom header; then, the configuration information of the encapsulation header includes: the configuration information of the Ethernet header and the configuration information of the custom header;

[0071] If the custom header is carried at L3, the format of the encapsulation header is: Ethernet header + IP header + custom header. The configuration information of the encapsulation header includes: the configuration information of the Ethernet header, the configuration information of the IP header, and the configuration information of the custom header.

[0072] If the custom header is carried at L4, the format of the encapsulation header is: Ethernet header + IP header + UDP header or TCP header + custom header; then the encapsulation header configuration information includes: Ethernet header configuration information, IP header configuration information, UDP header configuration information or TCP header configuration information, and custom header configuration information.

[0073] In some exemplary embodiments, the configuration information of the Ethernet header includes: a Media Access Control (MAC) destination address, a MAC source address, and an Ethernet type (EtherType) field;

[0074] The configuration information of the IP header includes: the IP header type (such as 4 for IPV4 and 6 for IPV6), the IP header length, and the specific IP header field content, which will not be described in detail here; the format and content of the IP header are configured to comply with the RFC791 protocol, wherein the Total Length field and the Header Checksum field are configured to 0, and are updated by the Ethernet transmission module in the first chip; the format and content of the IP header are configured to comply with the RFC8200 protocol, wherein the Payload Length field is configured to 0, and are updated by the Ethernet transmission module in the first chip;

[0075] The format and content of the configured UDP header comply with the RFC768 protocol, wherein the length and checksum fields are configured to be 0 and are updated by the Ethernet sending module in the first chip;

[0076] The configuration information of the TCP header complies with the RFC793 protocol;

[0077] The configuration information of the custom header includes: the length of the custom header, reserved fields, DATA_LEN and DST_ADDR, wherein DATA_LEN and DST_ADDR are configured to 0 and are updated by the Ethernet sending module in the first chip.

[0078] Step 202: Encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data.

[0079] In some exemplary embodiments, the custom header can be carried on any layer. For example, the custom header can be carried on L2 (i.e., data link layer), L3 (i.e., network layer), or L4 (i.e., transport layer).

[0080] Specifically, if the custom header is carried in L2, the format of the first Ethernet packet is: Ethernet header + custom header + valid data;

[0081] If the custom header is carried at L3, the format of the first Ethernet packet is: Ethernet header + IP header + custom header + valid data;

[0082] If the custom header is carried in L4, the format of the first Ethernet packet is: Ethernet header + IP header + UDP header or TCP header + custom header + valid data.

[0083] In some exemplary embodiments, encapsulating valid data into a first Ethernet packet according to configuration information of the encapsulation header includes:

[0084] At least one of an Ethernet header, an IP header, a UDP header or a TCP header is selected for encapsulating a first Ethernet packet according to the access address, and the selected at least one of the Ethernet header, IP header, UDP header or TCP header and a custom header, as well as valid data are encapsulated into the first Ethernet packet.

[0085] In some exemplary embodiments, selecting at least one of an Ethernet header, an IP header, a UDP header, or a TCP header for encapsulating the first Ethernet packet according to the access address includes:

[0086] In the correspondence between at least one of the pre-set Ethernet header, IP header, UDP header or TCP header for encapsulating the first Ethernet packet and the address range, search for at least one of the Ethernet header, IP header, UDP header or TCP header for encapsulating the first Ethernet packet corresponding to the address range where the access address is located.

[0087] It should be noted that different address ranges correspond to different MAC addresses and IP addresses in at least one of the Ethernet header, IP header, UDP header or TCP header used to encapsulate the first Ethernet packet.

[0088] It should be noted that since the MAC addresses and IP addresses of different chips are different, the chip's MAC address and IP address cannot be known when encapsulating the first Ethernet packet. In this case, the address ranges of the memories of different chips can be set to non-overlapping areas, so that different chips can be distinguished.

[0089] In some exemplary embodiments, if the first chip does not include a first switching module and no switching chip is located between the first chip and the second chip, sending the first Ethernet packet includes: sending the first Ethernet packet to the Media Access Control (MAC) layer; the MAC layer performs corresponding processing on the first Ethernet packet to obtain a second Ethernet packet (such as adding a cyclic redundancy check (CRC), adding a preamble, adding padding bytes, etc.); and sending the second Ethernet packet to the second chip via the first Ethernet transmission interface of the first chip. In this method, the reason why a switching chip or a first switching module is not required to implement the transmission of the first Ethernet packet is that it is suitable for point-to-point data transmission with a simple topology.

[0090] In some other exemplary embodiments, if the first chip includes a first switching module and no switching chip is included between the first chip and the second chip, sending the first Ethernet packet includes: sending the first Ethernet packet to the first switching module of the first chip, the first switching module of the first chip sending the first Ethernet packet to the MAC layer, the MAC layer performing corresponding processing on the first Ethernet packet to obtain a second Ethernet packet, and sending the second Ethernet packet to the second chip through the first Ethernet transmission interface of the first chip.

[0091] In other exemplary embodiments, if a switching chip is included between the first chip and the second chip, and the first chip does not include a first switching module, sending the first Ethernet packet includes: sending the first Ethernet packet to the MAC layer, the MAC layer performing corresponding processing on the first Ethernet packet to obtain a second Ethernet packet, and sending the second Ethernet packet to the switching chip through the first Ethernet transmission interface of the first chip.

[0092] The switching chip sends the second Ethernet packet to the second chip.

[0093] In some exemplary embodiments, the first Ethernet transmission interface of the first chip can be a standard 50 or 25 or 10 or 5 Gbps Ethernet transmission interface, or it can be an Ethernet transmission interface of other rates. The embodiments of the present application do not limit the specific rate of the first Ethernet transmission interface, and the size of the specific rate is not used to limit the protection scope of the embodiments of the present application.

[0094] The data transmission method provided in the embodiment of the present application directly encapsulates the valid data into a first Ethernet packet and sends it out when valid data needs to be sent, without having to first write the valid data into a double data rate (DDR), thereby effectively reducing the bandwidth of the DDR; the CPU does not need to be involved in the transmission of valid data, that is, no additional CPU core resources need to be occupied; thereby reducing the complexity of chip design, effectively reducing the chip area and power consumption, and thus reducing the chip cost.

[0095] Figure 3 A flowchart of a data transmission method provided in another embodiment of the present application.

[0096] Secondly, refer to Figure 3 Another embodiment of the present application provides a data transmission method, which is applied to a second chip. It should be noted that the second chip refers to a chip that requires inter-chip data transmission, and can be any type of chip, such as a baseband processing chip, a CPU chip, etc.

[0097] The method includes:

[0098] Step 300: Receive a first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data.

[0099] In some exemplary embodiments, if the second chip does not include a second switching module and no switching chip is included between the first chip and the second chip, the received first Ethernet packet refers to the first Ethernet packet received through the second Ethernet transmission interface of the second chip and obtained after corresponding processing by the MAC layer of the second chip, and the Ethernet packet received by the second Ethernet transmission interface of the second chip is the second Ethernet packet sent by the first chip.

[0100] In some exemplary embodiments, if the second chip includes a second switching module and no switching chip is included between the first chip and the second chip, the received first Ethernet packet refers to the first Ethernet packet obtained after being received through the second Ethernet transmission interface of the second chip, being processed accordingly through the MAC layer of the second chip, and being transmitted through the second switching module of the second chip, and the Ethernet packet received by the second Ethernet transmission interface of the second chip is the second Ethernet packet sent by the first chip.

[0101] In some exemplary embodiments, if a switching chip is included between the first chip and the second chip, and the second chip does not include a second switching module, the received first Ethernet packet refers to the first Ethernet packet received through the second Ethernet transmission interface of the second chip and obtained after corresponding processing by the MAC layer of the second chip, and the Ethernet packet received by the second Ethernet transmission interface of the second chip is the second Ethernet packet sent by the switching chip between the first chip and the second chip.

[0102] In some exemplary embodiments, the second Ethernet transmission interface of the second chip can be a standard 50 or 25 or 10 or 5 Gbps Ethernet transmission interface, or it can be an Ethernet transmission interface of other rates. The embodiments of the present application do not limit the specific rate of the second Ethernet transmission interface, and the size of the specific rate is not used to limit the protection scope of the embodiments of the present application.

[0103] In some exemplary embodiments, after receiving the first Ethernet packet, if there is no time to process the first Ethernet packet, the first Ethernet packet may be temporarily stored in the RAM.

[0104] In some exemplary embodiments, the encapsulation header may or may not include a custom header.

[0105] In some exemplary embodiments, the custom header includes: a valid data length DATA_LEN and an access address DST_ADDR.

[0106] In some exemplary embodiments, the custom header further includes a reserved field RESERVE, which can be used to adjust the length of the custom header or fill in other information that requires attention.

[0107] It should be noted that the specific positions of the valid data length DATA_LEN and the access address DST_ADDR in the custom header can be set arbitrarily, and the bit width occupied in the custom header can also be set arbitrarily.

[0108] In some exemplary embodiments, the packaging header further includes at least one of the following:

[0109] Ethernet header, IP header, UDP header, TCP header.

[0110] In some exemplary embodiments, the IP may be IPV4 or IPV6.

[0111] In some exemplary embodiments, the custom header can be carried on any layer. For example, the custom header can be carried on L2 (i.e., data link layer), L3 (i.e., network layer), or L4 (i.e., transport layer).

[0112] Specifically, if the custom header is carried in L2, the format of the first Ethernet packet is: Ethernet header + custom header + valid data;

[0113] If the custom header is carried at L3, the format of the first Ethernet packet is: Ethernet header + IP header + custom header + valid data;

[0114] If the custom header is carried in L4, the format of the first Ethernet packet is: Ethernet header + IP header + UDP header or TCP header + custom header + valid data.

[0115] Step 301: When the encapsulation header includes a custom header, and the custom header includes a valid data length and an access address, obtain the valid data length and the access address from the first Ethernet packet; wherein the access address is the access address of the valid data in the memory.

[0116] In some exemplary embodiments, when the encapsulation header does not include a custom header, the received first Ethernet packet may be directly discarded.

[0117] In some exemplary embodiments, before obtaining the valid data length and the access address from the first Ethernet packet, the method further includes: obtaining position offset information of the custom header in the first Ethernet packet;

[0118] Obtaining the valid data length and access address from the first Ethernet packet includes: obtaining the valid data length and access address from the first Ethernet packet according to the position offset information. Specifically, obtaining a custom header from the first Ethernet packet according to the position offset information, and obtaining the valid length and access address from the custom header.

[0119] In some exemplary embodiments, the position offset information refers to the offset of the custom header from the start position of the encapsulation header of the first Ethernet packet.

[0120] In some exemplary embodiments, the position offset information of the custom header in the first Ethernet packet may be obtained from the CPU.

[0121] Step 302: Obtain valid data from the first Ethernet packet according to the valid data length, and write the obtained valid data into the access address.

[0122] In some exemplary embodiments, obtaining valid data from the first Ethernet packet according to the valid data length includes: extracting data having a length equal to the valid data length from the payload data of the first Ethernet packet as the valid data.

[0123] In some exemplary embodiments, since most of the current mainstream chip designs are based on ARM cores and the on-chip interconnection uses the AXI bus, the acquired valid data can be written into the access address through the AXI bus, thereby combining the AXI bus with Ethernet transmission technology to achieve efficient, simple and flexible direct data transmission.

[0124] It should be noted that with the development of technology, if the on-chip interconnect uses other types of buses (non-AXI buses), the acquired valid data can also be written to the access address via other types of buses. The embodiments of the present application do not limit the specific type of bus used to write the acquired valid data to the access address, and the specific bus type is not used to limit the scope of protection of the embodiments of the present application.

[0125] The data transmission method provided in the embodiment of the present application directly obtains valid data from the first Ethernet packet and writes it into the corresponding access address when receiving the first Ethernet packet, without parsing and classifying the first Ethernet packet. The implementation logic is relatively simple, thereby reducing the complexity of chip design, effectively reducing the chip area and power consumption, and thus reducing the cost of the chip.

[0126] Figure 4 A block diagram of the chip provided in accordance with another embodiment of the present application.

[0127] Thirdly, refer to Figure 4 Another embodiment of the present application provides a chip, comprising: at least one Ethernet transmission module; each Ethernet transmission module comprises: an intra-chip bus write access request receiving submodule 401, a configuration information obtaining submodule 402, and an Ethernet packet encapsulation and transmission submodule 403;

[0128] The on-chip bus write access request receiving submodule 401 is configured to receive an on-chip bus write access request; wherein the on-chip bus write access request includes: valid data;

[0129] Configuration information acquisition submodule 402, used to obtain configuration information of the encapsulation header;

[0130] The Ethernet packet encapsulation and sending submodule 403 is configured to encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data.

[0131] In some exemplary embodiments, the on-chip bus write access request may be initiated by any other data processing module (e.g., the aforementioned SUBSYS) in the first chip after processing the data. The valid data is the data obtained after the data processing and needs to be transmitted to the second chip. In other words, the chip further includes:

[0132] The data processing module 404 is used to process the data accordingly to obtain valid data and initiate an intra-chip bus write access request.

[0133] It should be noted that after processing the data, the data processing module 404 generally initiates multiple on-chip bus write access requests for the processed data. That is to say, the valid data in each on-chip bus write access request initiated is only a small part of the processed data. The data processing module 404 can periodically initiate on-chip bus write access requests. After receiving the on-chip bus write access request, if there is no time to process the on-chip bus write access request, the on-chip bus write access request can be temporarily stored in the RAM of the on-chip bus write access request receiving sub-module 401. Since the valid data in the on-chip bus write access request is only a small part of the processed data, temporarily storing the on-chip bus write access request in the RAM of the request receiving sub-module 401 does not take up too much storage space, that is, there is no need to reserve too much storage space for data transmission.

[0134] It should be noted that the size of valid data in each initiated on-chip bus write access request can be set arbitrarily according to actual conditions. Generally, it can be set to an integer multiple of the bus bit width connecting the data processing module 404 and the Ethernet sending module.

[0135] In some exemplary embodiments, since most of the current mainstream chip designs are based on ARM cores and the on-chip interconnection uses the AXI bus, an on-chip bus write access request can be initiated through the AXI bus, that is, the data processing module 404 and the Ethernet sending module are interconnected through the AXI bus, thereby combining the AXI bus with the Ethernet transmission technology to achieve efficient, simple and flexible direct data transmission.

[0136] It should be noted that with the development of technology, if the on-chip interconnect uses other types of buses (non-AXI buses), the data processing module 404 and the Ethernet transmission module can also be connected via other types of buses. The embodiments of the present application do not limit the specific type of bus used to connect the data processing module 404 and the Ethernet transmission module, and the specific bus type is not used to limit the scope of protection of the embodiments of the present application.

[0137] In some exemplary embodiments, the on-chip bus write access request includes only valid data.

[0138] In some other exemplary embodiments, the intra-chip bus write access request includes valid data and an address range of the valid data in the memory of the second chip.

[0139] In some other exemplary embodiments, the write access request includes valid data.

[0140] In some other exemplary embodiments, the intra-chip bus write access request includes: valid data, valid data length and access address; wherein the access address is the address of the valid data in the memory of the second chip, such as an AXI bus write access request.

[0141] It should be noted that if the on-chip bus write access request does not include the valid data length and access address, the receiving chip needs to use the existing receiving chip to realize the reception of the first Ethernet packet. If the second chip proposed in the embodiment of the present application is used to implement it, the writing of valid data cannot be realized. This is because there is no valid data length and access address in the first Ethernet packet, so the second chip cannot know where the valid data should be written in the memory; if the write access request includes the valid data length and access address, then the receiving chip can use the second chip proposed in the embodiment of the present application to implement it.

[0142] In some exemplary embodiments, if the write access request includes a valid data length and an access address, the encapsulation header includes: a custom header, and the custom header includes: a valid data length DATA_LEN and an access address DST_ADDR; if the write access request does not include a valid data length DATA_LEN and an access address DST_ADDR, the encapsulation header also does not include a custom header.

[0143] In some exemplary embodiments, the custom header further includes a reserved field RESERVE, which can be used to adjust the length of the custom header or fill in other information that requires attention.

[0144] It should be noted that the specific positions of the valid data length DATA_LEN and the access address DST_ADDR in the custom header can be set arbitrarily, and the bit width occupied in the custom header can also be set arbitrarily.

[0145] In some exemplary embodiments, the packaging header further includes at least one of the following:

[0146] Ethernet header, IP header, UDP header, TCP header.

[0147] In some exemplary embodiments, the IP may be IPV4 or IPV6.

[0148] In some example embodiments, the configuration information of the package header may be acquired from the CPU of the first chip.

[0149] In some exemplary embodiments, the custom header can be carried on any layer. For example, the custom header can be carried on L2 (i.e., data link layer), L3 (i.e., network layer), or L4 (i.e., transport layer).

[0150] Specifically, if the custom header is carried in L2, the format of the encapsulation header is: Ethernet header + custom header; then, the configuration information of the encapsulation header includes: the configuration information of the Ethernet header and the configuration information of the custom header;

[0151] If the custom header is carried at L3, the format of the encapsulation header is: Ethernet header + IP header + custom header. The configuration information of the encapsulation header includes: the configuration information of the Ethernet header, the configuration information of the IP header, and the configuration information of the custom header.

[0152] If the custom header is carried at L4, the format of the encapsulation header is: Ethernet header + IP header + UDP header or TCP header + custom header; then the encapsulation header configuration information includes: Ethernet header configuration information, IP header configuration information, UDP header configuration information or TCP header configuration information, and custom header configuration information.

[0153] In some exemplary embodiments, the configuration information of the Ethernet header includes: a MAC destination address, a MAC source address, and an Ethernet type (EtherType) field;

[0154] The configuration information of the IP header includes: the IP header type (such as 4 for IPV4 and 6 for IPV6), the IP header length, and the specific IP header field content, which are not described in detail here; the format and content of the IP header are configured to comply with the RFC791 protocol, wherein the TotalLength field and the HeaderChecksum field are configured to 0, and are updated by the Ethernet transmission module in the first chip; the format and content of the IP header are configured to comply with the RFC8200 protocol, wherein the PayloadLength field is configured to 0, and are updated by the Ethernet transmission module in the first chip;

[0155] The format and content of the configured UDP header comply with the RFC768 protocol, wherein the Length and Checksum fields are configured to 0 and are updated by the Ethernet sending module in the first chip;

[0156] The configuration information of the TCP header complies with the RFC793 protocol;

[0157] The configuration information of the custom header includes: the length of the custom header, reserved fields, DATA_LEN and DST_ADDR, wherein DATA_LEN and DST_ADDR are configured to 0 and are updated by the Ethernet sending module in the first chip.

[0158] In some exemplary embodiments, the custom header can be carried on any layer. For example, the custom header can be carried on L2 (i.e., data link layer), L3 (i.e., network layer), or L4 (i.e., transport layer).

[0159] Specifically, if the custom header is carried in L2, the format of the first Ethernet packet is: Ethernet header + custom header + valid data;

[0160] If the custom header is carried at L3, the format of the first Ethernet packet is: Ethernet header + IP header + custom header + valid data;

[0161] If the custom header is carried in L4, the format of the first Ethernet packet is: Ethernet header + IP header + UDP header or TCP header + custom header + valid data.

[0162] In some exemplary embodiments, the first Ethernet packet encapsulation and sending submodule 403 is specifically configured to encapsulate the valid data into the first Ethernet packet according to the configuration information of the encapsulation header in the following manner:

[0163] At least one of an Ethernet header, an IP header, a UDP header or a TCP header is selected for encapsulating a first Ethernet packet according to the access address, and the selected at least one of the Ethernet header, IP header, UDP header or TCP header and a custom header, as well as valid data are encapsulated into the first Ethernet packet.

[0164] In some exemplary embodiments, the first Ethernet packet encapsulation and sending submodule 403 is specifically configured to select at least one of an Ethernet header, an IP header, a UDP header, or a TCP header for encapsulating the first Ethernet packet according to the access address in the following manner:

[0165] In the correspondence between at least one of the pre-set Ethernet header, IP header, UDP header or TCP header for encapsulating the first Ethernet packet and the address range, search for at least one of the Ethernet header, IP header, UDP header or TCP header for encapsulating the first Ethernet packet corresponding to the address range where the access address is located.

[0166] It should be noted that different address ranges correspond to different MAC addresses and IP addresses in at least one of the Ethernet header, IP header, UDP header or TCP header used to encapsulate the first Ethernet packet.

[0167] It should be noted that since the MAC addresses and IP addresses of different chips are different, the chip's MAC address and IP address cannot be known when encapsulating the first Ethernet packet. In this case, the address ranges of the memories of different chips can be set to non-overlapping areas, so that different chips can be distinguished.

[0168] In some exemplary embodiments, if the first chip does not include a first switching module, and no switching chip is located between the first chip and the second chip, the Ethernet packet encapsulation and transmission submodule 403 is specifically configured to transmit the first Ethernet packet in the following manner: the first Ethernet packet is transmitted to the MAC layer; the MAC layer processes the first Ethernet packet accordingly to obtain a second Ethernet packet; and the second Ethernet packet is transmitted to the second chip via the first Ethernet transmission interface of the first chip. In this manner, a switching chip or switching module is not required to transmit the first Ethernet packet because it is suitable for point-to-point data transmission with a simple topology. In other words, the chip also includes:

[0169] The first Ethernet transmission interface 405 is configured to send the second Ethernet packet output by the MAC layer to the second chip.

[0170] In other exemplary embodiments, if the first chip includes a first switching module and no switching chip is located between the first chip and the second chip, the Ethernet packet encapsulation and transmission submodule 403 is specifically configured to transmit the first Ethernet packet in the following manner: the first Ethernet packet is transmitted to the first switching module of the first chip; the first switching module of the first chip transmits the first Ethernet packet to the MAC layer; the MAC layer processes the first Ethernet packet accordingly to obtain a second Ethernet packet; and the second Ethernet packet is transmitted to the second chip via the first Ethernet transmission interface of the first chip. In other words, the chip further includes:

[0171] The first switching module 406 is configured to send the first Ethernet packet output by the Ethernet packet encapsulation and sending submodule 403 to the MAC layer, and the MAC layer processes the first Ethernet packet accordingly to obtain a second Ethernet packet;

[0172] The first Ethernet transmission interface 405 is configured to send the second Ethernet packet output by the MAC layer to the second chip.

[0173] In other exemplary embodiments, if a switch chip is included between the first chip and the second chip, and the first chip does not include a first switch module, the Ethernet packet encapsulation and transmission submodule 403 is specifically configured to transmit the first Ethernet packet in the following manner: the first Ethernet packet is transmitted to the MAC layer; the MAC layer processes the Ethernet packet accordingly to obtain a second Ethernet packet; and the second Ethernet packet is transmitted to the switch chip via the first Ethernet transmission interface of the first chip. In other words, the chip further includes:

[0174] The first Ethernet transmission interface 405 is used to send the second Ethernet packet output by the MAC layer to the switching chip.

[0175] The switching chip sends the second Ethernet packet to the second chip.

[0176] In some exemplary embodiments, the first Ethernet transmission interface of the first chip can be a standard 50 or 25 or 10 or 5 Gbps Ethernet transmission interface, or it can be an Ethernet transmission interface of other rates. The embodiments of the present application do not limit the specific rate of the first Ethernet transmission interface, and the size of the specific rate is not used to limit the protection scope of the embodiments of the present application.

[0177] The chip provided in the embodiment of the present application directly encapsulates the valid data into a first Ethernet packet and sends it out when valid data needs to be sent, without having to first write the valid data into a double data rate (DDR), thereby effectively reducing the bandwidth of the DDR. The CPU does not need to be involved in the transmission of valid data, that is, no additional CPU core resources need to be occupied. This reduces the complexity of the chip design, effectively reduces the chip area and power consumption, and thus reduces the cost of the chip.

[0178] It should be noted that all modules and sub-modules on the chip are implemented in hardware, and can be designed and implemented using a hardware description language (such as Verilog or very high-speed integrated circuit hardware description language (VHDL)). The specific implementation circuit is not limited in the embodiments of this application and is not used to limit the scope of protection of the embodiments of this application.

[0179] Figure 5 A block diagram of the chip provided in accordance with another embodiment of the present application.

[0180] Fourthly, refer to Figure 5 Another embodiment of the present application provides a chip, comprising: at least one Ethernet receiving module; each Ethernet receiving module comprises: an Ethernet packet receiving submodule 501 and a data writing submodule 502;

[0181] The Ethernet packet receiving submodule 501 is configured to receive a first Ethernet packet, wherein the first Ethernet packet includes an encapsulation header and valid data.

[0182] The data writing submodule 502 is used to obtain the valid data length and access address from the first Ethernet packet when the encapsulation header includes: a custom header, and the custom header includes: a valid data length and an access address; wherein the access address is the address of the valid data in the memory; obtain the valid data from the first Ethernet packet according to the valid data length, and write the obtained valid data into the access address.

[0183] In some exemplary embodiments, if the second chip does not include a second switching module and no switching chip is included between the first chip and the second chip, the received first Ethernet packet is the first Ethernet packet received through the second Ethernet transmission interface of the second chip and processed by the MAC layer of the second chip, and the Ethernet packet received by the second Ethernet transmission interface of the second chip is the second Ethernet packet sent by the first chip. In other words, the chip further includes:

[0184] The second Ethernet transmission interface 503 is used to receive the second Ethernet packet sent by the first chip, send the received second Ethernet packet to the MAC layer, and the MAC layer performs corresponding processing to obtain the first Ethernet packet, and then sends the first Ethernet packet to the Ethernet packet receiving submodule 501.

[0185] In some exemplary embodiments, if the second chip includes a second switching module and no switching chip is present between the first chip and the second chip, the received first Ethernet packet is a first Ethernet packet received through the second Ethernet transmission interface of the second chip, processed accordingly by the MAC layer of the second chip, and transmitted through the second switching module of the second chip, and the first Ethernet packet received by the second Ethernet transmission interface of the second chip is the second Ethernet packet sent by the first chip. In other words, the chip further includes:

[0186] The second Ethernet transmission interface 503 is used to receive the second Ethernet packet sent by the first chip, send the received second Ethernet packet to the MAC layer, and the MAC layer performs corresponding processing to obtain the first Ethernet packet, and sends the first Ethernet packet to the second switching module 504;

[0187] The second switching module 504 is configured to send the first Ethernet packet to the Ethernet packet receiving submodule 501 .

[0188] In some exemplary embodiments, if a switch chip is included between the first chip and the second chip, and the second chip does not include a second switch module, the received first Ethernet packet is a first Ethernet packet received through the second Ethernet transmission interface of the second chip and processed by the MAC layer of the second chip, and the Ethernet packet received by the second Ethernet transmission interface of the second chip is a second Ethernet packet sent by the switch chip between the first chip and the second chip. In other words, the chip further includes:

[0189] The second Ethernet transmission interface 503 is used to receive the second Ethernet packet sent by the switching chip, send the received second Ethernet packet to the MAC layer, and the MAC layer performs corresponding processing to obtain the first Ethernet packet, and then sends the first Ethernet packet to the Ethernet packet receiving submodule 501.

[0190] In some exemplary embodiments, the second Ethernet transmission interface 503 of the second chip can be a standard 50 or 25 or 10 or 5 Gbps Ethernet transmission interface, or an Ethernet transmission interface of other rates. The embodiment of the present application does not limit the specific rate of the second Ethernet transmission interface 503, and the size of the specific rate is not used to limit the protection scope of the embodiment of the present application.

[0191] In some exemplary embodiments, after the Ethernet packet receiving submodule 501 receives the first Ethernet packet, if the Ethernet packet receiving submodule 501 does not have time to process the first Ethernet packet, the first Ethernet packet may be temporarily stored in the RAM of the Ethernet packet receiving submodule 501 .

[0192] In some exemplary embodiments, the encapsulation header may or may not include a custom header.

[0193] In some exemplary embodiments, the custom header includes: a valid data length DATA_LEN and an access address DST_ADDR.

[0194] In some exemplary embodiments, the custom header further includes a reserved field RESERVE, which can be used to adjust the length of the custom header or fill in other information that requires attention.

[0195] It should be noted that the specific positions of the valid data length DATA_LEN and the address range DST_ADDR in the custom header can be set arbitrarily, and the bit width occupied in the custom header can also be set arbitrarily.

[0196] In some exemplary embodiments, the packaging header further includes at least one of the following:

[0197] Ethernet header, IP header, UDP header, TCP header.

[0198] In some exemplary embodiments, the IP may be IPV4 or IPV6.

[0199] In some exemplary embodiments, the custom header can be carried on any layer. For example, the custom header can be carried on L2 (i.e., data link layer), L3 (i.e., network layer), or L4 (i.e., transport layer).

[0200] Specifically, if the custom header is carried in L2, the format of the first Ethernet packet is: Ethernet header + custom header + valid data;

[0201] If the custom header is carried at L3, the format of the first Ethernet packet is: Ethernet header + IP header + custom header + valid data;

[0202] If the custom header is carried in L4, the format of the first Ethernet packet is: Ethernet header + IP header + UDP header or TCP header + custom header + valid data.

[0203] In some exemplary embodiments, when the encapsulation header does not include a custom header, the data writing submodule 502 may directly discard the received first Ethernet packet.

[0204] In some exemplary embodiments, the chip further includes:

[0205] A position offset information obtaining module 505 is configured to obtain position offset information of the custom header in the first Ethernet packet;

[0206] The data writing submodule 502 is specifically configured to obtain the valid data length and access address from the first Ethernet packet in the following manner: obtaining the valid data length and access address from the first Ethernet packet based on the position offset information. Specifically, a custom header may be obtained from the first Ethernet packet based on the position offset information, and the valid length and access address may be obtained from the custom header.

[0207] In some exemplary embodiments, the position offset information refers to the offset of the custom header from the start position of the encapsulation header of the first Ethernet packet.

[0208] In some exemplary embodiments, the position offset information of the custom header in the first Ethernet packet may be obtained from the CPU.

[0209] In some exemplary embodiments, since most of the current mainstream chip designs are based on ARM cores and the on-chip interconnection uses the AXI bus, the data writing sub-module 502 and the memory can be connected via the AXI bus, thereby combining the AXI bus with Ethernet transmission technology to achieve efficient, simple and flexible direct data transmission.

[0210] It should be noted that with the development of technology, if other types of buses are used for on-chip interconnection, the data writing submodule 502 and the memory can also be connected via other types of buses. This embodiment of the application does not limit the specific type of bus used to connect the data writing submodule 502 and the memory, and the specific bus type is not used to limit the scope of protection of this embodiment of the application.

[0211] The chip provided in the embodiment of the present application, when receiving a first Ethernet packet, directly obtains valid data from the first Ethernet packet and writes it into the corresponding access address without parsing and classifying the first Ethernet packet. The implementation logic is relatively simple, thereby reducing the complexity of the chip design, effectively reducing the chip area and power consumption, and thus reducing the cost of the chip.

[0212] It should be noted that all modules and sub-modules on the chip are implemented in hardware, and can be designed and implemented using a hardware description language (such as Verilog or VHDL). The specific implementation circuit is not limited in the embodiments of this application and is not used to limit the scope of protection of the embodiments of this application.

[0213] In a fifth aspect, another embodiment of the present application provides a chip, comprising: at least one Ethernet sending module of any one of the above-mentioned types, and at least one Ethernet receiving module of any one of the above-mentioned types.

[0214] Figure 6 A block diagram of the composition of a data transmission system provided in another embodiment of the present application.

[0215] Sixth aspect, refer to Figure 6 Another embodiment of the present application provides a data transmission system, including:

[0216] The first chip 601 is configured to receive an intra-chip bus write access request, wherein the intra-chip bus write access request includes valid data; obtain configuration information of an encapsulation header; encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein the first Ethernet packet includes the encapsulation header and the valid data;

[0217] The third chip 602 is configured to receive the first Ethernet packet, write the first Ethernet packet into a randomly allocated address in the memory, classify the first Ethernet packet, and then queue the first Ethernet packet into a queue designated by the central processor.

[0218] In some exemplary embodiments, the on-chip bus write access request may be initiated by any other data processing module in the first chip (e.g., the aforementioned SUBSYS) after processing the data. The valid data is the data obtained after the data processing and needs to be transmitted to the second chip. In other words, the first chip 601 is also used to:

[0219] The data is processed accordingly to obtain valid data, and an on-chip bus write access request is initiated.

[0220] It should be noted that after processing the data, the first chip 601 generally initiates multiple on-chip bus write access requests for the processed data. That is to say, the valid data in each on-chip bus write access request initiated is only a small part of the processed data. The first chip 601 can periodically initiate on-chip bus write access requests. After receiving the on-chip bus write access request, if there is no time to process the on-chip bus write access request, the on-chip bus write access request can be temporarily stored in the RAM of the first chip 601. Since the valid data in the on-chip bus write access request is only a small part of the processed data, temporarily storing the on-chip bus write access request in the RAM of the first chip 601 does not take up too much storage space, that is, there is no need to reserve too much storage space for data transmission.

[0221] It should be noted that the size of valid data in each initiated on-chip bus write access request can be set arbitrarily according to actual conditions. Generally, it can be set to an integer multiple of the bus bit width connecting the data processing module 404 and the Ethernet sending module.

[0222] In some exemplary embodiments, since most of the current mainstream chip designs are based on ARM cores and the on-chip interconnection uses the AXI bus, an on-chip bus write access request can be initiated through the AXI bus, that is, the data processing module 404 and the Ethernet sending module are interconnected through the AXI bus, thereby combining the AXI bus with the Ethernet transmission technology to achieve efficient, simple and flexible direct data transmission.

[0223] It should be noted that with technological development, if other types of buses are used for on-chip interconnection, the data processing module 404 and the Ethernet transmission module may also be connected via other types of buses. This embodiment of the application does not limit the specific type of bus used to connect the data processing module 404 and the Ethernet transmission module, and the specific bus type is not used to limit the scope of protection of this embodiment of the application.

[0224] In some exemplary embodiments, the on-chip bus write access request includes only valid data.

[0225] In some other exemplary embodiments, the on-chip bus write access request includes valid data, valid data length, and an access address.

[0226] In some exemplary embodiments, the packaging header includes at least one of the following:

[0227] Ethernet header, IP header, UDP header, TCP header.

[0228] In some exemplary embodiments, the IP may be IPV4 or IPV6.

[0229] In some example embodiments, the configuration information of the package header may be acquired from the CPU of the first chip.

[0230] In some exemplary embodiments, if the first chip does not include a first switching module, and no switching chip is located between the first chip and the third chip, the first chip 601 is configured to transmit the first Ethernet packet using the following method: the first Ethernet packet is transmitted to the MAC layer. The MAC layer processes the Ethernet packet accordingly to obtain a second Ethernet packet, and the second Ethernet packet is transmitted to the third chip via the first Ethernet transmission interface of the first chip. This method eliminates the need for a switching chip or switching module to transmit the first Ethernet packet because it is suitable for point-to-point data transmission with a simple topology.

[0231] In other exemplary embodiments, if the first chip includes a first switching module and no switching chip is included between the first chip and the third chip, the first chip 601 is specifically used to implement sending the first Ethernet packet in the following manner: sending the first Ethernet packet to the first switching module of the first chip, the first switching module of the first chip sends the first Ethernet packet to the MAC layer, the MAC layer performs corresponding processing on the first Ethernet packet to obtain a second Ethernet packet, and sends the second Ethernet packet to the third chip through the first Ethernet transmission interface of the first chip.

[0232] In other exemplary embodiments, if a switching chip 603 is included between the first chip and the third chip, and the first chip does not include a first switching module, the first chip 601 is specifically used to implement sending the first Ethernet packet in the following manner: sending the first Ethernet packet to the MAC layer, the MAC layer performs corresponding processing on the Ethernet packet to obtain a second Ethernet packet, and sending the second Ethernet packet to the switching chip 603 through the first Ethernet transmission interface of the first chip.

[0233] The switching chip 603 is configured to send the second Ethernet packet to the third chip.

[0234] In some exemplary embodiments, the first Ethernet transmission interface of the first chip can be a standard 50 or 25 or 10 or 5 Gbps Ethernet transmission interface, or it can be an Ethernet transmission interface of other rates. The embodiments of the present application do not limit the specific rate of the first Ethernet transmission interface, and the size of the specific rate is not used to limit the protection scope of the embodiments of the present application.

[0235] The data transmission method provided in the embodiment of the present application directly encapsulates the valid data into a first Ethernet packet and sends it out when valid data needs to be sent, without having to first write the valid data into a double data rate (DDR), thereby effectively reducing the bandwidth of the DDR; the CPU does not need to be involved in the transmission of valid data, that is, no additional CPU core resources need to be occupied; thereby reducing the complexity of chip design, effectively reducing the chip area and power consumption, and thus reducing the chip cost.

[0236] Figure 7 A block diagram of the composition of a data transmission system provided in another embodiment of the present application.

[0237] Seventh aspect, refer to Figure 7 Another embodiment of the present application provides a data transmission system, including:

[0238] The first chip 701 is configured to receive an intra-chip bus write access request, wherein the intra-chip bus write access request includes valid data, valid data length, and an access address; obtain configuration information of an encapsulation header; encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein the first Ethernet packet includes an encapsulation header and valid data; the encapsulation header includes a custom header, and the custom header includes the valid data length and the access address;

[0239] The second chip 701 is used to receive a first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data; when the encapsulation header includes: a custom header, and the custom header includes: a valid data length and an access address, obtain the valid data length and the access address from the first Ethernet packet; obtain valid data from the first Ethernet packet according to the valid data length, and write the obtained valid data into the access address.

[0240] In some exemplary embodiments, the write access request may be initiated by any other data processing module in the first chip (e.g., the aforementioned SUBSYS) after processing the data. The valid data is the data obtained after the data processing and needs to be transmitted to the second chip. In other words, the first chip 601 is also used to:

[0241] Process the data accordingly to obtain valid data and initiate a write access request.

[0242] It should be noted that after processing the data, the first chip 601 generally initiates multiple on-chip bus write access requests for the processed data. That is to say, the valid data in each on-chip bus write access request initiated is only a small part of the processed data. The first chip 601 can periodically initiate on-chip bus write access requests. After receiving the on-chip bus write access request, if there is no time to process the on-chip bus write access request, the on-chip bus write access request can be temporarily stored in the RAM of the first chip 601. Since the valid data in the on-chip bus write access request is only a small part of the processed data, temporarily storing the on-chip bus write access request in the RAM of the first chip 601 does not take up too much storage space, that is, there is no need to reserve too much storage space for data transmission.

[0243] In some exemplary embodiments, the custom header further includes a reserved field RESERVE, which can be used to adjust the length of the custom header or fill in other information that requires attention.

[0244] It should be noted that the specific positions of the valid data length DATA_LEN and the access address DST_ADDR in the custom header can be set arbitrarily, and the bit width occupied in the custom header can also be set arbitrarily.

[0245] In some exemplary embodiments, the packaging header further includes at least one of the following:

[0246] Ethernet header, IP header, UDP header, TCP header.

[0247] In some exemplary embodiments, the IP may be IPV4 or IPV6.

[0248] In some example embodiments, the configuration information of the package header may be acquired from the CPU of the first chip.

[0249] In some exemplary embodiments, the custom header can be carried on any layer. For example, the custom header can be carried on L2 (i.e., data link layer), L3 (i.e., network layer), or L4 (i.e., transport layer).

[0250] Specifically, if the custom header is carried in L2, the format of the encapsulation header is: Ethernet header + custom header; then, the configuration information of the encapsulation header includes: the configuration information of the Ethernet header and the configuration information of the custom header;

[0251] If the custom header is carried at L3, the format of the encapsulation header is: Ethernet header + IP header + custom header. The configuration information of the encapsulation header includes: the configuration information of the Ethernet header, the configuration information of the IP header, and the configuration information of the custom header.

[0252] If the custom header is carried at L4, the format of the encapsulation header is: Ethernet header + IP header + UDP header or TCP header + custom header; then the encapsulation header configuration information includes: Ethernet header configuration information, IP header configuration information, UDP header configuration information or TCP header configuration information, and custom header configuration information.

[0253] In some exemplary embodiments, the configuration information of the Ethernet header includes: a MAC destination address, a MAC source address, and an Ethernet type (EtherType) field;

[0254] The configuration information of the IP header includes: the IP header type (such as 4 for IPV4 and 6 for IPV6), the IP header length, and the specific IP header field content, which are not described in detail here; the format and content of the IP header are configured to comply with the RFC791 protocol, wherein the TotalLength field and the HeaderChecksum field are configured to 0, and are updated by the Ethernet transmission module in the first chip; the format and content of the IP header are configured to comply with the RFC8200 protocol, wherein the PayloadLength field is configured to 0, and are updated by the Ethernet transmission module in the first chip;

[0255] The format and content of the configured UDP header comply with the RFC768 protocol, wherein the Length and Checksum fields are configured to 0 and are updated by the Ethernet sending module in the first chip;

[0256] The configuration information of the TCP header complies with the RFC793 protocol;

[0257] The configuration information of the custom header includes: the length of the custom header, reserved fields, DATA_LEN and DST_ADDR, wherein DATA_LEN and DST_ADDR are configured to 0 and are updated by the Ethernet sending module in the first chip.

[0258] In some exemplary embodiments, the custom header can be carried on any layer. For example, the custom header can be carried on L2 (i.e., data link layer), L3 (i.e., network layer), or L4 (i.e., transport layer).

[0259] Specifically, if the custom header is carried in L2, the format of the first Ethernet packet is: Ethernet header + custom header + valid data;

[0260] If the custom header is carried at L3, the format of the first Ethernet packet is: Ethernet header + IP header + custom header + valid data;

[0261] If the custom header is carried in L4, the format of the first Ethernet packet is: Ethernet header + IP header + UDP header or TCP header + custom header + valid data.

[0262] In some exemplary embodiments, the first chip 601 is specifically configured to encapsulate valid data into a first Ethernet packet according to configuration information of the encapsulation header in the following manner:

[0263] At least one of an Ethernet header, an IP header, a UDP header or a TCP header is selected for encapsulating a first Ethernet packet according to the access address, and the selected at least one of the Ethernet header, IP header, UDP header or TCP header and a custom header, as well as valid data are encapsulated into the first Ethernet packet.

[0264] In some exemplary embodiments, the first chip 601 is specifically configured to select at least one of an Ethernet header, an IP header, a UDP header, or a TCP header for encapsulating the first Ethernet packet according to the access address in the following manner:

[0265] In the correspondence between at least one of the pre-set Ethernet header, IP header, UDP header or TCP header for encapsulating the first Ethernet packet and the address range, search for at least one of the Ethernet header, IP header, UDP header or TCP header for encapsulating the first Ethernet packet corresponding to the address range where the access address is located.

[0266] It should be noted that different address ranges correspond to different MAC addresses and IP addresses in at least one of the Ethernet header, IP header, UDP header or TCP header used to encapsulate the first Ethernet packet.

[0267] It should be noted that since the MAC addresses and IP addresses of different chips are different, the chip's MAC address and IP address cannot be known when encapsulating the first Ethernet packet. In this case, the address ranges of the memories of different chips can be set to non-overlapping areas, so that different chips can be distinguished.

[0268] In some exemplary embodiments, if the first chip does not include a first switching module, and no switching chip is located between the first chip and the second chip, the first chip 601 is specifically configured to transmit the first Ethernet packet using the following method: the first Ethernet packet is transmitted to the MAC layer. The MAC layer processes the Ethernet packet accordingly to obtain a second Ethernet packet, and the second Ethernet packet is transmitted to the second chip via the first Ethernet transmission interface of the first chip. This method does not require a switching chip or switching module to transmit the first Ethernet packet because it is suitable for point-to-point data transmission with a simple topology.

[0269] In some other exemplary embodiments, if the first chip includes a first switching module and no switching chip is included between the first chip and the second chip, the first chip 601 is specifically used to implement sending the first Ethernet packet in the following manner: sending the first Ethernet packet to the first switching module of the first chip, the first switching module of the first chip sends the first Ethernet packet to the MAC layer, the MAC layer performs corresponding processing on the first Ethernet packet to obtain a second Ethernet packet, and sends the second Ethernet packet to the second chip through the first Ethernet transmission interface of the first chip.

[0270] In other exemplary embodiments, if a switching chip 603 is included between the first chip and the second chip, and the first chip does not include a first switching module, the first chip 601 is specifically used to implement sending the first Ethernet packet in the following manner: sending the first Ethernet packet to the MAC layer, the MAC layer performs corresponding processing on the Ethernet packet to obtain a second Ethernet packet, and sending the second Ethernet packet to the switching chip 603 through the first Ethernet transmission interface of the first chip.

[0271] The switching chip 603 is configured to send the second Ethernet packet to the second chip.

[0272] In some exemplary embodiments, the first Ethernet transmission interface of the first chip can be a standard 50 or 25 or 10 or 5 Gbps Ethernet transmission interface, or it can be an Ethernet transmission interface of other rates. The embodiments of the present application do not limit the specific rate of the first Ethernet transmission interface, and the size of the specific rate is not used to limit the protection scope of the embodiments of the present application.

[0273] In some exemplary embodiments, if the second chip does not include a second switching module and no switching chip is included between the first chip and the second chip, the received first Ethernet packet refers to the first Ethernet packet received through the second Ethernet transmission interface of the second chip and obtained after corresponding processing by the MAC layer of the second chip, and the Ethernet packet received by the second Ethernet transmission interface of the second chip is the second Ethernet packet sent by the first chip.

[0274] In some exemplary embodiments, if the second chip includes a second switching module and no switching chip is included between the first chip and the second chip, the received first Ethernet packet refers to the first Ethernet packet obtained after being received through the second Ethernet transmission interface of the second chip, being processed accordingly through the MAC layer of the second chip, and being transmitted through the second switching module of the second chip, and the Ethernet packet received by the second Ethernet transmission interface of the second chip is the second Ethernet packet sent by the first chip.

[0275] In some exemplary embodiments, if a switching chip is included between the first chip and the second chip, and the second chip does not include a second switching module, the received first Ethernet packet refers to the first Ethernet packet received through the second Ethernet transmission interface of the second chip and obtained after corresponding processing by the MAC layer of the second chip, and the Ethernet packet received by the second Ethernet transmission interface of the second chip is the second Ethernet packet sent by the switching chip between the first chip and the second chip.

[0276] In some exemplary embodiments, the second Ethernet transmission interface 503 of the second chip can be a standard 50 or 25 or 10 or 5 Gbps Ethernet transmission interface, or an Ethernet transmission interface of other rates. The embodiment of the present application does not limit the specific rate of the second Ethernet transmission interface 503, and the size of the specific rate is not used to limit the protection scope of the embodiment of the present application.

[0277] In some exemplary embodiments, after the second chip 701 receives the first Ethernet packet, if the second chip 701 does not have time to process the first Ethernet packet, the first Ethernet packet may be temporarily stored in the RAM of the second chip 701 .

[0278] In some exemplary embodiments, when the encapsulation header does not include a custom header, the second chip 701 may directly discard the received first Ethernet packet.

[0279] In some exemplary embodiments, the second chip 701 is further configured to:

[0280] Get the position offset information of the custom header in the first Ethernet packet;

[0281] The second chip 701 is specifically configured to obtain the valid data length and access address from the first Ethernet packet in the following manner: obtaining the valid data length and access address from the first Ethernet packet based on the position offset information. Specifically, a custom header may be obtained from the first Ethernet packet based on the position offset information, and the valid length and access address may be obtained from the custom header.

[0282] In some exemplary embodiments, the position offset information refers to the offset of the custom header from the start position of the encapsulation header of the first Ethernet packet.

[0283] In some exemplary embodiments, the position offset information of the custom header in the first Ethernet packet may be obtained from the CPU.

[0284] The data transmission system provided in the embodiments of the present application, when valid data needs to be sent, directly encapsulates the valid data into a first Ethernet packet and sends it out, without first writing the valid data into a double data rate (DDR), effectively reducing DDR bandwidth. The transmission of valid data also does not require CPU participation, meaning no additional CPU core resources are occupied. This reduces chip design complexity, effectively reduces chip area and power consumption, and thus reduces chip cost. Upon receiving the first Ethernet packet, the valid data is directly retrieved from the first Ethernet packet and written to the corresponding access address, without parsing and classifying the first Ethernet packet. This simplifies the implementation logic, thereby reducing chip design complexity, effectively reducing chip area and power consumption, and thus reducing chip cost.

[0285] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0286] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present application as set forth in the appended claims.

Claims

1. A data transmission method, applied to a first chip, comprising: Receive an intra-chip bus write access request; wherein the intra-chip bus write access request includes: valid data and an access address, and the access address is an address of the valid data in the memory of the second chip; Get the configuration information of the encapsulation header; Encapsulating the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and sending the first Ethernet packet; wherein the first Ethernet packet includes: the encapsulation header and the valid data; The encapsulating the valid data into a first Ethernet packet according to the configuration information of the encapsulation header includes: selecting at least one of the Ethernet header, IP header, UDP header or TCP header for encapsulating the first Ethernet packet according to the access address and a correspondence between at least one of the Ethernet header, IP header, UDP header or TCP header preset for encapsulating the first Ethernet packet and the address range, and encapsulating the selected at least one of the Ethernet header, IP header, UDP header or TCP header and a custom header, as well as the valid data, into the first Ethernet packet.

2. The data transmission method according to claim 1, wherein: The on-chip bus write access request further includes: valid data length; The encapsulation header includes: a custom header, and the custom header includes: the valid data length and the access address.

3. The data transmission method according to claim 2, wherein: The custom header also includes: a reserved field.

4. The data transmission method according to claim 2, wherein: The encapsulation head further includes at least one of the following: Ethernet header, Internet Protocol header, User Datagram Protocol header, Transmission Control Protocol header.

5. A data transmission method, applied to a second chip, comprising: Receive a first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data; When the encapsulation header includes a custom header, and the custom header includes a valid data length and an access address, the valid data length and the access address are obtained from the first Ethernet packet; wherein the access address is an address of the valid data in the memory of the second chip; Valid data is obtained from the first Ethernet packet according to the valid data length, and the obtained valid data is written into the access address. The data transmission method according to claim 5 , wherein: Before obtaining the valid data length and access address from the first Ethernet packet, the method further includes: obtaining position offset information of the custom header in the first Ethernet packet; The acquiring the valid data length and the access address from the first Ethernet packet includes: acquiring the valid data length and the access address from the first Ethernet packet according to the position offset information.

7. A chip comprising: at least one Ethernet transmission module; Each of the Ethernet sending modules includes: an on-chip bus write access request receiving submodule, a configuration information acquiring submodule and an Ethernet packet encapsulation sending submodule; The on-chip bus write access request receiving submodule is configured to receive an on-chip bus write access request; wherein the on-chip bus write access request includes valid data and an access address, wherein the access address is an address of the valid data in the memory of the second chip; The configuration information acquisition submodule is used to obtain the configuration information of the encapsulation header; The Ethernet packet encapsulation and sending submodule is configured to encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein the first Ethernet packet includes: the encapsulation header and the valid data; The encapsulating the valid data into a first Ethernet packet according to the configuration information of the encapsulation header includes: selecting at least one of the Ethernet header, IP header, UDP header or TCP header for encapsulating the first Ethernet packet according to the access address and a correspondence between at least one of the Ethernet header, IP header, UDP header or TCP header preset for encapsulating the first Ethernet packet and the address range, and encapsulating the selected at least one of the Ethernet header, IP header, UDP header or TCP header and a custom header, as well as the valid data, into the first Ethernet packet.

8. The chip according to claim 7, wherein: The on-chip bus write access request further includes: valid data length; The encapsulation header includes: a custom header, and the custom header includes: the valid data length and the access address.

9. A chip comprising: at least one Ethernet receiving module; Each of the Ethernet receiving modules includes: an Ethernet packet receiving submodule and a data writing submodule; The Ethernet packet receiving submodule is configured to receive a first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data; The data writing submodule is used to: When the encapsulation header includes a custom header, and the custom header includes a valid data length and an access address, the valid data length and the access address are obtained from the first Ethernet packet; wherein the access address is an address of the valid data in the memory of the second chip; Valid data is obtained from the first Ethernet packet according to the valid data length, and the obtained valid data is written into the access address.

10. The chip according to claim 9, wherein: The Ethernet receiving module further includes: a position offset information acquisition submodule; The position offset information acquisition submodule is used to obtain the position offset information of the custom header in the first Ethernet packet; The data writing submodule is specifically configured to obtain the valid data length and the access address from the first Ethernet packet in the following manner: obtaining the valid data length and the access address from the first Ethernet packet according to the position offset information.

11. A chip, comprising: At least one Ethernet sending module according to any one of claims 7-8, and at least one Ethernet receiving module according to any one of claims 9-10.

12. A data transmission system comprising: The first chip is used for: Receiving an on-chip bus write access request; wherein the on-chip bus write access request includes: valid data; Get the configuration information of the encapsulation header; Encapsulating the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and sending the first Ethernet packet; wherein the first Ethernet packet includes: the encapsulation header and the valid data; The third chip is used for: A first Ethernet packet is received, the first Ethernet packet is written into a randomly assigned address in a memory, and the first Ethernet packet is classified and then queued into a queue designated by a central processing unit.

13. A data transmission system comprising: The first chip is used for: Receive an intra-chip bus write access request; wherein the intra-chip bus write access request includes: valid data, valid data length and access address; wherein the access address is the address of the valid data in the memory of the second chip; obtain configuration information of the package header; Encapsulating the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and sending the first Ethernet packet; wherein the first Ethernet packet includes: the encapsulation header and the valid data; the encapsulation header includes: a custom header, and the custom header includes: the valid data length and the access address; Encapsulating the valid data into a first Ethernet packet according to the configuration information of the encapsulation header includes: selecting at least one of the Ethernet header, IP header, UDP header, or TCP header for encapsulating the first Ethernet packet according to the access address and a preset correspondence between at least one of the Ethernet header, IP header, UDP header, or TCP header for encapsulating the first Ethernet packet and the address range, and encapsulating the selected at least one of the Ethernet header, IP header, UDP header, or TCP header and a custom header, and the valid data into the first Ethernet packet; The second chip is used for: receiving a first Ethernet packet; Acquire the valid data length and the access address from the first Ethernet packet; Valid data is obtained from the first Ethernet packet according to the valid data length, and the obtained valid data is written into the access address.

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