Mobile phones with flash memory reset function and their flash memory control devices

Abstract

A mobile phone with a flash memory reset function and a flash memory control device thereof, which resolves mobile phone malfunctions caused by abnormal flash memory conditions. The flash memory control device includes: an application processor configured to provide a hold signal and a chip select signal for resetting when determining, based on error information resulting from read errors of an integrated circuit operating by reading flash memory data, that an abnormal condition due to a read error of flash memory data has occurred more than a predetermined number of times; and a flash memory configured to reset the flash memory data upon receiving the hold signal and the chip select signal for resetting.

Description

Technical Field

[0001] The various embodiments generally relate to the control of flash memory, and more specifically, to a mobile phone and a flash memory control device thereof having a flash memory reset function to resolve mobile phone malfunctions caused by abnormal flash memory conditions. Background Technology

[0002] Recently, mobile phones have been manufactured to make calls or run applications, and are configured to display various information about the call or application on the screen, and to control the call or application by touching the screen.

[0003] For this purpose, mobile phones include a display touch panel with screen display function and touch sensing function.

[0004] A display touch panel refers to a panel in which the screen is configured to have both display and touch sensing capabilities.

[0005] For example, a display touch panel can be configured such that the elements configuring the display panel and the elements configuring the touch panel are partially shared. Such a panel can be referred to as an embedded display touch panel.

[0006] Mobile phones may include a touch integrated circuit coupled to a display touch panel. The touch integrated circuit may be configured to provide touch drive signals to the display touch panel for sensing touch, and to receive touch sensing signals from the display touch panel indicating that a touch has been sensed.

[0007] The mobile phone may also include a display integrated circuit coupled to a display touch panel. The display integrated circuit may be configured to provide source signals for displaying the screen to the display touch panel and to receive pixel sensing signals from the display touch panel that have sensed the characteristics of the pixels.

[0008] The mobile phone also includes flash memory for providing firmware and flash data to at least one of the display integrated circuit and the touch integrated circuit.

[0009] The display integrated circuit needs to be configured to perform Demura for eliminating mura on the screen. For this purpose, the flash memory can be configured to store correction values ​​for Demura as flash data, and to provide flash data for Demura in response to reading from the display integrated circuit.

[0010] The touch integrated circuit is configured to use flash memory data stored in the flash memory that stores the touch firmware when the mobile phone is powered on or displayed. For this purpose, the flash memory can be configured to store flash memory data for operation of the touch integrated circuit and to provide flash memory data in response to reading from the touch integrated circuit.

[0011] Typically, due to the effects of electrostatic discharge (ESD), display integrated circuits or touch integrated circuits may abnormally read flash memory data.

[0012] In this situation, the display integrated circuit or touch integrated circuit may malfunction due to abnormal reading of flash memory data.

[0013] Flash memory data read errors caused by electrostatic discharge can usually be resolved by removing and then installing the mobile phone battery or by turning it off and then on again.

[0014] However, resolving flash memory data read errors in this way can cause considerable inconvenience to users and may reduce product reliability.

[0015] Therefore, there is a need to develop technologies that can reliably resolve read errors of flash memory data without causing inconvenience to mobile phone users. Summary of the Invention

[0016] Various embodiments relate to a flash control device that can easily reset the flash data of a flash memory when a read error occurs.

[0017] Furthermore, various embodiments relate to providing a mobile phone with a flash reset function that can easily reset the flash data of the flash memory when a read error occurs in the touch integrated circuit used for flash memory data.

[0018] Furthermore, various embodiments relate to providing a mobile phone with a flash memory reset function that can easily reset the flash memory data when a read error occurs in the display integrated circuit used for flash memory data.

[0019] In an implementation, the flash memory control device may include: a flash memory configured to receive a hold signal and a chip select signal, and to store and provide flash memory data; and an application processor configured to provide a hold signal and a chip select signal for reset when it is determined, based on error information, that an abnormal situation caused by a read error of flash memory data has occurred more than a predetermined number of times, wherein the flash memory resets the flash memory data through the hold signal and the chip select signal for reset.

[0020] In an implementation, a mobile phone with flash memory reset functionality may include: a display touch panel configured to perform display and touch sensing; a touch integrated circuit configured to read flash memory data, provide a touch drive signal for sensing touch to the display touch panel using the flash memory data, receive a touch sensing signal that has been sensed, and provide error information due to a read error in the flash memory data; a flash memory configured to receive a hold signal and a chip select signal, store flash memory data, and provide flash memory data to the touch integrated circuit; and an application processor configured to provide a hold signal and a chip select signal for reset when it is determined, based on the error information, that an abnormal situation caused by a read error in the flash memory data has occurred more than a predetermined number of times, wherein the flash memory resets the flash memory data upon receiving the hold signal and the chip select signal for reset.

[0021] In an implementation, a mobile phone with flash memory reset functionality may include: a display touch panel configured to perform display and touch sensing; a display integrated circuit configured to read flash memory data, provide a source signal for display to the display touch panel using the flash memory data, and provide error information due to read errors in the flash memory data; a flash memory configured to receive a hold signal and a chip select signal, store flash memory data, and provide flash memory data to the display integrated circuit; and an application processor configured to provide a hold signal and a chip select signal for reset when it is determined, based on the error information, that an abnormal situation caused by read errors in the flash memory data has occurred more than a predetermined number of times, wherein the flash memory resets the flash memory data upon receiving the hold signal and the chip select signal for reset.

[0022] According to embodiments of this disclosure, when an abnormal situation caused by a read error of flash memory data occurs more than a predetermined number of times, the flash memory control device can reset the flash memory data of the flash memory by using a hold signal and a chip select signal, thereby easily resetting the flash memory data in response to the abnormal situation.

[0023] Furthermore, according to embodiments of this disclosure, when an abnormal situation occurs more than a predetermined number of times due to a read error in the display integrated circuit or touch integrated circuit used for flash memory data in a mobile phone, the flash memory data can be reset by using a hold signal and a chip select signal, thereby easily resolving the mobile phone malfunction in response to the abnormal situation.

[0024] Therefore, according to embodiments of this disclosure, mobile phones can easily resolve faults in response to abnormal situations caused by read errors in flash memory data, thereby achieving improved product reliability. Attached Figure Description

[0025] Figure 1This is a block diagram illustrating a mobile phone with flash memory reset function according to an embodiment.

[0026] Figure 2 This illustrates the application according to the implementation method. Figure 1 Block diagram of the flash memory control device of a mobile phone.

[0027] Figure 3 yes Figure 2 Detailed block diagram of the application processor.

[0028] Figure 4 This is a waveform diagram illustrating a flash memory data reset method according to an embodiment.

[0029] Figure 5 This is a block diagram illustrating a mobile phone with flash memory reset function according to another embodiment. Detailed Implementation

[0030] A mobile phone with flash memory reset function according to an embodiment of this disclosure can, as follows: Figure 1 The configuration shown is shown.

[0031] refer to Figure 1 The mobile phone may include a display touch panel 10, a display integrated circuit 20, a touch integrated circuit 30, an application processor 40, a flash memory 50, a key module 60, and a power management integrated circuit 70.

[0032] Among these components, the application processor 40 and the power management integrated circuit 70 can be configured as a single integrated circuit according to the manufacturer's needs. The key module 60 can be implemented as a button that electrically interfaces with the application processor 40. However, depending on the manufacturer's intent, the key module 60 can be configured as a touch-type module to provide key signals via touch.

[0033] The display touch panel 10 is used to display a screen and sense user touches. For this purpose, the display touch panel 10 forms the screen of a mobile phone and is configured to implement display and touch functions.

[0034] The display touch panel 10 can be configured to implement display functions using organic light-emitting diodes (OLEDs) or liquid crystals (LCs). As an embodiment of this disclosure, the display touch panel 10 is exemplified by implementing display functions using pixels formed by OLEDs. In embodiments of this disclosure, pixels for implementing display functions and patterns for implementing touch functions of the display touch panel 10 can be implemented in various ways; therefore, detailed descriptions thereof will be omitted.

[0035] The display integrated circuit 20 is configured to receive display data (not shown) from an external source such as a timing controller (not shown), generate a source signal DD corresponding to the display data, and provide the source signal DD to the display touch panel 10.

[0036] The display touch panel 10 has a large number of channels to support the size and resolution of the screen, and the display integrated circuit 20 is configured to provide a source signal DD corresponding to each channel of the display touch panel 10.

[0037] The brightness of each OLED forming each pixel of the display touch panel 10 may change due to degradation. To compensate for this, the display integrated circuit 20 is configured to receive a pixel sensing signal SS for sensing the characteristics of the pixels in each channel of the display touch panel 10.

[0038] The display integrated circuit 20 can be configured to compensate display data according to the degree of pixel degradation by using the received pixel sensing signal SS, and to provide a source signal DD corresponding to the compensated display data for each channel of the display touch panel 10.

[0039] The display touch panel 10 can be configured to have touch functionality via, for example, capacitive touch sensing. The display touch panel 10 can be implemented as an embedded component in which some of the components for touch are shared with the configuration for display.

[0040] In order to perform the touch function, the touch integrated circuit 30 is configured to provide a touch drive signal Tx for sensing touch to the display touch panel 10, and to receive a touch sensing signal Rx that has been sensed.

[0041] The touch integrated circuit 30 is configured to use flash memory data of the flash memory 50 storing the touch firmware when the mobile phone is powered on or displayed.

[0042] Therefore, the touch integrated circuit 30 is configured to read flash memory data when the mobile phone is powered on or displayed, provide a touch drive signal Tx for sensing touch to the display touch panel 10 using the flash memory data, and receive a touch sensing signal Rx from the display touch panel 10 that has been sensed by touch.

[0043] The touch integrated circuit 30 is configured to provide the application processor 40 with error information caused by the read error when a read error occurs due to electrostatic discharge (ESD) affecting the flash memory 50.

[0044] Flash memory 50 can be configured to store touch firmware and flash memory data for operation of touch integrated circuit 30, and to provide flash memory data in response to reading from touch integrated circuit 30.

[0045] The application processor 40 can synchronize display and touch by interfacing with the display integrated circuit 20 and the touch integrated circuit 30.

[0046] The application processor 40 receives error information from the touch integrated circuit 30 due to a read error, and when it determines based on the error information that the abnormal situation caused by the read error of flash memory data has occurred more than a predetermined number of times, it controls the flash memory 50 to perform a reset operation.

[0047] For example, application processor 40 can be configured to provide flash memory 50 with an enabled hold signal HOLD# and a disabled chip select signal CS# for reset, allowing flash memory 50 to perform a reset operation. See later. Figure 2 and Figure 3 To describe the hold signal HOLD# and the chip select signal CS#.

[0048] Flash memory 50 receives the hold signal HOLD# and the chip select signal CS# and performs a reset operation. (See below for further details.) Figure 4 Describe the reset operation.

[0049] The application processor 40 can interface with the key module 60 described above and can be controlled in response to user operations using the key module 60.

[0050] The aforementioned display integrated circuit 20, touch integrated circuit 30, application processor 40, and flash memory 50 require the same or different power for their operation, and said power can be provided from power management integrated circuit 70.

[0051] The power management integrated circuit 70 can provide various voltage levels for analog processes and voltages for digital processes by using an external power supply.

[0052] In the above description, the application processor 40 and the flash memory 50 can be understood as flash memory control devices according to embodiments of the present disclosure.

[0053] Application processor 40 and flash memory 50 can be configured as follows Figure 2 The interface shown is shown in the image.

[0054] exist Figure 2 In the application processor 40, there are a hold signal terminal providing a hold signal HOLD#, a chip select signal terminal providing a chip select signal CS#, a serial clock signal terminal providing a serial clock signal SCLK, a serial input signal terminal providing a serial input signal SI, a serial output signal terminal receiving a serial output signal SO, and a write protect signal terminal providing a write protect signal WP#.

[0055] exist Figure 2In the flash memory 50, there are a power supply terminal with an applied operating voltage VCC, a hold signal terminal for receiving a hold signal HOLD#, a chip select signal terminal for receiving a chip select signal CS#, a serial clock signal terminal for receiving a serial clock signal SCLK, a serial input signal terminal for receiving a serial input signal SI, a serial output signal terminal for providing a serial output signal SO, a write protection signal terminal for receiving a write protection signal WP#, and a ground terminal with an applied ground voltage GDN.

[0056] exist Figure 2 In this configuration, the hold signal terminal for the hold signal HOLD#, the chip select signal terminal for the chip select signal CS#, the serial clock signal terminal for the serial clock signal SCLK, the serial input signal terminal for the serial input signal SI, the serial output signal terminal for the serial output signal SO, and the write protect signal terminal for the write protect signal WP# of the application processor 40 and the flash memory 50 are interconnected to transmit signals.

[0057] exist Figure 2 In this configuration, the hold signal terminal of flash memory 50 is configured to apply a signal with a level corresponding to the enable or disable level of the hold signal HOLD#.

[0058] exist Figure 2 In this configuration, the hold signal HOLD#, the chip select signal CS#, and the write protect signal WP# are provided with a high level for disabling and a low level for enabling.

[0059] The hold signal HOLD# remains high under normal conditions and is disabled, transitioning to a low level to activate for reset operations. The chip select signal CS# remains high when flash memory 50 is not needed and transitions low when flash memory 50 is needed to reset flash memory data. The serial clock signal SCLK is provided with a pulse waveform that switches at a preset frequency to identify the serial input signal SI and the serial output signal SO. The serial input signal SI can be understood as the signal corresponding to the command used to control flash memory 50 via application processor 40, and the serial output signal SO can be understood as the output signal of flash memory data corresponding to the serial input signal SI. The write-protect signal WP# can be activated low to prevent writing to flash memory data and can be deactivated high to allow writing to flash memory data.

[0060] Among these signals, the hold signal HOLD# is switched to a low level to activate the chip, and the chip select signal CS# is switched to a high level to deactivate the chip, in order to perform a reset operation.

[0061] Therefore, application processor 40 can, as Figure 3 The configuration shown is shown.

[0062] refer to Figure 3 The application processor 40 is configured to receive error information ER caused by a read error from the touch integrated circuit 30, and output a hold signal HOLD# for controlling the activation of the flash memory 50 and a chip select signal CS# for deactivation, so that the flash memory 50 performs a reset operation for resetting.

[0063] For this purpose, the application processor 40 is exemplified as including an application control circuit 42, a chip select signal providing circuit 44, a hold signal providing circuit 46, and a clock signal providing circuit 48.

[0064] The application control circuit 42 is configured to receive error information ER, determine based on the error information ER whether an abnormal situation caused by a read error of flash memory data has occurred more than a predetermined number of times, and provide control signals to the chip selection signal providing circuit 44, the hold signal providing circuit 46 and the clock signal providing circuit 48 according to the determination result.

[0065] The hold signal providing circuit 46 is configured to provide a hold signal HOLD# that is disabled to a high level under normal conditions, and to provide a hold signal HOLD# that is switched to a low level and thus enabled for reset when the application control circuit 42 receives a control signal that determines that an abnormal condition caused by a read error of flash data has occurred more than a predetermined number of times.

[0066] The chip select signal providing circuit 44 is configured to provide a chip select signal CS# that is disabled to a high level when access to the flash memory 50 is not required, and to provide a chip select signal CS# that is enabled to a low level when access to the flash memory 50 is required. The chip select signal providing circuit 44 is also configured to provide a chip select signal CS# that is switched to a high level and remains disabled for a predetermined time when it receives a control signal from the application control circuit 42 that indicates an abnormal situation due to a flash memory data read error has occurred more than a predetermined number of times, and simultaneously provides a chip select signal CS# that is enabled to a low level due to the need for access. This is to reset the flash memory data.

[0067] It is understood that the clock signal providing circuit 48 provides the serial clock signal SCLK under the control of the application control circuit 42, and generates and provides the serial clock signal SCLK based on the clock signal provided externally. When the application control circuit 42 receives a control signal indicating that an abnormal situation caused by a read error of flash memory data has occurred more than a predetermined number of times, the clock signal providing circuit 48 can maintain or stop generating the serial clock signal SCLK according to the manufacturer's intention. Since the serial clock signal SCLK does not involve the reset of the flash memory data of flash memory 50, it is understood that the serial clock signal SCLK is unrelated to the reset operation.

[0068] although Figure 3 Although not shown, since the serial input signal SI and the serial output signal SO are independent of the reset operation, they can have levels corresponding to the high impedance state in response to the reset operation.

[0069] When the application processor 40 and flash memory 50 are as Figure 2 and Figure 3 When configured as shown, it can be done as follows Figure 4 The reset operation is performed as shown.

[0070] refer to Figure 4 When the hold signal HOLD# is received and enabled to a low level, a reset operation for resetting flash memory 50 can be initiated. The period during which the reset operation is performed can be understood as the period during which the hold signal HOLD# remains enabled to a low level. When the chip select signal CS# is disabled to a high level for reset, flash memory 50 can perform a flash data reset. When the chip select signal CS# is disabled, flash memory 50 can perform a flash data reset at time RT. To reset the flash data, flash memory 50 can reset the internal logic storing the flash data.

[0071] In the above-mentioned Figures 1 to 4 In this implementation, when the flash data read by the touch integrated circuit 30 from the flash memory 50 is free from errors due to electrostatic discharge, the touch integrated circuit 30 performs normal operation by using the flash data to provide a touch drive signal Tx for sensing touch on the display touch panel 10 and to receive a touch sensing signal Rx that has been sensed.

[0072] At this time, since no error message ER due to a read error of flash memory data is received from the touch integrated circuit 30, the application processor 40 can maintain the hold signal HOLD# in a high-level disabled state and provide the chip select signal CS# in a low-level enabled state for accessing the flash memory 50. At this time, the flash memory 50 does not perform a reset operation to reset the flash memory data.

[0073] However, when an error occurs due to electrostatic discharge affecting the flash data read by the touch integrated circuit 30 from the flash memory 50, the touch integrated circuit 30 provides the application processor 40 with error information ER caused by the flash data read error.

[0074] When an error message ER is received due to a read error of flash data, the application processor 40 determines, based on the error message ER, whether the abnormal situation caused by the read error of flash data has occurred more than a predetermined number of times.

[0075] When it is determined that an abnormal situation caused by a flash memory data read error has occurred more than a predetermined number of times, the application processor 40 can provide an enabled hold signal HOLD#, and then provide a disabled chip select signal CS# for a predetermined time to perform a reset.

[0076] When the enable hold signal HOLD# and the disable chip select signal CS# for reset are provided, the flash memory 50 ignores the status of the serial clock signal SCLK, serial input signal SI, serial output signal SO and write protection signal WP#, enters the reset operation through the enable hold signal HOLD#, and resets the flash memory data at time RT when the chip select signal CS# is disabled by switching to a high level.

[0077] Based on the above description, the embodiments of this disclosure can easily perform flash memory data reset in response to abnormal situations caused by flash memory data read errors, and can easily resolve mobile phone malfunctions.

[0078] At the same time, this disclosure can be as follows Figure 5 The implementation shown is as follows.

[0079] exist Figure 5 In this configuration, the display integrated circuit 20 is configured to read flash memory data, provide a source signal for display to the display touch panel 10 using the flash memory data, and provide error information due to errors in reading the flash memory data.

[0080] The application processor 40 is configured to receive error information from the display integrated circuit 20 and provide a hold signal HOLD# and a chip select signal CS#.

[0081] Flash memory 50 is configured to receive hold signal HOLD# and chip select signal CS#, store flash memory data, and provide flash memory data to display integrated circuit 20 in response to read requests from display integrated circuit 20.

[0082] For example, flash memory 50 can be configured to store correction values ​​for Demura as flash data and provide flash data for Demura in response to reading of display integrated circuit 20.

[0083] exist Figure 5 In the event that an error occurs due to electrostatic discharge affecting the flash memory data read by the display integrated circuit 20 from the flash memory 50, the display integrated circuit 20 provides the application processor 40 with error information ER caused by the read error of the flash memory data.

[0084] When an error message ER is received due to a read error of flash memory data, the application processor 40 determines, based on the error message ER, whether the abnormal situation caused by the read error of flash memory data has occurred more than a predetermined number of times.

[0085] When it is determined that an abnormal situation caused by a flash memory data read error has occurred more than a predetermined number of times, the application processor 40 can provide an enabled hold signal HOLD#, and then provide a disabled chip select signal CS# for a predetermined time to perform a reset.

[0086] When the enable hold signal HOLD# and the disable chip select signal CS# for reset are provided, the flash memory 50 ignores the status of the serial clock signal SCLK, serial input signal SI, serial output signal SO and write protection signal WP#, enters the reset operation through the enable hold signal HOLD#, and resets the flash memory data at time RT when the chip select signal CS# is disabled by switching to a high level.

[0087] In this case, the above operations of application processor 40 and flash memory 50 can be referred to Figures 2 to 4 To understand.

[0088] Therefore, even in Figure 5 In the event of an abnormal situation caused by an error in reading flash memory data by the display integrated circuit 20, the embodiments of this disclosure can also easily perform a flash memory data reset in response to an abnormal situation, and can easily resolve the mobile phone malfunction.

[0089] Therefore, according to embodiments of this disclosure, mobile phones can easily resolve faults in response to abnormal situations caused by read errors in flash memory data, thereby achieving improved product reliability.

Claims

1. A flash memory controller, comprising: Flash memory, including a first hold signal terminal for receiving a hold signal and a first chip select signal terminal for receiving a chip select signal, is configured to store flash memory data and provide the flash memory data in response to a read request from a touch integrated circuit or a display integrated circuit; as well as The application processor includes a second hold signal terminal for providing the hold signal and a second chip select signal terminal for providing the chip select signal. The application processor is configured as follows: Receive error information regarding read errors of the flash memory data from the touch integrated circuit or the display integrated circuit, and When it is determined, based on the error information, that an abnormal situation caused by the read error of the flash memory data has occurred more than a predetermined number of times, the hold signal and the chip select signal are provided. The flash memory resets its data based on the hold signal and the chip select signal received from the application processor.

2. The flash memory control device according to claim 1, wherein, The touch integrated circuit provides touch drive signals for sensing touch and receives touch sensing signals that have been sensed by the touch.

3. The flash memory control device according to claim 1, in, The display integrated circuit provides the source signal for display.

4. The flash memory control device according to claim 1, wherein, The flash memory resets the internal logic storing the flash memory data to reset the flash memory data.

5. The flash memory control device according to claim 1, in, The flash memory includes a power terminal that provides an operating voltage; The holding signal is transmitted through the interface between the first holding signal terminal and the second holding signal terminal. The chip select signal is transmitted through the interface between the first chip select signal terminal and the second chip select signal terminal.

6. The flash memory control device according to claim 1, wherein, When the flash memory receives the chip select signal for reset after receiving the hold signal for reset from the application processor, the flash memory performs a reset of the flash memory data.

7. A mobile phone with flash memory reset function, including: The display touch panel is configured to perform display and touch sensing. The touch integrated circuit is configured to read flash memory data, provide a touch drive signal to the display touch panel for sensing the touch using the flash memory data, receive a touch sensing signal that the touch has been sensed, and is configured to provide error information about a read error of the flash memory data; The flash memory includes a first hold signal terminal for receiving a hold signal and a first chip select signal terminal for receiving a chip select signal, stores the flash memory data, and provides the flash memory data to the touch integrated circuit in response to a read request from the touch integrated circuit; as well as The application processor includes a second hold signal terminal for providing the hold signal and a second chip select signal terminal for providing the chip select signal. The application processor is configured as follows: Receive error information about the read error of the flash memory data from the touch integrated circuit, and When it is determined, based on the error information, that an abnormal situation caused by the read error of the flash memory data has occurred more than a predetermined number of times, the hold signal and the chip select signal are provided. Specifically, when the flash memory receives the hold signal and the chip select signal from the application processor, the flash memory resets the flash memory data.

8. The mobile phone according to claim 7, wherein, The flash memory resets the internal logic storing the flash memory data to reset the flash memory data.

9. A mobile phone with flash memory reset function, including: The display touch panel is configured to perform display and touch sensing. The display integrated circuit is configured to read flash memory data, provide a source signal for display to the display touch panel using the flash memory data, and provide error information about read errors of the flash memory data; Flash memory includes a first hold signal terminal for receiving a hold signal and a first chip select signal terminal for receiving a chip select signal, stores the flash memory data, and provides the flash memory data to the display integrated circuit in response to a read request from the display integrated circuit; as well as The application processor includes a second hold signal terminal for providing the hold signal and a second chip select signal terminal for providing the chip select signal. The application processor is configured as follows: Receive error information about the read error of the flash memory data from the display integrated circuit, and When it is determined, based on the error information, that an abnormal situation caused by a read error of the flash memory data has occurred more than a predetermined number of times, the hold signal and the chip select signal are provided. Specifically, when the flash memory receives the hold signal and the chip select signal for reset from the application processor, the flash memory resets the flash memory data.

10. The mobile phone according to claim 9, wherein, The flash memory resets the internal logic storing the flash memory data to reset the flash memory data.

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