Method for producing a structure comprising a thin layer transferred to a support provided with a charge-trapping layer

Abstract

The invention relates to a method for manufacturing a structure (1) comprising a thin layer (5) transferred onto a support (2) provided with a charge trapping layer (3), the method comprising the following steps: - preparing the support (2), comprising forming a trapping layer (3) on a base substrate (6), the trapping layer (3) having a charge trapping layer of less than 10 18 at / cm 3 The hydrogen concentration is less than 10 20 at / cm 3 The method comprises attaching the support (2) to a donor substrate, comprising a barrier preventing the diffusion of hydrogen into the trapping layer (3) or a dielectric layer (4) with low hydrogen diffusivity; removing a portion of the donor substrate to form a thin layer (5); the manufacturing method exposes the structure (1) to a temperature lower than a maximum temperature of 1000° C. The invention also relates to the structure obtained at the end of the method.

Description

Field of the Invention

[0001] The invention relates to a method for producing a structure comprising a thin layer transferred to a support having a charge-trapping layer. Background Art

[0002] Integrated devices are usually built in the form of wafers on substrates that serve primarily as a support for their manufacture. However, the increasing degree of integration and performance levels expected of these devices has led to an increasingly significant correlation between their performance levels and the characteristics of the substrate on which they are formed. This is particularly true for radio frequency (RF) devices that process signals with frequencies between about 3 kHz and 300 GHz, particularly for the telecommunications sector (telephones, Wi-Fi, Bluetooth, etc.).

[0003] Using the example of device / substrate coupling, the electromagnetic fields originating from high-frequency signals propagating in the device penetrate into the depth of the substrate and interact with possible charge carriers present therein. This results in unnecessary consumption of some of the energy of the signal through insertion losses and possible influences between components through crosstalk.

[0004] Radio frequency devices such as filters, switches and antenna adapters, as well as power amplifiers, can be built on specially tuned substrates that take these phenomena into account and increase performance levels.

[0005] Thus, high-resistivity silicon-on-insulator (HR SOI) substrates are known, which comprise a silicon support substrate having a resistivity greater than 1 kiloohm·cm, a dielectric layer on the support substrate, and a thin silicon surface layer placed on the insulating layer. The substrate may also comprise a charge trapping layer arranged between the support substrate and the dielectric layer. The trapping layer may comprise undoped polysilicon. The manufacture of such substrates is described, for example, in FR2860341, FR2933233, FR2953640, US2015 / 115480, US7268060 or US6544656. Typically, the intention is to limit the temperature and / or duration of the heat treatment applied to such a substrate to avoid recrystallization of the trapping layer, which would reduce its radio frequency performance level.

[0006] There are other reasons why some semiconductor structures cannot be exposed to high temperatures (for example above 600° C. or 1000° C.) during their manufacture or use. This is the case for structures formed by an assembly of two substrates with different thermal expansion coefficients. One of the substrates forms a support for the structure onto which a thin layer obtained from the other substrate is transferred.

[0007] The nature of the thin layer, for example when it consists of a ferroelectric material, may also limit the processing temperature of the structure to its Curie temperature, above which the material loses its permanent polarization.

[0008] In addition, there is sometimes an incentive to limit the exposure temperature of the semiconductor structure when the thin layer contains components. These components can be formed directly on (or in) the structure or transferred to a support to form the structure. At temperatures higher than an exposure temperature of 400°C or 600°C, diffusion of dopants or metals constituting the components can render the components inoperable.

[0009] It is also possible to intentionally limit the temperature to which the structural elements are exposed. This is particularly true when the charge-trapping layer or dielectric layer is formed by LPCVD ("low pressure chemical vapor deposition") or PECVD ("plasma enhanced chemical vapor deposition") techniques. These inexpensive techniques are commonly applicable to a variety of substrates and operate at moderate temperatures of about 600 degrees.

[0010] However, the Applicant has observed that producing structures comprising a layer for trapping charges and a dielectric layer by manufacturing methods using only mild thermal treatments (ie not exposing the structure to temperatures above 1000° C.) results in structures having a much lower radio frequency (RF) performance level than expected.

[0011] As described in the publication "White paper - RF SOI Characterisation" published by SOITEC in January 2015, the RF performance of the substrate can be characterized by the second harmonic distortion measurement HD2. In the case of semiconductor structures including a charge trapping layer and subject to only moderate heat treatment, the applicant has observed that this HD2 characteristic can be between 55% and 75% of the expected value.

[0012] Purpose of the Invention

[0013] The present invention aims to at least partially solve this problem. More specifically, the object of the invention is to propose a method for manufacturing a semiconductor structure comprising transferring a thin layer onto a support provided with a layer for trapping charges, which method does not employ a thermal treatment exposing the structure to high temperatures, but still obtains a structure with a compatible RF performance level.

[0014] Brief description of the invention

[0015] In order to achieve this object, the invention proposes a method for manufacturing a structure comprising a thin layer transferred to a support provided with a charge trapping layer, the method comprising the following steps:

[0016] - preparing the support, comprising forming the capture layer on a base substrate, the capture layer having a thickness of less than 10 18 at / cm 3 The hydrogen concentration;

[0017] - bonding the support to a donor substrate via a dielectric layer having a thickness of less than 1020 at / cm 3 or comprising a barrier that prevents hydrogen from diffusing into the capture layer or having a low hydrogen diffusion rate;

[0018] - removing a portion of the donor substrate to form the thin layer;

[0019] The manufacturing method exposes the structure (1) to a temperature below a maximum temperature of 1000°C.

[0020] Forming a trapping layer with a low hydrogen concentration during the support preparation step avoids over-neutralization of charge trapping in the layer. Forming a dielectric layer that also has a low hydrogen concentration or prevents diffusion of the hydrogen avoids or limits its diffusion into the trapping layer, particularly during the thermal treatments to which the dielectric layer is exposed during the manufacturing method and after the bonding step. Alternatively, a barrier may be provided in the dielectric layer to prevent diffusion of hydrogen from the dielectric layer into the trapping layer.

[0021] According to other advantageous and non-limiting features of the invention, alone or in any technically feasible combination:

[0022] The capture layer is deposited at a deposition temperature between 600° C. and 950° C., and the step of preparing the support body comprises: a first annealing stage of annealing the capture layer (3) in a hydrogen-poor atmosphere at a temperature between the deposition temperature and 1000° C.;

[0023] The capture layer is deposited by LPCVD technology;

[0024] The trapping layer is formed by deposition at a temperature between 950°C and 1100°C;

[0025] The deposition of the capture layer is carried out in an epitaxial frame;

[0026] The dielectric layer is deposited with a thickness greater than 10 20 at / cm 3 A material having a hydrogen concentration of , followed by a second annealing stage in a hydrogen-poor atmosphere is produced;

[0027] The second annealing stage lasts at least one hour at between 800°C and 900°C in a neutral atmosphere;

[0028] By reducing the hydrogen concentration to greater than 10 20 at / cm 3 Depositing a material onto the capture layer to produce the dielectric layer;

[0029] - The dielectric layer is produced by thermal oxidation of the trapping layer at a temperature between 800°C and 1000°C.

[0030] The dielectric layer includes the barrier, and the barrier is in direct contact with the trapping layer;

[0031] The barrier is composed of a SiN or AlN layer;

[0032] The dielectric layer with low hydrogen diffusion rate comprises an oxide having nitrogen and a nitrogen / oxygen ratio greater than or equal to 0.01 or 0.05;

[0033] The dielectric layer with low hydrogen diffusion rate comprises silicon oxide with nitrogen and a nitrogen / oxygen ratio between 0.01 and 0.25 or between 0.05 and 0.1.

[0034] The manufacturing method comprises: a step of forming an embrittlement plane in the donor substrate before the bonding step, and wherein the removing step is performed by fracturing the donor substrate at the embrittlement plane;

[0035] The thin layer is made of piezoelectric material and / or ferroelectric material;

[0036] The thin layer is made of lithium tantalate or lithium niobate.

[0037] According to another aspect, the present invention proposes a structure that cannot be exposed to high temperatures, for example above 600° C. or 1000° C., comprising:

[0038] - base substrate;

[0039] - a trapping layer, the trapping layer being disposed on the base substrate and having a thickness less than 10 18 at / cm 3 The hydrogen concentration;

[0040] - a dielectric layer disposed on the trapping layer, the dielectric layer having a dielectric thickness less than 10 20 at / cm 3 or comprising a barrier preventing hydrogen from diffusing into the capture layer or having a low hydrogen diffusion rate;

[0041] - a thin layer placed on said dielectric layer.

[0042] According to other advantageous and non-limiting features of the invention, alone or in any technically feasible combination:

[0043] The thin layer consists of a ferroelectric material having a permanent polarization and a Curie temperature between 600°C and 1000°C;

[0044] The dielectric layer is in contact with the capture layer and the thin layer;

[0045] The dielectric layer having a low hydrogen diffusion rate comprises an oxide having nitrogen and a nitrogen / oxygen ratio greater than or equal to 0.01 or 0.05;

[0046] The dielectric layer with low diffusivity comprises silicon oxide with nitrogen and a nitrogen / oxygen ratio between 0.01 and 0.25 or between 0.05 and 0.1. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Other features and advantages of the present invention will become apparent from the following detailed description of the invention with reference to the accompanying drawings, in which:

[0048] [ Figure 1 ] Figure 1 A structure is shown, the method of making of which is the object of this description. DETAILED DESCRIPTION

[0049] Figure 1 A structure 1 is shown, the method of manufacturing of which is the object of this description. The structure 1 has a thin surface layer 5, a dielectric layer 4, for example comprising an oxide such as silicon oxide, and a support 2. The support 2 has a charge trapping layer 3 disposed on a substrate 6. The trapping layer 3 is interposed between the dielectric layer 4 and the base substrate 6. Preferably, the dielectric layer 4 is in contact with the trapping layer 3 and the thin layer 5.

[0050] Typically, the structure 1 may be in the form of a circular wafer which may be 100 mm, 200 mm, 300 mm or even 450 mm in diameter.

[0051] As described in the documents forming the prior art presented in the introduction, the structure 1 can be produced in various ways. As a general rule, the structure 1 can be produced by a manufacturing method comprising joining the support 2 and the donor substrate, with the dielectric layer inserted between these two elements, followed by a step of removing a portion of the donor substrate to form the thin layer 5. The step of removing part of the donor substrate can be performed by chemical mechanical thinning of this substrate. Preferably, by applying SmartCut TM The structure 1 is manufactured using a technique according to which a layer for forming a thin layer 5 is defined by means of an embrittlement plane formed by implanting a light substance into a donor substrate. The layer is then removed from the donor substrate by fracture at the embrittlement plane and transferred to a support 2 provided with a capture layer 3 by means of a dielectric layer 4 interposed between the support 2 and the donor substrate.

[0052] The base substrate 6 is typically several hundred microns thick. Preferably, the base substrate has a high resistivity greater than 1000 ohm cm, even more preferably greater than 2000 ohm cm. This therefore limits the density of charges, holes or electrons that may move in the base substrate. However, the present invention is not limited to base substrates 6 having such resistivities, and the present invention also provides RF performance advantages when the base substrate has a more compatible resistivity of about several hundred ohm cm, such as less than 1000 ohm cm, or less than 500 ohm cm or even less than 10 ohm cm.

[0053] For reasons of availability and cost, the base substrate 3 is preferably made of single crystal silicon. For example, it can be a CZ silicon substrate with a low interstitial oxygen content between 6 ppm and 10 ppm, or a FZ silicon substrate with a particularly naturally very low interstitial oxygen content. It can also be a CZ silicon substrate with a high interstitial oxygen content (indicated by the expression "high Oi") greater than 26 ppm. For example, it can be sapphire, glass, quartz, silicon carbide, etc. In certain cases, in particular when the capture layer 3 is sufficiently thick, for example greater than 30 micrometers thick, the base substrate 6 can have a standard resistivity of less than 1 kilo-ohm-cm.

[0054] The trapping layer 3 can be very different in nature, as documented in the literature forming the prior art. In general, it is an amorphous layer with structural defects such as dislocations, grain boundaries, amorphous regions, interstices, inclusions, holes, etc. These structural defects form traps for charges that tend to circulate in the material, for example at incomplete or dangling chemical bonds. This prevents conduction in the trapping layer, which therefore has a high resistivity.

[0055] Advantageously, and for simplicity of implementation, the trapping layer 3 is formed of a polysilicon layer. Its thickness, in particular when it is formed on a resistive base substrate 6, may range from 0.3 μm to 3 μm. However, other thicknesses below or above this range are conceivable, depending on the level of RF performance expected from the structure 1.

[0056] In order to seek to preserve the polycrystalline quality of this layer during the thermal treatments that may be applied to structure 1 , it may be advantageous to provide an amorphous layer, for example made of silicon dioxide, on base substrate 6 before depositing charge-trapping layer 3 .

[0057] Alternatively, the trapping layer 3 can be formed by implanting a relatively heavy substance (for example argon) in the surface thickness of the base substrate 6, in order to form therein structural defects constituting electric traps. This layer 3 can also be formed by porosification of the surface thickness of the base substrate 6 or by any other method capable of forming structural defects in the surface thickness of the substrate 6, which are capable of trapping charges.

[0058] The thin surface layer 5 can be of any suitable type. When the structure 1 is used to accommodate integrated semiconductor components, the thin layer 5 can be composed of single crystal silicon or any other semiconductor material such as germanium, silicon germanium, silicon carbide. When the structure 1 is used to accommodate a surface acoustic wave filter, the thin layer 5 can be composed of piezoelectric and / or ferroelectric materials, such as lithium tantalate or lithium niobate. The thin layer 5 can also include: a finished or semi-finished integrated component formed on a donor substrate and transferred to the support 2 during the step of manufacturing the structure 1. Typically, the thickness of the thin layer can be between 10nm and 10 microns.

[0059] The method for manufacturing the Figure 1 The method of the structure shown. This method constitutes the preliminary experiment leading to the present invention. According to the experimental method, a charge trapping layer 3 of polycrystalline silicon is formed on a silicon-based substrate 6 by deposition using LPCVD technology carried out between 600°C and 650°C. The trapping layer 3 is about 1 micron thick.

[0060] A 300 nm to 1000 nm thick silicon oxide layer, which forms the dielectric layer 4 of the structure 1, is deposited onto the capture layer 3 using a PECVD technique performed at a temperature of 600° C. After this deposition, a densification anneal is performed at 600° C. for about 1 hour in a neutral or oxidizing atmosphere. The layer is then polished by a chemical mechanical polishing step (CMP), resulting in the removal of about 200-800 nanometers of oxide, to provide a surface with a roughness of less than 0.3 nm RMS over an area of ​​5*5 microns.

[0061] The lithium tantalate ferroelectric donor substrate is implanted with hydrogen ions through the first face of the lithium tantalate ferroelectric donor substrate to form a masked embrittlement plane. A first layer is thus defined between the embrittlement plane and the first face of the donor substrate. The donor substrate is bonded to a silicon oxide layer 4 placed on a support 2, and then the donor substrate is fractured at the embrittlement plane using a moderate heat treatment of about 400°C. The first layer of the donor substrate is released to expose the free face of the layer, so that the layer can be prepared to improve crystal quality and surface condition. The preparation includes a step of thinning the first layer by chemical mechanical polishing and a step of heat treatment at 500°C for 1 hour in a neutral atmosphere.

[0062] The RF performance level expected from the resulting structure is estimated by determining the value of the HQF (Harmonic Quality Factor) as taught in US 2015 / 0168326. The HQF value can be estimated from the depth resistivity profiles of the trapping layer 4 and the base substrate 6.

[0063] The structure 1 thus prepared is then subjected to a characterization measurement known as "second harmonic distortion" (HD2). This measurement is carried out at 900 MHz and is documented in the "Whitepaper – RF SOI wafer characterisation" document presented in the introduction. More specifically, a coplanar waveguide is formed by depositing an aluminium wire on the free face of a thin surface layer of lithium tantalate. A signal with a frequency of 900 MHz is then applied to one end of the waveguide and the second harmonic signal HD2 is measured at the other end. The weaker the second harmonic signal, the higher the performance level of the structure.

[0064] The HD2 measurements and HQF estimates are particularly relevant characteristics of structure 1 because they are highly representative of the performance of the integrated RF device that will be formed on the structure.

[0065] Surprisingly, the values ​​of the HD2 characteristics of structure 1 at the end of the method just described correspond only to about 50% to 75% of the expected results provided by the HQF estimation.

[0066] Further studies have enabled the Applicant to realise that this low performance level is related to the presence of excess hydrogen in the charge trapping layer 3 and the dielectric layer 4. The dielectric layer (in this case SiO2) has a carbon content greater than 10 20 at / cm 3 of hydrogen, and the capture layer 3 has more than 10 18 at / cm 3 of hydrogen.

[0067] The dielectric layer 4, which is particularly rich in hydrogen, forms a type of reservoir and, when the difference in hydrogen concentration between the dielectric layer 4 and the trapped layer 3 is too great, and in view of the thermal treatment applied to the structure 1, the hydrogen remaining in this layer 4 is able to diffuse towards the trapped layer 3. The trapped layer is therefore supplied with hydrogen by the dielectric layer 4. This hydrogen is then able to neutralize the electrical traps of the trapped layer 3, in particular at the interface of the trapped layer 3 with the dielectric layer 4. It should be noted that in conventional structures exposed to temperatures exceeding 1000° C., for example in the final stages of finishing the structure, the hydrogen contained in the dielectric layer 4 or in the trapped layer 3 is removed by diffusion during the thermal treatment and, therefore, this difference between the HD2 measurement result and the HQF estimation does not appear significantly.

[0068] The Applicant then exploited these discovered mechanisms to develop a manufacturing method that does not employ thermal treatments that expose the structure to high temperatures, but that produces a structure with compatible RF performance levels. "Compatible" means that the HD2 measurements do not deviate by more than 20% from their HQF estimates.

[0069] In general, the method aims to form a trapping layer 3 with a relatively low hydrogen concentration to avoid over-neutralization of charge traps. It also aims to form a dielectric layer 4 with a low hydrogen concentration or to limit the diffusion of hydrogen to avoid or limit the migration of hydrogen into the trapping layer, taking into account the thermal treatment applied to the structure.

[0070] More specifically, the method repeats the steps just described of preparing the support 2, bonding the support 2 to the donor substrate and removing a portion of the donor substrate. For all the reasons described in the introduction to the present application, the structure 1 cannot be exposed to temperatures exceeding 1000° C. during its manufacture, during the bonding step or after this step. However, in this method, the aim is to form a layer having a thickness of less than 10° C. during the step of preparing the support. 18 at / cm 3 The trapping layer 3 with a low hydrogen concentration is formed to avoid excessive neutralization of the traps in the layer 3. At the same time, the purpose is to form the following dielectric layer 4, which also has a low hydrogen concentration (less than 10 20 at / cm 3 ) or to limit the diffusion of this hydrogen in order to avoid the formation of hydrogen reservoirs that would then be able to diffuse towards the trapping layer 3 or at the interface with this layer. Alternatively, a barrier preventing the diffusion of hydrogen towards the trapping layer may be provided in the dielectric layer. Advantageously, when the dielectric layer does not have a barrier layer or when it is not able to trap the hydrogen it contains, the aim is to limit the hydrogen concentration in the dielectric layer to less than 10 19 at / cm 3 , or even less than 10 18 at / cm 3 .

[0071] Several embodiments are conceivable for producing such a trapping layer 3 and a dielectric layer 4 .

[0072] Thus, according to a first embodiment of the trapping layer 3, it can be formed by deposition at moderate temperatures, for example strictly between 600° C. and 950° C. This can be the deposition of a polysilicon layer formed by LPCVD technology carried out in a deposition furnace. It has been found that such a deposition leads to the formation of a layer comprising more than 10 18 at / cm 3 And usually between this value and 10 19 at / cm 3 The hydrogen concentration in the trapping layer is between 3.

[0073] In order to reduce this concentration, according to this first embodiment, there is a first annealing stage of the trapping layer in a hydrogen-poor atmosphere (ie less than 5 ppm) at a temperature between the deposition temperature and 1000° C. Advantageously, the temperature of the first annealing stage is higher than 620° C. and preferably lower than 900° C., for at least one hour and preferably for several hours. The hydrogen present in the trapping layer 3 diffuses out effectively under these preferential annealing conditions, reducing its concentration to less than 10 18 at / cm 3 threshold without compromising the polycrystalline nature of the trapping layer due to recrystallization effects.

[0074] The first annealing stage can be performed directly after the deposition of the trapping layer 3 or after the formation of the dielectric layer 4 when the dielectric layer 4 is at least partially deposited onto the trapping layer 3, as will be explained in the remainder of this description.

[0075] According to a second embodiment of the trapping layer 3, the trapping layer 3 is deposited on the base substrate 6 at high temperature, for example at a temperature between 950° C. and 1100° C. This can be the deposition of polycrystalline silicon produced in an epitaxial reactor. Under such deposition conditions, the trapping layer 3 has a hydrogen concentration several times lower than that of a layer formed by the LPCVD technique. In all cases, care should be taken to ensure that this concentration is less than 10 18 at / cm 3 In this second embodiment, in which the trapping layer 3 is directly formed so as to have a low hydrogen concentration, the first annealing stage for out-diffusion of hydrogen provided in the previous embodiment is not necessary.

[0076] The dielectric layer 4 can be formed, for its part, by deposition on the capture layer 3. Alternatively, or in addition, it can be formed in whole or in part by deposition on the first face of the donor substrate. It is possible to choose to form the dielectric layer 4 on the support or on the donor substrate, depending on whether they can be exposed to relatively high temperatures.

[0077] Therefore, and according to a first embodiment of the dielectric layer 4, the dielectric layer 4 is manufactured by depositing silicon oxide in a deposition furnace using the PECVD technique. This deposition is carried out at moderate temperatures, typically between 600° C. and 800° C. In this case, the dielectric layer 4 has a thickness greater than 10 20 at / cm 3 The significant hydrogen concentration.

[0078] In order to reduce this concentration, a second annealing stage, called "densification", is applied, similar to the first annealing stage described above. It therefore involves annealing in a hydrogen-poor atmosphere (i.e. less than 5 ppm) and exposing the layer 4 to a temperature higher than its deposition temperature. It can be a neutral or oxidizing atmosphere. Preferably, this temperature is higher than 800° C., typically between 800° C. and 900° C. This annealing lasts at least one hour, and preferably several hours, so as to finally diffuse hydrogen out of the dielectric layer 4 and possibly release hydrogen from the self-trapping layer 3. At the end of this densification annealing, the dielectric layer 4 has a density of less than 10 20 at / cm 3 The hydrogen concentration of the trapping layer 3 is less than 10 18 at / cm 3 of hydrogen concentration.

[0079] It should be noted that the second densification annealing stage may modify the properties of the dielectric layer other than its hydrogen concentration. It may in particular lead to a reduction in the diffusivity of hydrogen, that is to say the ability of this substance to diffuse into the material constituting the dielectric layer, making hydrogen even at relatively high concentrations (about 10 20 at / cm 3 ) is also unlikely to diffuse toward the trapping layer 3.

[0080] It is generally preferred to place the dielectric layer 4 on the support 2 rather than on the donor substrate. In practice, the support 2 can usually be heat treated at the temperature of the first and / or second annealing stage, which is not always the case for the donor substrate. For example, the substrate may have an embrittled plane, or consist of a ferroelectric material with a relatively low Curie temperature, or include components that, in each of these cases, limit the thermal budget that can be applied to it to a relatively short time (i.e. less than 1 hour). However, the invention does not exclude that, in some suitable cases, the dielectric layer 4 can be at least partially formed on the donor substrate.

[0081] When the dielectric layer 4 is formed on the trapping layer 3, and both layers have been deposited at a relatively low temperature, it is not necessary to apply the first and second annealing stages separately after the respective deposition steps, as just described. As already briefly mentioned, a single annealing stage can be performed under conditions similar to the first and second annealing stages after the dielectric layer 4 has been formed on the trapping layer 3 at a low temperature. In other words, in this case, a separate annealing of the trapping layer 3 is not required before the deposition of the dielectric layer 4.

[0082] According to a second embodiment of the dielectric layer 4, the dielectric layer 4 can be produced by thermal oxidation of the capture layer 3. Such a treatment can be carried out by exposing the support 2 provided with the capture layer 3 to an oxidation furnace at a temperature strictly between 800° C. and 1000° C. and in an oxygen-rich atmosphere. It can be a dry or wet atmosphere. As known per se, the duration of this exposure is chosen according to the desired thickness of the dielectric layer 4. It is generally preferred to limit the oxidation temperature to 1000° C. in order to avoid any risk of recrystallization of the capture layer 3. Moreover, according to the second embodiment of this layer already described above, it is preferred to produce such a dielectric layer 3 by oxidation of a capture layer 3 formed at high temperature. In fact, such a layer has a greater temperature stability with respect to the risks of recrystallization.

[0083] When the trapping layer 3 is made of silicon (which is usually the case), the dielectric layer 4 made of silicon dioxide, formed by thermal oxidation of the trapping layer, has a particularly low hydrogen concentration of about a few tenths of a tantalum. 17 at / cm 3 Optionally, a step of polishing the surface of the capture layer 3 thus oxidized may be introduced in order to make it compatible with the subsequent bonding step.

[0084] The dielectric layer 4 can also be prepared according to the third embodiment, which is of particular interest when it is not possible to expose the dielectric layer 4 to relatively high temperatures, for example above 800° C. In this case, the dielectric layer 4 is formed at a relatively low temperature, for example according to the first embodiment of the layer, and care is taken to include in the dielectric layer 4 a barrier for preventing the diffusion of hydrogen into the trapping layer.

[0085] Therefore, and although the dielectric layer 4 may have a thickness greater than 10 20 at / cm 3 The hydrogen concentration of the dielectric layer 4 is reduced, but the diffusion of hydrogen contained in the dielectric layer 4 to the trapping layer 3 is prevented, which in turn has a hydrogen concentration of less than 10 18 at / cm 3 This thus avoids neutralizing the charge traps of this layer 3. In a variant, the dielectric layer 4 consists entirely of a barrier that retains any hydrogen that may be contained therein.

[0086] The barrier may consist of or include a layer of silicon nitride or aluminum nitride, the thickness of which is greater than 10 nanometers and typically between 10 and 100 nanometers. The barrier may be deposited directly onto the capture layer 3, for example by means of a PECVD technique, before forming the remainder of the dielectric layer 4, for example made of silicon dioxide and hydrogen-rich. Alternatively, the barrier may be formed on the donor substrate, and in this case after the remainder of the dielectric layer 4 has been formed, so that the barrier can be brought into contact with the capture layer 3 during the next step of bonding the donor to the support 2.

[0087] In another variation, the barrier layer is composed of a layer having a very low hydrogen concentration (about 10 17 at / cm 3 In this case, the barrier forms a buffer layer that absorbs hydrogen from the dielectric layer and thus prevents hydrogen from diffusing toward the trapping layer 3. In this case, taking into account the thickness of the dielectric layer and its hydrogen concentration, a barrier layer of sufficient thickness will be provided so that after the hydrogen diffuses into the barrier layer, its hydrogen concentration does not exceed 10 20 at / cm 3 This variant can be realized when the dielectric layer is formed by deposition on the donor substrate side, and the barrier is formed by thermal oxidation of the trapping layer 3 , as described in relation to the second embodiment of the dielectric layer 4 .

[0088] According to yet another solution, provision can be made for the dielectric layer 4 to have any concentration of hydrogen, but this layer 4 has a low diffusion rate of this hydrogen, which therefore remains sufficiently trapped therein so as not to diffuse significantly into the trapping layer 3. In this case, the dielectric layer 4 can consist entirely of a layer formed by a material that prevents the diffusion of the hydrogen it contains. Thus, it can involve a deposited oxide with nitrogen and a nitrogen / oxygen ratio greater than or equal to 0.01 or advantageously greater than or equal to 0.05, for example silicon oxide SiO N . When the dielectric layer 4 is based on very ordinary silicon oxide, a nitrogen / oxygen ratio of no more than 0.1 or 0.25 can be chosen so as not to excessively modify the properties of this material and maintain a behavior comparable or close to that of simple silicon oxide SiO2. It should be noted that such a nitrogen-rich oxide layer can be easily formed by deposition techniques such as PECVD, at least one of whose carrier gases can be chosen to be nitrogen, which can be introduced into the oxide layer in a controlled manner. The nitrogen / oxide ratio can be measured by a technique called EDX (Energy Dispersive X-ray Spectroscopy), or established by nitrogen and oxygen measurements determined by SIMS (Secondary Ion Mass Spectrometry) measurements in the oxide layer 4.

[0089] In general, when the structure comprising the following is annealed at 500°C for 1 hour and results in a hydrogen concentration in the trapping layer of less than 10 18 at / cm 3 When , it can be considered that the dielectric layer 4 has a low hydrogen diffusion rate:

[0090] - a dielectric layer comprising a concentration of at least 10 20 at / cm 3 of hydrogen and provided in contact with the layer,

[0091] - Initial concentration is less than 10 18 at / cm 3 A 1 micron trapping layer of hydrogen is made of polysilicon.

[0092] The dielectric layer 4 may consist throughout its thickness of a material with a low diffusion rate, for example a deposited oxide containing nitrogen in the above-mentioned proportions. Alternatively, in the configuration presented in the previous alternative, provision may be made for only one barrier layer to be formed of this material with a low diffusion rate to prevent the diffusion of hydrogen towards the trapping layer 3.

[0093] The bonding step may be preceded by polishing at least some of the contact surfaces, in particular those corresponding to the exposed surfaces of the deposited capture and / or dielectric layers. Furthermore, as has been seen, the bonding step is followed by the removal of a portion of the donor substrate to form the thin layer 5. This removal may be achieved by thinning or breaking the donor substrate. In order to improve the properties of the thin layer 5, a step of preparing the transferred layer may be provided, for example a polishing and / or thermal annealing step.

[0094] The steps of bonding, removing a portion of the donor substrate and preparing the transferred layer are carried out at moderate temperatures, exposing the structure 1 to temperatures always below 1000° C., preferably below 800° C. or 600° C. More generally, the aim is to limit the temperature exposure of the dielectric layer 4 during the manufacturing method, at least during and after the bonding step, so as to limit the diffusion of hydrogen from this layer into the trapping layer 3. As a general rule, the higher the concentration in the dielectric layer (kept below 10 20 at / cm 3 threshold), the more the maximum temperature to which the dielectric layer 4 and the structure 1 are exposed will be limited.

[0095] Regardless of the chosen embodiment of the trapping layer 3 and the dielectric layer 4, at the end of the manufacturing method just described a structure 1 is obtained, such as Figure 1 As shown, it includes:

[0096] - base substrate 6;

[0097] - a capture layer 3, which is arranged on a base substrate 6 and has a thickness of less than 10 18 at / cm 3 The hydrogen concentration;

[0098] - a dielectric layer 4, which is arranged on the capture layer 3 and advantageously in contact with this layer. The dielectric layer 4 has a thickness of less than 10 20 at / cm 3 or includes a barrier to prevent hydrogen diffusion into the capture layer 3, or has any hydrogen concentration but has a very low hydrogen diffusion rate.

[0099] - A thin layer 5 arranged on the dielectric layer 4 and preferably in contact with this layer. This thin layer 5 may consist of a semiconductor material such as silicon, an insulator such as a ferroelectric material or a layer comprising integrated semiconductor components.

[0100] Advantageously, the hydrogen concentration in the dielectric layer is less than 10 19 at / cm 3 , or even 10 18 at / cm 3 .

[0101] The dielectric layer may comprise an oxide with nitrogen and a nitrogen / oxygen ratio greater than or equal to 0.01 or 0.05. In this case, its hydrogen concentration may be arbitrary. It may consist of or contain silicon oxide with nitrogen and a nitrogen / oxygen ratio between 0.01 and 0.25 or between 0.05 and 0.1.

[0102] In case the thin layer consists of a ferroelectric material with a Curie temperature below 1000°C and typically between 600°C and 1000°C, the structure can be manufactured without exposing the thin layer to temperatures above the Curie temperature and thus retaining its permanent polarization.

[0103] For example, a plurality of support bodies 2 are produced, which include a silicon base substrate 6 having a resistivity of 3000 ohm·cm, and a capture layer 3 made of polycrystalline silicon with a thickness of 1 micron and formed by LPCVD, and a dielectric layer made of silicon oxide with a thickness of 300 nanometers and formed by PECVD technology are sequentially produced on the silicon base substrate 6.

[0104] A densification annealing phase of the stack is applied to the first batch of supports thus produced, at a temperature of 600° C. for 1 hour in an atmosphere rich in oxygen and with less than 5 ppm of hydrogen.

[0105] The second and third batches were each exposed to a densification annealing stage according to the invention at a temperature of 800° C. to 900° C. for at least 1 hour, said densification annealing stage being oxygen-rich and having less than 5 ppm of hydrogen.

[0106] After the densification annealing stage, the hydrogen concentrations in the trapping layer ("H Trapping - After Densification") and the dielectric layer ("H Dielectric") were measured.

[0107] Using Smart Cut TM Method A thin surface layer 5 made of lithium tantalate is transferred onto the support 2 of each of these batches. This layer is prepared so that it is finally 600 nm thick. The steps of manufacturing the structure include a mild annealing not exceeding 600° C. On the three batches of structures thus prepared, the hydrogen concentration of the trapping layer 3 (“H-trapping-structures”), the second harmonic (“HD2” - for an applied signal of 15 dBm) and the resistivity distribution of the support 2 are measured to determine the quality factor (“HQF”). Note that this HQF value allows to estimate the desired, compatible value of the RF performance of the structure.

[0108] The average results of the first, second and third batches are shown in the following table:

[0109] Table 1

[0110]

[0111] It can be seen that the RF performance level of the structures of the first batch, which received the treatment from the prior art, is far below the expected (HD2 / HQF ratio of 65%). It can be seen that the hydrogen concentrations in the different layers exceed the limit values, in particular the hydrogen concentration of the trapping layer 3 just after the densification annealing stage ("After Densification") and in the final structure ("Structure").

[0112] In contrast, the RF performance levels of the structures of the second and third batches, which were treated according to the invention, were clearly at the expected levels (HD2 / HQF ratios of 83% and 100%, respectively).

[0113] It can be seen that the hydrogen concentration in the trapping layer 3 measured after the structure is completely manufactured is greater than the concentration measured just after the densification annealing stage. However, this concentration remains less than or equal to 10 18 at / cm 3 This allows the RF performance to remain compatible. Even after being heat treated during the manufacture of the structure 1, the hydrogen present in the dielectric layer does not migrate significantly towards the trapping layer.

[0114] It should be noted that the receptivity of the structure 1 with the trapping layer 3 below the dielectric layer 4 is more sensitive to the hydrogen contained in this layer, the thinner the trapping layer is. In fact, for the same amount of hydrogen diffused from the dielectric layer 4 into the trapping layer 3, the concentration of hydrogen in this trapping layer is greater in a relatively thin trapping layer than in a relatively thick trapping layer. Therefore, the solution of the invention is particularly advantageous when the trapping layer is less than 1 micron or 750 nm thick or less than or equal to 500 nm thick. In such structures with relatively thin trapping layers of less than 1 micron, it is particularly possible to choose to include a barrier layer or SiO2 which limits the diffusion of hydrogen and may have a thickness of, for example, 20-50 nm. N The layer is integrated into the dielectric layer 4 as close as possible to the trapping layer. For example, a silicon oxide layer can be formed on the trapping layer and this layer can be prepared using a nitrogen-based plasma to superficially incorporate this nitrogen before it is bonded to another portion of the dielectric layer 4 arranged on the donor substrate side. A barrier layer made of nitrogen-rich SiO2 is thus formed over the surface thickness of the oxide layer, which prevents the hydrogen contained in the rest of the dielectric layer 4 from diffusing toward the trapping layer.

[0115] As a reminder, the RF performance of a structure has a deterministic influence on the quality factor of the components formed on that structure. Thus, in a further observation, the Applicant has verified that the anti-resonant conductance of a resonator formed on a structure produced using the method according to the invention is directly related to the RF performance of the structure. Such a resonator can be formed by a cross comb formed on a substrate that is the same or similar to those of Batch 1 or Batch 2 described above. The quality factor of such a resonator is generally determined as the ratio between the resistance at the anti-resonant frequency and the bandwidth over which this resistance is more than half. On resonators produced on structures of Batch 2 and Batch 3 according to the invention, this quality factor was evaluated to be much higher than the quality factor of resonators produced on structures of Batch 1.

[0116] Of course, the invention is not limited to the embodiments described and variants may be added without departing from the scope of the invention as defined by the claims.

[0117] In particular, the thin layer 5 may include or be formed from a ferroelectric material, for example LiTaO3, LiNbO3, LiAlO3, BaTiO3, PbZrTiO3, KNbO3, BaZrO3, CaTiO3, PbTiO3 or KTaO3.

[0118] The donor substrate from which the thin layer 5 is obtained may take the form of a circular wafer of standardized size, for example 150 mm or 200 mm in diameter. However, the invention is by no means limited to these sizes or to this shape. The donor substrate may have been removed from a crystalline ingot of ferroelectric material, this removal being carried out so that the donor substrate has a predetermined crystal orientation, or the donor substrate may even comprise a layer of ferroelectric material bonded to a substrate support.

[0119] The crystallographic orientation of the thin layer of ferroelectric material can be selected according to the intended application. Thus, for LiTaO3 material, it is common practice to select an orientation between 30° and 60° XY, or between 40° and 50° XY, especially in cases where the properties of the thin layer are intended to be used to form a surface acoustic wave (SAW) filter. With respect to LiNbO3 material, it is common practice to select an orientation of approximately 128° XY. However, the present invention is in no way limited to a particular crystal orientation.

Claims

1. A method for manufacturing a structure (1), the structure (1) comprising a thin layer (5), the thin layer (5) consisting of a piezoelectric material and / or a ferromagnetic material and being transferred to a support (2) provided with a charge trapping layer (3), the method comprising the following steps: - preparing the support (2), comprising forming the capture layer (3) on a base substrate (6), wherein the capture layer (3) has a thickness of less than 10 18 at / cm 3 The hydrogen concentration; - bonding the support (2) to a donor substrate via a dielectric layer (4) comprising silicon oxide with nitrogen in its entire thickness or in only one barrier layer and with a nitrogen / oxygen ratio between 0.01 and 0.25; - removing a portion of the donor substrate to form the thin layer (5); The manufacturing method exposes the structure (1) to a temperature lower than a maximum temperature of 1000° C. at least during and after the step of bonding.

2. The manufacturing method according to claim 1, wherein: The capture layer (3) is deposited at a deposition temperature between 600°C and 950°C, and the step of preparing the support (2) comprises a first annealing stage of annealing the capture layer (3) in a hydrogen-poor atmosphere at a temperature between the deposition temperature and 1000°C.

3. The manufacturing method according to claim 2, wherein: The trapping layer is deposited by LPCVD technology.

4. The manufacturing method according to claim 1, wherein: The capture layer (3) is formed by deposition at a temperature between 950°C and 1100°C.

5. The manufacturing method according to claim 4, wherein: The deposition of the capture layer (3) is carried out in an epitaxial frame.

6. The manufacturing method according to claim 1, wherein: The nitrogen / oxygen ratio is between 0.05 and 0.

1.

7. The manufacturing method according to claim 1, comprising: The step of bonding is preceded by the step of forming an embrittlement plane in the donor substrate, and wherein the step of removing is performed by fracturing the donor substrate at the embrittlement plane.

8. The manufacturing method according to claim 1, wherein: The thin layer (5) is made of lithium tantalate or lithium niobate.

9. A structure (1), comprising: - a base substrate (6); - a capture layer (3) disposed on the base substrate (6) and having a thickness of less than 10 18 at / cm 3 The hydrogen concentration; a dielectric layer (4) disposed on the trapping layer (3), the dielectric layer (4) comprising silicon oxide with nitrogen and a nitrogen / oxygen ratio between 0.01 and 0.25 throughout its thickness or in only one barrier layer; - a thin layer (5) of piezoelectric and / or ferromagnetic material disposed on the dielectric layer (4).

10. The structure (1) according to claim 9, wherein: The thin layer (5) consists of a ferroelectric material having a permanent polarization and a Curie temperature between 600°C and 1000°C.

11. Structure (1) according to one of claims 9 and 10, wherein: The dielectric layer (4) is in contact with the capture layer (3) and the thin layer (5).

12. The structure (1) according to claim 9, wherein: The nitrogen / oxygen ratio is between 0.05 and 0.1.

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