Memory device, memory system, and method of operating a memory device

Abstract

A memory device includes a plurality of pins to receive a control signal from an external device, a first memory bank having first memory cells, wherein the first memory bank is activated in a first operation mode and a second operation mode, a second memory bank having second memory cells, wherein the second memory bank is deactivated in the first operation mode and activated in the second operation mode, a processing unit configured to perform an operation on first data output from the first memory cells and second data output from the second memory cells in the second operation mode, and a processing-in-memory (PIM) mode controller configured to select mode information indicating one of the first operation mode and the second operation mode in response to the control signal, and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0112495, filed on September 3, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a memory device, a controller for controlling the memory device, a memory system including the memory device, and a method for operating the memory device. Background Technology

[0004] Dynamic Random Access Memory (DRAM) is a type of random access semiconductor memory that stores each bit in a memory cell consisting of capacitors and transistors. Due to its high response speed and high operating speed, DRAM can be used as the main memory of a system. Typically, DRAM writes data or outputs written data under the control of the host. Recently, DRAM has been developed that includes an internal processor configured to perform operations as part of the host or central processing unit (CPU). This paradigm is called processing-in-memory (PIM). Summary of the Invention

[0005] Example embodiments of this disclosure provide a memory device operating in dual operating modes, a memory system including the memory device, a controller for controlling the memory device, and a method for operating the memory device.

[0006] Example embodiments of this disclosure provide a memory device that performs internal operations under optimal environmental conditions, a memory system including the memory device, a controller for controlling the memory device, and a method for operating the memory device.

[0007] The exemplary embodiments of this disclosure provide a memory device implemented with a dual-operation-mode architecture, a memory system including the memory device, a controller for controlling the memory device, and a method for operating the memory device.

[0008] According to an example embodiment of this disclosure, a memory device is provided, comprising: a plurality of pins for receiving control signals from an external device; a first memory bank having a first memory cell, wherein the first memory bank is activated in a first operating mode and a second operating mode; a second memory bank having a second memory cell, wherein the second memory bank is deactivated in the first operating mode and activated in the second operating mode; a processing unit configured to perform operations on first data output from the first memory cell and second data output from the second memory cell in the second operating mode; and a memory processing (PIM) mode controller configured to select mode information indicating one of the first and second operating modes in response to the control signals, and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode based on the mode information.

[0009] According to an example embodiment of this disclosure, a memory system is provided, comprising: a memory device configured to operate in one of a first operating mode and a second operating mode in response to a mode change command, wherein the memory device includes a first memory bank and a second memory bank; and a controller configured to control the memory device, wherein the controller includes a PIM mode generator configured to generate a mode change command for selecting one of the first operating mode and the second operating mode, wherein the memory device includes: a plurality of pins for receiving a plurality of control signals from the controller; a PIM mode controller configured to activate one of the first memory bank and the second memory bank in the first operating mode in response to the mode change command, and to activate at least one of the first memory bank and at least one of the second memory banks in the second operating mode; and a processing unit configured to perform operations on first data output from the activated first memory bank and second data output from the activated second memory bank.

[0010] According to an example embodiment of this disclosure, a method of operating a memory device includes: receiving a mode change request from a controller; changing the operating mode of the memory device in response to the mode change request; receiving an internal operation request in the changed operating mode; and performing an operation on data output from at least two activated storage banks in response to the internal operation request.

[0011] According to an example embodiment of this disclosure, a controller for controlling a memory device is provided. The controller includes: a clock generator configured to generate a clock and output the clock to the memory device; a command address generator configured to generate a command address signal to operate the memory device; a command address transmitter configured to transmit the command address signal in response to the clock; and a PIM mode generator configured to generate a mode change command for selecting one of a first operating mode and a second operating mode, wherein, among a plurality of memory banks of the memory device, one memory bank is activated in response to the operation command in the first operating mode, and at least two memory banks are activated in response to the operation command in the second operating mode, and the operating mode and internal operating environment of the memory device are dynamically changed in response to the mode change command.

[0012] According to an example embodiment of this disclosure, a memory device is provided, comprising: a pin for receiving a mode change command from a controller; a PIM mode controller configured to activate one of a first memory bank and a second memory bank in a first operating mode when the mode change command identifies a first operating mode, and to activate the first memory bank and the second memory bank in a second operating mode when the mode change command identifies a second operating mode; and a processing unit configured to perform operations on first data output when the first memory bank is activated and second data output when the second memory bank is activated. Attached Figure Description

[0013] The above and other features of this disclosure will be more clearly understood by describing exemplary embodiments thereof in conjunction with the accompanying drawings.

[0014] Figure 1 This is a diagram of a memory system according to an exemplary embodiment of the present disclosure.

[0015] Figure 2 This is a view illustrating a memory system according to an example embodiment of the present disclosure.

[0016] Figure 3 This is a view showing a refresh management unit according to an example embodiment of this disclosure.

[0017] Figure 4 This is a view showing a memory parameter management unit according to an example embodiment of the present disclosure.

[0018] Figure 5 This is a view showing the mode register group management unit according to an example embodiment of the present disclosure.

[0019] Figure 6 This is a view illustrating a memory system according to another example embodiment of the present disclosure.

[0020] Figure 7 This is a view illustrating a memory system according to another example embodiment of the present disclosure.

[0021] Figure 8 This is a view illustrating a memory system according to another example embodiment of the present disclosure.

[0022] Figure 9 It shows Figure 8 A view of an example of the opcodes shown.

[0023] Figure 10 This is a view illustrating timing associated with mode changes in a memory system according to an example embodiment of this disclosure.

[0024] Figure 11 This is a view illustrating a memory system according to another example embodiment of the present disclosure.

[0025] Figure 12 It shows the relationship with Figure 11 The view shown depicts the timing associated with the mode change of the memory system.

[0026] Figure 13 This is a view illustrating a memory device according to an example embodiment of the present disclosure.

[0027] Figure 14 This is a ladder diagram illustrating the internal operation process of a memory device according to an example embodiment of the present disclosure.

[0028] Figure 15 This is a view illustrating a memory system performing at least one command / address calibration according to an example embodiment of the present disclosure.

[0029] Figure 16 This is a view illustrating a memory system according to an example embodiment of the present disclosure.

[0030] Figure 17 This is a view illustrating a computing system according to another example embodiment of the present disclosure.

[0031] Figure 18 This is a view illustrating a computing system according to another example embodiment of the present disclosure.

[0032] Figure 19 This is a view showing a data center using a memory device according to an example embodiment of the present disclosure. Detailed Implementation

[0033] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. Throughout the disclosure, similar reference numerals may refer to similar elements.

[0034] Generally, in Process in Memory (PIM) mode, multiple memory banks are activated by a single command, while in normal mode, a single memory bank is activated by a single command. Therefore, the internal operation or operating environment of a memory device can vary significantly depending on its operating mode. Consequently, both the memory device and the controller can dynamically change modes to alter the operating mode.

[0035] In a memory system according to an example embodiment of the present disclosure, information about changes in operating mode can be shared by the memory device and controller, including internal processes, to reduce unnecessary memory setup time (e.g., memory parameter setup time, mode register set (MRS) setup time, etc.) caused by changes in operating mode.

[0036] Figure 1 This is a diagram of a memory system according to an example embodiment. Reference Figure 1 The memory system can change the operating mode of the memory device from normal mode to Process in Memory (PIM) mode, and vice versa. PIM mode is the mode in which the memory device performs operations. Therefore, in normal mode, a single memory bank is activated by a single command, while in PIM mode, multiple memory banks can be activated by a single command.

[0037] In a memory system according to an exemplary embodiment of this disclosure, a memory device having two operating modes can dynamically change its operating mode and dynamically change its internal operating environment based on the operating mode. In an exemplary embodiment of this disclosure, the controller of the memory system can generate commands for controlling the memory device and send these commands to the memory device. It can also internally and dynamically change memory parameters (e.g., tRCD, tRC, tRRD, tFAW, etc.), MRS values ​​(RL, WL, WR, RAS, etc.), and refresh modes provided in the controller to control the memory device. In an exemplary embodiment of this disclosure, the memory device can receive commands for mode changing from the controller and can internally change its internal settings, the values ​​of which are the same as the controller's MRS values. In an exemplary embodiment of this disclosure, the memory device can receive commands for mode changing from the controller and can dynamically change the normal mode in which a single memory bank operates and the PIM mode in which multiple memory banks operate.

[0038] In exemplary embodiments of this disclosure, the controller can generate and apply a full memory precharge command before and after an operating mode change to dynamically change the operating mode of the memory device. In exemplary embodiments of this disclosure, the memory device can receive a mode change command from the controller and can internally perform a full memory precharge operation before and after an operating mode change.

[0039] In the memory system according to an example embodiment of the present disclosure, information associated with the operating mode can be shared by the memory device and the controller to dynamically change the operating mode without unnecessary memory setup time. In other words, each of the memory device and controller according to the present disclosure can be implemented via a dual-mode architecture to dynamically change modes. Therefore, the memory system according to the present disclosure can achieve easy mode changing and optimal performance.

[0040] Figure 2 This is a view illustrating a memory system 10 according to an exemplary embodiment of the present disclosure. References Figure 2 The memory system 10 may include a memory device (MEM) 100 and a controller (CNTL) 200.

[0041] The memory system 10 can be implemented as a multi-chip package (MCP) or a system-on-a-chip (SoC).

[0042] The memory device 100 can be configured to store data received from the controller 200 or to output read data to the controller 200. The memory device 100 can be used as operational memory, working memory, or buffer memory in a computing system. In embodiments of this disclosure, the memory device 100 can be a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a small out-of-line DIMM (SODIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FBDIMM), a column-buffered DIMM (RBDIMM), a miniature DIMM, a micro DIMM, a registered DIMM (RDIMM), or a load-reducing DIMM (LRDIMM).

[0043] In embodiments of this disclosure, memory device 100 may be volatile memory. For example, volatile memory may include at least one of the following: Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Low Power Double Data Rate SDRAM (LPDDR SDRAM), Graphics Double Data Rate SDRAM (GDDR SDRAM), Rambus DRAM (RDRAM), and Static RAM (SRAM). In another embodiment of this disclosure, memory device 100 may be non-volatile memory. For example, non-volatile memory may include one of the following: NAND flash memory, Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and NOR flash memory.

[0044] Memory device 100 may include a serial presence detection (SPD) chip. The SPD chip may be configured to store information related to the characteristics of memory device 100. In embodiments of this disclosure, the SPD chip may store memory device information such as the module type, operating environment, wiring layout, module configuration, and storage capacity of memory device 100. In embodiments of this disclosure, the SPD chip may include a programmable read-only memory, such as an electrically erasable programmable read-only memory (EEPROM). Memory device 100 may include a PIM mode controller 101, a first memory bank 105, a second memory bank 106, a processing unit (ALU) 107, and a memory interface circuit (MEM I / F) 110.

[0045] The PIM mode controller 101 can be configured to: select mode information indicating a normal mode (or, a first operating mode) or a PIM mode (or, a second operating mode) in response to control signals received via multiple pins; and control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode in response to the selected mode information. Additionally, the PIM mode controller 101 may include a mode memory 102, a memory parameter controller 103, and an MRS controller 104.

[0046] The pattern memory 102 can be configured to store one of the normal mode and the PIM mode.

[0047] The memory parameter controller 103 can be configured to change the parameters of the memory device 100 according to the operating mode stored in the mode memory 102. The memory parameters may include activation (ACT) to internal read or write latency time (tRCD), ACT to ACT or REF command cycle (tRC), ACT to ACT command latency (tRRD), four-active window (tFAW), etc.

[0048] MRS controller 104 can be configured to change the mode register set (MRS) according to the operating mode stored in mode memory 102. In this case, RL (AL+CL), write latency (WL), CAS latency (CL), write command (WR), row address strobe (RAS), column address strobe (CAS), etc., can be stored in the MRS.

[0049] One of the first memory bank 105 and the second memory bank 106 can be configured to perform read or write operations in normal mode. In embodiments of this disclosure, one of the first memory bank 105 and the second memory bank 106 can be activated in normal mode.

[0050] The first storage bank 105 and the second storage bank 106 can be configured to operate simultaneously in PIM mode. In embodiments of this disclosure, the first storage bank 105 and the second storage bank 106 can be activated simultaneously in PIM mode. For ease of description, Figure 1 Only two memory banks, 105 and 106, are shown in the diagram. However, more than two memory banks can be provided in the memory device 100.

[0051] The processing unit PE (ALU) 107 can be configured to perform operations on first data in the first memory bank 105 and second data in the second memory bank 106 in PIM mode. Similarly, the processing unit PE (ALU) 107 can be configured to perform operations on third data in the third memory bank and fourth data in the fourth memory bank.

[0052] The memory interface circuit 110 can be configured to provide an interface connection with the host interface circuit (host I / F) 210 of the controller 200. The memory interface circuit 110 can be connected to the controller 200 via multiple pins. These pins may include pins for transmitting clock signals CLK, pins for transmitting control signals C and R, and pins for transmitting data DQ. The controller 200 can be connected to the memory device 100 via multiple pins and can be configured to control the memory device 100. The controller 200 may include a pattern generator 201, a refresh management unit 202, a memory parameter management unit 203, an MRS management unit 204, and the host interface circuit 210.

[0053] Pattern generator 201 can be configured to generate normal patterns and PIM patterns using refresh-related pattern information, memory parameter-related pattern information, or MRS-related pattern information.

[0054] The refresh management unit 202 can be configured to output refresh-related mode information. For example, the refresh management unit 202 can output per-bank refresh (PBR) mode information corresponding to the normal mode and full-bank refresh (ABF) mode information corresponding to the PIM mode.

[0055] The memory parameter management unit 203 can be configured to output memory parameter-related mode information. For example, the memory parameter management unit 203 can output memory parameter mode information corresponding to the normal mode and memory parameter mode information corresponding to the PIM mode.

[0056] MRS management unit 204 can be configured to output MRS-related mode information. For example, MRS management unit 204 can output MRS mode information corresponding to the normal mode and MRS mode information corresponding to the PIM mode.

[0057] The pattern generator 201, refresh management unit 202, memory parameter management unit 203, and MRS management unit 204 can be collectively referred to as the pattern controller. The pattern controller can be implemented through circuitry.

[0058] In embodiments of this disclosure, the controller 200 may be configured as an additional chip or may be integrated with the memory device 100. For example, the controller 200 may be implemented on a motherboard. Alternatively, the controller 200 may be an integrated memory controller (IMC) included in a microprocessor. Alternatively, the controller 200 may be located in an input / output hub. Furthermore, the input / output hub including the controller 200 may be referred to as a memory controller hub (MCH).

[0059] Generally, a change in PIM mode causes a change in the internal operation of the memory device. For example, a normal read has a read latency corresponding to the time it takes to send cell data to the input / output terminals in response to a read command. On the other hand, a PIM read has a read latency corresponding to the time it takes to send cell data to the input / output terminals in response to a read command. Since multiple memory banks operate simultaneously in PIM mode, the PIM mode can vary depending on the internal noise environment. For this purpose, the parameter associated with the core margin is binary.

[0060] The memory system 10 according to an example embodiment of this disclosure can change refresh, memory parameters, or MRS according to normal mode / PIM mode. Therefore, the memory system 10 can establish an optimal environment based on the operating mode to significantly improve PIM operation performance. Furthermore, the memory system 10 can initiate operations to change between normal mode and PIM mode to prevent invalid memory operations. Additionally, the memory system 10 can prevent unnecessary settings when changing operating modes to improve overall system performance. Moreover, when the memory system 10 is not operating in PIM mode, it can prevent performance degradation of the memory device.

[0061] The dual-mode architecture of the controller 200 for dynamic mode changing will be described in more detail below.

[0062] Figure 3 This is a view illustrating a refresh management unit 202 according to an example embodiment of this disclosure. References Figure 3 The refresh management unit 202 may include a refresh command generator 202-1 and a decoder 202-2.

[0063] The refresh command generator 202-1 can generate a first refresh signal corresponding to the normal mode and a second refresh signal corresponding to the PIM mode. In embodiments of this disclosure, the first refresh signal and the second refresh signal can be complementary to each other. The first refresh signal and the second refresh signal can be provided from the refresh command generator 202-1 to the decoder 202-2. The first refresh signal and the second refresh signal can be output via different pins.

[0064] Decoder 202-2 can output one of the first refresh signal and the second refresh signal as refresh-related mode information (REF).

[0065] Figure 4 This is a view illustrating a memory parameter management unit 203 according to an exemplary embodiment of the present disclosure. Reference Figure 4 The memory parameter management unit 203 may include a memory parameter counter 203-1 and a decoder 203-2.

[0066] The memory parameter counter 203-1 can generate a first memory parameter signal corresponding to the normal mode and a second memory parameter signal corresponding to the PIM mode. In embodiments of this disclosure, the first memory parameter signal and the second memory parameter signal can be complementary to each other.

[0067] Decoder 203-2 can output one of the first memory parameter signal and the second memory parameter signal as memory parameter related mode information (MPS). For example, when receiving one of the first memory parameter signal and the second memory parameter signal, decoder 203-2 can output memory parameter related mode information (MPS).

[0068] For ease of description, Figure 4 Only one memory parameter counter is shown, but it will be understood that this disclosure is not limited thereto.

[0069] Figure 5 This is a view illustrating an MRS management unit 204 according to an example embodiment of this disclosure. Reference Figure 5 The MRS management unit 204 may include WR counter 204-1, WL counter 204-3, RAS counter 204-5, and decoders 204-2, 204-4 and 204-6.

[0070] WR counter 204-1 can generate a first WR signal corresponding to the normal mode and a second WR signal corresponding to the PIM mode. In embodiments of this disclosure, the first WR signal and the second WR signal can be complementary to each other. Decoder 204-2 can receive one of the first WR signal and the second WR signal from WR counter 204-1 and output one of the first WR signal and the second WR signal as WR MRS related mode information MRS1.

[0071] WL counter 204-3 can generate a first WL signal corresponding to the normal mode and output it through a first pin, and generate a second WL signal corresponding to the PIM mode and output it through a second pin. In embodiments of this disclosure, the first WL signal and the second WL signal can be complementary signals. Decoder 204-4 can output one of the first WL signal and the second WL signal as WL MRS related mode information MRS2.

[0072] RAS counter 204-5 can generate a first RAS signal corresponding to the normal mode and a second RAS signal corresponding to the PIM mode. In embodiments of this disclosure, the first RAS signal and the second RAS signal can be complementary to each other. Decoder 204-6 can output one of the first RAS signal and the second RAS signal as RAS MRS related mode information MRS3.

[0073] although Figure 5 The MRS management unit 204 shown only outputs the WR signal, WL signal and RAS signal to the decoders 204-2, 204-4 and 204-6, but it will be understood that this disclosure is not limited thereto, and other signals may be generated and provided to the decoders 204-2, 204-4 and 204-6.

[0074] Figure 2 The memory system 10 shown sends the operating mode (normal mode / PIM mode) from the controller 200. However, it will be understood that this disclosure is not limited thereto. The operating mode (normal mode / PIM mode) can be controlled internally within the memory device. In other words, the operating mode may not need to be provided from the controller 200.

[0075] Figure 6 This is a view illustrating a memory system 20 according to another exemplary embodiment of this disclosure. Reference Figure 6 The memory system 20 includes a memory device 100a for generating operating modes. Figure 6 The memory system 20 and Figure 2 The difference between the memory systems 10 lies in the memory device 100a.

[0076] The memory device 100a may include a PIM mode controller 101a, a first memory bank 105 and a second memory bank 106, a processing unit 107 and a memory interface circuit 110. The PIM mode controller 101a may include a mode controller 102a, a memory parameter controller 103 and an MRS controller 104.

[0077] The mode controller 102a can be configured to receive operating modes (normal mode / PIM mode) from the controller 200 and control the operating mode of the memory device 100a.

[0078] In embodiments of this disclosure, before and after changing the operating mode of the memory device 100a, the memory device 100a may internally precharge the first memory bank 105 and the second memory bank 106. In another embodiment of this disclosure, before and after changing the operating mode of the memory device 100a, the controller 200 may issue a full memory bank precharge command to precharge the first memory bank 105 and the second memory bank 106.

[0079] The memory system 20 according to the example embodiment may have a structure that is binary to select a first operating mode (e.g., normal mode) and a second operating mode (e.g., PIM mode). During the mode change, the corresponding signal can change from a "low" level to a "high" level. It will be understood that the mode change of this disclosure is not limited thereto.

[0080] Figure 7 This is a view illustrating a memory system according to another exemplary embodiment of the present disclosure. References Figure 7 The memory system 30 may include a memory device 100b and a controller 200b.

[0081] The memory device 100b may include a PIM mode controller 101b, a first memory bank, a second memory bank, and a processing unit PE. The PIM mode controller 101b may include a mode selector 101-1b, a PIM mode generator 101-2b, a tRAS counter 102b, a tWR counter 103b, and RL control logic 104b.

[0082] The mode selector 101-1b of the memory device 100b can receive first operating mode information MD1 (e.g., a mode change command) from the PIM mode generator 201b of the controller 200b, or second operating mode information MD2 from the PIM mode generator 101-2b of the memory device 100b, and in response, can select whether to operate in the first operating mode or the second operating mode. For example, the mode selector 101-1b can output a mode selection signal MSEL with a low level L corresponding to the first operating mode, or it can output a mode selection signal MSEL with a high level H corresponding to the second operating mode. The mode selector 101-1b and the PIM mode generator 101-2b can be referred to as a PIM mode controller.

[0083] Each of the tRAS counter 102b, tWR counter 103b, and RL control logic 104b can determine whether to operate in the first or second operating mode in response to the mode selection signal MSEL.

[0084] The PIM mode generator 201b of the controller 200b can receive a refresh signal REF, at least one memory parameter signal MPS, and multiple MRS signals MRS1, MRS2 and MRS3, and can receive one of a first operating mode and a second operating mode and generate a first operating mode information MD1 corresponding to the selected mode.

[0085] The refresh management unit 202b can output a refresh signal REF with a low level L corresponding to the first operating mode or a refresh signal REF with a high level H corresponding to the second operating mode. The refresh command generator 202-1b can output a full-bank refresh command ABR or a per-bank refresh command PBR in response to a refresh activation signal. The refresh activation signal can be REFEN.

[0086] The memory parameter management unit 203b can output at least one memory parameter signal MPS having a low level L corresponding to the first operating mode or at least one memory parameter signal MPS having a high level H corresponding to the second operating mode.

[0087] MRS management unit 204b can output MRS signals MRS1 to MRS3 with a low level L corresponding to the first operating mode or MRS signals MRS1 to MRS3 with a high level H corresponding to the second operating mode.

[0088] What will be understood is... Figure 7The tRAS counter 102b, tWR counter 103b, and RL control logic 104b shown are merely examples. In addition to tRAS, tWR, and RL, various other factors can exist, which are mode-selectable via the mode selection signal MSEL.

[0089] The following shows an example of a pattern change.

[0090] Table 1

[0091] factor Mode 1 Mode 2 refresh Each memory refresh Full memory refresh tRCD / tRAS 15ns / 33ns 20ns / 38ns RL 20 10

[0092] In the first operating mode, the refresh operation can be a per-bank refresh operation, with tRCD of 15ns, tRAS of 33ns, and RL of 20. In the second operating mode, the refresh operation can be a full-bank refresh, with tRCD of 20ns, tRAS of 38ns, and RL of 10. It will be understood that the above values ​​for the first and second operating modes are merely example values.

[0093] In the first operating mode, the memory device 100b can perform normal read / write operations on multiple memory banks. In the second operating mode, the memory device 100b can perform predetermined internal operations (e.g., XOR operation, convolution operation, encryption / decryption operation, etc.) on the first and second memory banks.

[0094] In embodiments of this disclosure, in the second operating mode, the first memory bank and the second memory bank can be activated simultaneously. In another embodiment of this disclosure, in the second operating mode, the first memory bank and the second memory bank can be activated at different times.

[0095] The memory system according to an example embodiment of this disclosure can send mode information in the form of commands.

[0096] Figure 8 This is a view illustrating a memory system 40 according to another exemplary embodiment of the present disclosure. Reference Figure 8 The memory system 40 may include a memory device 300 and a controller 400. The memory device 300 and the controller 400 can send and receive mode information through corresponding interface circuits 310 and 410. Figure 8 For ease of description, the clock signal CLK, row address signal R, column address signal C, and data signal DQ are shown. It will be understood that various other signals can be transmitted between interface circuits 310 and 410.

[0097] The PIM mode controller 302 can receive the mode register enable signal MR_EN and the opcode OP from the command decoder 361, and can output the mode selection signal MSEL. In response to the mode selection signal MSEL, the tRAS counter 303, the tWR counter 304, and the RL control logic 305 can determine whether to operate in normal mode or PIM mode. The clock divider 306 can be configured to receive the clock signal CLK and output an operating clock signal PE_CLK suitable for the processing unit PE. In embodiments of this disclosure, the operating clock signal PE_CLK can have a lower frequency than the clock signal CLK. The PIM mode controller 302, the tRAS counter 303, the tWR counter 304, the RL control logic 305, and the clock divider 306 can constitute a single intellectual property (IP), and therefore can be referred to as the PIM mode controller 301.

[0098] Command decoder 361 can receive clock signal CLK, control signals R and C, and data signal DQ, and can decode the received control signals R and C and the received data signal DQ to determine the operating mode. Command decoder 361 can output the opcode OP and the mode register enable signal MR_EN corresponding to the operating mode.

[0099] Figure 9 It shows Figure 8 A view of an example of the opcode OP shown. (Reference) Figure 9 In the default mode (normal mode), the opcode OP can be '0000000X', where X is any value. When all memory banks enter PIM mode, the opcode OP can be '1100101X'. When only memory banks 0 to 7 enter PIM mode, the opcode OP can be '0110101X'. When all memory banks exit PIM mode, the opcode OP can be '1101010X'.

[0100] Figure 10 This is a view illustrating timing associated with mode changes in a memory system according to an example embodiment of this disclosure. Reference Figure 10 When the mode change command MRS, memory array MA[4∶0], and opcode OP[7∶0] are received during normal mode operation, the mode selection signal MSEL, which indicates the PIM mode, can change from low to high in response to the mode change command MRS. Simultaneously, an internal operating clock signal PE_CLK, obtained by dividing the clock signal CLK, can be generated.

[0101] In embodiments of this disclosure, in PIM mode, the first and second memory banks can be activated in response to the first memory bank activation command B0 ACT and the second memory bank activation command B1 ACT. In embodiments of this disclosure, the memory banks in the memory array MA[4:0] corresponding to '01000' can enter PIM mode. In embodiments of this disclosure, the memory banks can enter or exit PIM mode in response to the opcode OP[7:0].

[0102] exist Figures 8 to 10 In this context, mode changing is performed via a mode change command. However, this disclosure is not necessarily limited to this. Mode information of this disclosure can be sent through various combinations of different control signals. For example, mode changing can be performed via an activation command (ACT) and a precharge command (PRE).

[0103] Figure 11 This is a view illustrating a memory system 50 according to another exemplary embodiment of the present disclosure. References Figure 11 The memory system 50 may include a memory device 300a and a controller 400a.

[0104] The memory device 300a can perform a mode change using the activation signal ACT and the precharge signal PRE. Unlike... Figure 8 The command decoder 361a shown in the memory device 300a can perform mode changes using the activation signal ACT, the bank address / row address BA / RA, and the precharge signal PRE.

[0105] The PIM mode controller 302a, tRAS counter 303, tWR counter 304, RL control logic 305 and clock divider 306 can constitute a single intellectual property (IP) and therefore can be referred to as PIM mode controller 301a.

[0106] Figure 12 It shows the relationship with Figure 11 The view shown depicts the timing associated with mode changes in the memory system 50. (Reference) Figure 12 PIM mode can be entered using RA / BA codes (e.g., specific codes) and the activation command ACT. Alternatively, PIM mode can be exited using a combination of a predetermined RA / BA code, the activation command ACT, and the precharge command PRE of the same BA. Furthermore, the clock PE_CLK supplied to the processing unit PE can be controlled (on / off) using the signal MSEL generated by the internal PIM mode controller. Specific codes can be sent via BA[3:0] and RA[15:0] to perform mode setting.

[0107] Figure 13This is a view showing a memory device 700 according to an example embodiment of the present disclosure.

[0108] refer to Figure 13 The memory device 700 may include a PIM mode controller 701, multiple processing units (PE) 707, a memory cell array 710, a row decoder 720, a column decoder 730, a sense amplifier circuit 740, an address register 750, memory bank control logic 752, a refresh counter 754, a row address multiplexer (RA MUX) 756, a column address latch 758, control logic 760, a repair control circuit 766, a timing control circuit 764, an input / output gating circuit 770, an error correction circuit 780, a data input / output buffer 782, and a PBT circuit 790.

[0109] The PIM mode controller 701 can control the operating mode of the memory device 700 to dynamically change it to normal mode or PIM mode, as shown in the reference. Figures 1 to 12 As described.

[0110] Each processing unit (PE) in the processing unit (PE) 707 can be configured to perform operations on the storage bank activated in PIM mode.

[0111] The memory cell array 710 may include a first memory bank 711 to an eighth memory bank 718. It will be understood that the number of memory banks in the memory cell array 710 is not limited thereto. For example, the memory cell array 710 may include fewer or more than eight memory banks.

[0112] The line decoder 720 may include first storage bank line decoders 721 to eighth storage bank line decoders 728, which are respectively connected to the first storage bank 711 to the eighth storage bank 718.

[0113] The column decoder 730 may include first storage column decoders 731 to eighth storage column decoders 738, which are respectively connected to the first storage bank 711 to the eighth storage bank 718.

[0114] The readout amplifier circuit 740 may include first memory readout amplifiers 741 to eighth memory readout amplifiers 748 respectively connected to the first memory bank 711 to the eighth memory bank 718.

[0115] First memory banks 711 to eighth memory banks 718, first memory bank row decoders 721 to eighth memory bank row decoders 728, first memory bank column decoders 731 to eighth memory bank column decoders 738, and first memory bank sense amplifiers 741 to eighth memory bank sense amplifiers 748 can each constitute the first to eighth memory banks. Each memory bank among the first to eighth memory banks 711 may include a plurality of memory cells MC formed at the intersection of word line WL and bit line BL.

[0116] Address register 750 can receive and store address ADDR, which has bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from the external memory controller. Address register 750 can provide the received bank address BANK_ADDR to the bank control logic 752, the received row address ROW_ADDR to the row address multiplexer 756, and the received column address COL_ADDR to the column address latch 758.

[0117] The bank control logic 752 can generate a bank control signal in response to the bank address BANK_ADDR. Among the first bank row decoders 721 to the eighth bank row decoders 728, the bank row decoder corresponding to the bank address BANK_ADDR can be activated in response to the bank control signal. Among the first bank column decoders 731 to the eighth bank column decoders 738, the bank column decoder corresponding to the bank address BANK_ADDR can be activated in response to the bank control signal.

[0118] The row address multiplexer 756 can receive the row address ROW_ADDR from the address register 750 and the refresh row address REF_ADDR from the refresh counter 754. The row address multiplexer 756 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 756 can be applied to each of the first bank row decoders 721 to the eighth bank row decoders 728.

[0119] Among the first to eighth bank row decoders 721, the bank row decoder activated by the bank control logic 752 can decode the row address RA output from the row address multiplexer 756 to activate the word line corresponding to the row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address. In addition, the activated bank row decoder can activate the redundant word line corresponding to the redundant row address output from the repair control circuit 766, and simultaneously activate the word line corresponding to the row address.

[0120] Column address latch 758 can receive column address COL_ADDR from address register 750 and can temporarily store the received column address COL_ADDR. Column address latch 758 can incrementally increment the received column address COL_ADDR in burst mode. Column address latch 758 can apply the temporarily stored or incrementally incremented column address COL_ADDR to each of the first bank column decoders 731 to the eighth bank column decoder 738.

[0121] Among the first bank column decoders 731 to the eighth bank column decoders 738, the bank column decoder activated by the bank control logic 752 can activate the sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 770. Furthermore, the activated bank column decoder can perform a column repair operation in response to the column repair signal CRP output from the repair control circuit 766.

[0122] Control logic 760 can be configured to control the operation of memory device 700. For example, control logic 760 can generate control signals that cause semiconductor memory device 700 to perform write or read operations. Control logic 760 may include: a command decoder 761 configured to decode commands (CMD) received from the memory controller; and a mode register or mode register group 762 configured to set the operating mode of memory device 700.

[0123] For example, command decoder 761 can decode write enable signal / WE, row address strobe signal / RAS, column address strobe signal / CAS, chip select signal / CS, etc., to generate operation control signals ACT, PCH, WR, and RD corresponding to command CMD. Control logic 760 can provide operation control signals ACT, PCH, WR, and RD to timing control circuit 764. Operation control signals ACT, PCH, WR, and RD may include activation signal ACT, precharge signal PCH, write signal WR, and read signal RD. Timing control circuit 764 can generate a first control signal CTL1 that controls the voltage level of word line WL in response to operation control signals ACT, PCH, WR, and RD, and a second control signal CTL2 that controls the voltage level of bit line BL in response to operation control signals ACT, PCH, WR, and RD, and can provide the first control signal CTL1 and the second control signal CTL2 to memory cell array 710.

[0124] The repair control circuit 766 can generate repair control signals CRP and SRP for controlling repair operations in at least one of the first and second cell regions of the memory bank based on the row address ROW_ADDR and column address COL_ADDR (or access address) of address ADDR and the fuse information of the corresponding word lines. The repair control circuit 766 can provide the redundant row address to the corresponding memory bank row decoder, provide the column repair signal CRP to the corresponding memory bank column decoder, and provide the selected signal and enable signal SRA to the block control circuit associated with the corresponding redundant array block. For example, the enable signal SRA can be provided to the row decoder 720.

[0125] The repair control circuit 766 can generate an hPPR word line enable signal in response to address ADDR in the hPPR mode stored in the mode register group 762. Additionally, the repair control circuit 766 can generate an sPPR word line enable signal sPPR_WL_EN in response to address ADDR in the sPPR mode stored in the mode register group 762. Furthermore, the repair control circuit 766 can disable the sPPR logic in the sPPR_OFF mode stored in the mode register group 762 and can generate a normal word line enable signal to access previous data. In embodiments of this disclosure, the repair control circuit 766 can modify the repair unit based on address ADDR and fuse information. For example, the repair control circuit 766 can modify the type and number of repair address bits based on address ADDR and fuse information.

[0126] The input / output gating circuit 770 may include one or more input / output gating circuits. Together with the circuitry that gating input / output data, each input / output gating circuit may include: input data masking logic; a read data latch configured to store data output from the first memory bank 711 to the eighth memory bank 718; and a write driver configured to write data to the first memory bank 711 to the eighth memory bank 718.

[0127] The codeword CW to be read from one of the memory banks 711 to 718 is read by the read amplifier corresponding to that memory bank and can be stored in the read data latch. After ECC decoding is performed by the error correction circuit 780, the codeword CW stored in the read data latch can be provided to the memory controller through the data input / output buffer 782. After ECC encoding is performed by the error correction circuit 780, the data DQ to be written to one of the memory banks 711 to 718 can be written to that memory bank through the write driver.

[0128] The data input / output buffer 782 can provide data DQ to the error correction circuit 780 based on the clock signal CLK provided from the memory controller during a write operation, and can provide data DQ provided from the error correction circuit 780 to the memory controller during a read operation.

[0129] Error correction circuit 780 can generate parity bits based on data bits of data DQ provided from data input / output buffer 782 during write operation and can provide codeword CW including data DQ and parity bits to input / output gating circuit 770, and input / output gating circuit 770 can write the codeword into memory, such as one of first memory bank 711 to eighth memory bank 718.

[0130] Additionally, the error correction circuit 780 can receive a codeword CW read from a memory bank from the input / output gating circuit 770 during a read operation. The error correction circuit 780 can perform ECC decoding on the data DQ using the parity bits included in the read codeword CW to correct at least one erroneous bit included in the data DQ and provide the error-corrected bit to the data input / output buffer 782.

[0131] PBT circuit 790 can be configured to respond to slave controller 200 (see...) Figure 2 The test data TDATA received by each memory bank in the memory bank is used to perform parallel test operations to perform repair operations when the error is correctable and output result values ​​based on the results.

[0132] Additionally, the PBT circuit 790 can be configured to pass the memory bank in response to the test pass signal PBTPASS, regardless of the result value of the test operation on the corresponding memory bank. In embodiments of this disclosure, the test pass signal PBTPASS can be output from the mode register group 762 during a parallel bit test operation.

[0133] Even when the memory device 700 according to an example embodiment of this disclosure includes unrepairable memory cells using the repair control circuit 766, the memory device 700 can still perform a masking process on the output terminals of the unrepairable memory cells in response to the test pass signal PBTPASS. Therefore, the memory device 700 can control the output terminals of each memory cell, allowing defective chips to operate as good chips.

[0134] Figure 14 This is a ladder diagram illustrating the internal operation process of a memory device according to an exemplary embodiment of the present disclosure. Referring below, reference will be made to... Figures 1 to 14 This describes the internal operation of the memory device MEM.

[0135] The memory device MEM can receive a mode change request from the controller CNTL (S10). In embodiments of this disclosure, the mode change request may include a mode change command. In another embodiment of this disclosure, the mode change request may include mode information corresponding to a combination of multiple control signals.

[0136] The memory device MEM can set its operating mode in response to a mode change request for changing the operating mode (S11). For example, in S11, the operating mode can be set to PIM mode in response to a mode change request for changing the operating mode from normal mode to PIM mode. The memory device MEM can receive an internal operation request from the controller CNTL (S12). The memory device MEM can perform an internal operation in response to the internal operation request (S13). After the internal operation is completed, the memory device MEM can send completion information to the controller CNTL (S14).

[0137] The memory device MEM can receive a mode change request from the controller CNTL to change the operating mode from PIM mode to normal mode (S15).

[0138] In embodiments of this disclosure, a mode change request may include information for changing the setting value of the Mode Register Set (MRS). In embodiments of this disclosure, changing the operating mode may include changing the MRS-related opcode value in response to the mode change request. In embodiments of this disclosure, the mode change request may include an activation command and a precharge command. In embodiments of this disclosure, a clock may be received from the controller, and the received clock may be divided to generate an internal operating clock.

[0139] Figure 15 This is a view illustrating a memory system performing at least one command / address calibration according to an example embodiment of the present disclosure.

[0140] refer to Figure 15 The memory system 1000 may include a controller 1800 and a memory device 1900. The controller 1800 may include a clock generator 1801, a command / address (CA) generator 1802, a command / address reference generator 1803, a register 1804, a comparator 1806, a phase / timing controller 1808, and data input / output units 1810 and 1812. The controller 1800 can provide the clock signal CK generated by the clock generator 1801 to the memory device 1900 via a clock signal line.

[0141] In embodiments of this disclosure, the memory system 1000 may include an additional command / address reference signal (CA_Ref) line in the interface. The command / address reference signal (CA_Ref) line can be used to send and receive the command / address reference signal CA_Ref and / or the command / address reference value in calibration mode.

[0142] The calibration result value using the command / address reference value can be provided to the phase / timing controller 1808 to adjust the phase / timing of the command / address signal CA. Due to the additional command / address reference signal (CA_Ref) line, the calibration operation to adjust the phase / timing of the command / address signal CA can be performed simultaneously with the operation of sending the command / address (CA) signal.

[0143] The CA generator 1802 can generate a command / address signal CA with a phase or timing adjusted in response to the control signal CTR of the phase / timing controller 1808, and can send the command / address signal CA to the memory device 1900 via the CA bus.

[0144] Command / address reference generator 1803 can be configured to be the same as command / address generator 1802, and can generate a first command / address reference signal CA_Ref1, which is the same signal as the command / address signal CA generated from command / address generator 1802.

[0145] The first command / address reference signal CA_Ref1 can be provided to register 1804. Alternatively, the first command / address reference signal CA_Ref1 can be sent to the CA reference bus via data output unit 1812 and provided to memory device 1900 via the CA reference bus.

[0146] Register 1804 can store the first command / address reference signal CA_Ref1. Comparator 1806 can compare the first command / address reference signal CA_Ref1 stored in register 1804 with the third command / address reference signal CA_Ref3 output from data input unit 1810. Comparator 1806 can compare the data of the first command / address reference signal CA_Ref1 with the data of the third command / address reference signal CA_Ref3 to generate a pass or fail signal P / F.

[0147] The phase / timing controller 1808 can generate a control signal CTR that indicates the phase shift of the command / address signal CA based on the pass or fail signal P / F from the comparator 1806. The control signal CTR can adjust the phase or timing of the command / address signal CA to generate a phase-adjusted command / address signal CA.

[0148] The data input unit 1810 can receive the second command / address reference signal CA_Ref2 sent via the CA reference bus from the memory device 1900, and can send the received second command / address reference signal CA_Ref2 as the third command / address reference signal CA_Ref3 to the comparator 1806.

[0149] The data output unit 1812 can receive the first command / address reference signal CA_Ref1 generated by the command / address reference generator 1803, and send the received first command / address reference signal CA_Ref1 to the CA reference bus.

[0150] The memory device 1900 may include a clock buffer 1902, a command / address (CA) receiver 1904, a command / address reference (CA_Ref) receiver 1906, and data input / output units 1908 and 1910. The clock buffer 1902 can receive a clock signal CK transmitted via a clock signal line to generate an internal clock signal ICK. The CA receiver 1904 can, in response to the internal clock signal ICK, receive a chip select signal / CS, a clock enable signal CKE, and a command / address signal CA transmitted via the CA bus.

[0151] The clock enable signal CKE can be used as a pseudo-command, which acts as a read command for the command / address signal CA sent via the CA bus. When the clock enable signal CKE is enabled, the CA receiver 1904 can receive the command / address signal CA.

[0152] Data input unit 1908 can receive a first command / address reference signal CA_Ref1 sent from controller 1800 via CA reference bus, and can send the received first command / address reference signal CA_Ref1 to command / address reference receiver 1906. Command / address reference receiver 1906 can be configured to be the same as CA receiver 1904. Command / address reference receiver 1906 can generate a second command / address reference signal CA_Ref2 in response to internal clock signal ICK using chip select signal / CS, clock enable signal CKE, and the first command / address reference signal CA_Ref1 sent via CA reference bus.

[0153] The second command / address reference signal CA_Ref2 can be the same signal output by the CA receiver 1904, which receives the chip select signal / CS, the clock enable signal CKE, and the command / address signal CA transmitted via the CA bus in response to the internal clock signal ICK. The second command / address reference signal CA_Ref2 can be sent to the CA reference bus via the data output unit 1910.

[0154] The CA calibration performed by the memory system 1000 will be described below. The CA generator 1802 of the controller 1800 can adjust the phase or timing of the command / address signal CA in response to the control signal CTR of the phase / timing controller 1808, and can send the phase-adjusted or timing-adjusted command / address signal CA to the CA bus. The command / address reference generator 1803 can generate a first command / address reference signal CA_Ref1 as the same signal as the command / address signal CA, and can send the first command / address reference signal CA_Ref1 to the CA reference bus.

[0155] The CA reference receiver 1906 of the memory device 1900 can receive the first command / address reference signal CA_Ref1 according to the internal clock signal ICK and the clock enable signal CKE, and generate a second command / address reference signal CA_Ref2. The second command / address reference signal CA_Ref2 of the memory device 1900 can be transmitted through the CA reference bus.

[0156] The memory device 1900 can send a second command / address reference signal CA_Ref2, transmitted via the CA reference bus, to comparator 1806 as a third command / address reference signal CA_Ref3. Comparator 1806 can compare the data of the first command / address reference signal CA_Ref1 with the data of the third command / address reference signal CA_Ref3 to generate a pass or fail signal P / F. Note that the second command / address reference signal CA_Ref2 is converted into the third command / address reference signal CA_Ref3 by the data input unit 1810. The phase / timing controller 1808 can generate a control signal CTR indicating the phase shift of the command / address signal CA based on the pass or fail signal P / F from comparator 1806. The CA generator 1802 can generate a command / address signal CA with a phase adjusted according to the control signal CTR.

[0157] Due to the repetition of such CA calibration operations, the phase / timing controller 1808 of the controller 1800 can determine that the middle of the position is the middle of the command / address signal (CA) window, and can generate a command / address signal CA such that the middle of the command / address signal (CA) window is set on the edge of the clock signal CK, and send the generated command / address signal CA to the memory device 1900. Therefore, the memory device 1900 can receive a command / address signal CA on the rising / falling edge of the clock signal CK such that the middle of the valid window is set on the rising / falling edge of a pair of clock signals CK and CKB.

[0158] A memory system 1000 according to an example embodiment of the present disclosure may include: a controller 1800 that generates a PIM pattern; and a memory device 1900 that receives pattern information from the controller 1800 to control an operating mode.

[0159] Controller 1800 may also include a PIM pattern generator 1820 for generating pattern information corresponding to one of the PIM / normal modes. The PIM pattern generator 1820 can determine memory parameters / MRS settings / refresh type based on the PIM / normal mode.

[0160] The memory device 1900 may include a PIM mode controller 1920 for receiving mode information to operate in PIM mode or normal mode. The PIM mode controller 1920 may determine the refresh type, set the MSR, adjust AC parameters, or determine the refresh mode based on the mode information.

[0161] The memory system according to an example embodiment of this disclosure can be disposed on a single substrate.

[0162] Figure 16 This is a view illustrating a memory system 2000 according to an exemplary embodiment of the present disclosure. References Figure 16 The memory system 2000 may include a controller chip 2100 and a memory chip 2200 mounted on a substrate 2001. In embodiments of the present invention, the controller chip 2100 and the memory chip 2200 may be connected via the substrate 2001 having an interpolator. Each of the controller chip 2100 and the memory chip 2200 may be configured to perform... Figures 1 to 15 The dynamic pattern change described in the text.

[0163] The memory device according to the example embodiments of this disclosure can be applied to a computing system.

[0164] Figure 17 This is a view illustrating a computing system 3000 according to another exemplary embodiment of the present disclosure. Reference Figure 17 The computing system 3000 may include at least one volatile memory module (DIMM) 3100, at least one non-volatile memory module (NVDIMM) 3200 and at least one central processing unit (CPU) 3300.

[0165] The computing system 3000 can be one of the following devices: such as computers, portable computers, ultra-mobile personal computers (UMPCs), workstations, data servers, netbooks, personal data assistants (PDAs), network tablets, cordless phones, mobile phones, smartphones, e-books, portable multimedia players (PMPs), digital cameras, digital audio recorders / players, digital picture / video recorders / players, portable game consoles, navigation systems, black boxes, three-dimensional (3D) televisions, devices capable of wirelessly sending and receiving information, wearable devices, various electronic devices constituting a home network, various electronic devices constituting a computer network, various electronic devices constituting a telematics network, radio frequency identification (RFID), and various electronic devices constituting a computing system, etc.

[0166] At least one non-volatile memory module 3200 may include at least one non-volatile memory. In exemplary embodiments of this disclosure, at least one non-volatile memory may include NAND flash memory, vertical NAND flash memory (VNAND), NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), thyristor random access memory (TRAM), etc.

[0167] In embodiments of this disclosure, at least one of the memory modules 3100 and 3200 may include an interface circuit IF and a PIM mode controller, such that the at least one memory module can perform a reference... Figures 1 to 15 The described dynamic pattern changes.

[0168] In embodiments of this disclosure, memory modules 3100 and 3200 may be connected to at least one central processing unit 3300 via a DDRx interface (where x is an integer of 1 or greater).

[0169] At least one central processing unit 3300 can control the volatile memory module 3100 and the non-volatile memory module 3200. In embodiments of this disclosure, at least one central processing unit 3300 may include a general-purpose microprocessor, a multi-core processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a combination thereof.

[0170] Internal operating methods according to exemplary embodiments of this disclosure can be performed within stacked memory package chips.

[0171] Figure 18 This is a view illustrating a computing system 4000 according to another exemplary embodiment of the present disclosure. Reference Figure 18The computing system 4000 may include a host processor 4100 and at least one memory package chip 4210 controlled by the host processor 4100.

[0172] In embodiments of this disclosure, the host processor 4100 and the memory package chip 4210 can send and receive data via channel 4001.

[0173] The memory package chip 4210 may include stacked memory chips and controller chips. For example... Figure 18 As shown, the memory package chip 4210 may include a plurality of DRAM chips disposed on the DRAM controller chip. It will be understood that the configuration of the memory package chip according to this disclosure is not limited thereto.

[0174] In embodiments of this disclosure, each memory chip can be configured to perform... Figures 1 to 17 The dynamic mode changes and internal operations described herein. However, this disclosure is not necessarily limited thereto. Internal operations can be performed between the stacked memory chips and the controller chip of the memory package chip 4210. In this case, it is also possible to perform operations with... Figures 1 to 17 The operation mode change is performed dynamically in a manner similar to that described in [the text].

[0175] The data communication method according to the example embodiments of this disclosure can be applied to data centers.

[0176] Figure 19 This is a view illustrating a data center using a memory device according to an example embodiment of this disclosure. References Figure 19 Data center 7000 is a facility that collects various types of data and provides services, and may also be referred to as a data storage center. Data center 7000 can be a system for managing search engines and databases, or a computing system used in companies such as banks or organizations such as government agencies. Data center 7000 may include application servers 7100 to 7100n and storage servers 7200 to 7200m. The number of application servers 7100 to 7100n and the number of storage servers 7200 to 7200m may be selected differently according to exemplary embodiments of this disclosure, and the number of application servers 7100 to 7100n and storage servers 7200 to 7200m may differ from each other.

[0177] Application server 7100 or storage server 7200 may include at least one of the following: processors 7110 (e.g., 7110 to 7110n) and 7210 (e.g., 7210 to 7210m) and memory 7120 (e.g., 7120 to 7120n) and 7220 (e.g., 7220 to 7220m). Taking storage server 7200 as an example, processor 7210 can control the overall operation of storage server 7200 and can access memory 7220 to execute commands and / or data loaded in memory 7220. Memory 7220 may be double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVMDIMM). According to embodiments of this disclosure, the number of processors 7210 included in storage server 7200 may be selected differently.

[0178] In embodiments of this disclosure, processor 7210 and memory 7220 may provide a processor-memory pair. In embodiments of this disclosure, the number of processors 7210 and memory 7220 may differ from each other. Processor 7210 may include a single-core processor or a multi-core processor. The description of storage server 7200 can be similarly applied to application server 7100. According to embodiments of this disclosure, application server 7100 may not include storage device 7150. Storage server 7200 may include at least one storage device 7250. Storage device 7250 may be configured to perform dynamic mode changes between PIM mode and normal mode, as referenced... Figures 1 to 18 As described.

[0179] Application servers 7100 to 7100n and storage servers 7200 to 7200m can communicate with each other via network 7300. Network 7300 can be implemented using Fibre Channel (FC), Ethernet, etc. FC can be a medium for data transmission at relatively high speeds and can employ optical switches to provide high performance / high availability. Storage servers 7200 to 7200m can be configured as file storage, block storage, or object storage depending on the access method of network 7300.

[0180] In an example embodiment of this disclosure, network 7300 may be a storage area network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). As another example, the SAN may be an IP-SAN implemented using a TCP / IP network and according to the SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In another example embodiment of this disclosure, network 7300 may be a general-purpose network, such as a TCP / IP network. For example, network 7300 may be implemented according to protocols such as FC over Ethernet (FCoE), network attached storage (NAS), NVMe over Fabrics (NVMe-oF), etc.

[0181] In the following description, the focus will be on application server 7100 and storage server 7200. The description of application server 7100 can be applied to another application server 7100n, and the description of storage server 7200 can be applied to another storage server 7200m.

[0182] Application server 7100 can store data requested by users or clients in one of storage servers 7200 to 7200m via network 7300. Additionally, application server 7100 can retrieve data requested by users or clients from one of storage servers 7200 to 7200m via network 7300. For example, application server 7100 can be a web server, a database management system (DBMS), etc.

[0183] Application server 7100 can access memory 7120n or storage device 7150n included in another application server 7100n via network 7300, or access memory 7220 to 7220m or storage device 7250 to 7250m included in storage servers 7200 to 7200m via network 7300. Therefore, application server 7100 can perform various operations on data stored in application servers 7100 to 7100n and / or storage servers 7200 to 7200m. For example, application server 7100 can execute commands for moving or copying data between application servers 7100 to 7100n and / or storage servers 7200 to 7200m. In this scenario, data can be moved from storage servers 7200 to 7200m to storage devices 7250 to 7250m of storage servers 7200 to 7200m via storage devices 7220 to 7220m, or directly to storage devices 7120 to 7120n of application servers 7100 to 7100n. Data moved via network 7300 can be encrypted for security or privacy purposes.

[0184] Taking storage server 7200 as an example, interface 7254 can provide physical connections between processor 7210 and controller 7251, as well as physical connections between NIC 7240 and controller 7251. For example, interface 7254 can be implemented using a Direct Attached Storage (DAS) method, in which storage device 7250 is directly connected to a dedicated cable. Alternatively, interface 7254 can be implemented using various interface methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral PCI Component Interconnect (PCI Fast), PCIe (NV Fast), NVMe (NVM Fast), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Memory (UFS), Embedded Universal Flash Memory (eUFS), Compact Flash Memory (CF) card interface, etc.

[0185] The storage server 7200 may also include a switch 7230 and a NIC 7240. The switch 7230 can selectively connect the processor 7210 and the storage device 7250 to each other, or selectively connect the NIC 7240 and the storage device 7250 to each other, under the control of the processor 7210.

[0186] In exemplary embodiments of this disclosure, NIC 7240 may include a network interface card, network adapter, etc. NIC 7240 can connect to network 7300 via a wired interface, wireless interface, Bluetooth interface, optical interface, etc. NIC 7240 may include internal memory, digital signal processor (DSP), host bus interface, etc., and can connect to processor 7210 and / or switch 7230 via the host bus interface. The host bus interface can be implemented as one of the above examples of interface 7254. In exemplary embodiments of this disclosure, NIC 7240 may be integrated with at least one of processor 7210, switch 7230, and storage device 7250.

[0187] In storage servers 7200 to 7200m or application servers 7100 to 7100n, the processor can send data to storage devices 7150 to 7150n and 7250 to 7250m, or send commands to memories 7120 to 7120n and 7220 to 7220m to program or retrieve data. In this case, the data can be error-corrected data corrected by an error-correcting code (ECC) engine. The data is data that has undergone Data Bus Inversion (DBI) or Data Masking (DM) and may include Cyclic Redundancy Check (CRC) information. The data can be encrypted for security or privacy.

[0188] Storage devices 7150 to 7150n and 7250 to 7250m can send control signals and command / address signals to NAND flash memory devices 7252 to 7252m in response to a read command received from the processor. Therefore, when reading data from NAND flash memory devices 7252 to 7252m, a read enable signal RE can be input as a data output control signal to output data to the DQ bus. The read enable signal RE can be used to generate a data strobe DQS. Command and address signals can be latched in the page buffer based on the rising or falling edge of the write enable signal WE.

[0189] Controller 7251 can control the overall operation of storage device 7250. Each of storage devices 7250 to 7250m includes a corresponding controller among controllers 7251 to 7251m. In an example embodiment of this disclosure, controller 7251 may include static random access memory (SRAM). Controller 7251 can write data to NAND flash memory 7252 in response to a write command, or can read data from NAND flash memory 7252 in response to a read command. For example, write commands and / or read commands may be provided from processor 7210 in storage server 7200, processor 7210m in another storage server 7200m, or processors 7110 to 7110n in application servers 7100 to 7100n. DRAM 7253 may temporarily store (e.g., buffer) data to be written to or read from NAND flash memory 7252. In addition, DRAM 7253 may store metadata. Each of the storage devices 7250 to 7250m includes a corresponding DRAM among DRAMs 7253 to 7253m. Metadata is user data or data generated by the controller 7251 for managing the NAND flash memory 7252. Storage device 7250 may include a security element (SE) for security or privacy purposes.

[0190] Each application server among application servers 7100 to 7100n may include switches 7130 to 7130n and network interface circuits 7140 to 7140n, respectively. Each storage server among storage servers 7200 to 7200m may include switches 7230 to 7230m and network interface circuits 7240 to 7240m, respectively. Additionally, each storage device among storage devices 7250 to 7250m may include network interface circuits 7254 to 7254m, respectively.

[0191] This disclosure discloses a method for controlling a DRAM with an arithmetic operation device (PE / ALU) incorporated therein, and also discloses a mode changing method. The memory system according to this disclosure may include a DRAM with an arithmetic operation device incorporated therein, a memory controller for controlling the DRAM, a signal for activating the arithmetic operation device in the DRAM, a selector for changing the mode in the DRAM, and a unit for managing DRAM refresh / parameters / MRS, etc., according to the mode.

[0192] In embodiments of this disclosure, a mode in which ACT / RD / WR / PRECHARGE operations can be performed simultaneously on multiple memory banks via a single command (not provided in conventional DRAM) can significantly improve the performance of arithmetic devices. According to this disclosure, the mode in which multiple memory banks of the DRAM operate and the normal mode (where only one memory bank is operated by a single command) can be dynamically changed during DRAM operation. Due to the dynamic changes in the normal mode and the mode in which multiple memory banks operate simultaneously, unnecessary setup time required for mode switching can be eliminated. Therefore, system performance can be improved.

[0193] As described above, exemplary embodiments of this disclosure provide a memory device, a memory system including the memory device, a controller for controlling the memory device, and a method for operating the memory device. The operating mode or internal operating environment can be dynamically changed to perform internal operations in an optimal state.

[0194] In addition, internal operations can be performed under optimal conditions to improve system performance.

[0195] While exemplary embodiments of the present disclosure have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made thereto without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A memory device, comprising: Multiple pins are used to receive control signals from external devices; A first storage bank has a first storage unit, wherein the first storage bank is activated in a first operating mode and a second operating mode; The second storage bank has a second storage unit, wherein the second storage bank is deactivated in the first operating mode and activated in the second operating mode; The processing unit is configured to perform operations on first data output from the first storage unit and second data output from the second storage unit in the second operating mode; and A PIM mode controller in the memory is configured to select mode information indicating one of the first and second operating modes in response to the control signal, and to control at least one memory parameter, at least one mode register set MRS value, or refresh mode based on the mode information. The PIM mode controller includes a clock divider configured to receive a clock from the external device and generate an internal operating clock for driving the processing unit in the second operating mode.

2. The memory device according to claim 1, wherein, The PIM mode controller further includes a memory parameter controller, which is configured to control the at least one memory parameter based on the mode information.

3. The memory device according to claim 1, wherein, The PIM mode controller also includes an MRS controller, which is configured to change at least one MRS value based on the mode information.

4. The memory device according to claim 1, wherein, Perform a per-storage-bank refresh operation in the first operating mode, and Perform a full memory refresh operation in the second operation mode.

5. The memory device according to claim 1, wherein, The at least one memory parameter includes activation to internal read or write latency, activation to activation or refresh command cycle, activation to activation command latency, or four activation windows.

6. The memory device according to claim 3, wherein, Changing the at least one MRS value includes controlling the counter using write latency, column address strobe latency, write command, row address strobe, column address strobe, or the sum of additive latency and column address strobe latency.

7. The memory device according to claim 1, wherein, The PIM mode controller dynamically changes the first operating mode and the second operating mode in response to the control signal.

8. The memory device according to claim 1, further comprising: The command decoder is configured to receive the control signal and output the corresponding mode change command. The PIM mode controller further includes: A mode selector is configured to select one of the first operating mode and the second operating mode in response to the mode change command.

9. The memory device according to claim 1, wherein, Both the first and second memory cells are precharged before and after the change of operating mode.

10. The memory device according to claim 1, wherein, Before and after the operating mode change, a full memory precharge operation is performed internally.

11. The memory device according to claim 1, wherein, The PIM mode controller uses a predetermined row address / memory address code and an activation command to enter the second operation mode, and uses a combination of the predetermined row address / memory address code, the activation command, and a precharge command for the memory address to exit the second operation mode.

12. A memory system, comprising: A memory device configured to operate in one of a first operating mode and a second operating mode in response to a mode change command, wherein the memory device includes a first memory bank and a second memory bank; and A controller is configured to control the memory device, wherein the controller includes a PIM pattern generator in the memory, the PIM pattern generator being configured to generate a pattern change command for selecting one of the first operating mode and the second operating mode. The memory device includes: Multiple pins are used to receive multiple control signals from the controller; A PIM mode controller is configured to, in response to the mode change command, activate one of the first and second storage units in the first operating mode, and activate at least one of the first storage units and at least one of the second storage units in the second operating mode; and The processing unit is configured to perform operations on first data output from an activated first memory bank and second data output from an activated second memory bank. The PIM mode controller includes a clock divider configured to receive a clock from the controller and generate an internal operating clock for driving the processing unit in the second operating mode.

13. The memory system according to claim 12, wherein, Before and after changing the operating mode of the memory device, the controller issues a memory precharge command for precharging the first memory bank and the second memory bank.

14. The memory system according to claim 12, wherein, Before and after changing the operating mode of the memory device, the memory device internally precharges the first memory bank and the second memory bank.

15. The memory system according to claim 12, wherein, The controller controls the memory device to dynamically change the refresh mode, at least one memory parameter, or the MRS value of the mode register group according to the selected mode.

16. The memory system according to claim 12, wherein, The controller includes: The refresh management unit is configured to output refresh information for either a full bank refresh operation or a per bank refresh operation, depending on the selected mode. A memory parameter management unit is configured to change at least one memory parameter according to a selected mode; and The Mode Register Group MRS Management Unit is configured to output MRS setting information that changes at least one MRS value based on the selected mode.

17. A method of operating a memory device, the method comprising: Receive mode change requests from the controller; When the mode change request indicates a first operating mode, one of the first and second memory banks of the memory device is activated. When the mode change request indicates a second operating mode, the first storage and the second storage are activated; as well as In response to an internal operation request, perform an operation on data output from at least two activated storage banks. The method further includes: receiving a clock from the controller and generating an internal operating clock for driving the processing unit in the second operating mode.

18. The method according to claim 17, wherein, The mode change request includes information for changing the MRS value of the mode register group.

19. The method of claim 18, further comprising: The MRS-related opcode value is changed in response to the mode change request.

20. The method according to claim 18, wherein, The mode change request includes an activation command and a precharge command.

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