Memory and programming method and reading method thereof

Abstract

The present disclosure relates to a memory and a programming method and a reading method thereof. The programming method includes: obtaining a programming temperature of a memory cell to be programmed of the memory, wherein the programming temperature is the temperature of the memory cell to be programmed; applying a programming voltage to the memory cell to be programmed to change the storage state of the memory cell to be programmed; applying a verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; if so, determining whether the bit line voltage of the memory cell to be programmed is higher than a second target voltage after a second sensing time, and if so, stopping programming of the cell to be programmed, wherein the first sensing time includes a first temperature compensation time adjusted according to the programming temperature, and the second sensing time includes a second temperature compensation time adjusted according to the programming temperature, and the first temperature compensation time and the second temperature compensation time are different.

Description

Technical Field

[0001] The present application relates to a storage device, and more particularly, to a programming method, a reading method, and an apparatus for a memory. Background Art

[0002] Flash memory is a non-volatile memory that can retain stored data without power. Compared to traditional hard drives, flash memory has advantages such as faster read speeds, lower power consumption, and better shock resistance, which is why it is being used in more and more applications. For example, flash memory is often used in electronic systems such as personal computers, digital cameras, digital media players, digital recorders, vehicles, wireless devices, cellular phones, and removable storage modules. As the application field of flash memory expands, it also faces increasingly complex application environments. Therefore, reliability under different temperatures has become an important product verification project for flash memory.

[0003] After programming the memory cells, the threshold voltage of each memory cell changes to achieve information storage. During the use of the memory, you may encounter situations such as low-temperature programming and high-temperature reading; high-temperature programming and low-temperature reading. However, due to its physical properties, the polysilicon channel in flash memory is sensitive to temperature, and its resistance has a high dependence on temperature. For example, at a low programming temperature, the threshold voltage distribution of the storage state may be wide. When reading at a high temperature, the threshold voltage of the memory cell drifts, the threshold voltage distribution may be different, and the difference between the storage states may also change. Such temperature dependence may cause deviations in the threshold voltage determined at different stages of programming and the storage state determined at the reading stage, ultimately leading to data reading errors.

[0004] Therefore, a memory device with good reliability at different temperatures is needed.

[0005] It should be understood that this background technology section is intended in part to provide a useful background for understanding the present technology, but does not mean that these contents are necessarily prior art already known to those skilled in the art before this application. Summary of the Invention

[0006] One aspect of the present disclosure provides a method for programming a memory, which includes: obtaining a programming temperature of a memory cell to be programmed of the memory, wherein the programming temperature is the temperature of the memory cell to be programmed; applying a programming voltage to the memory cell to be programmed to change the storage state of the memory cell to be programmed; applying a verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; if so, determining whether the bit line voltage of the memory cell to be programmed is higher than a second target voltage after a second sensing time, and if so, stopping programming of the cell to be programmed, wherein the first sensing time includes a first temperature compensation time adjusted according to the programming temperature, and the second sensing time includes a second temperature compensation time adjusted according to the programming temperature, and the first temperature compensation time and the second temperature compensation time are different.

[0007] In one embodiment, the first sensing time includes a first predetermined sensing time and a first temperature compensation time, and the second sensing time includes a second predetermined sensing time and a second temperature compensation time, the first predetermined sensing time being smaller than the second predetermined sensing time.

[0008] In one embodiment, the first temperature compensation time and the second temperature compensation time are determined according to a difference between the programming temperature and a predetermined reference temperature.

[0009] In one embodiment, the reference temperature is 85°C.

[0010] In one embodiment, the first temperature compensation time and the second temperature compensation time are respectively determined according to a curve of a change in a sensing current over time when the memory cell to be programmed is turned on within a corresponding time period at the programming temperature.

[0011] In one embodiment, when the slope time of the variation curve decreases, the first temperature compensation time is set to be smaller than the second temperature compensation time.

[0012] In one embodiment, the faster the charge loss rate in the corresponding time period is, the shorter the corresponding first temperature compensation time or second temperature compensation time is.

[0013] In one embodiment, the first temperature compensation time and the second temperature compensation time are determined according to a difference between a programming temperature and a reference temperature and a curve of a change in a sensing current over time when the memory cell to be programmed is turned on at the programming temperature.

[0014] In one embodiment, the programming method further includes: reprogramming the memory cell to be programmed when the bit line voltage is less than or equal to the first target voltage after the first sensing time or when the bit line voltage is less than or equal to the second target voltage after the second sensing time, wherein the reprogramming includes: changing the programming voltage; applying the changed programming voltage to the memory cell to be programmed to change the storage state of the memory cell to be programmed; applying the verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether the bit line voltage of the memory cell to be programmed is higher than the first target voltage after the first sensing time; if so, detecting whether the bit line voltage of the memory cell to be programmed is higher than the second target voltage after the second sensing time, if so, stopping programming of the memory cell to be programmed, and if not, repeating the above steps until the bit line voltage of the memory cell to be programmed is higher than the second target voltage.

[0015] In one embodiment, the programming method further includes: increasing a programming voltage when reprogramming the memory cell to be programmed.

[0016] In one embodiment, the programming method further includes: gradually increasing the programming voltage with the same step voltage when reprogramming the memory cell to be programmed multiple times.

[0017] In one embodiment, the programming method further includes: applying a read voltage to a programmed memory cell to turn on the programmed memory cell; and determining a storage state of the programmed memory cell after a read sensing time, wherein the read sensing time includes a read temperature compensation time, the read temperature compensation time being determined based on a temperature when the programmed memory cell is read, and having the same relationship curve with respect to temperature as the second temperature compensation time used when programming the programmed memory cell.

[0018] Another aspect of the present disclosure provides a memory, which includes an input / output circuit and a memory circuit. The input / output circuit includes: a bus interface configured to receive data from outside the memory and transmit data from the memory to the outside; and an input / output controller configured to control the operation of the bus interface. The memory circuit includes: a memory array including a plurality of memory cells; and a memory controller configured to control the operation of the plurality of memory arrays. When programming a memory cell to be programmed among the plurality of memory cells, the memory controller is configured to: obtain a programming temperature of the memory cell to be programmed in the memory array; apply a programming voltage to the memory cell to be programmed to change a storage state of the memory cell to be programmed; apply a verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, determine whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; if so, determine whether the bit line voltage of the memory cell to be programmed is higher than a second target voltage after a second sensing time, and if so, stop programming the memory cell to be programmed. The first sensing time includes a first temperature compensation time adjusted according to the programming temperature, and the second sensing time includes a second temperature compensation time adjusted according to the programming temperature, and the first temperature compensation time and the second temperature compensation time are different. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other advantages and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0020] Figure 1 A schematic diagram showing the storage state of a storage unit in a memory according to an embodiment of the present disclosure is shown.

[0021] Figure 2 A method for programming a memory cell in a memory according to an embodiment of the present disclosure is shown.

[0022] Figure 3 The relationship between the sensing current and the temperature compensation time according to an embodiment of the present disclosure is shown.

[0023] Figure 4 Sense voltage variation caused by temperature compensation time according to an embodiment of the present disclosure is shown.

[0024] Figure 5 A schematic diagram of a memory according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0025] Exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. However, the present invention may be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0026] It should also be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on or directly connected to the other element or layer, or there can be elements or layers between them. When an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. For this purpose, the term “connected” may refer to a physical connection, an electrical connection, and / or a fluid connection, with or without intervening elements.

[0027] Throughout the specification, the same reference numerals denote the same components. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

[0028] Although the terms "first", "second" etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, without departing from the teaching of one or more embodiments, the first element discussed below can be referred to as the second element. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second" etc. can also be used to distinguish between different classes or groups of elements in this article. For the sake of simplicity, the terms "first", "second" etc. can respectively represent "first class (or first group)", "second class (or second group)" etc.

[0029] The terms used herein are used only for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the term "comprising" specifies the presence of the features, regions, steps, operations, elements and / or components set forth, but does not exclude the presence or addition of one or more other features, regions, steps, operations, elements, components and / or groups thereof.

[0030] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientations depicted in the figures. In an exemplary embodiment, when the device in one of the figures is flipped, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Thus, depending on the specific orientation of the figure, the exemplary term "lower" can encompass both "lower" and "upper" orientations. Similarly, when the device in one of the figures is flipped, the element described as being "below" or "below" the other elements will then be oriented "above" the other elements. Thus, the exemplary term "lower" or "below" can encompass both "upper" and "lower" orientations.

[0031] As used herein, "about" or "approximately" includes the stated value and the mean within an acceptable deviation of the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0033] As is customary in the art, some exemplary embodiments are described and illustrated in the figures with respect to functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented using electrical circuits (or optical circuits) such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, and the like, which can be formed using semiconductor-based or other manufacturing technologies. Where blocks, units, and / or modules are implemented using microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented using dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module in some exemplary embodiments can be physically separated into two or more interacting and discrete blocks, units, and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0034] Figure 1 A schematic diagram showing the storage state of a storage unit in a memory according to an embodiment of the present disclosure is shown. The memory according to an embodiment of the present disclosure may include multiple storage units, and the storage units can store multiple storage states. Figure 1 As shown, the exemplary memory cell may include storage states 101, 102, and 103, which may correspond to programming states such as "00", "01", "11", etc., for example. Figure 1 This schematic diagram is merely a schematic diagram for the purpose of illustrating the technical solution of the present disclosure. Other storage states and a greater or fewer number of storage states are also possible in the memory of the present disclosure. There is a gap between the voltages corresponding to the different storage states 101, 102, and 103. When reading the storage state of a memory cell, the different storage states can be distinguished based on threshold voltages 111 and 121. The first threshold voltage 111 is between the first storage state 101 and the second storage state 102, and the second threshold voltage 121 is between the second storage state 102 and the third storage state 103. During the reading process, when the determined voltage is lower than the first threshold voltage 111, the storage state of the corresponding memory cell is the first storage state 101; when the determined voltage is higher than the first threshold voltage 111 and lower than the second threshold voltage 121, the storage state of the corresponding memory cell is the second storage state 102; and when the determined voltage is higher than the second threshold voltage 121, the storage state of the corresponding memory cell is the third storage state 103.

[0035] When programming a memory cell, the memory cell's storage state can be gradually changed from low to high by increasing the programming voltage in steps. Each step of programming a memory cell can be divided into two stages: programming and verification. The verification stage can be further divided into two stages: coarse sensing and fine sensing. Figure 2 A method 200 for programming a memory cell in a memory according to an embodiment of the present disclosure is shown, wherein step 202 is a programming phase, steps 203 to 204 are a coarse sensing phase, and step 205 is a fine sensing phase.

[0036] like Figure 2 As shown, the memory cell is programmed to Figure 1 Taking the third storage state 103 shown as an example, the memory programming method 200 according to the present disclosure may include obtaining a programming temperature (step 201). When programming a memory cell to be programmed in the memory, the temperature of the memory cell during programming can be obtained, for example, by a temperature sensor. This temperature can be the current temperature of the cell to be programmed, and this temperature can be used to determine the temperature compensation time used in subsequent steps. It should be noted that the step of obtaining the programming temperature does not necessarily have to be performed first, and it can also be performed after other steps, as long as the temperature is determined before determining the temperature compensation time.

[0037] In step 202, a programming voltage may be applied to the memory cell to be programmed. For example, a programming voltage may be applied to the word line corresponding to the memory cell to be programmed, and at the same time, the bit line corresponding to the memory cell to be programmed is placed at a low voltage, thereby changing the charge on the floating gate of the memory cell to be programmed to store state information.

[0038] After the programming phase, it is necessary to verify whether the programmed memory cell has reached the desired storage state. To this end, the programming method 200 according to the present disclosure includes a coarse sensing phase (steps 203 and 204). In step 203, a verification voltage is applied to the memory cell to be programmed to turn on the memory cell to be programmed. For example, a verification voltage may be applied to the control electrode (i.e., the corresponding word line) of the memory cell to be programmed. After the memory cell to be programmed is turned on, the charge stored therein will be lost over time. Accordingly, the bit line voltage sensed on the bit line corresponding to the memory cell to be programmed will also decrease. This process may last for a period of time, for example, for a first sensing time.

[0039] After the first sensing time, it can be determined whether the bit line voltage of the memory cell to be programmed is higher than the first target voltage (step 204). The target voltage can correspond to Figure 1The first threshold voltage 111 in the bit line is higher than the first target voltage. If the bit line voltage is higher than the first target voltage, the subsequent fine sensing phase is performed. Otherwise, the programming state does not reach the expected state and the memory cell needs to be reprogrammed. During the reprogramming operation, the programming voltage can be increased to reprogram the memory cell. When the bit line voltage is higher than the first target voltage, it indicates that the storage state of the memory cell to be programmed is, for example, Figure 1 The second storage state 102 or the third storage state 203 shown in FIG. Whether the current storage state is the second storage state 102 or the third storage state 203 can be further determined by a subsequent fine sensing phase.

[0040] Entering the fine verification phase, after a second sensing time, it can be verified that the bit line voltage of the memory cell to be programmed is higher than the second target voltage (step 205). If the bit line voltage is higher than the second target voltage, the programming operation is completed and programming of the memory cell to be programmed can be stopped. Otherwise, the programming state has not reached the expected state and the memory cell needs to be reprogrammed. During the reprogramming operation, the programming voltage can be increased to reprogram the memory cell. In some embodiments, during each reprogramming, a specific step voltage can be increased relative to the previous programming voltage. The same step voltage can be used in consecutive reprogramming processes, or different step voltages can be used. For example, after the first programming, coarse sensing, and / or fine sensing cycle, if the expected storage state is not reached, the programming phase is entered again, and the programming voltage used is increased by a predetermined step voltage compared to the previous cycle. If the expected storage state is still not reached in this cycle, the programming voltage is increased by the predetermined step voltage in the next cycle until the expected storage state is reached.

[0041] In the above process, the first sensing time may include a first predetermined sensing time and a first temperature compensation time, and the second sensing time may include a second predetermined sensing time and a second temperature compensation time. The first predetermined sensing time and the second predetermined sensing time may be predetermined, for example, obtained through experimentation or set by a user, and the first predetermined sensing time may be less than the second predetermined sensing time. The first temperature compensation time and the second temperature compensation time are used to compensate for the effect of the memory operating temperature on programming and reading operations. For example, low temperatures may cause a decrease in saturation current. By adding the temperature compensation time to the original predetermined sensing time, the current flow time is increased or decreased to compensate for differences in current, voltage, etc. caused by temperature differences. In conventional temperature compensation methods, the same temperature compensation time is used for both the coarse sensing stage and the fine sensing stage. However, since the charge loss rate during the sensing stages is not always the same, using the same temperature compensation time for the coarse sensing stage and the fine sensing stage, which are sequential in time, may result in unequal voltage offsets in the two stages, causing a change in the difference in the sensed voltage between the two stages, leading to inaccurate verification and ultimately affecting the accuracy of data storage.

[0042] Specifically, if Figure 3 As shown in FIG, the current drop rate caused by charge loss when the memory cell is turned on is initially fast, and then gradually slows down. In fact, the relationship between current I and time t (for example, temperature compensation time) is approximately inversely proportional. Under such a current-time relationship, if we want to make Figure 4 The sensing voltage change △V in the coarse sensing phase due to charge loss during the temperature compensation time coarse And the sensing voltage change △V during the fine sensing phase fine To keep it consistent, it is necessary to ensure that the current change △I caused by the temperature compensation time during the coarse sensing stage and the fine sensing stage is coarse and △I fine Stay consistent. Figure 3 The curve shown in the figure requires setting different temperature compensation times to obtain the same current change △I coarse and △I fine Since the current drops rapidly in the coarse sensing stage, the first temperature compensation time t coarse Set to be shorter; since the current drops slowly in the fine sensing stage, the second temperature compensation time t fine Set to be longer, that is, to satisfy t fine >t coarse .

[0043] The temperature compensation time can be determined based on the difference between the operating temperature of the memory and a reference temperature (e.g., 85°C). For example, the temperature compensation time for the coarse sensing stage and the fine sensing stage at the reference temperature can be determined in advance through experiments or statistics. When the operating temperature is different from the reference temperature, the temperature compensation time can be adjusted accordingly based on the difference between the operating temperature and the reference temperature. In some embodiments, when the temperature compensation time is adjusted accordingly based on the difference between the operating temperature and the reference temperature, the temperature compensation time can be further adjusted based on the relationship between the current change and time determined by the physical characteristics of the programming cell (such as the number of carriers).

[0044] According to the memory programming method disclosed in the present invention, by adjusting the temperature compensation time of the coarse sensing stage and the fine sensing stage differently, the actual temperature compensation effects of the coarse sensing stage and the fine sensing stage can be ensured to be the same, thereby ensuring the accuracy of data storage and improving the reliability of the memory in dealing with various temperatures.

[0045] When reading a memory cell programmed according to the above method, only the read phase corresponding to the above-described fine sensing phase can be used to read the memory cell. That is, the read process includes only one sensing phase. During this sensing phase, a read voltage can be applied to the memory cell to turn on the memory cell, for example, by applying a read voltage to the word line corresponding to the memory cell. After a read sensing time, the storage state of the memory cell is determined, for example, by sensing the bit line voltage corresponding to the memory cell. During the read phase, the read sensing time includes a predetermined read sensing time and a read temperature compensation time. This read temperature compensation time has the same temperature-dependent relationship curve as the second temperature compensation time used when programming the memory cell. That is, if the read temperature and the programming temperature are the same, the read temperature compensation time is the same as the second temperature compensation time. If the read temperature and the programming temperature are different, the corresponding read temperature compensation time can be obtained based on the read temperature along the same temperature-compensation time curve. This temperature-compensation time curve can be obtained through statistical analysis, experimentation, user settings, or other methods.

[0046] Figure 5 A schematic diagram of a memory according to an embodiment of the present disclosure is shown.

[0047] like Figure 5As shown, the memory 500 according to the embodiment of the present disclosure may include an input / output (I / O) circuit 510 and a storage circuit 520. The I / O circuit 510 is used for communication between the storage circuit and an external device. The I / O circuit 510 may include a bus interface 512 (for example, a PCIE interface, an NVMe interface, etc.), which can receive data from outside the memory and transmit data from the memory to the outside. The I / O circuit 510 also includes an input / output controller 511, which controls the operation of the bus interface. The storage circuit 520 is used to store data, and may include storage arrays 531-534 and a storage controller 521, wherein each of the storage arrays 531-534 may include multiple storage units, and the storage controller 521 is used to control the operations of the multiple storage arrays (for example, read operations, write operations, etc.). For example, the storage controller 521 may perform the above combined operations. Figure 1-4 It should be noted that although Figure 5 Four storage arrays are shown in FIG. 5 , but the present application is not limited thereto, and the memory 500 may include any number of storage arrays.

[0048] The memory 500 according to the embodiment of the present application may further include a temperature sensor, which may be located in the I / O circuit 510 or the memory circuit 520. When the temperature sensor is located in the I / O circuit 510, the I / O controller 511 may transmit the current temperature of the memory sensed by the temperature sensor to the memory controller 521 as the programming temperature of the memory cell to be programmed. When the temperature sensor is located in the memory circuit 520, the memory controller 521 may be configured to use the current temperature of the memory cell to be programmed sensed by the temperature sensor as the programming temperature of the memory cell to be programmed. When programming a memory cell to be programmed among a plurality of memory cells, the memory controller is configured to: obtain a programming temperature of the memory cell to be programmed in the memory array; apply a programming voltage to the memory cell to be programmed to change the storage state of the memory cell to be programmed; apply a verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determine whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; if so, determine whether the bit line voltage of the memory cell to be programmed is higher than a second target voltage after a second sensing time, and if so, stop programming the cell to be programmed, wherein the first sensing time includes a first temperature compensation time adjusted according to the programming temperature, and the second sensing time includes a second temperature compensation time adjusted according to the programming temperature, and the first temperature compensation time and the second temperature compensation time are different.

[0049] In one embodiment, the first sensing time includes a first predetermined sensing time and a first temperature compensation time, and the second sensing time includes a second predetermined sensing time and a second temperature compensation time, the first predetermined sensing time being smaller than the second predetermined sensing time.

[0050] In one embodiment, the first temperature compensation time and the second temperature compensation time are determined according to a difference between the programming temperature and a predetermined reference temperature.

[0051] In one embodiment, the reference temperature is 85°C.

[0052] In one embodiment, the first temperature compensation time and the second temperature compensation time are respectively determined according to a curve of a change in a sensing current over time when the memory cell to be programmed is turned on within a corresponding time period at the programming temperature.

[0053] In one embodiment, when the slope time of the variation curve decreases, the first temperature compensation time is set to be smaller than the second temperature compensation time.

[0054] In one embodiment, the faster the charge loss rate in the corresponding time period is, the shorter the corresponding first temperature compensation time or second temperature compensation time is.

[0055] In one embodiment, the first temperature compensation time and the second temperature compensation time are determined according to a difference between a programming temperature and a reference temperature and a curve of a change in a sensing current over time when the memory cell to be programmed is turned on at the programming temperature.

[0056] In one embodiment, the controller is further configured to: reprogram the memory cell to be programmed when the bit line voltage is less than or equal to the first target voltage after the first sensing time or when the bit line voltage is less than or equal to the second target voltage after the second sensing time, wherein the reprogramming includes: changing the programming voltage; applying the changed programming voltage to the memory cell to be programmed to change the storage state of the memory cell to be programmed; applying the verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether the bit line voltage of the memory cell to be programmed is higher than the first target voltage after the first sensing time; if so, then after the second sensing time, detecting whether the bit line voltage of the memory cell to be programmed is higher than the second target voltage, if so, stopping programming of the memory cell to be programmed, and if not, repeating the above steps until the bit line voltage of the memory cell to be programmed is higher than the second target voltage.

[0057] In one embodiment, the controller is further configured to increase the programming voltage when reprogramming the memory cell to be programmed.

[0058] In one embodiment, the controller is further configured to: when reprogramming the memory cell to be programmed multiple times, gradually increase the programming voltage with the same step voltage.

[0059] In one embodiment, when reading a programmed memory cell to be read among a plurality of memory cells, the configuration is as follows: applying a read voltage to the memory cell to be read to turn on the memory cell to be read; and determining a storage state of the memory cell to be read after a read sensing time, wherein the read sensing time includes a read temperature compensation time, and the read temperature compensation time has the same relationship curve with respect to temperature as a second temperature compensation time used when programming the memory cell to be read.

[0060] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the present invention. Therefore, the disclosed preferred embodiments of the present invention are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A method for programming a memory, comprising: Acquiring a programming temperature of a memory cell to be programmed of the memory, wherein the programming temperature is the temperature of the memory cell to be programmed; Applying a programming voltage to the memory cell to be programmed to change the storage state of the memory cell to be programmed; applying a verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; and If yes, then after the second sensing time, it is detected whether the bit line voltage of the memory cell to be programmed is higher than the second target voltage, The first sensing time includes a first predetermined sensing time and a first temperature compensation time adjusted according to the programmed temperature, and the second sensing time includes a second predetermined sensing time and a second temperature compensation time adjusted according to the programmed temperature, the first temperature compensation time and the second temperature compensation time are different, and the first predetermined sensing time is less than the second predetermined sensing time.

2. The programming method according to claim 1, wherein: The first temperature compensation time and the second temperature compensation time are determined according to a difference between the programming temperature and a predetermined reference temperature.

3. The programming method according to claim 2, wherein: The reference temperature is 85°C.

4. The programming method according to claim 1, wherein: The first temperature compensation time and the second temperature compensation time are respectively determined according to a curve of a change in a sensing current over time when the memory cell to be programmed is turned on within a corresponding time period at the programming temperature.

5. The programming method according to claim 4, wherein: When the slope time of the variation curve decreases, the first temperature compensation time is set to be smaller than the second temperature compensation time. The programming method according to claim 5 , wherein: The faster the charge loss rate in the corresponding time period is, the shorter the corresponding first temperature compensation time or second temperature compensation time is.

7. The programming method according to claim 1, wherein: The first temperature compensation time and the second temperature compensation time are determined according to a difference between the programming temperature and a reference temperature and a curve of a change in a sensing current over time when the memory cell to be programmed is turned on at the programming temperature.

8. The programming method according to claim 1, further comprising: When the bit line voltage is less than or equal to the first target voltage after the first sensing time or when the bit line voltage is less than or equal to the second target voltage after the second sensing time, reprogramming the memory cell to be programmed; Wherein, the reprogramming includes: changing the programming voltage; applying a changed programming voltage to the memory cell to be programmed to change the storage state of the memory cell to be programmed; applying the verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than the first target voltage after the first sensing time; If so, after the second sensing time, detect whether the bit line voltage of the memory cell to be programmed is higher than the second target voltage. If so, stop programming the memory cell to be programmed. If not, repeat the above steps until the bit line voltage of the memory cell to be programmed is higher than the second target voltage.

9. The programming method according to claim 8, further comprising: When reprogramming the memory cell to be programmed, the programming voltage is increased.

10. The programming method according to claim 9, further comprising: When reprogramming the memory cell to be programmed is performed multiple times, the programming voltage is gradually increased with the same step voltage.

11. The programming method according to claim 1 , further comprising: applying a read voltage to the programmed memory cell to turn on the programmed memory cell; A storage state of the programmed memory cell is determined after a read sensing time, wherein the read sensing time includes a read temperature compensation time, the read temperature compensation time being determined based on a temperature when the programmed memory cell is read and having the same relationship curve with respect to temperature as the second temperature compensation time used when programming the programmed memory cell.

12. A memory comprising: a storage array comprising a plurality of storage units; as well as a storage controller configured to control operations of the plurality of storage arrays, The storage controller is configured to: Obtaining a programming temperature of a memory cell to be programmed in the memory array; Applying a programming voltage to the memory cell to be programmed to change the storage state of the memory cell to be programmed; applying a verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; and If yes, then after the second sensing time, determining whether the bit line voltage of the memory cell to be programmed is higher than a second target voltage, The first sensing time includes a first predetermined sensing time and a first temperature compensation time adjusted according to the programmed temperature, and the second sensing time includes a second predetermined sensing time and a second temperature compensation time adjusted according to the programmed temperature, the first temperature compensation time and the second temperature compensation time are different, and the first predetermined sensing time is less than the second predetermined sensing time.

13. The memory according to claim 12, wherein: Also includes: Input / output circuits, including: a bus interface configured to receive data from outside the memory and transmit data from the memory to the outside; as well as an input / output controller configured to control the operation of the bus interface; The input / output circuit further includes a temperature sensor configured to sense a temperature of the memory, and The input / output controller is further configured to transmit the temperature of the memory to the memory controller as a programming temperature of the memory cell to be programmed.

14. The memory according to claim 12, wherein: The memory circuit further includes a temperature sensor configured to sense the temperature of the memory cell to be programmed, and The memory controller is further configured to use the temperature of the memory cell to be programmed as a programming temperature of the memory cell to be programmed.

15. The memory according to claim 12 or 14, wherein: The first temperature compensation time and the second temperature compensation time are determined according to a difference between the programming temperature and a predetermined reference temperature.

16. The memory according to claim 15, wherein The reference temperature is 85°C.

17. The memory according to claim 12, wherein: The first temperature compensation time and the second temperature compensation time are respectively determined according to a curve of a change in a sensing current over time when the memory cell to be programmed is turned on within a corresponding time period at the programming temperature.

18. The memory according to claim 17, wherein When the slope time of the variation curve decreases, the first temperature compensation time is set to be smaller than the second temperature compensation time.

19. The memory according to claim 17, wherein The faster the charge loss rate in the corresponding time period is, the shorter the corresponding first temperature compensation time or second temperature compensation time is.

20. The memory according to claim 12, wherein The first temperature compensation time and the second temperature compensation time are determined according to a difference between the programming temperature and a reference temperature and a curve of a change in a sensing current over time when the memory cell to be programmed is turned on at the programming temperature.

21. The memory according to claim 12, wherein the controller is further configured to: When the bit line voltage is less than or equal to the first target voltage after the first sensing time or when the bit line voltage is less than or equal to the second target voltage after the second sensing time, the memory cell to be programmed is reprogrammed. in, The reprogramming includes: changing the programming voltage; applying a changed programming voltage to the memory cell to be programmed to change the storage state of the memory cell to be programmed; applying the verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than the first target voltage after the first sensing time; If so, after the second sensing time, detect whether the bit line voltage of the memory cell to be programmed is higher than the second target voltage. If so, stop programming the memory cell to be programmed. If not, repeat the above steps until the bit line voltage of the memory cell to be programmed is higher than the second target voltage. 22 . The memory according to claim 21 , wherein the controller is further configured to increase the programming voltage when reprogramming the memory cell to be programmed. 23 . The memory according to claim 22 , wherein the controller is further configured to: gradually increase the programming voltage with a same step voltage when reprogramming the memory cell to be programmed multiple times.

24. The memory according to claim 12, wherein When reading a programmed memory cell to be read from the plurality of memory cells, the method is configured as follows: Applying a read voltage to the memory cell to be read so that the memory cell to be read is turned on; as well as The storage state of the memory cell to be read is determined after a read sensing time, wherein the read sensing time includes a read temperature compensation time, the read temperature compensation time is determined based on the temperature when the memory cell to be read is read, and has the same relationship curve relative to temperature as a second temperature compensation time used when programming the memory cell to be read.

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