Efficient read threshold calculation method for parameterized pv level modeling

Abstract

The present disclosure relates to methods and systems for improving performance related to reading data stored in a memory cell. The method includes selecting a first voltage read range and a second voltage read range from a plurality of voltage read ranges associated with a number of bits that can be stored in the memory cell. The method includes receiving a first set of parameters representing a first probability distribution of first candidate voltage read thresholds within the first voltage read range. The method includes receiving a second set of parameters representing a second probability distribution of second candidate voltage read thresholds within the second voltage read range. The method includes generating a voltage read threshold based on inputs of an objective function. The method includes reading data stored in the memory cell based on the voltage read threshold.

Description

TECHNICAL FIELD

[0001] The disclosure relates generally to a memory system and an operating method of a memory system, and more particularly, to a method and system for improving performance related to reading data stored in a memory cell. BACKGROUND

[0002] In NAND flash memory, a memory cell can store one or more bits as a voltage value. For example, a single-level cell stores one bit, and a measured voltage value can be compared to a single voltage threshold to determine the logical value (e.g., "0" or "1") of the bit. A multi-level cell (MLC) can store two bits, and a measured voltage value can be compared to three voltage thresholds to determine the logical value of each bit. Generally, the logical value stored in a memory cell is determined by a voltage range (e.g., 1-2V, 2-3V, 3-4V, etc.) between each of the three voltage thresholds, and the threshold voltage of the cell is within the voltage range. As each memory cell stores more bits, the threshold voltage range becomes smaller, resulting in an increased error rate in determining the value of the memory cell.

[0003] Error correction codes (ECC) are generally used in various types of data storage devices, including NAND flash memory. ECC is also often used in data transmission processes. ECC refers to a code that adds redundant data or parity data to a message so that even if some errors are introduced during transmission or storage, the receiver can recover the message. Generally, ECC can correct errors depending on the capability of the code used. ECC decoding can include hard decoding, such as Bose-Chaudhuri-Hocquenghem (BCH) decoding, in which the logical value stored in a memory cell is determined by the voltage range in which the threshold voltage of the cell falls. ECC decoding can also include soft decoding, such as low-density parity-check code (LDPC) decoding, in which the logical value stored in a memory cell is represented as a probability distribution.

[0004] The accuracy of reading threshold voltages is critical to storage devices including solid state drives using NAND flash memory technology, as better reading threshold voltages produce lower raw bit error rates (RBER), which determine SSD system performance such as input / output operations per second (IOP) and throughput. However, the optimal reading threshold voltage of a memory cell can change according to a large number of variable factors during the lifetime of the storage device. In theory, if all factors affecting the reading threshold voltage change were known, the optimal reading threshold could be determined from the characteristics of the offline memory. For example, a lookup table could be generated, where the table relates the optimal reading threshold to possible combinations of the variable factors under different implementations of the factors. However, such a table is practically difficult to implement, in part because it requires a large number of implementations and can not produce the optimal voltage reading threshold, as not all possible combinations and implementations can be determined offline. SUMMARY

[0005] Techniques related to improving performance with respect to generating voltage read ranges are described. The techniques involve a computer system for reading data from a storage device and an implementation method on such a computer system. In an example, the computer system includes a processor and a memory communicatively coupled with the processor. The memory is configured to store client data, a voltage read range generator, and computer-readable instructions. The voltage read range generator receives a first set of parameters representing a first probability distribution within a first voltage read range and a second set of parameters representing a second probability distribution within a second voltage read range. The computer-readable instructions, when executed by the processor, configure the computer system to perform an operation. The operation includes generating a voltage read threshold based on an input of an objective function and the first voltage read range and the second voltage read range.

[0006] In one example, a method for improving performance related to reading data stored in a memory cell is disclosed. The method includes selecting a first voltage read range and a second voltage read range from a plurality of voltage read ranges associated with a number of bits that can be stored in the memory cell. The method includes receiving a first set of parameters representing a first probability distribution of a first candidate voltage read threshold within the first voltage read range. The method includes receiving a second set of parameters representing a second probability distribution of a second candidate voltage read threshold within the second voltage read range. The method includes generating a voltage read threshold based on an input of an objective function. The method includes reading the data stored in the memory cell based on the voltage read threshold.

[0007] Reference to this illustrative example is not intended to limit or restrict the disclosure to such example, but rather the example is intended to provide an example for helping to understand the disclosure. Additional embodiments and examples are discussed in the DETAILED DESCRIPTION and further described therein. BRIEF DESCRIPTION OF DRAWINGS

[0008] An understanding of the nature and advantages of various embodiments can be realized by reference to the following drawings.

[0009] Figure 1 An example of a high-level block diagram of an error correction system according to certain embodiments of the present disclosure is shown.

[0010] Figure 2 An example of a computer system including a host and a storage device according to certain embodiments of the present disclosure is shown.

[0011] Figure 3 An example of bit storage in a NAND flash memory according to certain embodiments of the present disclosure is shown.

[0012] Figure 4 An example of a computer system including a voltage read threshold generator according to certain embodiments of the present disclosure is shown.

[0013] Figure 5 An example of how a neural network can be used to generate voltage read thresholds according to certain embodiments of the present disclosure is shown.

[0014] Figure 6 A plot depicting example voltage read thresholds generated according to some embodiments of the present disclosure is shown.

[0015] Figure 7 A plot depicting an example and a log representation of the difference between two program verify level model curves depicting an objective function according to some embodiments of the present disclosure is shown.

[0016] Figure 8 An example of a graph showing an approximation of a log function and an approximation error according to some embodiments of the present disclosure is shown.

[0017] Figure 9 An example of a graph showing an approximation of a log of a probability distribution function Φ(x) and an approximation error according to some embodiments of the present disclosure is shown.

[0018] Figure 10 An example of a flow of reading a storage cell using a threshold read voltage according to certain embodiments of the present disclosure is shown.

[0019] Figure 11 An example of a plot depicting adjustment of a candidate voltage read threshold according to certain embodiments of the present disclosure is shown.

[0020] Figure 12 An example of a computing system for generating voltage read thresholds according to certain embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0021] Techniques are described for improving performance related to generating voltage read thresholds. The techniques involve a computer system that reads data from a storage device and an implementation method on such a computer system. In an example, the computer system includes a processor and a memory communicatively coupled with the processor. The memory is configured to store client data, voltage read thresholds, and computer-readable instructions. A voltage read range generator receives a first set of parameters representing a first probability distribution within a first voltage read range and a second set of parameters representing a second probability distribution within a second voltage read range. The computer-readable instructions, when executed by the processor, configure the computer system to perform an operation. The operation includes generating a voltage read threshold based on inputs of an objective function and the first voltage read range and the second voltage read range. The first voltage read range represents a first set of bit values. For example, when a voltage level of a read memory cell is less than the voltage read threshold, the bits of the memory cell are determined to have a first bit value and these bits represent data stored in the memory cell. The second voltage read range represents a second set of bit values. For example, when a voltage level of a read memory cell is greater than the voltage read threshold, the bits of the memory cell are determined to have a second bit value and these bits represent data stored in the memory cell.

[0022] To illustrate this, consider an example of a NAND flash memory using triple level cell (TLC) technology, where each memory cell stores three bits of data. Seven voltage read thresholds are needed to determine the logical values of the three bits stored in the memory cell. Within a block of a die of the NAND flash memory, the memory cells can be organized into a most significant bit (MSB) page, a least significant bit (LSB) page, and a central significant bit (CSB) page. Three of the seven voltage read thresholds are associated with the MSB page, two of the seven voltage read thresholds are associated with the LSB page, and the remaining two of the seven voltage read thresholds are associated with the CSB page.

[0023] In this example, the voltage read thresholds associated with a page are associated with program verify (PV) levels that indicate values of bits. Each of these PV levels has a probability distribution with a voltage corresponding to the PV level. When reading data from a memory cell, a read voltage can be represented by a position in one of the probability distributions of the respective PV levels. For example, in a three-bit memory cell, there are PV levels 0-7 that correspond to “000,” “001,” and so on up to bit values “111.” Some probability distributions of a particular PV level can overlap with adjacent PV levels, which can cause bit errors when reading data associated with the PV levels. A voltage read threshold generator can determine voltage read thresholds using an objective function and sets of parameters that describe the probability distributions of each adjacent PV level. A computer system can use the generated voltage read thresholds to read data from a memory cell.

[0024] Embodiments of the present disclosure provide several advantages related to computer storage. For example, embodiments provide better voltage read thresholds relative to existing systems (e.g., relative to existing systems that do not change these thresholds or change these thresholds using a pre-defined table). Better read thresholds result in lower raw bit error rates (RBER), and corresponding improvements in performance metrics such as IOP and throughput of the data storage device. Using the methods described herein reduces MAC operations by approximately 3000x, and provides similar levels of savings in load store operations.

[0025] Embodiments of the present disclosure are described in connection with LDPC codewords and NAND flash memory for clarity of explanation. However, embodiments are not limited thereto and are applicable to any other encoding and decoding processes and any other type of data storage.

[0026] Figure 1 An example of a high-level block diagram of an error correction system 100 according to certain embodiments of the present disclosure is shown. In this example, LDPC codes are described in connection with data storage. However, embodiments of the present disclosure are not limited thereto. Rather, embodiments are equally applicable to other uses of LDPC codes, including, for example, data transmission.

[0027] An LDPC code is a linear block code defined by a sparse parity check matrix H consisting of 0s and Is. The term "sparse matrix" is used herein to refer to a matrix in which the number of non-zero values in each column and each row is much smaller than its dimension. The term "column weight" is used herein to refer to the number of non-zero values in a particular column of the parity check matrix H. The term "row weight" is used herein to refer to the number of non-zero values in a particular row of the parity check matrix H. Generally, if the column weights of all columns in the parity check matrix corresponding to an LDPC code are similar, the code is referred to as a "regular" LDPC code. On the other hand, if at least one of the column weights is different from the other column weights, the LDPC code is referred to as "irregular." In general, irregular LDPC codes provide better error correction capability than regular LDPC codes.

[0028] LDPC codes are also described in terms of the way in which they are constructed. Random computer search or algebraic construction is possible. Random computer search construction describes an LDPC code with a parity check matrix designed by a random computer-based program. Algebraic construction means that the parity check matrix is constructed based on combinatorial methods. Quasi-cyclic LDPC (QC-LDPC) codes belong to the latter construction method. One advantage of QC-LDPC codes is that they are relatively easy to implement in terms of encoding process. The main feature of QC-LDPC codes is that the parity check matrix is composed of circulant sub-matrices, which can be based on an identity matrix or a smaller random matrix. A permutation vector can also be used to create the circulant sub-matrices.

[0029] As shown, the LDPC encoder 110 receives information bits that include data that needs to be stored in the storage system 120. The LDPC encoded data is output by the LDPC encoder 110 and written to the storage system 120.

[0030] In various embodiments, the storage system 120 can include various storage types or media, such as (e.g., magnetic, solid state) disk drive storage, flash storage, etc. In some embodiments, these techniques are applied in a transceiver, and data is transmitted and received over wired and / or wireless channels, rather than being written to or read from storage. In this case, errors can be introduced in the received codeword during transmission of the codeword.

[0031] When the stored data is requested or otherwise needed (e.g., by an application or user that stored the data), the detector 130 receives the data from the storage system 120. The received data can include some noise or errors. The detector 130 performs detection on the received data and outputs decisions and / or reliability information. For example, a soft output detector outputs reliability information and a decision for each detected bit (e.g., a logical value of "1" or "0"). On the other hand, a hard output detector outputs a decision about each bit without providing corresponding reliability information. As an example, a hard output detector can output a decision that a particular bit is "1" or "0" without indicating the degree of detector certainty in the decision. In contrast, a soft output detector outputs a decision and reliability information associated with the decision. In general, the reliability value in a given decision indicates the degree of detector certainty. In one example, a soft output detector outputs a log-likelihood ratio (LLR), where the sign indicates the decision (e.g., a positive value corresponds to a decision of "1" and a negative value corresponds to a decision of "0") and the magnitude indicates the degree of detector certainty in the decision (e.g., a larger magnitude indicates a higher reliability or certainty).

[0032] The decisions and / or reliability information are passed to the LDPC decoder 140 that performs LDPC decoding using the decisions and reliability information. A soft input decoder utilizes both the decisions and reliability information to decode the codeword. A hard decoder utilizes only the decision values in the decoder to decode the codeword. The decoded bits generated by the LDPC decoder 140 are passed to the appropriate entity (e.g., a user or application that requested the decoded bits). Through proper encoding and decoding, the information bits match the decoded bits.

[0033] In various embodiments, the illustrated systems can be implemented using a wide variety of technologies including application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and / or general purpose processors (e.g., Advanced RISC Machines (ARM) cores).

[0034] LDPC codes are generally represented by a bipartite graph. One set of nodes, variable or bit nodes, corresponds to the elements of a codeword, while the other set of nodes, e.g., check nodes, corresponds to the set of parity check constraints satisfied by the codeword. Generally, the edge connections are chosen randomly. The error correction capability of an LDPC code is improved if short length cycles are avoided in the graph. In a (r, c) regular code, each of the n variable nodes (V1, V2,..., Vn) is connected to r check nodes and each of the m check nodes (C1, C2,..., Cm) is connected to c bit nodes. In irregular LDPC codes, the check node degree is not uniform. Similarly, the variable node degree is not uniform. In QC-LDPC codes, the parity check matrix H is constructed as p x p matrix blocks such that a bit in a block participates in only one check equation in that block and each check equation in a block involves only one bit from the block. In QC-LDPC codes, a cyclic shift of a codeword by p produces another codeword. Here p is the size of a square matrix that is either a zero matrix or a circulant matrix. This is a generalization of a cyclic code in which a cyclic shift of a codeword by 1 produces another codeword. The p x p matrix blocks can be either zero matrices or cyclic shifted identity matrices of size p x p.

[0035] Message passing algorithms are generally used to decode LDPC codes. There are several variants of message passing algorithms in the art, such as the min-sum (MS) algorithm, the sum-product algorithm (SPA), etc. Message passing uses a network of variable nodes and check nodes. The connections between variable nodes and check nodes are described by and correspond to the values of the parity check matrix.

[0036] In an example, a hard decision message passing algorithm can be performed. In a first step, each of the variable nodes sends a message to one or more check nodes connected to that variable node. In this case, the message is the value that each of the variable nodes believes to be its correct value.

[0037] In a second step, each of the check nodes uses the information it previously received from the variable nodes to compute a response to send to the variable nodes connected to it. This step can be referred to as check node update (CNU). The response message corresponds to the value that the check node believes the variable node should have based on the information received from the other variable nodes connected to that check node. The response is computed using a parity check equation that forces the sum of the values of all variable nodes connected to a particular check node to be zero (modulo 2).

[0038] At this point, if all the equations at all the check nodes are satisfied, the decoding algorithm declares that the correct codeword has been found and the decoding algorithm terminates. If the correct codeword is not found, the iteration continues with another update from the variable nodes using the messages received by the variable nodes from the check nodes to decide, according to the majority rule, whether the bit at the variable node position should be a zero or a one. The variable node then sends this hard decision message to the check nodes connected to the variable node. The iteration continues until the correct codeword is found, a certain number of iterations is performed according to the check sum of the codeword (e.g., the decoded codeword), or a maximum number of iterations is performed without finding the correct codeword. It should be noted that a soft decision decoder works similarly, however, each of the messages passed between the check nodes and the variable nodes also includes a reliability of each bit.

[0039] In another example, a soft message passing algorithm can be performed. In this example, L(qij) represents the message sent by a variable node v i to a check node c j ; L(r ji ) represents the message sent by a check node c j to a variable node v i ; and L(c i ) represents the initial LLR value for each variable node v i . Variable node processing for each L(qij) can be accomplished by the following steps:

[0040] (1) Read L(c i ) and L(r ji ) from memory.

[0041] (2) Compute

[0042] (3) Compute each L(Qi-sum) - L(r ij ).

[0043] (4) Output L(Qi-sum) and write back to memory.

[0044] (5) If this is not the last column of memory, go to step 1 and increment i by 1.

[0045] (6) Compute parity sums (e.g., check sums), stop if they are all equal to zero, the number of iterations reaches a threshold and the parity sums are greater than another threshold, or the number of iterations is equal to a maximum limit; otherwise, perform check node processing.

[0046] Check node processing for each L(rji) can be performed as follows:

[0047] (1) Read a row of qij from memory.

[0048] (2) Calculate L(Rj-sum) as follows:

[0049]

[0050] α ij =sign(L(q) ij )), β ij =|L(q) ij )|,

[0051]

[0052] (3) Calculate the individual verification node

[0053] (4) Let L(r) ji Write back to memory.

[0054] (5) If this is not the last line of memory, go to step one and increment j by 1.

[0055] Figure 2 An example of a computer system including a host 210 and a storage device 220 according to certain embodiments of the present disclosure is shown. The host 210 performs I / O operations 212 including writing data to the storage device 220 and reading data from the storage device 220. In the example, writing data includes using one or more LDPC encoders (…). Figure 2 (Not shown in the image) Encodes the data to generate LDPC codewords stored in storage device 220. Reading the data includes using one or more LDPC decoders (…). Figure 2 (Not shown in the image) The LDPC codewords are decoded to output the decoded data from the storage device 220. Encoding and decoding (e.g., LDPC encoder and decoder) are part of an ECC system that can be implemented between the host 210 and the storage device 220.

[0056] In the example, storage device 220 includes a plurality of memory dies 222 (the number of which is...) Figure 2 (Displayed as "L" in the image). Conversely, each memory die 222 includes a number of blocks 224 (the number of which is within the range of...). Figure 2 The memory cells are organized as “M”. Each of block 224 contains a number of word lines 226 (this number is in...). Figure 2The memory cells can be floating gate transistors such as floating gate MOSFETs. The memory cells can be grouped and / or referenced using a wide variety of configurations including columns, bit lines, pages, and word lines. Other groupings of memory cells 102 are possible, including groupings across different chips, dies, planes, etc. In some embodiments, a page of a block can represent a minimum programmable unit and a minimum readable unit.

[0057] For NAND flash, each block 224 contains sixty-four pages for single-level cell (SLC) flash, one hundred twenty-eight pages for multi-level cell (MLC) flash, three hundred eighty-four pages for triple-level cell (TLC) flash. The size of a page can vary from 2 KB to 8 KB. In MLC flash, two bits within a single cell do not map to the same page. Instead, a set of most significant bits (MSBs) from a group of cells forms a page, referred to as an MSB page. A set of least significant bits (LSBs) from the same group of cells forms a page, referred to as an LSB page. Similarly, for TLC, there are MSB pages and LSB pages. Additionally, bits from the same group and between the MSBs and LSBs form a page, referred to as a central significant bit (CSB) page.

[0058] In some instances, one or more components of the storage device 220 can become unusable due to a failure occurring before or during operation of the storage device 220. The cause of the failure can be due to defects during the manufacturing process, mechanical stress on the storage device 220 before or during use, degradation of dielectric material in the memory cells, etc. Failures can occur at the memory cell level, which can propagate the failure within other components of the storage device 220 and cause a failure. A group of memory cells can be considered failed when data from any one of the memory cells in the group is not writable and / or readable. Additionally or alternatively, a group can be considered failed when at least one of the memory cells in the group is neither writable nor readable. In such cases, an EEC scheme (e.g., a combination of an ECC encoding process and an ECC decoding process) can be used to protect and / or recover data in the failed group.

[0059] Figure 3An example of bit storage in NAND flash memory according to certain embodiments of the present disclosure is shown. Four such memories are shown: single-level cell (SLC) NAND flash memory 310, multi-level cell (MLC) NAND flash memory 320, triple-level cell (TLC) NAND flash memory 330, and quad-level cell (QLC) NAND flash memory 340. Generally, one or more bits are stored in a cell according to the type of NAND flash memory. Storage relies on a mapping that associates a logical value (e.g., "0" or "1") of a bit to a voltage level. The voltage level corresponds to a range of voltages (also referred to herein as a voltage range) such that if a voltage is read as a voltage level and falls within the voltage range, the voltage level can be declared to belong to the voltage range and the bit in the cell is determined to have a logical value corresponding to the voltage range.

[0060] For SLC NAND flash memory 310, one bit (e.g., an information bit or a parity bit) can be stored in a cell. Thus, the cell has two possible voltage levels. A mapping defines a voltage read threshold between the two levels. To check whether the cell contains a "0" or a "1", a read voltage is taken and compared to the voltage read threshold to identify the relevant voltage level and, accordingly, the logical value of the bit. For example, if the read voltage value is less than the voltage read threshold, the first voltage level is identified and the logical value of the bit is determined to be "0". Otherwise, the second voltage level is identified and the logical value of the bit is determined to be "1".

[0061] In contrast, for MLC NAND flash memory 320, two bits can be stored in a cell. Thus, the cell has four possible voltage levels. A mapping defines three voltage read thresholds between the four levels. To check whether each bit contained in the cell is a "0" or a "1", a read voltage is taken and compared to the three voltage read thresholds to identify the relevant voltage level and, accordingly, the logical value of the bit.

[0062] Similarly, for TLC NAND flash memory 330 and QLC NAND flash memory 340, three bits and four bits can be stored in a cell, respectively. Thus, the cells of TLC NAND flash memory 330 and QLC NAND flash memory 340 have eight and sixteen possible voltage levels, respectively. A mapping of TLC NAND flash memory 330 defines seven voltage read thresholds between the eight voltage levels. A mapping of QLC NAND flash memory 340 defines fifteen voltage read thresholds between the sixteen voltage levels. To check whether each bit included in the cell is a "0" or a "1", a read voltage is taken and compared to the voltage read thresholds to identify the relevant voltage level and, accordingly, the logical value of the bit.

[0063] Figure 4 An example of a neural network 400 that can be included in a computing system for generating a voltage read threshold according to certain embodiments of the present disclosure is shown. A feature map 402 associated with one or more input conditions (e.g., a first cumulative distribution 502 or a second cumulative distribution 504) is input to the neural network 400. In turn, the neural network 400 outputs a probability distribution parameter 404. As shown, the neural network 400 includes multiple layers. Features from the feature map 402 are connected to input nodes in an input layer 410 of the neural network 400. The probability distribution parameter 404 is generated by output nodes of an output layer 430. One or more hidden layers 420 of the neural network 400 exist between the input layer 410 and the output layer 430. The neural network 400 is pre-trained to process features from the feature map 402 through the different layers 410, 420, and 430 to output the probability distribution parameter 404. While reference is made to a neural network, it is understood that other types of machine learning models can be used to generate the probability distribution parameter 404. Figure 5 While additional detail is provided, an example of a probability distribution parameter is a set of parameters describing characteristics of a Skew Normal Distribution (e.g., location ξ, scale ω, and shape α) that models a range of voltages in a memory block.

[0064] In some embodiments, the neural network 400 is a multi-layer neural network representing a network of interconnected nodes such as an artificial deep neural network, where knowledge about nodes (e.g., information about particular features represented by nodes) is shared between layers and knowledge specific to each layer is also retained. Each node represents a piece of information. Knowledge can be exchanged between nodes through node-to-node interconnections. The input to the neural network 400 activates a set of nodes. In turn, the set of nodes activates other nodes, propagating knowledge about the input. The activation process is repeated on other nodes until nodes in an output layer are selected and activated.

[0065] As shown, the neural network 400 includes a hierarchy of layers representing a hierarchy of layers of nodes interconnected in a feed-forward manner. An input layer 410 exists at the lowest level. The input layer 410 includes a set of nodes referred to herein as input nodes. When the feature map 402 is input to the neural network 400, each of the input nodes of the input layer 410 is connected to each feature of the feature map. Each of the connections has a weight. These weights are a set of parameters derived from training of the neural network 400. The input nodes transform the features by applying an activation function to the features. Information resulting from the transformation is passed to nodes at a higher level of the hierarchy.

[0066] The output layer 430 exists at the highest level. The output layer 430 includes one or more output nodes. Each output node provides a particular value of a probability distribution parameter. The number of output nodes depends on the number of probability distribution parameters required. For example, if three probability distribution parameters are required to determine a characteristic of a voltage range curve of a memory cell associated with the neural network 400, three output nodes are used, each node generating and outputting one of the three probability distribution parameters. In other words, there is a one-to-one correspondence or mapping between the number of output nodes and the number of probability distribution parameters.

[0067] The hidden layers 420 exist between the input layer 410 and the output layer 430. The hidden layers 420 include “N” hidden layers, where “N” is an integer greater than or equal to 1. In turn, each of the hidden layers further includes a set of nodes referred to herein as hidden nodes. Example hidden layers include an up-sampling layer, a convolutional layer, a fully connected layer, and a data transformation layer.

[0068] At the lowest level of the hidden layers 420, the hidden nodes of that layer are interconnected with the input nodes. At the highest level of the hidden layers 420, the hidden nodes of that layer are interconnected with the output nodes. The input nodes are not directly interconnected with the output nodes. If there are multiple hidden layers, the input nodes are interconnected with the hidden nodes of the lowest hidden layer. In turn, these hidden nodes are interconnected with the hidden nodes of the next hidden layer, and so on.

[0069] An interconnection represents a piece of information about two interconnected nodes. The interconnections have numerical weights that can be adjusted (e.g., based on a training data set) so that the neural network 400 adapts to the input and is able to learn.

[0070] Generally, the hidden layers 420 allow for sharing of knowledge about the input nodes of the input layer 410 among the output nodes of the output layer 430. To do so, a transformation f is applied to the input nodes by the hidden layers 420. In examples, the transformation f is non-linear. Different non-linear transformations f can be used, including, for example, a rectified function f(x) = max(0, x). In examples, a particular non-linear transformation f is selected based on cross-validation. For example, given known examples (x, y), where x e X and y e Y, the function f: X -> Y is selected when it produces the best match.

[0071] The neural network 400 also uses a loss function, / , (or also referred to as a cost function, c), to find the optimal solution. The optimal solution represents a case where the loss of no solution is less than the loss of the optimal solution. In an example, the loss function / includes a mean squared error function that minimizes the mean squared error between the output f(x) and the target value y for all examples (x, y). A backpropagation algorithm that uses gradient descent to minimize the loss function is used to train the neural network 400. In an example, the training is supervised training. During supervised training, the target value y can be set as the probability distribution parameter for a particular combination of operating conditions and storage conditions. Information about the probability distribution parameter and these conditions can be used as training labels. The output f(x) can be the learned probability distribution parameter based on the particular combination as input. The goal of the training is to improve the parameters of the neural network to minimize the difference between the target value y and the output f(x).

[0072] As such, the hidden layer 420 retains knowledge about the input nodes. A set of knowledge is shared among the output nodes based on the interconnections of the hidden nodes and the input nodes.

[0073] In the diagram, the neural network 400 is a deep learning neural network for NAND flash memory. To train the network, labeled data is collected by measuring the NAND data and cell distribution under certain combinations of operating conditions and memory cell locations. The corresponding probability distribution parameters are also collected. For conditions with continuous values, discrete values are generated and used.

[0074] A deep learning neural network is created with “K” input nodes and output nodes, where “K” is the number of factors (e.g., features) that define the input conditions. The output nodes are used to perform an activation function to compute the probability distribution parameter for a certain combination of input conditions. The number of layers and the size of each layer depend on the NAND flash memory and the amount of data that the memory can store. The number of layers and the size can be selected as hyperparameters of the trained model.

[0075] Once trained, a particular combination of operating conditions and storage conditions (e.g., current conditions) is provided to the deep learning neural network. In turn, the deep learning neural network computes the optimal read threshold voltage for the particular conditions. The probability distribution parameter is the output of the deep learning neural network and can be provided to the voltage read threshold generator.

[0076] Figure 5Examples of computer systems including a voltage readout threshold generator 510 according to certain embodiments of the present disclosure are shown. In some cases, the computer system may include a storage system such as a solid-state drive (SSD). As shown, the computer system 500 also includes a neural network 506, a second neural network 508, a floating-point unit (FPU) 512, and an approximation generator 514 and outputs a candidate readout threshold 518. For an n-bit multi-layer cell NAND flash memory, the threshold voltage for each cell can be programmed to 2. n There are several possible values. In an ideal multi-cell NAND flash memory, each value corresponds to a non-overlapping threshold voltage range. However, in many systems, due to operating conditions, the threshold voltage ranges of each value may partially overlap. See also... Figure 8 Examples of this overlap will be discussed in detail.

[0077] For example, neural network 506 can receive a first cumulative distribution function (CDF) representing a skewed distribution model of a first threshold voltage range. The first CDF can be generated by another neural network, iteratively simulated to determine the parameter representation of the threshold voltage range. The first CDF 502 can correspond to the first layer of a multi-layer cell NAND flash memory. Each multi-layer cell has multiple levels based on the number of bits stored in the cell. In one example, a three-layer cell (TLC) stores three bits per multi-layer cell and has 2... n There are one or eight levels. Each of the eight levels of a three-dimensional TLC corresponds to a voltage range that can be represented by CDF 502. The neural network 506 can receive a second CDF 504 representing a skewed distribution model of a second threshold voltage range. The second CDF 504 can correspond to a second layer of the multilayer cell. The neural network 506 can be about Figure 4 The neural network 506 described and trained to output a probability distribution parameter 514. The neural network 506 can output various parameters, including but not limited to position, variance, and parameters derived from Θ. L =(ξ L ,ω L ,α L The first CDF 502 and the value of Θ are represented by ) R =(ξ R ,ω R ,α R The θ represents the skewness of each of the second CDF 504. The neural network 506 can represent the first set of parameters Θ of the first CDF 502. L And represents the second set of parameters Θ of the second CDF 504. R (Collectively referred to as "probability distribution parameter 514") is provided to the voltage reading threshold generator 510.

[0078] The voltage reading threshold generator 510 can be a processor running firmware-level code. The voltage reading threshold generator 510 can receive probability distribution parameters 514 from the neural network 506. The voltage reading threshold generator 510 can use a first set of parameters Θ... L The second set of parameters Θ R The voltage read threshold is generated as input to the objective function. An example of the objective function is a function that has a root at the voltage read threshold (e.g., a crossover point) and minimizes the error rate when reading data stored in multi-level memory cells.

[0079] In one example, the objective function can be expressed as O(x) = f(x; Θ). L )-f(x;Θ R ), where f(x; Θ L ) represents a function describing the probability distribution of the first programming verification level associated with the first voltage range, f(x; Θ) R ) represents a function describing the probability distribution of the second programming verification level associated with the second voltage range. For example, the probability distribution function of a skewed distribution is equal to and and

[0080] The voltage readout threshold generator 510 can determine a logarithmic representation of an objective function that can be estimated by one or more low-order polynomials. The voltage readout threshold generator 510 can provide the logarithmic representation of the objective function to a floating-point unit. For example, t l (x) represents the value from the first programming verification level and is determined by... Calculate t R (x) represents the value from the second programming verification level and is determined by... Calculation. The voltage readout threshold generator 510 can use these terms to calculate the logarithmic representation of the objective function L(x), which can be expressed as:

[0081]

[0082] The voltage read threshold generator 510 can evaluate the approximate objective function at one candidate read threshold with less than 30 multiplications. In contrast, a neural network with 4 hidden layers and 128 nodes per layer requires over 99K MAC operations to evaluate the PDFs of two distributions at one candidate read threshold. Thus, the proposed scheme reduces the requirement of MAC operations by about 3000 times and provides a similar level of saving in load-store operations. For example, by approximating the functions log(·) and log(Φ(·)) with low order polynomials of the function argument, such that the coefficients of the polynomials are low precision floating point values, the computational efficiency of L(x) is improved. For example, p l (t) = a o + a1t + a2t 2 +... + a m t m and p lΦ (t) = b0+ b1t +... + b n t n represent mth and nth order approximations of log(t) and log(Φ(t)), respectively. These approximations can be made more accurate by dividing the domain of the function argument and using different polynomials for each range. Figure 8 and Figure 9 show examples of piecewise approximations of the functions log(·) and log(Φ(·)), respectively. In some examples, the values of the polynomials can be computed using Horner's method or Estrin's method, depending on the pipeline structure of the processor running the firmware.

[0083] The voltage read threshold generator 510 or the FPU 512 can use fused multiply- accumulate operations performed by the processor running the firmware on low precision floating point values to efficiently compute the values of each of the polynomials. The voltage read threshold generator can use the approximate functions to define the approximate objective function represented by:

[0084]

[0085] The voltage read threshold generator 510 can also provide the first set of parameters and the second set of parameters to a floating point unit (FPU) 512. An example of the FPU 512 can be a coprocessor to perform approximation operations at a target accuracy. The FPU 512 can receive a set of coefficients from the approximation generator 516 (e.g., a polynomial generator) to utilize a low order polynomial to approximate a logarithmic representation of the target function such that the coefficients are low precision floating point values. In one example, the voltage read threshold generator 512 can partition the domain of the target function for the approximation generator 516 and the FPU 512. The FPU 512 can compute a piecewise approximation by receiving a plurality of sets of polynomials from the approximation generator 516 that correspond to the partitioned segments of the domain. The FPU 512 can efficiently use multiple accumulation operations for each polynomial of the piecewise approximation. The voltage read threshold generator 510 can generate an approximation of the target function. The voltage read threshold generator 510 estimates a root of the approximation of the target function A(x) by evaluating A(x) at a candidate read threshold and updating the candidate read threshold until a root of the approximation of the target function is determined. In one example, an interval [x1, x2] is initialized as [ξ L ,ξ R ] and a first candidate read threshold is generated at the midpoint of the interval. The voltage read threshold generator 510 updates the interval according to the value of the approximation of the target function at the first candidate read threshold. The first candidate read threshold corresponds to a candidate voltage read level of the multi-layer memory cell. For example, the first candidate read threshold corresponds to a voltage level within a voltage range associated with a PV level of the multi-layer memory cell.

[0086] In another example, the voltage read threshold generator 510 can use the secant method to estimate the candidate read threshold by estimating a gradient of the approximation of the target function A(x) using a finite difference of each iteration and generating the candidate read threshold using the estimated gradient. For this example, the gradient of the approximation of the target function A(x) can be computed accurately as:

[0087]

[0088] where the term b lΦ (t) is represented by d lΦ (t) = b1+ b2t + b3t 2 +... + b n t n-1 . The d lΦ (t) can be an (n-1) order polynomial that shares coefficients with the polynomial p lΦ . The FPU 512 can evaluate the polynomial p lΦ and in evaluating the polynomial p lΦThe output is used during the period of the value. The voltage read threshold generator 510 uses the gradient at the candidate read threshold to determine the step size in the Netwon's method to converge to the optimal read threshold in fewer iterations.

[0089] The approximation generator 516 can be a ROM that stores the polynomial coefficients. In one example, the approximation generator 516 can store half-precision values (i.e., 16-bit wide). The approximation generator can use a 5thorder polynomial with a 5-segment approximation of the target function O(x). Using this configuration, the approximation generator requires a total of 960 bits of ROM. In contrast, when Vt— ξ, ω, a are quantized to 64 levels respectively, a LUT storing 16-bit wide PDF values requires 512 KB of ROM. Thus, the systems and methods described herein provide over 4000x savings in ROM.

[0090] Figure 6 A plot 600 of example voltage read thresholds generated according to some embodiments of the disclosure is depicted. For example, the plot 600 depicts a first curve 602 representing a probability distribution of a first voltage range 608 and a second curve 604 representing a probability distribution of a second voltage range 610 as described with respect to Figure 5 The voltage threshold generator computes a voltage threshold 606 that is an intersection point between the first voltage range 608 and the second voltage range 610 as shown by the intersection of the first curve 602 and the second curve 604. In Figure 6 In the depicted example, the first curve 602 and the second curve 604 depict a logarithmic function of the two voltage ranges. Each of the first voltage range 608 and the second voltage range 610 is modeled by a set of skew distribution parameters as shown by the legend of the plot 600.

[0091] Figure 7 A plot 700 of an example of a log representation of a difference between a target function and two programmed verify level model curves according to some embodiments of the disclosure is depicted. For example, the target function curve 702 can be the target function described with respect to Figure 5 A log representation of a difference curve 704 between a first curve such as the first curve 602 and a second curve such as the second curve 604 can also be computed.

[0092] The voltage read threshold generator can generate a root (e.g., a zero intersection) of the target function curve 702 or the difference curve 704. However, it is computationally challenging to perform the computation of the root of the target function curve 702 on the firmware. The voltage read threshold generator can compute the root of the difference curve 704, which represents a log of the difference between the first curve 602 and the second curve 604.

[0093] Figure 8An example depicts a graph showing an approximation of a logarithmic function and an approximation error, according to some embodiments of the disclosure. For example, a first function 802 log(x) can be approximated by using a low order polynomial. In some cases, the coefficients of the low order polynomial used to approximate the first function are different than the coefficients used to approximate the first function 802. In Figure 8 In the example of FIG. 8A, a five order polynomial is used to approximate the first function 802. An approximation curve 804 shows a piecewise approximation of the first function 802. An approximation error curve 806 represents the error as a difference between the approximation curve 804 and the first function 802.

[0094] Figure 9 An example depicts a graph showing an approximation of a logarithmic function and an approximation error, according to some embodiments of the disclosure. For example, a first function 802 log(x) can be approximated by using a low order polynomial. In some cases, the coefficients of the low order polynomial used to approximate the first function are different than the coefficients used to approximate the first function 802. In Figure 9 In the example of FIG. 8A, a five order polynomial is used to approximate the first function 802. An approximation curve 804 shows a piecewise approximation of the first function 802. An approximation error curve 806 represents the error as a difference between the approximation curve 804 and the first function 802.

[0095] Figure 10 An example shows a flow 1000 for reading a storage cell using a threshold read voltage, according to certain embodiments of the disclosure. The flow 1000 can begin at operation 1002, where a computer system selects a first voltage read range and a second voltage read range from a plurality of program verify (PV) levels. For example, the computer system includes a controller and a memory such as a NAND flash memory (or some other type of storage device). The controller can store client data in the client’s memory. In doing so, it includes selecting a voltage range corresponding to storage cells in a multi-layer storage block. When reading from a storage device that has more than one data bit in a storage cell, a first voltage read range and a second voltage read range corresponding to respective levels of the memory cells are selected. The respective widths of the first voltage read range and the second read range are determined based on the number of bits that can be stored within the storage cell.

[0096] In one example, the computer system can select a first voltage read range (e.g., 1.8V-2.5V) and a second voltage read range (e.g., 2.5V-3.2V) that can correspond to adjacent PV levels from the plurality of PV levels. The first voltage read range can correspond to a first PV level representing a first set of bits stored within a storage cell. The second voltage read range can represent a second set of bits stored within the storage cell that are different than the first set of bits.

[0097] At operation 1004, the computer system receives a first set of parameters representing a first probability distribution of a first candidate voltage read threshold within a first range of voltage readings. In an example, the computer system receives a first set of parameters representing a mean, a variance, and a skewness of the first probability distribution. The computer system can receive the first set of parameters from a neural network trained to determine a mean, a variance, and a skewness representing a skew distribution from a CDF of an associated PV level.

[0098] At operation 1006, the computer system receives a second set of parameters representing a second probability distribution of a second candidate voltage read threshold within a second range of voltage readings. In an example, the computer system receives a second set of parameters representing a mean, a variance, and a skewness of the second probability distribution. The computer system can receive the second set of parameters from a neural network trained to determine a representation of a skew distribution from a cumulative distribution function (CDF) of an associated PV level.

[0099] At operation 1008, the computer system generates a voltage read threshold based on inputs to an objective function. In an example, the computer system generates a voltage read threshold by using the first set of parameters Θ L and the second set of parameters Θ R as inputs to the objective function. The computer system can generate an approximation function of the objective function and determine a root of the objective function that occurs at a voltage read threshold (e.g., a crossing point).

[0100] In one example, the computer system can generate a logarithmic representation of the objective function. The computer system can approximate the logarithmic representation by using one or more low-order polynomials. The computer system can determine the logarithmic representation as described with respect to Figures 1 to 5 The computing system can partition a domain (e.g., an interval of values) of the objective function. The computer system can generate a piecewise approximation for each partition of the objective function. The computing system can generate a plurality of low-order polynomials corresponding to individual segments of the partitioned domain. The computing system can aggregate the low-order polynomials of the piecewise approximation into an approximation of the objective function that includes polynomial terms for each partition of the objective function. The computing system can estimate a root of the approximation of the objective function A(x) by evaluating values of A(x) at various candidate voltage read levels. The candidate voltage read level associated with the root of the approximation of the objective function corresponds to a crossing point voltage level between adjacent PV levels of a multilayer memory cell.

[0101] At operation 1010, the computer system reads the data stored in the memory cell using the voltage read threshold. In an example, the client data is stored in the memory as a codeword containing bits based on an ECC encoding process. In this example, reading the client data includes decoding the codeword based on an ECC decoding process that uses the values of the bits based on the voltage read threshold. In particular, the computer system can perform a voltage measurement and compare the voltage measurement value to the voltage read threshold. Based on the comparison, the computer system determines the logical value of the bit. The logical value and applicable soft information are input to the ECC decoding process to decode and output the information bits corresponding to the client data.

[0102] Figure 11 is an example of a graph depicting adjustment of a candidate voltage read threshold according to certain embodiments of the present disclosure. For example, graph 1102 shows adjusting a candidate voltage read threshold using bisection. Bisection is a method of finding a root of a continuous function, such as an objective function or an approximation of an objective function. Bisection iteratively defines an interval between two values and selects a sub-interval within the interval where the function value changes sign. In Figure 11 In another example of a graph depicting, graph 1104 shows adjusting a candidate voltage read threshold using secant method. The secant method is a method of finding a root using a secant line of a function. The secant method will converge to the root value when the initial values are sufficiently close to the root of the function.

[0103] Figure 12 is an example of a computer system 1200 that can implement the present disclosure, such as Figure 1 the error correction system 100 of Figure 2 the host 210 and storage 220 of Figure 4 the neural network 400 of Figure 12 is an example of a computer system 1200 that can implement the present disclosure, such as Figure 1 the error correction system 100 of

[0104] As shown in Figure 12 the computer 1220 can include a processor 1260 in communication with some peripherals via a bus subsystem 1290. These peripherals can include the user output device 1230, the user input device 1240, the communication interface 1250, and a storage subsystem such as a random access memory (RAM) 1270 and a disk drive 1280.

[0105] User input devices 1240 include all possible types of devices and mechanisms used to input information to computer 1220. These can include a keyboard, a keypad, a touch screen incorporated into the display, audio input devices such as voice recognition systems, microphones, and other types of input devices. In various embodiments, user input devices 1240 are typically implemented as a computer mouse, a trackball, a trackpad, a joystick, a wireless remote, a drawing tablet, a voice command system, an eye tracking system, and the like. User input devices 1240 typically allow a user to select objects, icons, text, and the like that appear on the display 1210 through commands such as "clicking" a button or the like.

[0106] User output devices 1230 include all possible types of devices and mechanisms used to output information from computer 1220. These can include a display screen, such as display 1210, non-visual displays such as audio output devices, and the like.

[0107] Communication interface 1250 provides an interface to other communication networks and devices. Communication interface 1250 can serve as an interface for receiving data from and transmitting data to other systems. Embodiments of communication interface 1250 typically include an Ethernet card, a modem (telephone, satellite, cable

[0108] In various embodiments, computer system 1200 also includes software that acts as an intermediary between users and the basic computer resources described in the preceding paragraphs. Such software includes, for example, an operating system 1264. Operating system 1264, which can be stored on disk storage 1280, acts to control other components of the computer system 1200 by executing basic operating system tasks. Examples of operating systems include UNIX, Linux, Microsoft Windows®, Apple macOS®, and the like. In some embodiments, computer 1220 includes one or more Xeon microprocessors from Intel® as processor 1260. Further, in one embodiment, computer 1220 includes a UNIX-based operating system.

[0109] RAM 1270 and disk drive 1280 are examples of tangible media configured to store data such as computer-readable instructions, including human-readable code, that provide the functionality of embodiments of the present disclosure. Other types of tangible media include floppy disks, removable hard disks, optical storage media such as CD-ROMs, DVDs and bar codes, semiconductor memories such as flash memories, non-transitory read-only memories (ROMS), battery-backed volatile memories, networked storage devices, and the like. RAM 1270 and disk drive 1280 can be configured to store basic programming and data structures that provide functionality of the present disclosure.

[0110] Software code modules and instructions that provide the functionality of this disclosure may be stored in RAM 1270 and disk drive 1280. These software modules may be executed by processor 1260. RAM 1270 and disk drive 1280 may also provide a storage library for storing data used according to this disclosure.

[0111] RAM 1270 and disk drive 1280 may include multiple memories, including main random access memory (RAM) for storing instructions and data during program execution and read-only memory (ROM) for storing fixed, non-transitory instructions. RAM 1270 and disk drive 1280 may include a file storage subsystem for providing persistent (non-volatile) storage for program and data files. RAM 1270 and disk drive 1280 may also include removable storage systems, such as removable flash memory.

[0112] Bus subsystem 1290 provides a mechanism for enabling various components and subsystems of computer 1220 to communicate with each other as intended. Although bus subsystem 1290 is schematically shown as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses.

[0113] Figure 12 These are examples of computer systems capable of implementing this disclosure. It will be apparent to those skilled in the art that many other hardware and software configurations are suitable for use with this disclosure. For example, the computer may be a desktop, portable, rack-mount, or tablet configuration. Furthermore, the computer may be a network of networked computers. Further, the use of other microprocessors, such as the Pentium... TM or Itanium TM Microprocessor; Opteron from Advanced Micro Devices, Inc. TM Or Athlon XP TM Microprocessors, etc. Furthermore, consider other types of operating systems, such as those from Microsoft... Examples include Solaris, LINUX, and UNIX from Sun Microsystems, Inc. In another embodiment, the above technology can be implemented on a chip or auxiliary processing board.

[0114] Various embodiments of the present disclosure can be implemented in the form of logic in software or hardware or a combination of both. The logic can be stored in a non-transitory computer-readable or machine-readable storage medium as a set of instructions adapted to direct a processor of a computer system to perform a set of steps disclosed in embodiments of the present disclosure. The logic can form part of a computer program product adapted to direct an information processing apparatus to perform a set of steps disclosed in embodiments of the present disclosure. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will appreciate other ways and / or methods to implement the present disclosure.

[0115] The data structures and code described herein can be stored in part or in whole on a computer-readable storage medium and / or hardware module and / or hardware device. Computer-readable storage media includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media during analog or digital transmission, or the like. Hardware modules or devices described herein include, but are not limited to, special-purpose hardware computer chips that are programmed to perform certain operations, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), dedicated or shared processors and / or the like.

[0116] The methods and processes described herein can be partially or fully embodied as code and / or data stored in a computer-readable storage medium or device, so that when a computer system reads and executes the code and / or data, the computer system performs the associated methods and processes. These methods and processes can also be partially or fully embodied in hardware modules or devices, so that when the hardware modules or devices are activated, they perform the associated methods and processes. Combinations of code, data and hardware modules or devices can be used to implement the methods and processes disclosed herein.

[0117] While the foregoing embodiments have been described in some detail for purposes of clarity and the like, it will be appreciated that certain modifications can be made within the scope of the disclosure. Accordingly, various embodiments have been described as representative of their underlying principles. The disclosed embodiments are illustrative rather than restrictive.

Claims

1. A computer-implemented method for reading client data from a memory, the computer- implemented method comprising: selecting a first voltage read range and a second voltage read range from a plurality of voltage read ranges associated with a number of bits storable in a memory cell, wherein each voltage read range comprises a plurality of candidate voltage read levels; receiving a first set of parameters representing a first probability distribution of first candidate voltage read thresholds within the first voltage read range; receiving a second set of parameters representing a second probability distribution of second candidate voltage read thresholds within the second voltage read range; generating a voltage read threshold based on an input of an objective function, wherein the input comprises the first set of parameters and the second set of parameters, and wherein the voltage read threshold is one of the plurality of candidate voltage read levels; and reading data stored in the memory cell based on the voltage read threshold.

2. The computer-implemented method of claim 1, wherein generating the voltage read threshold comprises: determining the objective function as a representation of a difference between the first probability distribution and the second probability distribution; dividing the objective function into one or more segments; generating at least one approximate objective function corresponding to a segment of the one or more segments of the objective function; and computing an approximation of the voltage read threshold from the at least one approximate objective function.

3. The computer-implemented method of claim 1, wherein the first set of parameters and the second set of parameters are received from a neural network.

4. The computer-implemented method of claim 1, wherein reading data stored in a memory cell comprises: determining a voltage level of the memory cell; comparing the voltage level to the voltage read threshold; and determining one or more bit values of one or more bits stored in the memory cell based on a result of the comparison, the one or more bits representing the data.

5. The computer-implemented method of claim 4, wherein the first voltage read range corresponds to a first set of bit values, the second voltage read range corresponds to a second set of bit values, and wherein the one or more bit values are determined to be the first set of bit values when the voltage level is less than the voltage level threshold.

6. The computer-implemented method of claim 1, wherein the first set of parameters is specific to a first tier of a multi-tier cell of a memory block, and wherein the first set of parameters comprises a mean, a variance, and a skew; and the second set of parameters is specific to a second tier of the multi-tier cell of the memory block, and wherein the second set of parameters comprises a mean, a variance, and a skew.

7. The computer-implemented method of claim 1, further comprising: selecting a third voltage read range from the plurality of voltage read ranges; receiving a third set of parameters representing a third probability distribution of third candidate voltage read thresholds within the third voltage read range; generating a different voltage read threshold based on inputs to the objective function, wherein the inputs include the first set of parameters and the third set of parameters, and wherein the different voltage read threshold is one of the third candidate voltage read levels; and reading additional data stored in a memory cell based on the different voltage read threshold.

8. The computer-implemented method of claim 1, wherein generating the voltage read threshold comprises: determining the voltage read threshold based on using one of a bisection method or a secant method in solving the objective function.

9. A non-transitory computer storage medium storing instructions associated with reading client data from a memory, and when executed by the non-transitory computer storage medium, performing operations associated with reading client data from a memory, the operations comprising: selecting a first voltage read range and a second voltage read range from a plurality of voltage read ranges associated with a number of bits storable in a memory cell, wherein each voltage read range includes a plurality of candidate voltage read levels; receiving a first set of parameters representing a first probability distribution of first candidate voltage read thresholds within the first voltage read range; receiving a second set of parameters representing a second probability distribution of second candidate voltage read thresholds within the second voltage read range; generating a voltage read threshold based on inputs to an objective function, wherein the inputs include the first set of parameters and the second set of parameters, and wherein the voltage read threshold is one of the plurality of candidate voltage read levels; and reading data stored in the memory cell based on the voltage read threshold.

10. The non-transitory computer storage medium of claim 9, wherein generating the voltage read threshold comprises: determining the objective function as a representation of a difference between the first probability distribution and the second probability distribution; dividing the objective function into one or more segments; generating at least one approximate objective function corresponding to a segment of the one or more segments of the objective function; and computing an approximation of the voltage read threshold from the at least one approximate objective function.

11. The non-transitory computer storage medium of claim 9, wherein the first set of parameters and the second set of parameters are received from a neural network.

12. The non-transitory computer storage medium of claim 9, wherein reading data stored in a memory cell comprises: determining a voltage level of the memory cell; comparing the voltage level to the voltage read threshold; and determining one or more bit values of one or more bits stored in the memory cell based on a result of the comparison, the one or more bits representing the data.

13. The non-transitory computer storage medium of claim 12, wherein the first voltage read range corresponds to a first set of bit values, the second voltage read range corresponds to a second set of bit values, and wherein the one or more bit values are determined to be the first set of bit values when the voltage level is less than the voltage level threshold.

14. The non-transitory computer storage medium of claim 9, wherein the first set of parameters is specific to a first tier of a multi-tier cell of a storage block, and wherein the first set of parameters comprises a mean, a variance, and a skew; and the second set of parameters is specific to a second tier of the multi-tier cell of the storage block, and wherein the second set of parameters comprises a mean, a variance, and a skew.

15. The non-transitory computer storage medium of claim 9, wherein the operations further comprise: selecting a third voltage read range from the plurality of voltage read ranges; receiving a third set of parameters representing a third probability distribution of third candidate voltage read threshold values within the third voltage read range; generating a different voltage read threshold based on inputs to the objective function, wherein the inputs comprise the first set of parameters and the third set of parameters, and wherein the different voltage read threshold is one of the third candidate voltage read levels; and reading additional data stored in a memory cell based on the different voltage read threshold.

16. A computer system comprising: a non-transitory computer storage medium storing instructions associated with reading client data from memory, and that when executed by the non-transitory computer storage medium, perform operations associated with reading client data from memory, the operations comprising: selecting a first voltage read range and a second voltage read range from a plurality of voltage read ranges associated with a number of bits storable in a memory cell, wherein each voltage read range comprises a plurality of candidate voltage read levels; receiving a first set of parameters representing a first probability distribution of first candidate voltage read threshold values within the first voltage read range; receiving a second set of parameters representing a second probability distribution of second candidate voltage read threshold values within the second voltage read range; generating a voltage read threshold based on inputs to an objective function, wherein the inputs comprise the first set of parameters and the second set of parameters, and wherein the voltage read threshold is one of the plurality of candidate voltage read levels; and reading data stored in the memory cell based on the voltage read threshold.

17. The computer system of claim 16, wherein the operations of generating a voltage read threshold comprise: determining the objective function as a representation of a difference between the first probability distribution and the second probability distribution; dividing the objective function into one or more segments; generating at least one approximate objective function corresponding to a segment of the one or more segments of the objective function; and computing an approximation of the voltage read threshold from the at least one approximate objective function.

18. The computer system of claim 16, wherein the first set of parameters and the second set of parameters are received from a neural network.

19. The computer system of claim 16, wherein the operations of reading data stored in a memory cell comprise: determining a voltage level of the memory cell; comparing the voltage level to the voltage read threshold; and determining one or more bit values of one or more bits stored in the memory cell based on a result of the comparison, the one or more bits representing the data.

20. The computer system of claim 19, wherein the first voltage read range corresponds to a first set of bit values, the second voltage read range corresponds to a second set of bit values, and wherein when the voltage level is less than the voltage read threshold, the one or more bit values are determined to be the first set of bit values.

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