Metal gate device manufacturing method, equipment, medium, device and photolithography machine

Abstract

The present invention belongs to the field of microelectronics technology, and in particular relates to a method for manufacturing a metal gate device and corresponding equipment, media, devices and photolithography machines. By selectively constructing a photolithography area, the gate oxide of the device is "buried", which, on the one hand, solves the problem of the device being too high; on the other hand, the metal gate area is relatively sunken, avoiding the problem of large pieces of metal gate being excessively removed during grinding.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and in particular relates to a metal gate device manufacturing method, equipment, medium, device and photolithography machine. Background Art

[0002] As the feature sizes of microelectronic devices continue to shrink, high-k metal gate (HKMG) has gradually replaced the silicon dioxide insulation layer-polysilicon gate configuration and become an essential process for manufacturing related devices. Compared with the polysilicon process, HKMG is more conducive to improving device characteristics. However, in some special processes, the following technical problems often exist:

[0003] On the one hand, if Figure 13 As shown, due to the thick gate oxide layer of the high voltage metal oxide semiconductor (HVMOS), the height of this type of device is greater than that of other types of MOS devices, resulting in the problem of being unable to uniformly remove the dummy polysilicon DP (Dummy Poly).

[0004] On the other hand, Figure 14 As shown, the area of ​​the metal gate of the high-voltage device is relatively large. After the metal gate is polished too much, the metal gate often becomes thin. Summary of the Invention

[0005] The present invention discloses a method for manufacturing a metal gate device and corresponding equipment, medium, device and photolithography machine, which overcome or improve the above two problems while ensuring the electrical characteristics of the device.

[0006] In the manufacture of metal gate devices, a mask positioning window opening step is introduced to open the hard mask of the first device area of ​​the relevant device to form a first operating area; the first operating area includes a portion of the first isolation area and a portion of the first active area AA (Active Area).

[0007] The opened portion of the first isolation area and the opened portion of the first active area AA are used as the target locations for subsequent process steps, and subsequent processes are carried out; wherein, the outer surfaces of the first isolation area and the AA area are flush or the step height thereof is required to be less than the first preset step height.

[0008] In the active area immersion step, the first material of the surface layer of the first active area AA in the first operating area is removed by a first etching process to a preset depth, so that the first isolation area and the first active area AA form a first recessed area of ​​a preset depth; due to the introduction of the recessed area, the height of the subsequent process structure is reduced and more functional units can be implanted.

[0009] By introducing an adjustment repair step, the sidewalls and bottom surface of the first recessed area are further repaired; a first repair film is generated on the sidewalls and bottom surface; wherein the surface layer of the active area AA in the first operating area damaged by the first etching process is partially covered or filled.

[0010] A re-diving step is further introduced to remove the first repair film through a second etching process; at the same time or further, the surface dielectric of the first isolation area in the first operating area is removed; wherein, the first isolation area is used to isolate the functional area of ​​the device or divide the functional area, and a second recessed area of ​​a preset depth is formed through the first isolation area and the first active area; the recessed area is formed by partitioning the AA area and the first isolation area on the basis of the first recessed area, preparing for the construction of the gate oxide.

[0011] Furthermore, in the gate oxide construction step, a first gate oxide layer is grown to the second recessed area, so that the first gate oxide layer reaches a preset first thickness; at this time, the surface of the first gate oxide layer and the surface of the first isolation area located in the first working area form a third recessed area; the step height of the third recessed area is less than the third preset step height; at this point, the preparation of the in-situ metal gate is ready for isolation and space preparation.

[0012] Therefore, in the metal gate preparation step, the structure of the metal gate in the first device region is completed by forming the first metal gate to the third recessed area and making the first metal gate surrounded by the interlayer dielectric layer and reach the fourth preset step height.

[0013] Furthermore, the first etching process may adopt a dry etching process; and adopt a process with a selectivity greater than a first etching preset value; the first etching preset value may be obtained from statistics of relevant production lines.

[0014] Furthermore, the first repair film is produced by a thermal oxidation method; wherein the hard mask can be produced by SiN material; the thermal oxidation method is recommended to adopt a linear thermal oxidation process.

[0015] Furthermore, the depth of the first concave area should be less than the first concave preset value; the depth of the second concave area should be less than the second concave preset value; the first concave preset value and the second concave preset value are positively correlated or conform to a preset proportional relationship.

[0016] For application scenarios where the first device area is a high-voltage device area, if the first isolation area adopts an STI (Shallow Trench Isolation) shallow trench isolation structure; the dielectric constant of the interlayer dielectric layer can be greater than or equal to 10, and the dielectric constant of the interlayer dielectric layer is generally selected from a material less than or equal to 50.

[0017] Furthermore, a second device area is also simultaneously prepared on the same substrate where the first device area is located. The rated operating voltage of the second device area is a second withstand voltage value, and the rated operating voltage of the first device area is a first withstand voltage value. For an embodiment of the present invention, the first withstand voltage value may be higher than a preset multiple N of the second withstand voltage value; wherein N is a real number greater than 1.

[0018] Corresponding to the above method, the present invention also discloses a metal gate device production equipment, including a mask positioning unit, an active area immersion unit, an adjustment and repair unit, a re-immersion unit, a gate oxide construction unit and a metal gate preparation unit.

[0019] The mask positioning unit opens the hard mask of the first device area of ​​the device to be processed to form a first operating area; the first operating area includes a partial area of ​​the first isolation area and a partial area of ​​the first active area AA; the surface of the opened part of the first isolation area and the opened part of the first active area AA are flush or the step height is less than the first preset step height.

[0020] The active area submersible unit removes the first material of the surface layer of the first active area AA in the first operating area at a preset depth through a first etching process and forms a first recessed area at a preset depth.

[0021] Adjust the repair unit to repair the sidewalls and bottom surface of the first recessed area; generate a first repair film on the sidewalls and bottom surface; dive into the unit again to remove the first repair film through a second etching process; and simultaneously or further remove the first isolation area in the first operating area and form a second recessed area of ​​a preset depth.

[0022] The gate oxide structure unit grows a first gate oxide layer to the second recessed area so that the first gate oxide layer reaches a preset first thickness; the surface of the first gate oxide layer and the surface of the first isolation area located in the first working area form a third recessed area; and the step height of the third recessed area is made smaller than a third preset step height.

[0023] The metal gate preparation unit manufactures the first metal gate to the third recessed area; wherein the first metal gate is surrounded by the interlayer dielectric layer and reaches a fourth preset step height; thereafter, it can be handed over to other equipment for subsequent processes.

[0024] Furthermore, the first etching process may adopt a dry etching process; and its selectivity is required to be greater than a first etching preset value; the first etching preset value is obtained from statistics of relevant production lines.

[0025] Furthermore, a thermal oxidation method is used to obtain a first repair film, and SiN is used to make a hard mask structure.

[0026] Furthermore, the above-mentioned thermal oxidation method can select a linear thermal oxidation process; and optimize the following parameters; specifically: the depth of the first recessed area is less than the first recessed preset value; the depth of the second recessed area is less than the second recessed preset value; the first recessed preset value is positively correlated with the second recessed preset value or conforms to a preset proportional relationship.

[0027] The embodiment of the present invention is applicable to a metal gate process of a high-voltage device. When the first device region is a high-voltage device region, the first isolation region may adopt an STI shallow trench isolation structure.

[0028] Furthermore, the dielectric constant of the interlayer dielectric layer can be selected to be greater than or equal to 10, and the dielectric constant of the dielectric layer can be selected to be less than or equal to 50.

[0029] Furthermore, a second device region may be simultaneously fabricated on the same substrate as the first device region. If the rated operating voltage of the second device region is the second withstand voltage value, and the rated operating voltage of the first device region is the first withstand voltage value, the first withstand voltage value is required to be higher than the second withstand voltage value by a predetermined multiple N, where N is a real number greater than 1. Typically, N is much greater than 1.

[0030] For computer storage media, the method disclosed in the present invention can be solidified on its internal storage unit and read by related equipment to guide production; in addition, high-voltage power electronic devices and photolithography machines using the above-mentioned process naturally become several implementation directions of the present invention. Their structure and work flow are similar to the above-mentioned methods and equipment, and will not be repeated here.

[0031] It should be noted that the terms "first", "second" and similar terms used in this article are only for describing the various components of the technical solution, and do not constitute a limitation of the technical solution, nor can they be understood as an indication or suggestion of the importance of the corresponding elements; elements with terms such as "first", "second" and similar terms indicate that the corresponding technical solution contains at least one of the element. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solution of the present invention and facilitate a further understanding of the technical effects, technical features and purposes of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings. The accompanying drawings constitute an essential part of the specification and are used together with the embodiments of the present invention to illustrate the technical solution of the present invention, but do not constitute a limitation to the present invention.

[0033] The same reference numerals in the accompanying drawings represent the same components, specifically:

[0034] Figure 1 Schematic diagram of mask positioning and window opening steps according to an embodiment of the present invention;

[0035] Figure 2Schematic diagram of the steps of sneaking into the active area according to an embodiment of the present invention;

[0036] Figure 3 A schematic diagram of the repair steps for adjusting the embodiment of the present invention;

[0037] Figure 4 Schematic diagram of the steps of re-entering the active area according to an embodiment of the present invention;

[0038] Figure 5 Schematic diagram of gate oxide construction steps according to an embodiment of the present invention;

[0039] Figure 6 Schematic diagram of the steps for preparing a metal gate according to an embodiment of the present invention;

[0040] Figure 7 This is an electron microscope image of the active area penetration step of an embodiment of the present invention;

[0041] Figure 8 for Figure 7 A partial enlarged view of

[0042] Figure 9 This is an electron microscope image of the gate oxide structure steps of an embodiment of the present invention;

[0043] Figure 10 for Figure 9 A partial enlarged view of

[0044] Figure 11 A comparison diagram of an embodiment of the present invention and a prior art example;

[0045] Figure 12 for Figure 11 A partial enlarged view of

[0046] Figure 13 A schematic diagram of the CMP non-uniformity state in the prior art;

[0047] Figure 14 Schematic diagram of metal grid over-grinding in the prior art;

[0048] Figure 15 Schematic diagram of the process of the present invention;

[0049] Figure 16 This is a structural diagram of a module embodiment of the present invention;

[0050] in:

[0051] 100—First operating area,

[0052] 101—first device area,

[0053] 102 — second device area,

[0054] 111—first depression area,

[0055] 201a, 201b, 201c—one of the first isolation areas;

[0056] 202—First Quarantine Area 2;

[0057] 222—second depressed area;

[0058] 301 —hard mask region 1;

[0059] 302 —hard mask region 2;

[0060] 333—third depression area;

[0061] 401—first repair film;

[0062] 501--first gate oxide layer;

[0063] 601—first metal grid;

[0064] 602 — second metal grid;

[0065] 701 — first dielectric layer;

[0066] 702 — second dielectric layer;

[0067] 800—comparison observation area;

[0068] 801—First Observation Area;

[0069] 802—Second Observation Area;

[0070] 803—Third Observation Area;

[0071] 804—Fourth Observation Area;

[0072] 901—Schematic diagram of prior art defect 1 (dummy polysilicon not cleared);

[0073] 911—Media grinding device;

[0074] 902—Schematic diagram of prior art defect 2 (over-polished metal grid);

[0075] 922—Metal grid grinding device. DETAILED DESCRIPTION

[0076] The present invention will be further described in detail below with reference to the accompanying drawings and examples. Of course, the specific embodiments described below are only intended to explain the technical solutions of the present invention, rather than to limit the present invention. In addition, the parts described in the embodiments or drawings are merely illustrative of the relevant parts of the present invention, rather than the entire present invention.

[0077] like Figure 15As shown in the flowchart of the embodiment of the method of the present invention, the mask positioning window opening step 20 is opened as follows Figure 1 The hard mask 301 of the first device region is shown, thereby forming the first working region 100 .

[0078] The first operating area 100 includes partial areas of the first isolation areas 201 a , 201 b , and 201 c and partial areas of the first active area AA 101 a and 101 b .

[0079] At this time, the opened portions of the first isolation regions 201a, 201b, and 201c are flush with the outer surface of the opened portions of the first active region AA, ie, 101a and 101b, or the step height thereof is smaller than the first preset step height.

[0080] like Figure 2 As shown, the first active area AA in the first operating area 100 , that is, the first material with a preset first penetration depth on the surface layers 101 a and 101 b is removed through a first etching process.

[0081] The first isolation regions 201 a , 201 b , 201 c and the first active area AA, ie 101 a and 101 b , form a first recessed region 111 of a predetermined depth.

[0082] like Figure 3 , adjust the repair step 40 to repair the sidewalls and bottom surface of the first recessed area 111; generate a first repair film 401 on the sidewalls and bottom surface; wherein, the active area AA damaged by the first etching process in the first operating area 100, that is, the surface portion of 101a and 101b is covered or filled by the first repair film 401.

[0083] like Figure 4 , it again enters step 50 to remove the first repair film 401 through the second etching process; at the same time or further removes the surface dielectric of the first isolation regions 201a, 201b, and 201c in the first operating area 100.

[0084] The first isolation regions 201a, 201b, 201c are used to isolate or divide functional regions of the device. The first isolation regions 201a, 201b, 201c and the first active areas AA (ie, 101a, 101b) form a second recessed region 222 of a predetermined depth.

[0085] like Figure 5 In the gate oxide formation step 60, a first gate oxide layer 501 is grown to the second recessed area 222, so that the first gate oxide layer 501 reaches a preset first thickness; wherein the surface of the first gate oxide layer 501 and the surface of the first isolation regions 201a, 201b, and 201c located in the first operating area 100 form a third recessed area 333; and the step height of the third recessed area 333 should be less than the third preset step height.

[0086] like Figure 6 The metal gate preparation step 70 forms a first metal gate 601 to the third recessed area 333; the first metal gate 601 can usually be surrounded by the interlayer dielectric layer 701 and reach a fourth preset step height.

[0087] Furthermore, the first etching process in the embodiment of the present invention may adopt a dry etching process; and the selectivity of the dry etching process should be greater than a first etching preset value; wherein the first etching preset value is obtained by statistics of relevant production lines.

[0088] Further improvements include using a thermal oxidation method to prepare the first repair film 401 ; and using SiN as the material of the hard mask 301 .

[0089] In addition, the embodiments of the present invention can further improve the technical effect by adopting a linear thermal oxidation process.

[0090] Furthermore, the depth of the first recessed area 111 can be smaller than the first recessed preset value; the depth of the second recessed area 222 can be smaller than the second recessed preset value; wherein the first recessed preset value and the second recessed preset value are positively correlated or conform to a preset proportional relationship.

[0091] More specifically, the first device region in the embodiment of the present invention may be a high-voltage device region, and the first isolation region may adopt an STI shallow trench isolation structure.

[0092] Furthermore, the dielectric layer 701 in the embodiment of the present invention may be made of a material having a dielectric constant greater than or equal to 10 and less than or equal to 50.

[0093] For high-voltage devices, a second device area 102 can also be simultaneously prepared on the same substrate where the first device area 101 is located. The rated operating voltage of the second device area 102 is the second withstand voltage value, and the rated operating voltage of the first device area 101 is the first withstand voltage value; the first withstand voltage value is higher than the second withstand voltage value by a preset multiple N; where N is a real number greater than 1.

[0094] Another implementation of the present invention is as follows Figure 16 As shown, a metal gate device production device includes a mask positioning unit 22, an active area diving unit 33, an adjustment and repair unit 44, a re-diving unit 55, a gate oxide construction unit 66 and a metal gate preparation unit 77.

[0095] Among them, the mask positioning unit 22 opens the hard mask 301 of the first device area of ​​the device to be processed to form a first operating area 100; the first operating area 100 includes partial areas of the first isolation areas 201a, 201b, and 201c and partial areas of the first active area AA; the outer surface layers of the opened parts of the first isolation areas 201a, 201b, and 201c and the opened parts of the first active area AA are flush or the step height is less than the first preset step height.

[0096] On the other hand, the active area diving unit 33 removes the first material of the first active area AA in the first operating area 100 by a first etching process to a preset first diving depth; the first isolation regions 201a, 201b, 201c and the first active area AA form a first recessed area 111 with a preset depth.

[0097] On the other hand, the repair unit 44 is adjusted to repair the side walls and bottom surface of the first recessed area 111; a first repair film 401 is generated on the side walls and bottom surface; wherein the surface portion of the active area AA damaged by the first etching process in the first operating area 100 is covered or filled with the first repair film 401.

[0098] On the other hand, the unit 55 is re-entered to remove the first repair film 401 through a second etching process; at the same time or further, the surface medium of the first isolation areas 201a, 201b, and 201c in the first operating area 100 is removed; wherein, the first isolation areas 201a, 201b, and 201c are used to isolate the functional areas of the device or divide the functional areas, and the first isolation areas 201a, 201b, and 201c and the first active area AA form a second recessed area 222 of a preset depth.

[0099] Furthermore, the gate oxide structure unit 66 grows a first gate oxide layer 501 to the second recessed area 222, so that the first gate oxide layer 501 reaches a preset first thickness; the surface of the first gate oxide layer 501 and the surface of the first isolation region 201a, 201b, 201c located in the first working area 100 form a third recessed area 333; the step height of the third recessed area 333 should be less than the third preset step height.

[0100] Furthermore, the metal gate preparation unit 77 manufactures the first metal gate 601 to the third recessed area 333 , wherein the first metal gate 601 is surrounded by the interlayer dielectric layer 701 and reaches a fourth preset step height; thereafter, other steps are continued to complete the preparation of the workpiece.

[0101] Corresponding improvements include material optimization and photolithography process selection. For example, the first etching process can use a dry etching process; the selectivity of the dry etching process should be greater than the first etching preset value; the first etching preset value can be obtained from statistics of relevant production lines.

[0102] Furthermore, the first repair film 401 can be made by a thermal oxidation method; and the hard mask film 301 can be made by SiN.

[0103] Furthermore, the thermal oxidation method may adopt a linear thermal oxidation process.

[0104] Furthermore, the depth of the first recessed area 111 should be less than the first recessed preset value; the depth of the second recessed area 222 should be less than the second recessed preset value; wherein the first recessed preset value and the second recessed preset value are positively correlated or conform to a preset proportional relationship.

[0105] More specifically, the first device region may be a high voltage device region, and the first isolation region may adopt an STI shallow trench isolation structure; the dielectric constant of the interlayer dielectric layer 701 may be selected from a material greater than or equal to 10 and less than or equal to 50.

[0106] On the other hand, a second device area 102 can be simultaneously prepared on the same substrate as the first device area 101. The rated operating voltage of the second device area 102 is a second withstand voltage value, and the rated operating voltage of the first device area 101 is a first withstand voltage value; the first withstand voltage value is higher than the second withstand voltage value by a preset multiple N; wherein N is a real number greater than 1, and usually N is much greater than 1.

[0107] Based on Figure 4 In the steps shown, the level of the metal gate 601 is lower than that of other MOS devices; therefore, the probability of the metal gate 601 area being ground during the grinding process is reduced, and relatively less is ground away, thereby increasing the height of the metal gate 601 relative to other areas of the component.

[0108] like Figure 6 Through the method disclosed in the embodiment of the present invention, the gate oxide of the device can be "buried", solving the problem of the device being too high; in addition, this method makes the area of ​​the metal gate relatively sink, avoiding the problem of large pieces of metal gate being excessively removed during grinding.

[0109] like Figure 13 Schematic diagram of the CMP non-uniformity state in the prior art, such as Figure 14 Schematic diagram of metal grid over-grinding in the prior art; due to the introduction of the method and product of the present invention, the related technical problems are improved or overcome to varying degrees.

[0110] Specifically, if Figure 7-12 This is an electron microscope image of an embodiment of the present invention. The structure of the embedded region, the layout of the gate oxide structure and the comparison with the prior art further verify the effectiveness of the method of the present invention and related technical effects.

[0111] In addition, it should be noted that the above embodiments are only for the purpose of more clearly illustrating the technical solutions of the present invention. Those skilled in the art will understand that the implementation methods of the present invention are not limited to the above content, and obvious changes, replacements or substitutions based on the above content do not exceed the scope covered by the technical solutions of the present invention; other implementation methods will also fall within the scope of the present invention without departing from the concept of the present invention.

Claims

1. A method for manufacturing a metal gate device, for uniformly removing dummy polysilicon and / or preventing excessive removal of the metal gate. The invention is characterized in that it comprises: a mask positioning window opening step (20): opening a hard mask (301) of a first device region to form a first operating region (100); the first operating region (100) includes a part of a first isolation region and a part of a first active region AA; the opened part of the first isolation region and the first active region AA The opened part has the outer surfaces of the two areas flush or the step height is less than the first preset step height; the active area diving step (30): removing the first material of the surface layer of the first active area AA in the first operating area (100) by a first etching process with a preset first diving depth; the first isolation area and the first active area AA form a first recessed area (111) with a preset depth; the adjustment and repair step (40): repairing the sidewalls and bottom surface of the first recessed area (111); generating a first repair film (401) on the sidewalls and the bottom surface; the surface portion of the first active area AA in the first operating area (100) damaged by the first etching process; being covered or filled with the first repair film (401); the re-diving step (50): removing the first repair film (401) by a second etching process; and simultaneously or further removing the first A surface dielectric of the first isolation region in an operating area (100); the first isolation region is used for isolating a device functional area or dividing a functional area, and the first isolation region and the first active area AA form a second recessed region (222) of a preset depth; a gate oxide construction step (60): growing a first gate oxide layer (501) to the second recessed region (222), so that the first gate oxide layer (501) reaches a preset first thickness; the surface of the first gate oxide layer (501) and the surface of the first isolation region located in the first operating area (100) form a third recessed region (333); the step height of the third recessed region (333) is less than a third preset step height; a metal gate preparation step (70): making a first metal gate (601) to the third recessed region (333); the first metal gate (601) is formed by an interlayer dielectric layer (701) Surrounding and reaching a fourth preset step height; the first device area is a high-voltage device area; a second device area is also synchronously prepared on the same substrate where the first device area is located, the rated operating voltage of the second device area is a second withstand voltage value, and the rated operating voltage of the first device area is a first withstand voltage value; the first withstand voltage value is higher than the second withstand voltage value by a preset multiple N; wherein N is a real number greater than 1.

2. The method for manufacturing a metal gate device according to claim 1, wherein: The first etching process adopts a dry etching process; the selectivity of the dry etching process is greater than a first etching preset value; the first etching preset value is obtained by statistics of relevant production lines.

3. The method for manufacturing a metal gate device according to claim 1, wherein: The first repair film (401) is made by a thermal oxidation method; and the hard mask film (301) is made by SiN.

4. The method for manufacturing a metal gate device according to claim 3, wherein: The thermal oxidation method adopts a linear thermal oxidation process.

5. The method for manufacturing a metal gate device according to claim 1, wherein: The depth of the first concave area (111) is less than a first concave preset value; the depth of the second concave area (222) is less than a second concave preset value; the first concave preset value and the second concave preset value are positively correlated or conform to a preset proportional relationship.

6. The method for manufacturing a metal gate device according to any one of claims 1 to 5, wherein: The first isolation region adopts an STI shallow trench isolation structure; the dielectric constant of the interlayer dielectric layer (701) is greater than or equal to 10, and the dielectric constant of the interlayer dielectric layer (701) is less than or equal to 50.

7. A metal gate device production apparatus comprising: A mask positioning unit (22), an active area diving unit (33), an adjustment and repair unit (44), a re-diving unit (55), a gate oxide construction unit (66), and a metal gate preparation unit (77); wherein: the mask positioning unit (22) opens a hard mask (301) of a first device area of ​​a device to be processed to form a first operating area (100); the first operating area (100) includes a portion of a first isolation area and a portion of a first active area AA; the outer surfaces of the opened portion of the first isolation area and the opened portion of the first active area AA are flush or have a step height less than The first preset step height; the active area diving unit (33) removes the first material of the first active area AA surface layer in the first operating area (100) by a first etching process; the first isolation area and the first active area AA form a first recessed area (111) of a preset depth; the adjustment and repair unit (44) repairs the sidewalls and bottom surface of the first recessed area (111); a first repair film (401) is formed on the sidewalls and the bottom surface; wherein the first active area AA in the first operating area (100) damaged by the first etching process The surface portion of the device is covered or filled with the first repair film (401); the re-entry unit (55) removes the first repair film (401) through a second etching process; and simultaneously or further removes the surface dielectric of the first isolation region in the first operating area (100); wherein the first isolation region is used for isolating the functional region of the device or dividing the functional region, and the first isolation region and the first active area AA form a second recessed region (222) of a preset depth; the gate oxide structure unit (66) grows the first gate oxide layer (501) to the second recessed region region (222), so that the first gate oxide layer (501) reaches a preset first thickness; the surface of the first gate oxide layer (501) and the surface of the first isolation region located in the first operating region (100) form a third recessed region (333); the step height of the third recessed region (333) is less than a third preset step height; the metal gate preparation unit (77) makes a first metal gate (601) to the third recessed region (333); wherein the first metal gate (601) is surrounded by an interlayer dielectric layer (701) and reaches a fourth preset step height.

8. The metal gate device production equipment according to claim 7, wherein: The first etching process adopts a dry etching process; the selectivity of the dry etching process is greater than a first etching preset value; the first etching preset value is obtained by statistics of relevant production lines.

9. The metal gate device production equipment according to claim 8, wherein: The first repair film (401) is made by a thermal oxidation method; and the hard mask film (301) is made by SiN.

10. The metal gate device production equipment according to claim 9, wherein: The thermal oxidation method adopts a linear thermal oxidation process.

11. The metal gate device production equipment according to claim 7, wherein: The depth of the first concave area (111) is less than a first concave preset value; the depth of the second concave area (222) is less than a second concave preset value; the first concave preset value and the second concave preset value are positively correlated or conform to a preset proportional relationship.

12. The metal gate device production equipment according to any one of claims 7 to 11, wherein: The first device region is a high-voltage device region, and the first isolation region adopts an STI shallow trench isolation structure; the dielectric constant of the interlayer dielectric layer (701) is greater than or equal to 10, and the dielectric constant of the interlayer dielectric layer (701) is less than or equal to 50; a second device region (102) is also synchronously prepared on the same substrate as the first device region, the rated operating voltage of the second device region (102) is a second withstand voltage value, and the rated operating voltage of the first device region is a first withstand voltage value; the first withstand voltage value is higher than the second withstand voltage value by a preset multiple N; N is a real number greater than 1.

13. A computer storage medium comprising: A storage medium for storing computer programs; When the computer program is executed by a microprocessor, the method for manufacturing a metal gate device according to any one of claims 1 to 6 is implemented.

14. A high-voltage power electronic device, wherein: The high-voltage circuit of the high-voltage power electronic device is obtained by any method according to claims 1 to 6; the power electronic device is classified by detecting or setting the first recessed area (111), the second recessed area (222), and the third recessed area (333).

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