Semiconductor device, method for manufacturing the same, three-dimensional memory, and storage system

Abstract

Embodiments of the present invention disclose a semiconductor device, a manufacturing method thereof, a three-dimensional memory, and a storage system. The semiconductor device includes: forming a high-voltage well region and a low-voltage well region which are spaced apart in a substrate; forming a first gate oxide layer corresponding to the high-voltage well region and a second gate oxide layer corresponding to the low-voltage well region on the substrate; respectively forming a first gate and a second gate on the first gate oxide layer and the second gate oxide layer; respectively forming a first dielectric portion and a second dielectric portion on the upper surfaces of the first gate and the second gate; forming a first opening and a second opening located on both sides of the first gate in the first gate oxide layer, or forming a first opening and a second opening in the first gate oxide layer, forming a third opening in the first dielectric portion, and forming a fourth opening in the second dielectric portion; and forming a first metal contact structure corresponding to the first opening and the second opening in the substrate. Embodiments of the present invention do not require an additional SAB process, can simplify the process steps, and reduce the process cost.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to electronic devices, and more specifically, to a semiconductor device and a method for manufacturing the same, a three-dimensional memory, and a storage system. Background Art

[0002] In complementary metal oxide semiconductors (COMS), there are both low voltage metal oxide semiconductor transistors (LVMOS) and high voltage metal oxide semiconductor transistors (HVMOS).

[0003] At present, in the manufacturing process, the COMS device includes a substrate, a gate oxide layer formed on the substrate, and a high-voltage gate and a low-voltage gate formed on the gate oxide layer. Since the energy of the ion implantation of the doping structure forming the high-voltage gate is relatively large, and the thickness of the gate oxide layer corresponding to the high-voltage gate is greater than the thickness of the gate oxide layer corresponding to the low-voltage gate, when forming the doping structure corresponding to the high-voltage gate, it is necessary to pattern the portion of the gate oxide layer corresponding to the high-voltage gate, and in the subsequent process of forming metal silicide, in order to selectively protect the area where metal silicide does not need to be formed, it is also necessary to form a self-aligned barrier layer (SalicideBlock, SAB) on the substrate, and a corresponding mask is required to form an opening structure, and then a metal silicide is formed corresponding to the opening structure to reduce the contact resistance.

[0004] As mentioned above, for the memory, due to the different voltage requirements of HVMOS and LVMOS, multiple process flows are required to form metal silicide in the substrate corresponding to the high-voltage gate and the low-voltage gate, which makes the process more complicated, increases the process time, and increases the process cost. Summary of the invention

[0005] The embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, a three-dimensional memory and a storage system, which can integrate the process flow in the semiconductor device manufacturing process, eliminate the SAB process, and further simplify the process steps, shorten the process time and reduce the process cost.

[0006] On the one hand, an embodiment of the present invention further provides a method for preparing a semiconductor device, comprising:

[0007] Providing a substrate, wherein a high-voltage well region and a low-voltage well region are formed in the substrate;

[0008] Form a first gate oxide layer and a second gate oxide layer on the substrate, where the first gate oxide layer corresponds to the high-voltage well region and the second gate oxide layer corresponds to the low-voltage well region;

[0009] Form a first gate and a second gate on the first gate oxide layer and the second gate oxide layer respectively;

[0010] Form a first dielectric portion and a second dielectric portion on the surface of the first gate away from the first gate oxide layer and the surface of the second gate away from the second gate oxide layer respectively;

[0011] Form the first opening and the second opening in the first gate oxide layer, form a third opening in the first dielectric portion, and form a fourth opening in the second dielectric portion, and the first opening and the second opening are located on both sides of the first gate respectively; and

[0012] Form a metal contact layer, where the metal contact layer includes a first metal contact structure formed in the first opening and the second opening, a third metal contact structure formed in the third opening, and a fourth metal contact structure formed in the fourth opening.

[0013] Further, the step of forming the first dielectric portion and the second dielectric portion on the surface of the first gate away from the first gate oxide layer and the surface of the second gate away from the second gate oxide layer respectively includes:

[0014] Form a stacked oxide layer and nitride layer covering the substrate, the first gate, and the second gate;

[0015] Process the oxide layer and the nitride layer to form a first sidewall on the sidewall of the first gate and the first dielectric portion on the surface of the first gate away from the first gate oxide layer, and form a second sidewall on the sidewall of the second gate and the second dielectric portion on the surface of the second gate away from the second gate oxide layer.

[0016] Further, both the first sidewall and the second sidewall include the stacked oxide layer and nitride layer.

[0017] Further, both the first dielectric portion and the second dielectric portion only include the oxide layer.

[0018] Further, the sidewalls of the first opening and the second opening are tapered away from the substrate.

[0019] Further, forming the first opening and the second opening in the first gate oxide layer, forming the third opening in the first dielectric portion, and forming the fourth opening in the second dielectric portion includes:

[0020] Removing part of the first dielectric portion and part of the second dielectric portion to form the third opening and the fourth opening.

[0021] Further, forming the first opening and the second opening in the first gate oxide layer, forming the third opening in the first dielectric portion, and forming the fourth opening in the second dielectric portion includes:

[0022] Removing all of the first dielectric portion and all of the second dielectric portion to form the third opening and the fourth opening.

[0023] Further, after the steps of forming the first opening and the second opening in the first gate oxide layer, forming the third opening in the first dielectric portion, and forming the fourth opening in the second dielectric portion, it further includes:

[0024] Doping the substrate corresponding to the first opening, the second opening, and both sides of the second gate to form a first doped region on both sides of the first gate and a second doped region on both sides of the second gate.

[0025] Further, the step of forming the metal contact layer includes:

[0026] Forming a metal layer covering the substrate, the first gate, and the second gate;

[0027] Removing the metal layer to form the metal contact layer, and the metal contact layer includes a first metal contact structure formed in the substrate corresponding to the first opening and the second opening, a second metal contact structure formed in the substrate corresponding to both sides of the second gate, a third metal contact structure formed in the first gate corresponding to the third opening, and a fourth metal contact structure formed in the second gate corresponding to the fourth opening.

[0028] Further, the orthographic projection of the first metal contact structure on the substrate is within the coverage of the first doped region, and the orthographic projection of the second metal contact structure on the substrate is within the coverage of the second doped region.

[0029] Further, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0030] Further, the thicknesses of the first dielectric portion and the second dielectric portion are both equal to the thickness of the first gate oxide layer.

[0031] On the other hand, an embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes:

[0032] Providing a substrate, in which a high-voltage well region and a low-voltage well region are formed at intervals;

[0033] Forming a first gate oxide layer and a second gate oxide layer on the substrate, and the first gate oxide layer corresponds to the high-voltage well region, and the second gate oxide layer corresponds to the low-voltage well region;

[0034] Forming a first gate and a second gate on the first gate oxide layer and the second gate oxide layer respectively;

[0035] Forming a first dielectric portion and a second dielectric portion on the surface of the first gate away from the first gate oxide layer and the surface of the second gate away from the second gate oxide layer respectively;

[0036] Forming a first opening and a second opening in the first gate oxide layer, and the first opening and the second opening are respectively located on both sides of the first gate; and

[0037] Forming a metal contact layer, and the metal contact layer includes a first metal contact structure, and the first metal contact structure is formed in the substrate and corresponds to the first opening and the second opening. Wherein, during the process of forming the metal contact layer, the first dielectric portion and the second dielectric portion respectively serve as barrier layers for the first gate and the second gate.

[0038] Further, the step of forming the first dielectric portion and the second dielectric portion on the surface of the first gate away from the first gate oxide layer and the surface of the second gate away from the second gate oxide layer respectively includes:

[0039] Forming a stacked oxide layer and nitride layer covering the substrate, the first gate, and the second gate;

[0040] Processing the oxide layer and the nitride layer to form a first sidewall on the sidewall of the first gate and the first dielectric portion on the surface of the first gate away from the first gate oxide layer, and forming a second sidewall on the sidewall of the second gate and the second dielectric portion on the surface of the second gate away from the second gate oxide layer.

[0041] Further, both the first sidewall and the second sidewall include the stacked oxide layer and nitride layer.

[0042] Furthermore, both the first dielectric portion and the second dielectric portion only include the oxide layer.

[0043] Furthermore, the side walls of the first opening and the second opening are both tapered away from the substrate.

[0044] Furthermore, after the step of forming the first opening and the second opening in the first gate oxide layer, the following steps are further included:

[0045] The substrate is doped corresponding to the first opening, the second opening, and both sides of the second gate to form a first doped region on both sides of the first gate and a second doped region on both sides of the second gate.

[0046] Furthermore, the step of forming the metal contact layer further includes:

[0047] Form a metal layer covering the substrate, the first dielectric portion, and the second dielectric portion;

[0048] Remove the metal layer to form the metal contact layer, and the metal contact layer includes the first metal contact structure formed in the substrate corresponding to the first opening and the second opening, and the second metal contact structure formed in the substrate corresponding to both sides of the second gate.

[0049] Furthermore, the orthographic projection of the first metal contact structure on the substrate is within the coverage of the first doped region, and the orthographic projection of the second metal contact structure on the substrate is within the coverage of the second doped region.

[0050] Furthermore, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0051] Furthermore, the thicknesses of both the first dielectric portion and the second dielectric portion are equal to the thickness of the first gate oxide layer.

[0052] On the other hand, an embodiment of the present invention further provides a semiconductor device, which includes:

[0053] A substrate, including a high-voltage well region and a low-voltage well region;

[0054] A first gate oxide layer and a second gate oxide layer are disposed on the substrate. The first gate oxide layer corresponds to the high-voltage well region, the second gate oxide layer corresponds to the low-voltage well region, and the first gate oxide layer includes a first opening and a second opening;

[0055] A first gate and a second gate, where the first gate is disposed on the first gate oxide layer, the second gate is disposed on the second gate oxide layer, and the first opening and the second opening are respectively located on both sides of the first gate;

[0056] A first dielectric portion and a second dielectric portion, where the first dielectric portion covers at least a part of the upper surface of the first gate, and the second dielectric portion covers at least a part of the upper surface of the second gate; and

[0057] A metal contact layer, including a first metal contact structure disposed in the substrate corresponding to the first opening and the second opening.

[0058] Further, the semiconductor device further includes a first sidewall located on the sidewall of the first gate and a second sidewall located on the sidewall of the second gate, and both the first sidewall and the second sidewall include a stacked oxide layer and nitride layer, and both the first dielectric portion and the second dielectric portion only include the oxide layer.

[0059] Further, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0060] Further, the thickness of the first dielectric portion and the thickness of the second dielectric portion are both equal to the thickness of the first gate oxide layer.

[0061] Further, the sidewalls of the first opening and the second opening are both tapered away from the substrate.

[0062] Further, a third opening is provided in the first dielectric portion, a fourth opening is provided in the second dielectric portion, and the metal contact layer further includes a second metal contact structure disposed in the substrate corresponding to both sides of the second gate, a third metal contact structure disposed in the first gate corresponding to the third opening, and a fourth metal contact structure disposed in the second gate corresponding to the fourth opening.

[0063] Further, the substrate further includes a first doped region disposed on both sides of the first gate corresponding to the first opening and the second opening, and a second doped region disposed on both sides of the second gate, where the orthographic projection of the first metal contact structure on the substrate is within the coverage of the first doped region, and the orthographic projection of the second metal contact structure on the substrate is within the coverage of the second doped region.

[0064] On the other hand, an embodiment of the present invention further provides a three-dimensional memory, which includes a memory cell array and a peripheral circuit electrically connected to the memory cell array, and the peripheral circuit includes the semiconductor device.

[0065] On the other hand, an embodiment of the present invention further provides a storage system, which includes the three-dimensional memory and a controller. The controller is coupled to the three-dimensional memory and is configured to control the three-dimensional memory to store data.

[0066] The beneficial effects of the embodiments of the present invention are as follows: After forming the first gate and the second gate, a first dielectric portion is formed on the upper surface of the first gate, and a second dielectric portion is formed on the upper surface of the second gate. Then, when forming a metal contact layer in the semiconductor device, the first dielectric portion and the second dielectric portion can be respectively used as the barrier layers of the first gate and the second gate, and there is no need to additionally add an SAB process. Therefore, the process steps can be simplified, the process time can be reduced, and the process cost can be lowered. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The technical solutions and other beneficial effects of the present invention will be made obvious by the following detailed description of the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0068] Figures 1a to 1f is a schematic structural diagram of a semiconductor device during preparation in some embodiments;

[0069] Figure 2 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0070] Figures 3a to 3e is a schematic structural diagram of a semiconductor device during preparation provided by an embodiment of the present invention;

[0071] Figure 4 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0072] Figures 5a to 5e is a schematic structural diagram of another semiconductor device during preparation provided by an embodiment of the present invention;

[0073] Figure 6 is a block diagram of a structure of a three-dimensional memory provided by an embodiment of the present invention;

[0074] Figure 7 is a block diagram of a structure of a storage system provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0075] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the embodiments of the present invention.

[0076] It should be understood that although terms such as first and second may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the embodiments of the present invention.

[0077] It should be understood that when a component is said to be "on" another component or "connected" to another component, it may be directly on the other component or connected to the other component, or there may also be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0078] As used herein, the term "layer" refers to a portion of a material that includes a region having a height. A layer has a top side and a bottom side, where the bottom side of the layer is relatively closer to the substrate, and the top side is relatively farther from the substrate. The layer may extend over the entire underlying or overlying structure, or may have a scope smaller than the scope of the underlying or overlying structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure having a height less than the height of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (wherein contacts, interconnect lines, and one or more dielectric layers are formed).

[0079] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.

[0080] It should be noted that the diagrams provided in the embodiments of the present invention only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the diagrams and are not drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and proportions of the components in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.

[0081] In some embodiments, during the preparation process of the semiconductor device, the process flow is relatively complex. For example, please refer to Figures 1a to 1f , wherein the preparation process of the semiconductor device includes:

[0082] Form a high-voltage region H and a low-voltage region L in the semiconductor substrate 1, and form a gate dielectric layer 4 on the semiconductor substrate 1.

[0083] Then, a high-voltage gate 2 is formed on the gate dielectric layer 4 corresponding to the high-voltage region H, and a low-voltage gate 3 is formed on the gate dielectric layer 4 corresponding to the low-voltage region L; as Figure 1a shown.

[0084] Next, a photoresist is coated on the gate dielectric layer 4, and the regions on both sides of the high-voltage gate 2 are exposed by the photoresist; as Figure 1b shown.

[0085] Further, the gate dielectric layer 4 is etched to form openings on both sides of the high-voltage gate 2; as Figure 1c shown.

[0086] Then, the semiconductor substrate 1 is doped. Among them, high-voltage doped regions 5 are formed at the openings corresponding to both sides of the high-voltage gate 2, and low-voltage doped regions 6 are formed on both sides of the low-voltage gate 3; as Figure 1d shown.

[0087] Next, an SAB self-aligned layer 7 is formed on the gate dielectric layer 4, the high-voltage gate 2, and the low-voltage gate 3, and part of the SAB self-aligned layer is removed to expose the regions where metal contact structures need to be formed, which may include both sides of the high-voltage gate 2, both sides of the low-voltage gate 3, the upper surface of the high-voltage gate 2, and the upper surface of the low-voltage gate 3, and the specific positions can be selected according to requirements; as Figure 1f shown.

[0088] Finally, a metal layer, such as nickel, is prepared. Then, the metal layer forms nickel silicide with silicon in the semiconductor substrate 1, that is, a metal-silicon structure 9, to improve the electrical connection impedance of the high-voltage doped regions 5 and the low-voltage doped regions 6.

[0089] In the above process, after doping the semiconductor substrate 1, an SAB process is also required to perform the patterning process of the SAB self-aligned barrier layer 7, so as to form the metal-silicon structure 9 in the semiconductor substrate 1, which makes the manufacturing process of the semiconductor device complex and is not conducive to cost reduction.

[0090] An embodiment of the present invention provides a method for manufacturing a semiconductor device. By retaining (which can be thickened) the oxide layer on the upper surface of the gate (i.e., the surface of the gate far from the gate oxide layer) during the process of preparing the gate sidewall, a dielectric part is formed. Subsequently, when preparing the metal contact layer, it can be used as a barrier layer for selective etching without the need to additionally prepare an SAB self-aligned barrier layer, which can save process steps.

[0091] Specifically, please refer to Figure 2 and Figures 3a to 3e , a method for manufacturing a semiconductor device provided by an embodiment of the present invention includes:

[0092] Step S10: Provide a substrate 10, in which a high-voltage well region 101 and a low-voltage well region 102 are formed at intervals.

[0093] Step S20: Form a first gate oxide layer 21 and a second gate oxide layer 22 on the substrate 10, where the first gate oxide layer 21 corresponds to the high-voltage well region 101 and the second gate oxide layer 22 corresponds to the low-voltage well region 102.

[0094] Step S30: Form a first gate 31 and a second gate 32 on the first gate oxide layer 21 and the second gate oxide layer 22 respectively.

[0095] Step S40: Form a first dielectric portion 41 and a second dielectric portion 42 on the surfaces of the first gate 31 away from the first gate oxide layer 21 and the second gate 32 away from the second gate oxide layer 22 respectively.

[0096] Step S50: Form a first opening 211 and a second opening 212 in the first gate oxide layer 21, form a third opening 411 in the first dielectric portion 41, and form a fourth opening 421 in the second dielectric portion 42, and the first opening 211 and the second opening 212 are located on both sides of the first gate 31 respectively.

[0097] Step S60: Form a metal contact layer, which includes a first metal contact structure 51 formed in the first opening 211 and the second opening 212, a third metal contact structure 53 formed in the third opening 411, and a fourth metal contact structure 54 formed in the fourth opening 421.

[0098] Furthermore, please refer to Figure 4 and Figures 5a to 5e , another method for manufacturing a semiconductor device provided by an embodiment of the present invention includes:

[0099] Step S10: Provide a substrate 10, in which a high-voltage well region 101 and a low-voltage well region 102 are formed at intervals.

[0100] Step S20: Form a first gate oxide layer 21 and a second gate oxide layer 22 on the substrate 10, where the first gate oxide layer 21 corresponds to the high-voltage well region 101 and the second gate oxide layer 22 corresponds to the low-voltage well region 102.

[0101] Step S30: Form a first gate 31 and a second gate 32 on the first gate oxide layer 21 and the second gate oxide layer 22 respectively.

[0102] Step S40: Form a first dielectric portion 41 and a second dielectric portion 42 on the surfaces of the first gate 31 away from the first gate oxide layer 21 and the second gate 32 away from the second gate oxide layer 22 respectively.

[0103] Step S50: Form a first opening 211 and a second opening 212 in the first gate oxide layer 21, and the first opening 211 and the second opening 212 are respectively located on both sides of the first gate 31.

[0104] Step S60: Form a metal contact layer, and the metal contact layer includes a first metal contact structure 51. The first metal contact structure 51 is formed in the substrate 10 and corresponds to the first opening 211 and the second opening 212. Wherein, during the process of forming the metal contact layer, the first dielectric portion 41 and the second dielectric portion 42 respectively serve as barrier layers for the first gate 31 and the second gate 32.

[0105] During the implementation and application process, in the embodiment of the present invention, after preparing the first gate 31 and the second gate 32, a first dielectric portion 41 is formed on the upper surface of the first gate 31, and a second dielectric portion 42 is formed on the upper surface of the second gate 32. Then, when forming the metal contact layer in the semiconductor device, openings can be made in the first dielectric portion 41 and the second dielectric portion 42, or the first dielectric portion 41 and the second dielectric portion 42 are respectively used as barrier layers for the first gate 31 and the second gate 32, and there is no need to additionally add an SAB process, thereby simplifying the process steps, reducing the process time, and lowering the process cost.

[0106] Specifically, the following will detail the method for manufacturing a semiconductor device provided by the present invention in combination with specific embodiments. In the specific embodiment of the present invention, the method for manufacturing the semiconductor device includes the following steps:

[0107] Step S10: Provide a substrate 10, in which a high-voltage well region 101 and a low-voltage well region 102 are formed at intervals.

[0108] Please refer to Figure 3a , in the specific embodiment, provide a substrate 10, and the substrate 10 can be a semiconductor substrate. Among them, the semiconductor substrate can be a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon-germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0109] Furthermore, the substrate 10 can be etched to form isolation trenches first, and then ion implantation is performed on the substrate 10 using a suitable mask to form a high-voltage well region 101 and a low-voltage well region 102 at intervals. The isolation trenches can be used to separate the high-voltage well region 101 and the low-voltage well region 102. The device operating voltage corresponding to the high-voltage well region 101 is higher, and the device operating voltage corresponding to the low-voltage well region 102 is lower.

[0110] Step S20: Form a first gate oxide layer 21 and a second gate oxide layer 22 on the substrate 10, where the first gate oxide layer 21 corresponds to the high-voltage well region 101 and the second gate oxide layer 22 corresponds to the low-voltage well region 102.

[0111] A gate oxide layer is formed on the substrate 10. Specifically, the material of the gate oxide layer includes silicon oxide, silicon oxynitride, and high-k materials. Among them, the high-k material can be hafnium dioxide.

[0112] The gate oxide layer includes a first gate oxide layer 21 corresponding to the high-voltage well region 101 and a second gate oxide layer corresponding to the low-voltage well region. Among them, since the voltage applied to the high-voltage well region 101 is greater than the voltage applied to the low-voltage well region 102, to prevent breakdown, in this embodiment, the thickness of the first gate oxide layer 21 is greater than the thickness of the second gate oxide layer 22.

[0113] Furthermore, the gate oxide layer further includes an isolation structure 23 filled in the isolation trench and protruding above the upper surfaces of the first gate oxide layer 21 and the second gate oxide layer 22 to further separate the high-voltage well region 101 and the low-voltage well region 102.

[0114] Step S30: Form a first gate 31 and a second gate 32 on the first gate oxide layer 21 and the second gate oxide layer 22 respectively.

[0115] Please continue to refer to Figure 3a , and a gate layer is formed on the gate oxide layer using a polysilicon material, and part of the gate layer is removed through a photomask process to form a first gate 31 on the first gate oxide layer 21 and a second gate 32 on the second gate oxide layer 22.

[0116] Step S40: Form a first dielectric portion 41 and a second dielectric portion 42 on the surface of the first gate 31 away from the first gate oxide layer 21 and the surface of the second gate 32 away from the second gate oxide layer 22 respectively.

[0117] Please continue to refer to Figure 3a , where step S40 includes: forming a stacked oxide layer and nitride layer covering the substrate 10, the first gate 31, and the second gate 32; and processing the oxide layer and nitride layer to form a first sidewall 61 on the sidewall of the first gate 31 and a first dielectric portion 41 on the upper surface of the first gate 31, and forming a second sidewall 62 on the sidewall of the second gate 32 and a second dielectric portion 42 on the upper surface of the second gate 32.

[0118] In a specific embodiment, a chemical vapor deposition process may be used to form a first silicon oxide layer covering the substrate 10, the first gate oxide layer 21, the second gate oxide layer 22, the upper surface and the sidewalls of the first gate 31, and the upper surface and the sidewalls of the second gate 32. Then, a part of the first silicon oxide layer is etched away, and the first silicon oxide layer covering the upper surface and the sidewalls of the first gate 31 is retained as the first dielectric sub - part and the first sub - sidewall 611, and the first silicon oxide layer covering the upper surface and the sidewalls of the second gate 32 is retained as the second dielectric sub - part and the second sub - sidewall 621.

[0119] Continuing with the chemical vapor deposition process, a first silicon nitride layer covering the substrate 10, the first gate oxide layer 21, the second gate oxide layer 22, the first sub - sidewall 611 and the first dielectric sub - part, the second sub - sidewall 621 and the second dielectric sub - part is formed. Then, a part of the first silicon nitride layer is etched away, and the first silicon nitride layer covering the first sub - sidewall 611 is retained as the third sub - sidewall 612, and the first silicon nitride layer covering the second self - sidewall 621 is retained as the fourth sub - sidewall 622.

[0120] Next, a second silicon oxide layer covering the substrate 10, the first gate oxide layer 21, the second gate oxide layer 22, the third sub - sidewall 612 and the first dielectric sub - part, the fourth sub - sidewall 622 and the second dielectric sub - part is formed. Then, a part of the second silicon oxide layer is etched away, and the second silicon oxide layer covering the third sub - sidewall 612 is retained as the fifth sub - sidewall 613, the second silicon oxide layer covering the first dielectric sub - part is retained as the third dielectric sub - part, the second silicon oxide layer covering the fourth sub - sidewall 622 is retained as the sixth sub - sidewall 623, and the second silicon oxide layer covering the second dielectric sub - part is retained as the fourth dielectric sub - part.

[0121] Then, a second silicon nitride layer covering the substrate 10, the first gate oxide layer 21, the second gate oxide layer 22, the fifth sub - sidewall 613 and the third dielectric sub - part, the sixth sub - sidewall 623 and the fourth dielectric sub - part is formed. Then, a part of the second silicon nitride layer is etched away, and the second silicon nitride layer covering the fifth sub - sidewall 613 is retained as the seventh sub - sidewall 614, and the second silicon oxide layer covering the sixth sub - sidewall 623 is retained as the eighth sub - sidewall 624.

[0122] It should be noted that the stacked first sub - sidewall 611, third sub - sidewall 612, fifth sub - sidewall 613, and seventh sub - sidewall 614 form the first sidewall 61 covering the sidewalls of the first gate 31, and the stacked second sub - sidewall 621, fourth sub - sidewall 622, sixth sub - sidewall 623, and eighth sub - sidewall 624 form the second sidewall 62 covering the sidewalls of the second gate 32.

[0123] In one embodiment, the first dielectric sub - part and the third dielectric sub - part are stacked to form a first dielectric part 41 covering the upper surface of the first gate 31, and the second dielectric sub - part and the fourth dielectric sub - part are stacked to form a second dielectric part 42 covering the upper surface of the second gate 32.

[0124] Wherein, the thickness of the first dielectric part 41 and the thickness of the second dielectric part 42 can both be equal to the thickness of the first gate oxide layer 21. Specifically, in the manufacturing process, the part of the first silicon oxide layer corresponding to the upper surface of the first gate 31 (i.e., the first dielectric sub - part), the part corresponding to the upper surface of the second gate 32 (i.e., the second dielectric sub - part) and / or the part of the second silicon oxide layer corresponding to the upper surface of the first gate 31 (i.e., the third dielectric sub - part), the part corresponding to the upper surface of the second gate 32 (i.e., the fourth dielectric sub - part) can be thickened so that the thicknesses of the first dielectric part 41 and the second dielectric part 42 are thicker than those in the related art and can be equal to the thickness of the first gate oxide layer 21. Further, when selectively etching the first dielectric part 41 and the second dielectric part 42 subsequently, since the first dielectric part 41, the second dielectric part 42 and the first gate oxide layer 21 will be etched in the same process, therefore, in this embodiment, setting the thicknesses of the first dielectric part 41 and the second dielectric part 42 to be the same as the thickness of the first gate oxide layer 21 will be more conducive to the synchronous etching of the first dielectric part 41, the second dielectric part 42 and the first gate oxide layer 21. For details, please refer to the subsequent embodiments.

[0125] Step S50: Form a first opening 211 and a second opening 212 in the first gate oxide layer 21, form a third opening 411 in the first dielectric part 41, and form a fourth opening 421 in the second dielectric part 42, and the first opening 211 and the second opening 212 are respectively located on both sides of the first gate 31.

[0126] Or, form a first opening 211 and a second opening 212 in the first gate oxide layer 21, and the first opening 211 and the second opening 212 are respectively located on both sides of the first gate 31.

[0127] Please combine Figure 3b 、 Figure 3c and Figure 3d , or please combine Figure 5a 、 Figure 5b and Figure 5c , wherein, step S50 further includes: doping the substrate 10 corresponding to the first opening 211, the second opening 212 and both sides of the second gate 32 to form a first doping region 11 located on both sides of the first gate 31 and a second doping region 12 located on both sides of the second gate 32.

[0128] Step S60: Form a metal contact layer. The metal contact layer includes a first metal contact structure 51 formed in the first opening 211 and the second opening 212, a third metal contact structure 53 formed in the third opening 411, and a fourth metal contact structure 54 formed in the fourth opening 421.

[0129] Alternatively, form a metal contact layer, and the metal contact layer includes a first metal contact structure 51. The first metal contact structure 51 is formed in the substrate 10 and corresponds to the first opening 211 and the second opening 212. Wherein, during the process of forming the metal contact layer, the first dielectric portion 41 and the second dielectric portion 42 serve as the barrier layers of the first gate 31 and the second gate 32 respectively.

[0130] Please refer to Figure 3e Or Figure 5d , wherein step S60 further includes: forming a second metal contact structure 52 in the substrate 10 corresponding to both sides of the second gate 32.

[0131] Specifically, in an embodiment of the present invention, please continue to combine Figures 3a to 3e , coat a first photoresist layer 71 on the first gate oxide layer 21, the second gate oxide layer 22, the first sidewall 61, the second sidewall 62, the first dielectric portion 41, and the second dielectric portion 42, and pattern the first photoresist layer 71 through exposure and development to form openings located on both sides of the first gate 31, an opening located on the first dielectric portion 41, and an opening located on the second dielectric portion 42, as Figure 3b shown.

[0132] Wherein, when the first photoresist layer 71 is a positive photoresist, the mask template has openings above both sides of the first gate 31, above the first dielectric portion 41, and above the second dielectric portion 42. After exposure and development, the portions of the photoresist corresponding to above both sides of the first gate 31, above the first dielectric portion 41, and above the second dielectric portion 42 are removed, that is, openings located on both sides of the first gate 31, an opening located on the first dielectric portion 41, and an opening located on the second dielectric portion 42 are formed.

[0133] The etching process is used to remove part of the first gate oxide layer 21 on both sides of the first gate 31 to form a first opening 211 and a second opening 212, remove part of the first dielectric portion 41 to form a third opening 411, and remove part of the second dielectric portion 42 to form a fourth opening 421. It should be noted that part of the first gate oxide layer 21 remains at the bottoms of the first opening 211 and the second opening 212, part of the first dielectric portion 41 remains at the bottom of the third opening 411, and part of the second dielectric portion 42 remains at the bottom of the fourth opening, so as to prevent the substrate 10, the first gate 31, and the second gate 32 from being exposed to the air during the manufacturing process, and to avoid damage to the surfaces of the substrate 10, the first gate 31, and the second gate 32, such as Figure 3c as shown

[0134] In other embodiments of the present invention, all of the first dielectric portion 41 can also be removed to form the third opening 411, and all of the second dielectric portion 42 can be removed to form the fourth opening 421, which can be selected according to actual needs and is not limited herein

[0135] It should be noted that in this embodiment, the thicknesses of the first dielectric portion 41 and the second dielectric portion 42 are both equal to the thickness of the first gate oxide layer 21, so that they can be etched synchronously during the etching process

[0136] In this embodiment, the side walls of the first opening 211, the second opening 212, the third opening 411, and the fourth opening 421 are all tapered away from the substrate 10, that is, the cross-sectional shapes of the first opening 211, the second opening 212, the third opening 411, and the fourth opening 421 are all trapezoidal in an inverted shape

[0137] A second photoresist layer 72 is coated on the first gate oxide layer 21, the second gate oxide layer 22, the first sidewall 61, the second sidewall 62, the first dielectric portion 41, and the second dielectric portion 42, and the second photoresist layer 72 is patterned by exposure and development, so that the second photoresist layer 72 covers the first gate oxide layer 21, the first sidewall 61, and the first dielectric portion 41, and exposes the upper parts of the first opening 211, the second opening 212, and the low-voltage well region 102

[0138] Ion implantation is performed corresponding to the first opening 211 and the second opening 212, and both sides of the second gate 32 to form a first doping region 11 on both sides of the first gate 31 and a second doping region 12 on both sides of the second gate 32, as Figure 3d shown

[0139] Next, the substrate 10 is cleaned with hydrofluoric acid to remove a portion of the first gate oxide layer 21 at the bottoms of the first opening 211 and the second opening 212, a portion of the first dielectric portion 41 at the bottom of the third opening 411, a portion of the second dielectric portion 42 at the bottom of the fourth opening 421, and a portion of the second gate oxide layer 22 on both sides of the second gate 32, so as to expose a portion of the upper surfaces of the substrate 10, the first gate 31, and the second gate 32.

[0140] A metal layer is formed on the substrate 10, the first gate 31, and the second gate 32, and the metal layer can entirely cover the upper part of the substrate 10. Among them, the metal layer passes through the first opening 211 and the second opening 212 to contact the substrate 10 on both sides of the first gate 31 to form a first metal contact structure 51, contacts the substrate 10 on both sides of the second gate 32 to form a second metal contact structure 52, passes through the third opening 411 to contact the first gate 31 to form a third metal contact structure 53, and passes through the fourth opening 421 to contact the second gate 32 to form a fourth metal contact structure 54, as Figure 3e shown.

[0141] It should be noted that the material of the metal layer includes nickel metal, and the metal layer reacts with silicon in the substrate 10, the first gate 31, and the second gate 32 to generate metal silicide. That is, the above reaction process is: forming silicon regions on both sides of the first gate 31 and the second gate 32 on the substrate 10, and forming silicon regions on the upper surface of the first gate 31 and the upper surface of the second gate 32 to expose the upper surfaces of the substrate 10, the first gate 31, and the second gate 32, and depositing or evaporating a layer of nickel metal on the silicon region, and then performing a rapid thermal process (RTP), such as a rapid thermal annealing process, so that the nickel metal reacts with the silicon in the silicon region to generate nickel silicide. During the reaction process, the nickel metal reacts with the silicon in the substrate 10, the first gate 31 and the second gate 32, so that the silicon in the substrate 10, the first gate 31 and the second gate 32 that contacts the nickel metal and the silicon near the upper surface of the substrate 10, the upper surface of the first gate 31 and the upper surface of the second gate 32 are all reacted to form metal silicides, and the first metal contact structure 51 and the second metal contact structure 52 are finally obtained. They are embedded in the substrate 10, and the third metal contact structure 53 and the fourth metal contact structure 54 are embedded in the first gate 31 and the second gate 32, respectively, thereby increasing the contact area between the first metal contact structure 51 and the first doping region 11, and increasing the contact area between the second metal contact structure 52 and the second doping region 12, so as to further improve the electrical connection effect of the semiconductor device. Furthermore, the bonding strength between the first metal contact structure 51, the second metal contact structure 52 and the substrate 10, the bonding strength between the third metal contact structure 53 and the first gate 31, and the bonding strength between the fourth metal contact structure 54 and the second gate 32 can also be improved.

[0142] In this embodiment, the first metal contact structure 51, the second metal contact structure 52, the third metal contact structure 53 and the fourth metal contact structure 54 can all reduce the electrical connection impedance and improve the electrical connection performance. The orthographic projection of the first metal contact structure 51 on the substrate 10 is located within the coverage range of the first doping region 11, and the orthographic projection of the second metal contact structure 52 on the substrate 10 is located within the coverage range of the second doping region 12. In this embodiment, the cross-sectional shape of the first opening 211 is an inverted trapezoid, and the first metal contact structure 51 is formed at the bottom of the first opening 211. The coverage area of ​​the first doping region 11 is generally greater than or equal to the orthographic projection area of ​​the first opening 211 on the substrate 10, and the first opening 211 is arranged in an inverted trapezoid, and its bottom area is smaller than the top area, thereby further ensuring that the orthographic projection of the first metal contact structure 51 on the substrate 10 is located within the coverage range of the first doping region 11, so as to prevent the first metal contact structure 51 from extending to the area outside the first doping region 11, thereby avoiding the occurrence of leakage or breakdown of the semiconductor device.

[0143] Continuing from the above, in this embodiment, the first dielectric portion 41 and the second dielectric portion 42 are respectively used as the barrier layers of the first gate 31 and the second gate 32. Thus, there is no need to additionally add the SAB process. It is only necessary to form openings in the first gate oxide layer 21, the first dielectric portion 41, and the second dielectric portion 42 in the same photomask. Then, a first metal contact structure 51 can be formed on both sides of the first gate 31, a third metal contact structure 53 can be formed on the upper surface of the first gate 31, and a fourth metal contact structure 54 can be formed on the upper surface of the second gate 32. In this embodiment, there is no need to newly add the SAB process, which can simplify the process steps, reduce the process time, and lower the process cost.

[0144] In another embodiment of the present invention, please refer to Figures 5a to 5e , coat a third photoresist layer 73 on the first gate oxide layer 21, the second gate oxide layer 22, the first sidewall 61, the second sidewall 62, the first dielectric portion 41, and the second dielectric portion 42, and pattern the third photoresist layer 73 through exposure and development to form openings on both sides of the first gate 31, as shown in Figure 5a .

[0145] Use an etching process to remove part of the first gate oxide layer 21 on both sides of the first gate 31 to form a first opening 211 and a second opening 212. It should be noted that a part of the first gate oxide layer 21 is still retained at the bottom of the first opening 211 and the second opening 212 to prevent the substrate 10 from being exposed to air during the process and avoid damage to the surface of the substrate 10, as shown in Figure 5b .

[0146] In this embodiment, the sidewalls of the first opening 211 and the second opening 212 are tapered away from the substrate 10, that is, the cross-sectional shapes of the first opening 211 and the second opening 212 are both trapezoidal in an inverted shape.

[0147] Coat a fourth photoresist layer 74 on the first gate oxide layer 21, the second gate oxide layer 22, the first sidewall 61, the second sidewall 62, the first dielectric portion 41, and the second dielectric portion 42, and pattern the fourth photoresist layer 74 through exposure and development so that the fourth photoresist layer 74 covers the first gate oxide layer 21, the first sidewall 61, and the first dielectric portion 41, and exposes the upper parts of the first opening 211, the second opening 212, and the low-pressure well region 102.

[0148] Perform ion implantation treatment corresponding to the first opening 211 and the second opening 212, and both sides of the second gate 32 to form a first doped region 11 on both sides of the first gate 31 and a second doped region 12 on both sides of the second gate 32, as shown in Figure 5c .

[0149] Next, hydrofluoric acid is used to clean the substrate 10 to remove a part of the first gate oxide layer 21 at the bottoms of the first opening 211 and the second opening 212, and a part of the second gate oxide layer 22 on both sides of the second gate 32, so as to expose a part of the upper surface of the substrate 10.

[0150] A metal layer is formed on the substrate 10, the first dielectric portion 41, and the second dielectric portion 42, and the metal layer can entirely cover the upper part of the substrate 10. Among them, the metal layer passes through the first opening 211 and the second opening 212 to contact the substrate 10 on both sides of the first gate 31 to form a first metal contact structure 51 and contact the substrate 10 on both sides of the second gate 32 to form a second metal contact structure 52, as Figure 5d shown.

[0151] It should be noted that the material of the metal layer includes nickel metal, and the metal layer reacts with silicon in the substrate 10 to generate metal silicide. That is, the above reaction process is as follows: silicon regions are formed on the substrate 10 on both sides of the first gate 31 and both sides of the second gate 32 to expose the upper surface of the substrate 10, and a layer of nickel metal is deposited or evaporated on the silicon regions, and then rapid thermal processing (Rapid Thermal Process, RTP), such as rapid thermal annealing process, is performed to make the nickel metal react with the silicon in the silicon regions to generate nickel silicide.

[0152] It can be understood that, as Figure 5e shown, after the metal contact layer is formed, an etching process can be used to form vias (i.e., the fifth opening 412 and the sixth opening 422) in the first dielectric portion 41 and the second dielectric portion 42, or contact holes (i.e., the fifth opening 412 and the sixth opening 422) can be etched together when the signal connection lines with the first gate 31 and the second gate 32 are prepared subsequently, which is not limited herein.

[0153] In this embodiment, both the first metal contact structure 51 and the second metal contact structure 52 can reduce the electrical connection impedance and improve the electrical connection performance. The orthographic projection of the first metal contact structure 51 on the substrate 10 is within the coverage range of the first doped region 11, and the orthographic projection of the second metal contact structure 52 on the substrate 10 is within the coverage range of the second doped region 12. In this embodiment, the cross-sectional shape of the first opening 211 is trapezoidal in reverse, so that the first metal contact structure 51 is formed at the bottom of the first opening 211, and the bottom area of the first opening 211 is smaller than the top area, thereby further ensuring that the orthographic projection of the first metal contact structure 51 on the substrate 10 is within the coverage range of the first doped region 11.

[0154] Continuing from the above, in this embodiment, the first dielectric portion 41 and the second dielectric portion 42 are respectively used as the barrier layers for the first gate 31 and the second gate 32. Thus, there is no need to additionally add the SAB process. During the formation of the metal contact layer, if no metal contact structure needs to be formed on the first gate 31 and the second gate 32, the first dielectric layer 41 and the second dielectric layer 42 can be used as the barrier layers to prevent the first gate 31 and the second gate 32 from contacting the metal layer. In this embodiment, there is no need to newly add the SAB process, thereby simplifying the process steps, reducing the process time, and lowering the process cost.

[0155] In addition, an embodiment of the present invention further provides a semiconductor device. Please refer to Figure 3e , in an embodiment of the present invention, the semiconductor device includes a substrate 10, a first gate oxide layer 21, a second gate oxide layer 22, a first gate 31, a second gate 32, a first dielectric portion 41, a second dielectric portion 42, and a metal contact layer.

[0156] Among them, the substrate 10 includes a high-voltage well region 101 and a low-voltage well region 102. The first gate oxide layer 21 is disposed on the substrate 10 corresponding to the high-voltage well region 101, and the second gate oxide layer 22 is disposed on the substrate 10 corresponding to the low-voltage well region 102. In addition, the first gate oxide layer 21 includes a first opening 211 and a second opening 212.

[0157] The first gate 31 is disposed on the first gate oxide layer 21, and the second gate 32 is disposed on the second gate oxide layer 22. The first opening 211 and the second opening 212 are respectively located on both sides of the first gate 31. The first dielectric portion 41 covers at least a part of the upper surface of the first gate 31, and the second dielectric portion 42 covers at least a part of the upper surface of the second gate 32. The metal contact layer includes a first metal contact structure 51 disposed in the substrate 10 corresponding to the first opening 211 and the second opening 212.

[0158] Furthermore, the semiconductor device further includes a first spacer 61 disposed on the sidewall of the first gate 31 and a second spacer 62 disposed on the sidewall of the second gate 32. Among them, the first dielectric portion 41 and the first spacer 61 are integrally formed, and the second dielectric portion 42 and the second spacer 62 are integrally formed.

[0159] Specifically, both the first spacer 61 and the second spacer 62 include a stacked oxide layer and a nitride layer, while both the first dielectric portion 41 and the second dielectric portion 42 only include an oxide layer. For example, the first spacer 61 and the second spacer 62 are stacked silicon oxide layers and silicon nitride layers, while the first dielectric portion 41 and the second dielectric portion 42 are silicon oxide layers. In the embodiment of the present invention, the thickness of the silicon oxide layer in the first dielectric portion 41 and the second dielectric portion 42 is thickened and is greater than the thickness of the silicon oxide layer in the first spacer 61 and the second spacer 62.

[0160] The thickness of the first gate oxide layer 21 is greater than that of the second gate oxide layer 22.

[0161] The thicknesses of the first dielectric portion 41 and the second dielectric portion 42 are both equal to the thickness of the first gate oxide layer 21.

[0162] Furthermore, the sidewalls of the first opening 211 and the second opening 212 are both tapered away from the substrate 10.

[0163] In this embodiment, a third opening 411 is provided in the first dielectric portion 41, a fourth opening 421 is provided in the second dielectric portion 42, and the metal contact layer further includes second metal contact structures 52 disposed in the substrate 10 on both sides of the second gate 32, a third metal contact structure 53 disposed in the first gate 31 corresponding to the third opening 411, and a fourth metal contact structure 54 disposed in the second gate 32 corresponding to the fourth opening 421.

[0164] In addition, the substrate 10 further includes a first doped region 11 disposed on both sides of the first gate 31 corresponding to the first opening 211 and the second opening 212, and a second doped region 12 disposed on both sides of the second gate 32. Among them, the orthographic projection of the first metal contact structure 51 on the substrate 10 is within the coverage of the first doped region 11, and the orthographic projection of the second metal contact structure 52 on the substrate 10 is within the coverage of the second doped region 12.

[0165] In another embodiment of the present invention, please refer to Figure 3e , the difference from the previous embodiment is that: a fifth opening 412 is provided in the first dielectric portion 41, a sixth opening 422 is provided in the second dielectric portion 42 to expose partial upper surfaces of the first gate 31 and the second gate 32, and the metal contact layer further includes second metal contact structures 52 disposed in the substrate 10 on both sides of the second gate 32.

[0166] And the above semiconductor devices are all manufactured by the manufacturing method of the semiconductor devices described in the above embodiments, so they have the same beneficial effects as the above embodiments, which will not be elaborated in this embodiment.

[0167] In summary, in the embodiment of the present invention, after the first gate 31 and the second gate 32 are prepared, in the same process of forming the gate sidewall, the first dielectric portion 41 is formed on the upper surface of the first gate 31, and the second dielectric portion 42 is formed on the upper surface of the second gate 32. Then, when forming the metal contact layer in the semiconductor device, openings can be formed in the first dielectric portion 41 and the second dielectric portion 42, or the first dielectric portion 41 and the second dielectric portion 42 can be selectively used as the barrier layers of the first gate 31 and the second gate 32 respectively, and there is no need to additionally add an SAB process. Therefore, the process steps can be simplified, the process time can be reduced, and the process cost can be lowered.

[0168] In addition, please refer to Figure 6 , the embodiment of the present invention further provides a three-dimensional memory 81, which includes a memory cell array 811 and a peripheral circuit 812 electrically connected to the memory cell array 811, and the peripheral circuit 812 includes the semiconductor device described in the above embodiment.

[0169] Furthermore, please refer to Figure 7 , the embodiment of the present invention further provides a storage system 80, which includes the three-dimensional memory 81 and a controller 82 described in the above embodiment, and the controller 82 is coupled to the three-dimensional memory 81 and is used to control the three-dimensional memory 81 to store data.

[0170] Specifically, the storage system 80 includes a controller 82 and one or more three-dimensional memories 81. Among them, the three-dimensional memory 81 includes one or more memory cell arrays 811 and a peripheral circuit 812. The storage system 80 can communicate with the host 90 through the controller 82. Among them, the controller 82 can be connected to one or more three-dimensional memories 81 through channels in one or more three-dimensional memories 81. Each three-dimensional memory 81 can be managed by the controller 82 through the channels in the three-dimensional memory 81.

[0171] The description of the above embodiments is only used to help understand the technical solution and its core idea of the present invention; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a substrate in which a high-voltage well region and a low-voltage well region are formed at intervals; Forming a first gate oxide layer and a second gate oxide layer on the substrate, wherein the first gate oxide layer corresponds to the high-voltage well region and the second gate oxide layer corresponds to the low-voltage well region; Respectively forming a first gate and a second gate on the first gate oxide layer and the second gate oxide layer; Forming a stacked oxide layer and nitride layer covering the substrate, the first gate, and the second gate; Processing the oxide layer and the nitride layer to form a first sidewall on the sidewall of the first gate and a first dielectric portion on the surface of the first gate away from the first gate oxide layer, and forming a second sidewall on the sidewall of the second gate and a second dielectric portion on the surface of the second gate away from the second gate oxide layer; Forming a first opening and a second opening in the first gate oxide layer, forming a third opening in the first dielectric portion, and forming a fourth opening in the second dielectric portion, and the first opening and the second opening are respectively located on both sides of the first gate; And Forming a metal contact layer, the metal contact layer including a first metal contact structure formed in the first opening and the second opening, a third metal contact structure formed in the third opening, and a fourth metal contact structure formed in the fourth opening.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Both the first sidewall and the second sidewall include the stacked oxide layer and nitride layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, Both the first dielectric portion and the second dielectric portion only include the oxide layer.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The sidewalls of the first opening and the second opening are tapered away from the substrate.

5. The method for manufacturing a semiconductor device according to claim 1, wherein, The step of forming the first opening and the second opening in the first gate oxide layer, forming the third opening in the first dielectric portion, and forming the fourth opening in the second dielectric portion includes: Removing a part of the first dielectric portion and a part of the second dielectric portion to form the third opening and the fourth opening.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The step of forming the first opening and the second opening in the first gate oxide layer, forming the third opening in the first dielectric portion, and forming the fourth opening in the second dielectric portion includes: Removing all of the first dielectric portion and all of the second dielectric portion to form the third opening and the fourth opening.

7. The manufacturing method of the semiconductor device according to claim 1, characterized in that, After the step of forming the first opening and the second opening in the first gate oxide layer, forming the third opening in the first dielectric portion, and forming the fourth opening in the second dielectric portion, further including: Performing doping treatment on the substrate corresponding to the first opening, the second opening, and both sides of the second gate to form a first doping region on both sides of the first gate and a second doping region on both sides of the second gate.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The step of forming the metal contact layer includes: Forming a metal layer covering the substrate, the first gate, and the second gate; The metal layer is removed to form the metal contact layer, and the metal contact layer includes the first metal contact structure formed in the substrate corresponding to the first opening and the second opening, the second metal contact structure formed in the substrate on both sides of the second gate, the third metal contact structure formed in the first gate corresponding to the third opening, and the fourth metal contact structure formed in the second gate corresponding to the fourth opening.

9. The method for manufacturing a semiconductor device according to claim 8, wherein, The orthographic projection of the first metal contact structure on the substrate is within the coverage of the first doped region, and the orthographic projection of the second metal contact structure on the substrate is within the coverage of the second doped region.

10. The method for manufacturing a semiconductor device according to claim 1, wherein, The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

11. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The thicknesses of the first dielectric portion and the second dielectric portion are both equal to the thickness of the first gate oxide layer.

12. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a substrate in which a high-voltage well region and a low-voltage well region are formed at intervals; Forming a first gate oxide layer and a second gate oxide layer on the substrate, and the first gate oxide layer corresponds to the high-voltage well region, and the second gate oxide layer corresponds to the low-voltage well region; Respectively forming a first gate and a second gate on the first gate oxide layer and the second gate oxide layer; Forming a stacked oxide layer and nitride layer covering the substrate, the first gate, and the second gate; Processing the oxide layer and the nitride layer to form a first sidewall on the sidewall of the first gate and a first dielectric portion on the surface of the first gate away from the first gate oxide layer, and forming a second sidewall on the sidewall of the second gate and a second dielectric portion on the surface of the second gate away from the second gate oxide layer; Forming a first opening and a second opening in the first gate oxide layer, and the first opening and the second opening are respectively located on both sides of the first gate; And Forming a metal contact layer, and the metal contact layer includes a first metal contact structure formed in the substrate and corresponding to the first opening and the second opening. Wherein, during the formation of the metal contact layer, the first dielectric portion and the second dielectric portion respectively serve as the barrier layers of the first gate and the second gate.

13. The method for manufacturing a semiconductor device according to claim 12, wherein, Both the first sidewall and the second sidewall include the stacked oxide layer and nitride layer.

14. The method for manufacturing a semiconductor device according to claim 12, wherein, Both the first dielectric portion and the second dielectric portion only include the oxide layer.

15. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The sidewalls of the first opening and the second opening are both tapered away from the substrate.

16. The method for manufacturing a semiconductor device according to claim 12, wherein, After the step of forming the first opening and the second opening in the first gate oxide layer, further comprising: Doping the substrate corresponding to the first opening, the second opening, and both sides of the second gate to form a first doped region on both sides of the first gate and a second doped region on both sides of the second gate.

17. The method for manufacturing a semiconductor device according to claim 16, wherein, The step of forming the metal contact layer further includes: Forming a metal layer covering the substrate, the first dielectric portion, and the second dielectric portion; The metal layer is removed to form the metal contact layer, and the metal contact layer includes the first metal contact structure formed in the substrate corresponding to the first opening and the second opening, and the second metal contact structure formed in the substrate corresponding to both sides of the second gate.

18. The manufacturing method of the semiconductor device according to claim 17, characterized in that, The orthographic projection of the first metal contact structure on the substrate is within the coverage of the first doped region, and the orthographic projection of the second metal contact structure on the substrate is within the coverage of the second doped region.

19. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

20. The method for manufacturing a semiconductor device according to claim 12, wherein, The thickness of the first dielectric portion and the thickness of the second dielectric portion are both equal to the thickness of the first gate oxide layer.

21. A semiconductor device, characterized in that, Comprising: A substrate including a high-voltage well region and a low-voltage well region; A first gate oxide layer and a second gate oxide layer are disposed on the substrate. The first gate oxide layer corresponds to the high-voltage well region, and the second gate oxide layer corresponds to the low-voltage well region. The first gate oxide layer includes a first opening and a second opening; A first gate and a second gate. The first gate is disposed on the first gate oxide layer, and the second gate is disposed on the second gate oxide layer. The first opening and the second opening are respectively located on both sides of the first gate; A first dielectric portion and a second dielectric portion. The first dielectric portion covers at least a part of the upper surface of the first gate, and the second dielectric portion covers at least a part of the upper surface of the second gate; A first sidewall and a second sidewall. The first sidewall is located on the sidewall of the first gate, and the second sidewall is located on the sidewall of the second gate. The first dielectric portion and the first sidewall are integrally formed, and the second dielectric portion and the second sidewall are integrally formed; and A metal contact layer including a first metal contact structure disposed in the substrate corresponding to the first opening and the second opening.

22. The semiconductor device according to claim 21, wherein, Both the first sidewall and the second sidewall include a stacked oxide layer and nitride layer, and both the first dielectric portion and the second dielectric portion only include the oxide layer.

23. The semiconductor device according to claim 21, wherein, The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

24. The semiconductor device according to claim 21, wherein, The thickness of the first dielectric portion and the thickness of the second dielectric portion are both equal to the thickness of the first gate oxide layer.

25. The semiconductor device according to claim 21, wherein The sidewalls of the first opening and the second opening are both tapered away from the substrate.

26. The semiconductor device according to claim 21, wherein, A third opening is provided in the first dielectric portion, and a fourth opening is provided in the second dielectric portion. The metal contact layer further includes a second metal contact structure disposed in the substrate corresponding to both sides of the second gate, a third metal contact structure disposed in the first gate corresponding to the third opening, and a fourth metal contact structure disposed in the second gate corresponding to the fourth opening.

27. The semiconductor device according to claim 26, wherein, The substrate further includes a first doped region disposed on both sides of the first gate corresponding to the first opening and the second opening, and a second doped region disposed on both sides of the second gate, wherein a positive projection of the first metal contact structure on the substrate is within the coverage of the first doped region, and a positive projection of the second metal contact structure on the substrate is within the coverage of the second doped region.

28. A three-dimensional memory, characterized in that, The three-dimensional memory includes a memory cell array and a peripheral circuit electrically connected to the memory cell array, and the peripheral circuit includes the semiconductor device according to any one of claims 21 to 27.

29. A storage system, characterized in that, The storage system includes the three-dimensional memory according to claim 28 and a controller, and the controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data.

Images