Surface mount devices bonded to an inner layer of a multilayer substrate

Abstract

This application relates to surface mount devices bonded to an inner layer of a multilayer substrate. An apparatus includes a primary layer of a substrate that includes an open region extending through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate positioned between the primary layer and the secondary layer. The inner layer includes a component bonding pad disposed on the inner layer and exposed via the open region of the primary layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to semiconductor assemblies, and more specifically, to surface mount devices bonded to an inner layer of a multilayer substrate. BACKGROUND

[0002] Integrated circuit (IC) die stacking can include a process of mounting multiple dies on top of each other, where the stacked dies are eventually packaged in a single semiconductor package to form a discrete electrical device. The adoption of stacked IC dies continues to increase in an effort to reduce the overall electrical device footprint and improve the electrical performance of the electrical device. SUMMARY

[0003] According to an aspect of the present application, an apparatus is provided. The apparatus comprises a primary layer of a substrate including an open region extending through the primary layer to an inner layer of the substrate; a secondary layer of the substrate; and the inner layer of the substrate positioned between the primary layer and the secondary layer, wherein the inner layer includes a plurality of component bonding pads disposed on the inner layer and exposed via the open region of the primary layer.

[0004] According to another aspect of the present application, an apparatus is provided. The apparatus comprises a primary layer of a substrate including a first outer surface of the substrate; a secondary layer of the substrate including an open region extending through the secondary layer to an inner layer of the substrate; and the inner layer of the substrate positioned between the primary layer and the secondary layer, wherein the inner layer includes a plurality of component bonding pads disposed on the inner layer and exposed via the open region of the secondary layer.

[0005] According to yet another aspect of the present application, a system is provided. The system comprises a memory device; and a substrate coupled to the memory device comprising: a primary layer including an open region extending through the primary layer to an inner layer of the substrate; a secondary layer; and the inner layer positioned between the primary layer and the secondary layer, wherein the inner layer includes a plurality of component bonding pads disposed on the inner layer and exposed via the open region of the primary layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will become more fully understood from the detailed description given herein below and from the accompanying drawings of various embodiments of the present disclosure. The drawings are, however, for explanation only and are not to be in any way limiting. The present disclosure is not limited to the embodiments depicted in the drawings.

[0007] Figure 1 A profile view of a surface mount device coupled to an inner layer of a multilayer substrate is illustrated in accordance with some embodiments of the present disclosure.

[0008] Figure 2ADetailed profile view of a surface mount device coupled to an inner layer of a multilayer substrate according to some embodiments of the disclosure.

[0009] Figure 2B Detailed profile view of a surface mount device coupled to different inner layers of a multilayer substrate according to some embodiments of the disclosure.

[0010] Figure 2C Top view of a surface mount device coupled to an inner layer of a multilayer substrate according to some embodiments of the disclosure.

[0011] Figure 3 Surface mount device coupled to an inner layer of a multilayer substrate according to some embodiments of the disclosure.

[0012] Figure 4 Detailed profile view of a surface mount device coupled to an inner layer of a multilayer substrate according to some embodiments of the disclosure.

[0013] Figure 5 Detailed profile view of a surface mount device coupled to an inner layer of a multilayer substrate and coupled to a printed circuit board according to some embodiments of the disclosure.

[0014] Figure 6 Flowchart of assembling a surface mount device at an inner layer of a multilayer substrate having an open region exposing the inner layer of the multilayer substrate according to some embodiments of the disclosure.

[0015] Figure 7 Template for a multilayer substrate having a bond pad at an inner layer of the multilayer substrate according to some embodiments of the disclosure.

[0016] Figure 8 Example computing system including a memory subsystem according to some embodiments of the disclosure.

[0017] Figure 9 Computing device assembled according to embodiments of the disclosure. DETAILED DESCRIPTION

[0018] Surface mount technology (SMT) describes a process in which electrical components or circuits are mounted directly onto a surface of a circuit board, such as a substrate or printed circuit board (PCB). Surface mount devices (SMD) refer to electrical components or circuits that are mounted directly onto a surface of a circuit board (e.g., the terminals of a surface mount device are coupled to bond pads at the surface of a substrate or PCB). In contrast, through-hole technology describes a process in which electrical components or circuits are mounted to a circuit board such that each lead of a through-hole device is inserted into a respective conductive hole in the circuit board. Surface mount devices can have one or more terminals, such as short pins or leads of various styles, flat contacts, an array of solder balls (e.g., ball grid array (BGA)), or termination points on the device body. Surface mount devices can be electrical components or electrical devices contained within a package that has terminals exposed outside of the package. The terminals can be electrically coupled to electrical components or circuits disposed within the package.

[0019] A multilayer substrate can have three or more layers, such as a primary layer, one or more inner layers, and a secondary layer. The primary layer can be the highest layer upon which one or more functional IC dies are stacked. The secondary layer can be the bottommost layer of the substrate and include a plurality of electrical contacts coupled to another object, such as a PCB. The electrical contacts of the secondary layer couple the electronics mounted to the substrate to external signals. One or more inner layers can be disposed between the primary layer and the secondary layer of the substrate. The electronics of electrical devices, such as IC dies and surface mount devices, can be enclosed in a package material that helps protect the electronics from the external environment.

[0020] There is an increasing demand for low profile integrated circuit devices that have a height of the integrated circuit device within specified limits. As the profile of an integrated circuit device is reduced, the profile of many of the electronics within the integrated circuit device is also reduced. However, some of the electronics, such as surface mount devices, have a profile that is too high to meet the specified profile limits of a low profile integrated circuit device, which can result in manufacturability issues. For example, some surface mount devices mounted on a multilayer substrate have a mounting height that extends very close to the outside of the package. The mounting height can refer to the distance that a device, such as a surface mount device, extends in a distal direction away from the outer surface of the substrate. Due to manufacturing tolerances, such surface mount devices can be exposed outside of the integrated circuit device, which results in yield loss and device failure.

[0021] Aspects of the disclosure address the above and other shortcomings by providing a multilayer substrate having an open region that exposes a bond pad at an inner layer of the multilayer substrate. The multilayer substrate can have a primary layer, one or more inner layers, and a secondary layer. The primary and secondary layers can comprise outer surfaces of the multilayer substrate. The open region can pass through the primary layer or through the secondary layer and create a cavity within the multilayer substrate. A surface mount device can be mounted to the bond pad at the inner layer such that at least a portion of the surface mount device is positioned within the cavity of the substrate. As such, a mounting height of the surface mount device is reduced.

[0022] Advantages of the disclosure include, but are not limited to, improved manufacturability and device yield. In particular, aspects of the disclosure allow for a reduction in a mounting height of a surface mount device, which allows for a reduction in a profile of a corresponding integrated circuit device. The reduction in mounting height can allow for a greater clearance between the surface mount device and an outer face of the package, which improves manufacturability and device yield.

[0023] It should be noted that surface mount devices are described in embodiments herein for illustrative purposes and not limitation. Aspects of the disclosure can be applied to different electrical devices or different electrical components, such as through-hole electrical devices.

[0024] Figure 1 A profile diagram of a surface mount device coupled to an inner layer of a multilayer substrate is illustrated in accordance with some embodiments of the disclosure.

[0025] The integrated circuit device 100 includes an integrated circuit 132 disposed on a multilayer substrate 102 (also referred to herein as a "substrate"). The integrated circuit 132 (and the surface mount device 120, the open region 116, and the surface 106 of the substrate 102) are enclosed or encapsulated in a package material, such as a ceramic or plastic material (e.g., an epoxy mold compound), as illustrated by the package 130.

[0026] The integrated circuit 132 can include one or more integrated circuit dies. In some embodiments, the integrated circuit 132 is a stacked integrated circuit, as illustrated in Figure 1 The integrated circuit 132 includes integrated circuit dies 104A and 104B (collectively referred to herein as "integrated circuit dies 104"). The integrated circuit dies 104 can include one or more types of integrated circuits. For example, the integrated circuit device 100 can be a memory device that can include a logic die and one or more volatile or non-volatile memory dies. In some embodiments, the integrated circuit die 104A can be a flip-chip that is directly bonded to the primary layer 102A of the substrate 102.

[0027] In some embodiments, one or more of the integrated circuit dies 104 can have one or more die pads. A die pad can be positioned at a surface, e.g., a top surface, of a respective integrated circuit die 104. A die pad (also referred to herein as a “contact pad”) can be a surface region of an integrated circuit die that is designated for external electrical contact, e.g., to electrically couple the integrated circuit die to another component. In some embodiments, a die pad is coated with a conductive material, e.g., gold or a gold alloy. A conductive wire can couple a die pad to a corresponding wire bond pad of the substrate 102.

[0028] In some embodiments, the substrate 102 includes three or more layers. As illustrated, the substrate 102 includes a primary layer 102A, an inner layer 102B, an inner layer 102C, and a secondary layer 102D (collectively referred to herein as “substrate 102”). In some embodiments, one or more of the various layers of the substrate 102 can include a dielectric material (e.g., an epoxy with fiberglass) that electrically insulates a layer from an adjacent layer. In some embodiments, a layer can include conductive leads or traces on a dielectric material and conductive vias within the dielectric material of the layer that electrically couple a conductive lead or trace of one layer to a conductive lead or trace of another layer. In some embodiments, one or more layers (or a surface thereof) can be oriented approximately parallel to each other. Approximately parallel can refer to + / - 10 degrees or more from absolute parallel, taking into account manufacturing tolerances.

[0029] In some embodiments, the primary layer 102A includes a surface 106 of an outer surface or top surface of the substrate 102. The primary layer 102A can include one or more open regions, e.g., open regions 116 that extend through the surface 106 of the primary layer 102A to an inner layer of the substrate 102. An open region 116 can expose a portion of a surface of a respective inner layer. An unexposed surface of a respective inner layer can be bonded to an adjacent layer, e.g., the primary layer 102A. In the illustrated example, the surface 110 of the inner layer 102B (in the absence of the surface mount device 120) is exposed through the open region 116 of the primary layer 102A.

[0030] The secondary layer 102D of the substrate 102 includes a surface 108 that is an outer surface of the substrate 102 (and external to the integrated circuit device 100). In some embodiments, the secondary layer 102D includes one or more electrical contacts, such as electrical contact 112A and electrical contact 112B (collectively referred to herein as "electrical contacts 112"). In some embodiments, electrical contacts of the integrated circuit device 100, such as electrical contacts 112, can be coupled (e.g., one or more of electrically coupled or physically coupled) to, for example, solder balls in a ball grid array, such as solder ball 124, that is illustrated. In some embodiments, electrical contacts can be configured to be electrically coupled to one or more of the adjacent layers using conductive vias, and to couple signals to and from the electrical contacts and the integrated circuit die 104 or the surface mount device 120.

[0031] In some embodiments, the substrate 102 contains one or more inner layers. Although two inner layers, inner layer 102B and inner layer 102C, are illustrated, in some embodiments, any number of inner layers can be implemented in accordance with aspects of the present disclosure. The inner layers 102B and 102C are positioned between the primary layer 102A and the secondary layer 102D. The inner layer 102B includes one or more portions of a surface that are exposed via one or more open regions in the primary layer 102A (further described below).

[0032] In some embodiments, a portion of a surface of an inner layer is exposed through an open region in the primary layer 102A. For example, one or more bond pads, such as bond pad 118A and bond pad 118B (collectively referred to herein as "bond pads 118"), are disposed on the exposed portion of the surface of the inner layer. A bond pad, such as a component bond pad, can be a surface region of a substrate that is designated for external electrical contact, such as to a terminal of a surface mount device 120 (e.g., to electrically couple the substrate to another component, such as a surface mount device), for example. In some embodiments, a plating material, such as a nickel-gold alloy, is disposed over the bond pad to facilitate the formation of a solder joint between the bond pad and a component, such as a surface mount device.

[0033] In some embodiments, one or more surface mount devices, such as surface mount device 120, can be directly coupled to respective bond pads, such as bond pads 118, of an inner layer, such as inner layer 102B. For example, the surface mount device 120 can include one or more terminals, such as terminal 122A and terminal 122B (collectively referred to herein as "terminals 122"), that are respectively coupled to bond pads 118A and 118B.

[0034] In some embodiments, the surface mount device 120 can include any type of electrical component or electrical device. For example, the surface mount device can include, among others, active components, passive components, electromechanical components, quad flat no-lead (QFN) components. In some embodiments, the surface mount device is a passive component, such as, for example, a capacitor or a resistor.

[0035] In some embodiments, a subset of the electrical contacts of the secondary layer 102D are configured to be coupled (e.g., using a via through the substrate 102) to a bond pad disposed on the surface 106 (e.g., an outer surface) of the primary layer 102A. It is noted that an electrical contact on the secondary layer 102D can be coupled to one or more bond pads. In some embodiments, another subset of the electrical contacts of the secondary layer 102D are configured to be coupled to a bond pad disposed on an inner layer exposed by an open region in the primary layer 102A. For example, a bond pad 118 on the surface 110 of the inner layer 102B is coupled (e.g., electrically coupled) to a corresponding electrical contact at the surface 108 of the secondary layer 102D.

[0036] Although illustrated as having a portion of the inner layer 102B exposed via the open region 116, in some embodiments, any inner layer of the substrate 102 can be exposed by an open region. For example, the inner layer 102C can have a portion of its surface exposed by an open region of the primary layer 102A and by another corresponding open region in the inner layer 102B. The corresponding open region of the inner layer 102B can have an open region that overlaps (partially or completely) the open region of the primary layer 102A.

[0037] In some embodiments, a conductive layer (e.g., a copper sheet) is disposed over an inner layer to provide shielding from electromagnetic (EM) interference. For example, a conductive shielding layer can be coupled to a ground potential to shield from EM interference to adjacent layers. Returning to the example where the inner layer 102B has a corresponding open region that exposes a portion of the surface of the inner layer 102C, a conductive shielding layer can be disposed between the inner layer 102C and the inner layer 102B to reduce EM interference between the inner layer 102B and the inner layer 102C. It is noted that the conductive shielding layer can be patterned such that the conductive shielding layer allows vias or open regions to pass through.

[0038] In some embodiments, a substrate, such as the substrate 102, having one or more open regions can be manufactured using one or more substrate manufacturing operations. The manufacturing operations of a 4-layer substrate will be described for purposes of illustration and not limitation. The manufacturing operations can be used to manufacture a substrate having any number of layers.

[0039] In a first substrate fabrication operation, inner layers can be patterned. A laminate (e.g., core) panel can include epoxy with glass fibers sandwiched between two conductive sheets (e.g., copper sheets). The core can be fabricated as two inner layers of a substrate. A photoresist material is applied to both sides of the core (e.g., on the copper sheets), and a mask with an appropriate pattern or layout is applied to each side. In some embodiments, one or more portions of the surface of the inner layers are patterned to have bond pads (e.g., the applied mask layout can have a bond pad pattern thereon). The resist material is photo-treated (e.g., ultraviolet light treated) to solidify (e.g., harden) the resist material in the pattern of the applied mask. The unhardened resist is removed. In some embodiments, the hardened resist remains on the copper that is to be retained. In other embodiments, the unhardened resist can remain on the copper that is to be retained. It should be noted that a positive or negative resist can be used depending on the implementation.

[0040] In a second substrate operation, the inner layers are etched. The core material can cause unwanted copper to be etched away from the core. For example, the core with hardened resist can be placed in a basic solution to etch away the unwanted copper, and leave the copper under the hardened resist. After the unwanted copper is removed, the hardened resist is removed leaving a patterned core (e.g., bond pads on the inner layers).

[0041] In a third substrate operation, a primary layer and a secondary layer are formed above and below the patterned core, respectively. For example, a thin copper foil is laid down and a sheet of pre-preg material (referred to herein as "pre-preg") is positioned above the copper foil. The pre-preg can be a sheet of fibers (e.g., glass cloth) pre-impregnated with uncured epoxy. The bottom copper foil and pre-preg can form the secondary layer (or the primary layer depending on the orientation of the patterned core). The patterned core can be placed on the topmost pre-preg sheet. More pre-preg sheets can be stacked on the patterned core, and another copper foil sheet is placed on the topmost pre-preg sheet. The later positioned pre-preg and copper foil sheets can become the primary layer (or the secondary layer depending on the orientation of the patterned core). The stack of materials can be hot pressed using a heated platen such that the materials are bonded together. The heat can cause the pre-preg to melt, and the applied pressure can help bond the materials together to form a substrate.

[0042] In embodiments where the open areas are created in the primary layer, the uppermost prepreg in the location that will form the open area can be removed. For example, the prepreg can be cut using a laser source (or saw) to remove the prepreg. In some embodiments, the uppermost copper sheet can also be cut to remove the copper in the location that will form the open area. After the prepreg and copper are cut to include the open area, the prepreg and copper sheet are positioned over the core and hot pressed as described above. In embodiments where the open areas are created in the secondary layer, the lowermost prepreg in the location that will form the open area can be removed. The lowermost copper sheet can also be cut to remove the copper in the location that will form the open area. After the prepreg and copper are cut to include the open area, the prepreg and copper sheet are positioned under the core and hot pressed as described above.

[0043] In a fourth substrate operation, vias can be formed in the substrate. In some embodiments, the substrate can be drilled to have holes for any vias to be formed in the substrate. Copper deposition techniques such as electroless copper deposition can be used to chemically deposit copper on the walls of any holes to create plated vias.

[0044] In a fourth substrate operation, outer layers such as the primary layer and the secondary layer can be patterned. In some embodiments, a photoresist material is applied to both outer layers of the substrate and a mask with the appropriate pattern or layout is applied to each side. The resist is photo processed to be cured in the pattern of the applied mask. The uncured resist is removed. In some embodiments, the portions of the outer copper layer that remain are exposed by the removal of the resist and then plated (as described below). In some embodiments, a resist material can also be applied to the portions of the surface of the inner layer that are exposed by the open areas. Even though the bond pads have been patterned, the mask can be patterned such that the bond pads of the inner layer are exposed with the removal of the uncured resist. In some embodiments, the resist in the open areas but not over the bond pads can be cured and remain after the uncured resist is removed.

[0045] In a fifth substrate operation, the outer layers can be plated and etched. In some embodiments, the substrate can be plated with copper using an electroplating operation. In the electroplating operation, copper is deposited on the walls of the holes (e.g., vias) and on the areas where the photoresist has been removed (e.g., traces). After the copper is deposited, a layer of tin can be deposited on the newly deposited copper. The layer of tin can serve as an etch resist. The remaining photoresist is removed to expose the underlying copper. The underlying copper can be removed using a removal such as an alkaline chemical. After the underlying copper is removed, the tin plating layer can be removed to expose the desired copper pattern.

[0046] In a sixth substrate operation, the substrate can be covered with a solder resist layer. The substrate can be cleaned and rinsed and coated with an epoxy solder resist ink, such as a green coat. The substrate can be imaged again using a mask. The epoxy solder resist ink can be used as a resist. The pattern can pattern copper exposed on the outer surface of the substrate, such as bond pads of the inner layer. The uncured resist can be stripped. The remaining epoxy solder resist ink can be cured using a heating process.

[0047] In a seventh substrate operation, the exposed copper on the outer layer (and portions of the substrate of the inner layer) can be plated. A chemical process can be used to plate the exposed copper. For example, an electroless nickel over gold (such as gold over nickel) process can plate the bond pads, such as the bond pads on the inner and primary layers.

[0048] Figure 2A A detailed profile of a surface mount device coupled to an inner layer of a multilayer substrate is illustrated in accordance with some embodiments of the present disclosure. Figure 1 The components of Figure 2A are considered part of the integrated circuit device 200 unless otherwise described. It should be noted that some portions of the substrate 102 are not illustrated for the sake of clarity, and can be considered part of the substrate 102 unless otherwise described. Figure 2A are considered part of the substrate 102 of the integrated circuit device 200 unless otherwise described.

[0049] As illustrated, the open region 116 extends through the primary layer 102A to the inner layer 102B of the substrate 102. The primary layer 102A includes a solder resist sublayer 224, a conductive sublayer 226, and a dielectric sublayer 228 (e.g., a prepreg material). The inner layer 102B is illustrated as having a conductive sublayer 230 and a dielectric sublayer 232. The solder resist layer can be a thin layer of material (e.g., a polymer) applied to conductive traces or a substrate of a printed circuit board (PCB) to prevent oxidation and help prevent solder bridges from forming between closely spaced bond pads. For example, the conductive sublayer can be patterned to form one or more conductive traces or bond pads. The conductive sublayer can include a conductive material such as copper. It should be noted that other inner layers of the substrate 102 can be constructed similarly to the inner layer 102B.

[0050] As illustrated, the open region 116 forms a cavity in the primary layer 102A and exposes bond pads 118 of the inner layer 102B. The bond pads 118 are coated with a plating material illustrated by plating layer 234A and plating layer 234B. Surface mount devices 120 are bonded to the bond pads 118. For example, terminal 122A is bonded to bond pad 118A and terminal 122B is bonded to 118B. Solder joints 236A and 236B are formed between respective ones of the terminals 122 of the surface mount devices 120 and corresponding ones of the bond pads 118 of the inner layer 102B. As illustrated, a portion of the surface mount devices 120 is within the cavity and a portion of the surface mount devices 120 extends above the cavity. In some embodiments, then, the entire surface mount devices 120 can be within the cavity.

[0051] Figure 2B Detailed profile views of surface mount devices coupled to different inner layers of a multilayer substrate are illustrated in accordance with some embodiments of the present disclosure. Figure 1 and Figure 2A are considered part of the integrated circuit device 240 of Figure 2B unless otherwise described. It should be noted that some portions of the substrate 102 are not illustrated for the sake of clarity, not limitation, and can be considered part of the substrate 102 of Figure 2B unless otherwise described.

[0052] As illustrated, the open region 254 in the primary layer 102A and the open region 256 in the inner layer 102B form cavities in the primary layer 102A and the inner layer 102B that expose bond pads 242A and 242B (collectively referred to herein as "bond pads 242") of the inner layer 102C. The open region 254 in the primary layer 102A overlaps the open region 256 in the inner layer 102B. The bond pads 242A and 242B are coated with a plating material illustrated by plating layer 244A and plating layer 244B. Surface mount devices 250 are bonded to the bond pads 242. For example, terminal 252A is bonded to bond pad 242A and terminal 152B is bonded to 242B. Solder joints 246A and 246B are formed between respective ones of the terminals 252A and 252B of the surface mount devices 120 and corresponding ones of the bond pads 242 of the inner layer 102C. As illustrated, a portion of the surface mount devices 250 is within the cavity and a portion of the surface mount devices 250 extends above the cavity.

[0053] It is noted that in some embodiments, the inner layer 102B and the inner layer 102C share a dielectric layer, also referred to as a core 258. In some instances, the core is roughly twice as thick as the corresponding dielectric layer of the primary layer 102A or the secondary layer 102D. For purposes of illustration, approximately half of the core adjacent to the inner layer 102B can be considered part of the inner layer 102B, and the remaining half of the core adjacent to the inner layer 102C can be considered part of the inner layer 102C. It is further noted that the open regions, such as the open regions 254 and 256, expose an inner face of the substrate 102, and in particular, expose bond pads of the inner layer 102C, such as the bond pads 242A and 242B. Since in some embodiments, the configuration of the substrate 102 includes a core shared between the inner layer 102B and the inner layer 102C, such as the core 258, the inner layer of the substrate in such embodiments can be referred to herein as an inner face of the secondary layer 102D or a surface of the inner layer 102C, such that the inner face of the secondary layer 102D or the surface of the inner layer 102C is exposed through the corresponding open region.

[0054] Figure 2C A top view of a surface mount device coupled to an inner layer of a multi-layer substrate is illustrated in accordance with some embodiments of the present disclosure. Figure 1 、 2A The components of Figure 2C are considered part of the view 260, unless otherwise described. The view 260 is a top view of the integrated circuit device 100 of Figure 1 and the integrated circuit device 200 of Figure 2A .

[0055] The view 260 shows a surface mount device 120 mounted to the bond pads 118 of the inner layer 102B. The terminal 122A of the surface mount device 120 is bonded to the bond pad 118A, and the terminal 122B of the surface mount device 120 is bonded to the bond pad 118B. In some embodiments, the cavity formed by the open region 116 in the primary layer 102A can be larger than the surface mount device 120 (e.g., in the X or Y direction, or both). As noted previously, a portion of the surface mount device 120 can extend above the cavity in the Z direction.

[0056] In some embodiments, the open regions, such as the open region 116, are surrounded by the primary layer (e.g., do not extend to the edges of the primary layer 102A). In other embodiments, one or more of the location, size, or shape of the open regions can be different than illustrated. For example, in other embodiments, one or more sides of the open region 116 can extend to the respective side of the primary layer 102A.

[0057] Figure 3 A surface mount device coupled to an inner layer of a multi-layer substrate is illustrated in accordance with some embodiments of the present disclosure. Figure 1 and Figure 2A The components ofFigure 3 portion of the integrated circuit device 300 unless otherwise described.

[0058] Integrated circuit device 300 illustrates a surface mount device 320 mounted to the bottom side of substrate 102. Surface mount device 320 is bonded to bonding pads 318A and 318B (collectively referred to herein as "bonding pads 318") of inner layer 102B via open areas 316A and 316B (collectively referred to herein as "open areas 316") extending through secondary layer 102D and inner layer 102C, respectively, to inner layer 102B of substrate 102. Bonding pads 318 are exposed through open areas 316 in secondary layer 102D and inner layer 102C. In other embodiments, it should be noted that any inner layer, such as inner layer 102C, may have bonding pads exposed through the open areas. Terminals 322A of surface mount device 320 are bonded to bonding pads 318A, and terminals 322B of surface mount device 320 are bonded to bonding pads 318B.

[0059] In some embodiments, the mounting height (IH) corresponding to the surface mount device 320 is less than the solder ball height (SBH) of one or more of the solder balls (e.g., solder ball 324) of the ball grid array. The solder ball height may refer to the distance that the solder ball extends from the outer surface of the secondary layer 102D. If the mounting height is less than the solder ball height, there is sufficient clearance from the top of the surface mount device 320 to mount the integrated circuit device 300 to another object (e.g., a PCB) without causing mounting issues (e.g., tilted components, non-solder joints, etc.).

[0060] In some embodiments, an encapsulation material may be disposed on the surface mount device 320. For example, the encapsulation material may encapsulate the surface mount device 320 to protect it from the external environment (e.g., from water ingress, etc.). In some embodiments, the encapsulation material may be the same as or similar to the packaging material. In some embodiments, the encapsulation material may be different from the packaging material. Some examples of encapsulation materials include, but are not limited to, one or more of epoxy, acrylic, or another material. In some embodiments, the encapsulation may be one or more of heat or light that is cured after being disposed on the surface mount device. In some embodiments, the encapsulation material may be selected to neutralize different coefficients of thermal expansion (CTE). In some embodiments, the encapsulation material may include one or more curing properties, such as high ionic purity, moisture resistance, resistance to degradation due to thermal cycling, low shrinkage, or flexibility resulting from a low modulus value.

[0061] Figure 4 Detailed outline diagram illustrating a surface mount device coupled to an inner layer of a multi-layer substrate according to some embodiments of the present disclosure. Figure 1 and 3 The components are considered Figure 4 portion of the integrated circuit device 400 unless otherwise described.

[0062] As illustrated, open region 316A extends through secondary layer 102D, and open region 316B of inner layer 102C extends through inner layer 102C to inner layer 102B of substrate 102. Open region 316A of secondary layer 102D is aligned with open region 316B of inner layer 102C such that open region 316A overlaps open region 316B. Secondary layer 102D can include one or more of a solder resist sublayer (not shown), a conductive sublayer 442, and a dielectric sublayer 444 (e.g., a pre-preg material). As illustrated, the electrical contacts of the secondary layer region are illustrated with a plating material (e.g., plating layer 440). The electrical contacts are coupled to solder balls (e.g., solder balls 324). Inner layer 102C is illustrated with a conductive sublayer 446 (e.g., approximately half of conductive sublayer 446) and a dielectric sublayer 448. As noted herein, inner layer 102B and inner layer 102C can share a core (e.g., dielectric sublayer 448). Inner layer 102B can include dielectric sublayer 448 (e.g., at least some of dielectric sublayer 448) and a conductive sublayer 450. As illustrated, open region 316 forms a cavity in secondary layer 102D and inner layer 102C that exposes bond pads 318A and 318B of inner layer 102B. Bond pads 318 are coated with a plating material illustrated by plating layer 434A and plating layer 434B. Surface mount devices 320 are bonded to bond pads 318. For example, terminal 322A is bonded to bond pad 318A and terminal 322B is bonded to 318B. Solder joints are formed between respective ones of terminals 322 of surface mount devices 320 and corresponding ones of bond pads 318 of inner layer 102B. As illustrated, a portion of surface mount devices 320 is within the cavity, and a portion of surface mount devices 320 extends outside the cavity.

[0063] Figure 5 A detailed profile view of a surface mount device coupled to an inner layer of a multilayer substrate and to a printed circuit board is illustrated in accordance with some embodiments of the disclosure. Figure 1 、 3 The components of Figures 1-4 are considered part of the system 500 of Figure 5 unless otherwise described.

[0064] System 500 shows a printed circuit board 502 mounted to a surface mount device 504. Figure 4The printed circuit board (PCB) can be similar to the substrate and constructed in a similar manner as the substrate, as described herein. The PCB 502 illustrates a multi-layer PCB. For clarity, the PCB is illustrated with 2 layers, as additional layers such as primary layers or additional inner layers are not illustrated but can be assumed to include additional layers in some embodiments. The multi-layer PCB can have 2 or more layers. As illustrated, the PCB 502 includes an open region 516 that extends through a secondary layer 502A of the PCB 502 to an inner layer 502B of the PCB 502. Bond pads 518A and 518B of the inner layer 502B are exposed through the open region 516. Plating material can be formed on the bond pads 518A and 518B. The PCB 502 and the integrated circuit device 400 are coupled using solder balls. For example, the solder balls 324 couple electrical contacts 542 (and plating 540) of the PCB 502 to corresponding electrical contacts of the integrated circuit device 400.

[0065] As shown, the surface mount device 520 is a two-terminal device having a terminal 522A and a terminal 522B (collectively referred to herein as "terminals 522"). The terminals 522 can extend the width of the surface mount device 520. The terminal 522A is coupled to the bond pad 518B of the PCB 502 and the bond pad 318A of the integrated circuit device 400. The terminal 522B is coupled to the bond pad 518A of the PCB 502 and the bond pad 318B of the integrated circuit device 400. A portion of the surface mount device 520 extends within the open region 516 of the PCB 502. A portion of the surface mount device 520 extends within the open region 316 of the integrated circuit device 400. A portion of the surface mount device 520 extends outside of the PCB 502 and the integrated circuit device 400.

[0066] The following can describe Figures 1 to 5 elements of FIG. 6 to help illustrate the method 600. It should be noted that the method 600 can be performed in any order and can include the same, different, more, or fewer operations. It should be further noted that the method 600 can be performed by one or more semiconductor manufacturing equipment pieces or manufacturing tools or semiconductor packaging tools or semiconductor assembly tools or bonding tools, hereinafter referred to as manufacturing equipment.

[0067] Figure 6 A flow diagram of assembling a surface mount device at an inner layer of a multi-layer substrate having an open region exposing the inner layer of the multi-layer substrate is illustrated in accordance with some embodiments of the present disclosure.

[0068] At operation 605 of the method 600, a manufacturing device provides a substrate. In some embodiments, the manufacturing device provides a substrate that includes a primary layer, a secondary layer, and an inner layer. The inner layer is positioned between the primary layer and the secondary layer. The primary layer includes an open region that exposes a portion of the inner layer that includes a bond pad. In some embodiments, the secondary layer includes an open region that exposes a portion of the inner layer that includes a bond pad. In some embodiments, the substrate can be any of the multilayer substrates described herein.

[0069] At operation 610, the manufacturing device deposits a solder paste at a bond pad positioned at an inner layer of the substrate. Solder paste refers to a material such as a strong metal solder suspended in a thick medium called flux. The flux is added to serve as a temporary adhesive to hold components in place until the soldering process melts the solder to form mechanical and electrical joints. In some embodiments, the solder paste can be deposited on the bond pad and other contacts on the substrate in a single operation or multiple operations (e.g., serial operations).

[0070] In some embodiments, to deposit a solder paste at a bond pad positioned at a portion of the inner layer, the manufacturing device aligns a stencil having stencil features that include patterned cutouts corresponding to the bond pads of the inner layer. The stencil features extend perpendicularly from a substantially planar surface of the stencil and are configured to fit within the open region of the primary layer (or the secondary layer). The manufacturing device uses the stencil features of the stencil to apply the solder paste to the bond pads. An example of a stencil is illustrated at Figure 7

[0071] At operation 615, the manufacturing device couples a surface mount device to the bond pad positioned at the inner layer of the substrate. In some embodiments, to couple a surface mount device to the bond pad positioned at the inner layer of the substrate, the manufacturing device deposits the surface mount device on the substrate at the open region of the substrate and performs a reflow operation that couples the surface mount device to the bond pad positioned at the inner layer of the substrate. The reflow operation can refer to an operation in which solder paste is used to temporarily attach a surface mount device to a bond pad. The assembly (e.g., the substrate with the surface mount device attached) is subjected to controlled heat to cause the solder paste to reflow in a molten state to create a permanent solder joint.

[0072] In some embodiments, where the open region is at the primary layer, a reflow operation can be performed to attach the surface mount device to the inner layer of the substrate. A die attach operation can be performed after the reflow operation to couple one or more dies to the substrate.

[0073] ​In some embodiments where the open region is at the secondary layer, a reflow operation can be performed to attach the surface mount device to the inner layer of the substrate and a different reflow operation can be performed to attach the solder balls to the electrical contacts at the secondary layer. In some embodiments, the two reflow operations can be performed in any order. In some embodiments, the reflow operation to attach the solder balls is performed prior to the reflow operation to attach the surface mount device to the inner layer of the substrate. In some embodiments, a single reflow operation can be performed to attach the surface mount device to the inner layer of the substrate and the solder balls at the electrical contacts at the secondary layer of the substrate.

[0074] Figure 7 A stencil illustrating a multi-layer substrate having bond pads at an inner layer of the multi-layer substrate according to some embodiments of the disclosure is illustrated. Stencil 700 illustrates a stencil that can be used to apply solder paste to bond pads located at an inner layer of a substrate. For purposes of illustration and not limitation, the illustrated substrate has an open region at the primary layer. In some embodiments, stencil 700 can be used with a substrate having an open region at the secondary layer.

[0075] Stencil 700 is illustrated with two views: a top view 701 and a profile view 702. Stencil 700 includes a patterned cutout region 710. Patterned cutout region 710 corresponds to the contact region of the substrate where solder paste will be disposed. For example, solder paste can be disposed at bond pads at the inner layer, bond pads except the primary layer, electrical contacts or bond pads at the secondary layer, etc. As such, patterned cutout region 710 can be aligned with the corresponding contact region of substrate 712. Solder paste can be applied to stencil 700 such that solder paste is disposed at the contact region of substrate 712, but not disposed to other regions of the substrate (regions that are not aligned with the cutout region).

[0076] Stencil 700 can include one or more stencil features, such as stencil feature 715. Stencil features extend perpendicularly from a substantially flat surface (e.g., ±10 degrees from a plane) and can be inserted into the open region at the primary layer (or secondary layer). In some embodiments, the bottom surface of the stencil feature can contact the inner layer exposed via the open region in substrate 712. The patterned cutout region of stencil feature 715 can be aligned with the bond pads at the inner layer exposed via the open region. Stencil feature 715 can allow solder paste to be applied to the bond pads at the inner layer.

[0077] Figure 8 An example computing system 800 including a memory sub-system 810 is illustrated according to some embodiments of the disclosure. Memory sub-system 810 can include media such as one or more volatile memory devices (e.g., memory devices 840), one or more non-volatile memory devices (e.g., memory devices 830), or a combination of such.

[0078] The memory subsystem 810 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include a solid state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a Secure Digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMM).

[0079] The computing system 800 can be, for example, a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial appliance), or a computing device that includes a memory and a processing device.

[0080] The computing system 800 can include a host system 820 coupled to one or more memory subsystems 810. In some embodiments, the host system 820 is coupled to different types of memory subsystems 810. Figure 8 One example of a host system 820 coupled to one memory subsystem 810 is illustrated. As with the example of a memory subsystem 810 coupled to a host system 820, the host system 820 can be coupled to different types of memory subsystems 810. Figure 8 “Coupled to” or “coupled with” is used generically to refer to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, and the like.

[0081] The host system 820 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 820 uses the memory subsystem 810 to, for example, write data to the memory subsystem 810 and read data from the memory subsystem 810.

[0082] The host system 820 can be coupled to the memory sub-system 810 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a small computer system interface (SCSI), a double data rate (DDR) memory bus, a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports double data rate (DDR)), an open NAND flash interface (ONFI), double data rate (DDR), low power double data rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 820 and the memory sub-system 810. When the memory sub-system 810 is coupled with the host system 820 by a PCIe interface, the host system 820 can further access components (e.g., the memory devices 830) using an NVM Express (NVMe) interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 810 and the host system 820. Figure 8 The memory sub-system 810 is illustrated as an example. In general, the host system 820 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0083] The memory devices 830 or 840 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as the memory devices 840) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0084] Some examples of non-volatile memory devices (such as the memory devices 830) include “not-and” (NAND) type flash memory and in-situ write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. Cross-point non-volatile memory arrays can perform bit storage based on bulk resistance changes in conjunction with a stacked cross-grid format data access array. Thus, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where a non-volatile memory cell can be programmed without needing to be previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0085] Each of the memory devices 830 can include one or more arrays of memory cells. One type of memory cell, a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the memory devices 830 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such. In some embodiments, a particular memory device can include SLC portions and MLC portions, TLC portions, or QLC portions of memory cells. The memory cells of the memory devices 830 can be grouped into pages, which can refer to a unit of the memory device for storing data. For some types of memory (such as NAND), pages can be grouped to form blocks.

[0086] Although non-volatile memory components are described, such as NAND-type flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of non-volatile memory cells, the memory devices 830 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), “not- or” (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0087] The memory sub-system controller 818 (or, for simplicity, the controller 818) can communicate with the memory devices 830 to perform operations such as reading data, writing data, or erasing data at the memory devices 830, and other such operations. The memory sub-system controller 818 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with specialized (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 818 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0088] The memory sub-system controller 818 can include a processing device 817 (processor) configured to execute instructions stored in local memory 819. In the illustrated example, the local memory 819 of the memory sub-system controller 818 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 810, including handling communications between the memory sub-system 810 and the host system 820.

[0089] In some embodiments, the local memory 819 can include memory registers that store memory pointers, fetched data, and the like. The local memory 819 can also include read-only memory (ROM) for storing microcode. Although the example memory sub-system 810 has been illustrated as including the memory sub-system controller 818, in another embodiment of the present disclosure, the memory sub-system 810 does not include the memory sub-system controller 818 and can instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system). Figure 8

[0090] In general, the memory sub-system controller 818 can receive commands or operations from the host system 820 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 830 and / or 840. The memory sub-system controller 818 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) associated with the memory devices 830. The memory sub-system controller 818 can further include host interface circuitry that communicates with the host system 820 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 830 and / or 840, and also convert responses associated with the memory devices 830 and / or 840 into information for the host system 820.

[0091] The memory sub-system 810 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 810 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive an address from the memory sub-system controller 818 and decode the address to access the memory devices 830.

[0092] ​In some embodiments, the memory device 830 includes a local media controller 835 that operates in conjunction with the memory sub-system controller 818 to perform operations on one or more memory units of the memory device 830. An external controller, such as the memory sub-system controller 818, can externally manage the memory device 830 (e.g., perform media management operations on the memory device 830). In some embodiments, the memory device 830 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 835) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0093] In some embodiments, the memory device 830 can be a non-volatile memory device. In some embodiments, a non-volatile memory device is a physical package of one or more dies (e.g., a memory device in its own discrete physical package with external pins or electrical contacts). A die can refer to a piece of functional electronic circuitry fabricated on a material substrate, such as a semiconductor material substrate. A memory device, such as the memory device 830, can include one or more dies. Each die can comprise one or more planes. For some types of non-volatile memory devices (e.g., “not-and” (NAND) devices), each plane consists of a group of physical blocks. One or more blocks can be grouped together to form a plane of a memory component in order to allow concurrent operations (e.g., parallelism) to occur on each plane (e.g., multi-plane writes). Each block consists of a group of pages. Each page consists of a group of memory cells that store data bits. In some embodiments, a memory cell can include one or more memory pages (also referred to herein as “logical pages” or “pages,” such as SLC, MLC, TLC, QLC pages) for storing one or more binary data bits corresponding to data received from a host system. For some memory devices, such as NAND devices, a block is the smallest unit that can be erased, and pages within a block cannot be erased individually. For some memory devices, such as NAND devices, a page is the smallest unit that can be written (e.g., programmed).

[0094] In some embodiments, a memory operation can include, but is not limited to, a program operation (e.g., a write operation), a read operation, or an erase operation. In some embodiments, a program operation can include multiple sub-operations, such as a program sub-operation, a read sub-operation, and a verify sub-operation. A program sub-operation programs data to a memory cell. The programmed data can also be stored in one or more registers of the memory device 830. A read operation reads data programmed to a memory cell. A verify operation compares read data from a read operation to match original data stored in a register.

[0095] In some embodiments, any of the components of the computing system 800 can be implemented on a device multilayer substrate having bond pads at an inner layer, such as the integrated circuit devices 100, 200, 240, 300, 400, and the system 500 described herein. For example, the memory device 830 or the memory device 840 (or a combination thereof) can be implemented in accordance with aspects of the present disclosure.

[0096] Figure 9 is a computing device assembled in accordance with embodiments of the present disclosure. The computing device 900 can include several components. In one embodiment, the components can be attached to one or more circuit boards, such as a motherboard. In alternative embodiments, some or all of these components are fabricated onto a single system on a chip (SoC) die, such as a SoC for a mobile device. In embodiments, the components in the computing device 400 include, but are not limited to, the integrated circuit device 100 (or the integrated circuit devices 200, 240, 300, 400, or the system 500) and at least one communication logic unit 908. In some embodiments, the communication logic unit 908 is fabricated in a separate integrated circuit chip that can be bonded to a substrate or motherboard that is shared with or electrically coupled to the integrated circuit device 100. It should be noted that in some embodiments, the integrated circuit device 100 can include any number or any type of integrated circuit dies.

[0097] The computing device 900 can include other components that can or can not be physically and electrically coupled with the motherboard or manufactured within a SoC die. These other components include, but are not limited to, volatile memory 910 (e.g., DRAM), non-volatile memory 912 (e.g., ROM or Flash memory), graphics processing units 914 (GPUs), digital signal processors 916, crypto processors 942 (e.g., specialized processors that execute cryptographic algorithms within hardware), a chipset 920, at least one antenna 922 (in some embodiments, two or more antennas can be used), a display or touchscreen display 924, a touchscreen controller 926, a battery 928 or another power source, power amplifiers (not shown), voltage regulators (not shown), a global positioning system (GPS) device 927, a compass (not shown), a motion co-processor or sensor 932, which can include an accelerometer, a gyroscope, and a compass, a microphone (not shown), a speaker 934, a camera 936, user input devices 938 (e.g., a keyboard, mouse, light pen, and touchpad), and mass storage 940 (e.g., hard disk drive, compact disk (CD), digital versatile disk (DVD), etc.). The computing device 900 can incorporate another transmission, telecommunication, or radio functionality not yet described herein. In some embodiments, the computing device 900 includes a radio for communicating over a distance by modulating and radiating electromagnetic waves in air or space. In further embodiments, the computing device 900 includes a transmitter and receiver (or transceiver) for communicating over a distance by modulating and radiating electromagnetic waves in air or space.

[0098] The communication logic 908 enables wireless communications for the transfer of data to and from the computing device 900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication logic 908 can implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, codesigned protocols, and any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 can include a plurality of communication logic 908. For instance, a first communication logic 908 can be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth, and a second communication logic 908 can be dedicated to longer range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0099] The processor 904 (also referred to herein as "processing device") can refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. The processor 904 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor 904 can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or processors implementing a combination of instruction sets. The processor 904 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like.

[0100] In various embodiments, the computing device 900 can be a laptop computer, netbook, notebook, ultrabook computer, smart phone, non-smart phone, tablet, tablet / laptop hybrid, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, the computing device 900 can be any other electronic device that processes data.

[0101] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0102] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0103] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0104] The algorithms and operations presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as follows from the description of the detailed description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure described herein.

[0105] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0106] The words "example" or "exemplary" are used herein to mean "serving as an example, instance, or illustration." Any aspect or design described herein as an "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the use of the words "example" or "exemplary" is intended to be presented in a specific manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise or from the context clearly indicates otherwise, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the aforementioned examples. In addition, as used in this application and the appended claims, the articles "a" and "an" are generally understood to mean "one or more" will refer to the singular form, unless otherwise or from the context clearly indicates otherwise. In addition, the use of the terms "embodiment" or "one embodiment" or "implementation" or "one implementation" or the like throughout the text may or may not mean the same embodiment or implementation. One or more embodiments or implementations described herein may be combined in a specific embodiment or implementation. As used herein, the terms "first," "second," "third," "fourth," etc. are meant as labels for distinguishing different elements and may not necessarily have sequential meanings according to their numerical designations.

[0107] Spatially relative terms, such as "above," "below," "between," "within," and "on" as used herein refer to an absolute position of one material layer or component relative to another layer or component. For example, a layer disposed "above" or "on" another layer or component can directly contact the other layer or component, or one or more intervening layers can also be present. Moreover, a layer disposed "between" two layers or components can directly contact the two layers or components or one or more intervening layers can also be present. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless otherwise explicitly stated, a feature disposed "between" two features can be directly in contact with the adjacent features or one or more intervening layers can also be present. Unless otherwise specified, spatially relative terms are not intended to be limited to the absolute orientations as depicted in the drawings, and are intended to encompass different orientations of the layer or component (e.g., rotation of 90 degrees, inversion, flipping) unless otherwise specified. For example, if a layer in a figure is flipped so that it is oriented 180 degrees to the orientation shown in the figure, the layer which is described as being "above" or "on" the other layer or component can be interpreted to be "below" or "on" the other layer or component without departing from the aspects of the disclosure.

[0108] In the foregoing specification, embodiments of the application have been described with reference to specific examples. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of the application as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A device comprising: a primary layer of a substrate comprising a first outer surface of the substrate; a secondary layer of the substrate including an open area extending through the secondary layer to an inner layer of the substrate; the inner layer of the substrate positioned between the primary layer and the secondary layer, wherein the inner layer includes a first plurality of component bond pads disposed on the inner layer and exposed through the open area of ​​the secondary layer, and wherein a plating material is disposed over the first plurality of component bond pads, and wherein the first plurality of component bond pads includes sidewalls that are at least partially exposed through the open area of ​​the secondary layer; a surface mount device comprising a first terminal and a second terminal, wherein the first terminal is coupled to a first component bond pad of the first plurality of component bond pads of the inner layer, and wherein the second terminal is coupled to a second component bond pad of the first plurality of component bond pads of the inner layer; and A printed circuit board (PCB) comprising an open area extending through an outer layer of the PCB to an inner layer of the PCB, wherein the inner layer of the PCB comprises a second plurality of component bonding pads disposed on the inner layer of the PCB; and wherein the first terminal of the surface mount device is coupled to a first component bonding pad of the second plurality of component bonding pads, and wherein the second terminal of the surface mount device is coupled to a second component bonding pad of the second plurality of component bonding pads. 2 . The apparatus of claim 1 , wherein the secondary layer comprises an outer surface of the substrate and a plurality of electrical contacts positioned at the outer surface, and wherein the plurality of electrical contacts are coupled to respective ones of a plurality of solder balls.

3. The apparatus of claim 1 , further comprising: An encapsulating material encapsulates the surface mounting device to protect it from the external environment.

4. The apparatus of claim 1, wherein the surface mount device comprises a passive surface mount device.

5. The apparatus of claim 1 , wherein the inner layer of the substrate is a first inner layer, the substrate further comprising: A second inner layer is positioned between the primary layer and the secondary layer. The apparatus of claim 5 , wherein the second inner layer is positioned between the first inner layer and the primary layer.

7. An apparatus according to claim 5, wherein the second inner layer is positioned between the first inner layer and the secondary layer, wherein the second inner layer includes an open area oriented to overlap with the open area of ​​the secondary layer, and wherein the first plurality of component bonding pads of the first inner layer are exposed through the open area of ​​the second inner layer and the open area of ​​the secondary layer.

Images