A semiconductor terminal structure with lateral variable doping and a preparation method thereof

Abstract

The present invention provides a semiconductor terminal structure with lateral variable doping and a preparation method thereof. The terminal structure includes an N-type semiconductor drift region, and the N-type semiconductor drift region includes a P-type semiconductor main junction, a P-type semiconductor field limiting ring, a P-type semiconductor VLD region, and an N+-type semiconductor field limiting ring. One side of the P-type semiconductor field limiting ring is connected to the P-type semiconductor VLD region, and the junction depth of the P-type semiconductor VLD region is greater than that of the P-type semiconductor main junction. Compared with the traditional semiconductor terminal structure, the present invention can achieve a more stable breakdown voltage, a lower leakage level, and a shorter terminal size, and is not easily affected by the surface fixed charges introduced by the manufacturing process line.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and particularly to a semiconductor terminal structure with lateral variable doping and a preparation method thereof. Background Art

[0002] The statements in this part merely provide background art related to the present invention and do not necessarily constitute prior art.

[0003] Power semiconductor devices need to select an appropriate terminal structure according to the target application to reduce the proportion of the terminal size in the chip, thereby increasing the current density of the chip under the same area. The earliest proposed field limiting ring (FLR) structure terminal was by Kao and Wollry. They proposed in 1967 that this structure can expand the space charge region on the semiconductor surface, and various terminal structures based on the superposition of the field limiting ring structure and field plates have emerged, such as Figure 1 shown in (a) of, these structures enable the breakdown voltage to reach about 85% of the parallel plane junction. On the other hand, since the lateral variable doping terminal (VLD) was proposed by R. Stengl and U. Gosele in 1985, it has been gradually applied and popularized in FRD and MOS devices. This type of terminal belongs to one of the junction terminal extension methods, as Figure 1 shown in (b) of, and its advantage compared with the traditional JTE terminal is that it can achieve a higher terminal injection dose and is less affected by external charges.

[0004] Currently, the structure size of the traditional field limiting ring superposed with field plates is still relatively large, occupying a relatively large chip area, while the injection dose of the single VLD terminal structure is still relatively low, basically in the order of 1e 12 ~1e 13 cm -2 order of magnitude. The current improvement methods include reducing the width of the field limiting ring or increasing the spacing of the injection windows to increase the injection dose, etc., but the improvement effects of the above solutions are relatively limited. Summary of the Invention

[0005] In order to solve the deficiencies of the prior art, the present invention provides a semiconductor terminal structure with lateral variable doping and a preparation method thereof, which can achieve a shorter terminal size, a more stable breakdown voltage, and a lower leakage level, and is not easily affected by the surface fixed charges introduced by the manufacturing process line.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] The first aspect of the present invention provides a semiconductor terminal structure with lateral variable doping.

[0008] A semiconductor terminal structure with lateral variable doping includes:

[0009] N+-type semiconductor substrate;

[0010] N-type semiconductor drift region, disposed on the upper surface of the N+-type semiconductor substrate, including a P-type semiconductor main junction, a P-type semiconductor field limiting ring, a P-type semiconductor VLD region, and an N+-type semiconductor field limiting ring. The P-type semiconductor field limiting ring is connected to one side of the P-type semiconductor VLD region. There is a gap between the P-type semiconductor VLD region and the N+-type semiconductor field limiting ring. The concentration of doping ions in the P-type semiconductor VLD region is less than the concentration of doping ions in the P-type semiconductor field limiting ring. The junction depth of the P-type semiconductor VLD region is greater than the junction depth of the P-type semiconductor main junction;

[0011] Insulating dielectric layer, disposed on the upper surface of the N-type semiconductor drift region, in contact with the upper surfaces of the P-type semiconductor main junction, a part of the P-type semiconductor field limiting ring, and a part of the N+-type semiconductor field limiting ring respectively;

[0012] Anode, extending outward from the upper surface of the P-type semiconductor main junction, covering one side surface and a part of the upper surface of the insulating dielectric layer;

[0013] Metal field plate, disposed opposite to the anode, extending outward from the upper surface of the N+-type semiconductor field limiting ring, covering the other side surface and a part of the upper surface of the insulating dielectric layer;

[0014] Cathode, disposed on the bottom surface of the N+-type semiconductor substrate.

[0015] Further, the P-type semiconductor VLD region is composed of a plurality of P-type sub-VLD regions. The depth of each P-type sub-VLD region gradually increases along the first direction, and the first direction is the width direction of the N-type semiconductor drift region.

[0016] Furthermore, the doping concentration of a single P-type sub-VLD region gradually decreases along the first direction.

[0017] Further, the doping concentrations of the plurality of P-type sub-VLD regions gradually decrease along the first direction, and the doping morphology presents a stepped distribution.

[0018] Further, the insulating dielectric layer includes an oxide layer and a passivation layer. The oxide layer is a silicon dioxide layer, and the passivation layer is a silicon nitride layer.

[0019] Further, the concentration of doping ions in the P-type semiconductor VLD region is less than the concentration of doping ions in the P-type semiconductor field limiting ring.

[0020] Further, the concentration of doping ions in the P-type semiconductor VLD region is less than the concentration of doping ions in the P-type semiconductor doping region.

[0021] In the second aspect of the present invention, a method for manufacturing a semiconductor terminal structure with lateral variable doping is provided.

[0022] A method for preparing a semiconductor terminal structure with lateral variable doping includes the following processes:

[0023] Provide an N+-type semiconductor substrate, and form an N-type semiconductor drift region on the upper surface of the N+-type semiconductor substrate through epitaxial growth;

[0024] Form an insulating dielectric layer on the upper surface of the N-type semiconductor drift region;

[0025] Through photolithography and first ion implantation in sequence, form a P-type semiconductor main junction and a P-type semiconductor field limiting ring in the N-type semiconductor drift region; through photolithography and multiple second ion implantations in sequence, form a P-type semiconductor VLD region in the N-type semiconductor drift region, and the junction depth of the P-type semiconductor VLD region is greater than the junction depth of the P-type semiconductor main junction;

[0026] Through photolithography and third ion implantation in sequence, form an N+-type semiconductor field limiting ring in the N-type semiconductor drift region;

[0027] Through ion sputtering, cover part of the upper surface of the N-type semiconductor drift region and part of the upper surface of the insulating dielectric layer to form an anode and a metal field plate respectively;

[0028] Through ion sputtering, deposit cathode material on the bottom surface of the N+-type semiconductor substrate to form a cathode.

[0029] Compared with the prior art, the beneficial effects of the present invention are:

[0030] 1. The semiconductor terminal structure with lateral variable doping and the preparation method thereof according to the present invention combine FLR and VLD terminal technologies, and adopt stepped VLD doping, which can achieve shorter terminal dimensions, more stable breakdown voltage and lower leakage level, and is not easily affected by surface fixed charges introduced by the manufacturing process line.

[0031] 2. The semiconductor terminal structure with lateral variable doping and the preparation method thereof according to the present invention, the P-type semiconductor VLD region is composed of multiple P-type sub-VLD regions, the depth of each P-type sub-VLD region 51 gradually deepens along the first direction, and the junction depth of the P-type semiconductor VLD region is greater than the junction depth of the P-type semiconductor main junction, so that the curvature of the outer corner of the main junction is negative, which can reduce the electric field at the edge corner of the main junction, make the breakdown of the device more stable, not easily burned out, and can improve the avalanche tolerance of the device. Brief Description of the Drawings

[0032] The specification drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention.

[0033] Figure 1 Schematic diagrams of two traditional terminal structures for the background art.

[0034] Figure 2 Schematic diagram of a semiconductor terminal structure with lateral variable doping provided in Embodiment 1 of the present invention.

[0035] Wherein, 1, anode metal field plate; 2, metal field plate; 3, P-type semiconductor main junction; 4, P-type semiconductor field limiting ring; 5, P-type semiconductor VLD region; 51, P-type sub-VLD region; 6, N+-type semiconductor field limiting ring; 7, insulating dielectric layer; 8, N-type semiconductor drift region; 9, N+-type semiconductor substrate; 10, cathode metal; X, first direction. Detailed implementation manners

[0036] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0037] It should be noted that the following detailed descriptions are all illustrative and are intended to provide further descriptions of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0038] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0039] Without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0040] Embodiment 1:

[0041] As Figure 2 shown, Embodiment 1 of the present invention provides a semiconductor terminal structure with lateral variable doping, and the terminal structure includes:

[0042] N+-type semiconductor substrate 9;

[0043] The N-type semiconductor drift region 8 is disposed on the upper surface of the N+-type semiconductor substrate 9 and includes a P-type semiconductor main junction 3, a P-type semiconductor field limiting ring 4, a P-type semiconductor VLD region 5, and an N+-type semiconductor field limiting ring 6. The P-type semiconductor field limiting ring 4 is connected to one side of the P-type semiconductor VLD region 5. There is a gap between the P-type semiconductor VLD region 5 and the N+-type semiconductor field limiting ring 6. The concentration of doping ions in the P-type semiconductor VLD region 5 is less than the concentration of doping ions in the P-type semiconductor field limiting ring 4. The junction depth of the P-type semiconductor VLD region is greater than the junction depth of the P-type semiconductor main junction;

[0044] The insulating dielectric layer 7 is disposed on the upper surface of the N-type semiconductor drift region 8 and is in contact with partial upper surfaces of the P-type semiconductor main junction 3, the P-type semiconductor field limiting ring 4, and the N+-type semiconductor field limiting ring 6 respectively;

[0045] The anode 1 extends outward from the upper surface of the P-type semiconductor main junction 3 and covers one side surface and partial upper surface of the insulating dielectric layer 7;

[0046] The metal field plate 2 is disposed opposite to the anode 1 and extends outward from the upper surface of the N+-type semiconductor field limiting ring 6 and covers the other side surface and partial upper surface of the insulating dielectric layer 7;

[0047] The cathode 10 is disposed on the bottom surface of the N+-type semiconductor substrate 9.

[0048] Preferably, in the semiconductor terminal structure with lateral variable doping, the P-type semiconductor VLD region 5 is composed of a plurality of P-type sub-VLD regions 51, and the depth of each P-type sub-VLD region 51 gradually increases along the first direction, and the first direction is the width direction of the N-type semiconductor drift region 8.

[0049] In this embodiment, the doping concentration of a single P-type sub-VLD region 51 gradually decreases along the first direction, and the doping concentrations of a plurality of P-type sub-VLD regions 51 gradually decrease along the first direction, and the doping morphology presents a stepped distribution.

[0050] In this embodiment, the insulating dielectric layer 7 includes an oxide layer and a passivation layer. The oxide layer is a silicon dioxide layer, and the passivation layer is a silicon nitride layer.

[0051] In this embodiment, the concentration of doping ions in the P-type semiconductor VLD region 5 is less than the concentration of doping ions in the P-type semiconductor main junction 3 and the P-type semiconductor field limiting ring 4.

[0052] Embodiment 2:

[0053] The embodiment 2 of the present invention provides a preparation method of a semiconductor terminal structure with lateral variable doping, including the following processes:

[0054] Provide an N+-type semiconductor substrate, and form an N-type semiconductor drift region on the upper surface of the N+-type semiconductor substrate through epitaxial growth;

[0055] Form an insulating dielectric layer on the upper surface of the N-type semiconductor drift region;

[0056] Form a P-type semiconductor main junction and a P-type semiconductor field limiting ring in the N-type semiconductor drift region through photolithography and first ion implantation in sequence; form a P-type semiconductor VLD region in the N-type semiconductor drift region through photolithography and multiple second ion implantations in sequence, and the junction depth of the P-type semiconductor VLD region is greater than that of the P-type semiconductor main junction;

[0057] Form an N+-type semiconductor field limiting ring in the N-type semiconductor drift region through photolithography and third ion implantation in sequence;

[0058] Through ion sputtering, cover part of the upper surface of the N-type semiconductor drift region and part of the upper surface of the insulating dielectric layer to form an anode and a metal field plate respectively;

[0059] Through ion sputtering, deposit a cathode material on the bottom surface of the N+-type semiconductor substrate to form a cathode.

[0060] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor terminal structure with lateral variable doping, characterized in that: Comprising: N+-type semiconductor substrate; N-type semiconductor drift region, disposed on the upper surface of the N+-type semiconductor substrate, including a P-type semiconductor main junction, a P-type semiconductor field limiting ring, a P-type semiconductor VLD region, and an N+-type semiconductor field limiting ring. The P-type semiconductor field limiting ring is connected to one side of the P-type semiconductor VLD region. There is a gap between the P-type semiconductor VLD region and the N+-type semiconductor field limiting ring. The concentration of doped ions in the P-type semiconductor VLD region is less than the concentration of doped ions in the P-type semiconductor main junction and the P-type semiconductor field limiting ring. The junction depth of the P-type semiconductor VLD region is greater than the junction depth of the P-type semiconductor main junction; The P-type semiconductor VLD region is composed of a plurality of P-type sub-VLD regions. The depth of each P-type sub-VLD region gradually increases along a first direction, and the first direction is the width direction of the N-type semiconductor drift region; Insulating dielectric layer, disposed on the upper surface of the N-type semiconductor drift region, in contact with the partial upper surfaces of the P-type semiconductor main junction, the P-type semiconductor field limiting ring, and the N+-type semiconductor field limiting ring respectively; Anode, extending outward from the upper surface of the P-type semiconductor main junction, covering one side surface and a partial upper surface of the insulating dielectric layer; Metal field plate, disposed opposite to the anode, extending outward from the upper surface of the N+-type semiconductor field limiting ring, covering the other side surface and a partial upper surface of the insulating dielectric layer; Cathode, disposed on the bottom surface of the N+-type semiconductor substrate.

2. The semiconductor terminal structure with lateral variable doping according to claim 1, characterized in that: The doping concentration of a single P-type sub-VLD region gradually decreases along the first direction.

3. The semiconductor terminal structure with lateral variable doping according to claim 1, characterized in that: The doping concentrations of the plurality of P-type sub-VLD regions gradually decrease along the first direction, and the doping morphology presents a stepped distribution.

4. The semiconductor terminal structure with lateral variable doping according to claim 1, characterized in that: The insulating dielectric layer includes an oxide layer and a passivation layer.

5. The semiconductor terminal structure with lateral variable doping according to claim 4, characterized in that: The oxide layer is a silicon dioxide layer.

6. The semiconductor terminal structure with lateral variable doping according to claim 4, characterized in that: The passivation layer is a silicon nitride layer.

7. A method for preparing a semiconductor terminal structure with lateral variable doping, for preparing the semiconductor terminal structure with lateral variable doping according to any one of claims 1-6, characterized in that: Including the following processes: Providing an N+-type semiconductor substrate, and forming an N-type semiconductor drift region on the upper surface of the N+-type semiconductor substrate by epitaxial growth; Forming an insulating dielectric layer on the upper surface of the N-type semiconductor drift region; Successively through photolithography and first ion implantation, forming a P-type semiconductor main junction and a P-type semiconductor field limiting ring in the N-type semiconductor drift region; successively through photolithography and multiple second ion implantations, forming a P-type semiconductor VLD region in the N-type semiconductor drift region, and the junction depth of the P-type semiconductor VLD region is greater than the junction depth of the P-type semiconductor main junction; Successively through photolithography and third ion implantation, forming an N+-type semiconductor field limiting ring in the N-type semiconductor drift region; Through ion sputtering, covering the partial upper surface of the N-type semiconductor drift region and the partial upper surface of the insulating dielectric layer, respectively forming an anode and a metal field plate; Through ion sputtering, depositing cathode material on the bottom surface of the N+-type semiconductor substrate to form a cathode.

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