Memory device

Abstract

The present application discloses a storage device. A memory cell includes: a substrate; a bit line vertically oriented along a first direction starting from the substrate; a nanosheet transistor including at least one nanosheet horizontally oriented along a second direction perpendicular to the first direction starting from the bit line; and a capacitor horizontally oriented along the second direction starting from the nanosheet transistor.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2020 - 0113116, filed on September 4, 2020, which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to semiconductor devices, and more particularly, to a memory device having enhanced electronic integration. Background art

[0004] The integration degree of two - dimensional (2D) semiconductor devices is mainly determined by the area occupied by memory cells, and thus it is greatly affected by the level of fine patterning technology. Therefore, although the integration degree of 2D semiconductor devices has been increasing, it is limited by the improvement of ultra - expensive equipment required for miniaturizing patterns. To overcome such limitations of 2D devices, memory devices having memory cells arranged in three - dimensional (3D) have been proposed. Summary of the invention

[0005] According to various embodiments of the present disclosure, 3D memory cells and a memory device with a higher integration degree are provided.

[0006] According to an embodiment of the present disclosure, a memory cell includes: a substrate; a bit line vertically oriented along a first direction starting from the substrate; a nanosheet transistor including at least one nanosheet horizontally oriented along a second direction perpendicular to the first direction starting from the bit line; and a capacitor horizontally oriented along the second direction starting from the nanosheet transistor.

[0007] According to an embodiment of the present disclosure, a memory cell includes: a substrate; a bit line vertically oriented along a first direction starting from the substrate; a first cylinder horizontally oriented along a second direction perpendicular to the first direction starting from the bit line; a second cylinder horizontally spaced apart from the first cylinder; at least two nanosheets horizontally oriented between the first cylinder and the second cylinder; a word line buried in the first cylinder and the second cylinder and surrounding at least two nanosheets; and a capacitor horizontally oriented along the second direction starting from the second cylinder.

[0008] According to an embodiment of the present disclosure, a memory cell includes: a substrate; a bit line vertically oriented along a first direction starting from the substrate; at least two nanosheets horizontally oriented along a second direction perpendicular to the first direction starting from the bit line; a word line including an enclosing portion surrounding the at least two nanosheets and first and second buried portions extending along the second direction from the enclosing portion; a first doped portion horizontally oriented starting from a first side of the nanosheet, connected to the bit line, and surrounding the first buried portion; a second doped portion horizontally oriented starting from a second side of the nanosheet and surrounding the second buried portion; and a capacitor horizontally oriented along the second direction starting from the second doped portion.

[0009] According to an embodiment of the present disclosure, a memory device includes: a peripheral circuit portion; and a memory cell array including a plurality of memory cells vertically arranged along a first direction starting from the peripheral circuit portion, wherein each of the plurality of memory cells includes: a bit line vertically oriented along the first direction; a nanosheet transistor including at least two nanosheets horizontally oriented along a second direction perpendicular to the first direction starting from the bit line; and a capacitor horizontally oriented along the second direction starting from the nanosheet transistor.

[0010] According to the present disclosure, in a memory device, a transistor and a capacitor can be 3D stacked on a substrate. Accordingly, the memory device can have an increased integration degree.

[0011] According to the present disclosure, a word line WL having a gate-all-around structure can electrically shield at least two nanosheets from word lines of vertically adjacent memory cells to each other.

[0012] These and other features and advantages of the present invention will be better understood through the following drawings and the detailed description of various embodiments of the present disclosure. Description of the Drawings

[0013] Figure 1 is a view schematically showing a configuration of a memory device according to an embodiment of the present disclosure.

[0014] Figure 2A is Figure 1 a cross-sectional view taken along line A-A' of

[0015] Figure 2B is Figure 1 a cross-sectional view taken along line B-B' of

[0016] Figure 3 is a view showing in detail Figure 1 the active layer ACT of

[0017] Figure 4A and Figure 4BThey are a perspective view and an exploded perspective view showing the arrangement of word lines WL and active layer ACT, respectively.

[0018] Figure 5A It is a view schematically showing the configuration of a storage device according to an embodiment of the present disclosure.

[0019] Figure 5B It is a sectional view taken along Figure 5A line A1 - A1′.

[0020] Figure 5C It is a sectional view taken along Figure 5A line B1 - B1′.

[0021] Figure 6 It is a view showing a mirror - type memory cell array sharing bit lines.

[0022] Figure 7 It is a view showing a mirror - type memory cell array sharing plate lines.

[0023] Figure 8A It is a view schematically showing the configuration of a storage device according to an embodiment of the present disclosure.

[0024] Figure 8B It is a sectional view taken along Figure 8A line A - A′.

[0025] Figure 9A It is a view schematically showing the configuration of a storage device according to an embodiment of the present disclosure.

[0026] Figure 9B It is a sectional view taken along Figure 9A line A - A′.

[0027] Figure 10 It is a view schematically showing the configuration of a storage device according to an embodiment of the present disclosure.

[0028] Figure 11A It is a sectional view taken along Figure 10 line A - A′.

[0029] Figure 11B It is a sectional view taken along Figure 10 line B - B′.

[0030] Figure 12 It is a view showing in detail Figure 10 the active layer ACT.

[0031] Figure 13 It is an exploded perspective view showing the arrangement of word lines WL and active layer ACT. Detailed Description of the Invention

[0032] In the following, embodiments of the present disclosure are described with reference to schematic cross-sectional views, plan views or block diagrams. The views can be changed or modified according to manufacturing techniques and / or tolerances. Therefore, the embodiments of the present disclosure are not limited to the specific types shown and illustrated herein, but may cover changes or modifications caused by manufacturing processes. For example, regions or areas shown in the drawings may be schematically illustrated, and the shapes shown for them are provided only as examples and do not limit the category or scope of the present disclosure.

[0033] Figure 1 is a view schematically showing the configuration of a storage device according to an embodiment of the present disclosure. Figure 2A is along Figure 1 a cross-sectional view taken along line A-A′. Figure 2B is along Figure 1 a cross-sectional view taken along line B-B′. Figure 3 is a view showing in detail Figure 1 the active layer ACT. Figure 4A and Figure 4B are a perspective view and an exploded perspective view showing the arrangement of the word line WL and the active layer ACT, respectively.

[0034] Referring to Figures 1 to 4B , the storage device 100 may include a storage cell MC. The storage cell MC may be located on a substrate structure LS. The storage cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. The bit line BL may be vertically oriented along a first direction D1 starting from the substrate structure LS. The transistor TR may be horizontally oriented along a second direction D2 perpendicular to the first direction D1 starting from the bit line BL. The capacitor CAP may be horizontally oriented along the second direction D2 starting from the transistor TR. The transistor TR may include a word line WL horizontally oriented along a third direction D3.

[0035] The substrate structure LS may include any material suitable for semiconductor processing. The substrate structure LS may include at least one or more of a conductive material, a dielectric material, and a semiconductor material. Various materials may be formed on the substrate structure LS. The substrate structure LS may include a semiconductor substrate. The semiconductor substrate may be formed of a silicon-containing material. For example, the substrate structure LS may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multi-layer structure thereof. The substrate structure LS may include other semiconductor materials, such as germanium. The substrate structure LS may include a compound semiconductor substrate, such as a III / V group semiconductor substrate (such as GaAs). The substrate structure LS may include a silicon-on-insulator (SOI) substrate.

[0036] According to one embodiment, the substrate structure LS may include a semiconductor substrate and a plurality of integrated circuits (ICs), multi-level metal wiring (MLM), or a combination thereof formed on the semiconductor substrate. The substrate structure LS may include a peripheral circuit portion PC. The peripheral circuit portion PC may include a plurality of control circuits for controlling the memory cells MC. The peripheral circuit portion PC may include a sense amplifier (SA) connected to the bit line BL and a sub-word line driver connected to the word line WL. The peripheral circuit portion PC is denoted by the reference numeral "PC" in Figure 5A , Figure 6 and Figure 7 in the drawings.

[0037] The bit line BL may include vertically oriented columns. The bit line BL may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include polysilicon doped with an N-type impurity or titanium nitride (TiN). The bit line BL may include a stack of titanium nitride and tungsten (TiN / W). The bit line BL may include vertically oriented metal columns.

[0038] The transistor TR may include a lateral transistor. The transistor TR may include a gate-all-around (GAA) transistor. The transistor TR may include an active layer ACT and a word line WL. The active layer ACT may be horizontally oriented along a second direction D2 starting from the bit line BL. The word line WL may be horizontally oriented along a third direction D3 perpendicular to the first direction D1 and the second direction D2. The active layer ACT may include a first doped portion SR, a second doped portion DR, and at least one channel portion CH1 and CH2. The at least one channel portion CH1 and CH2 may be located between the first doped portion SR and the second doped portion DR. The first doped portion SR may provide a first edge of the active layer ACT, and the second doped portion DR may provide a second edge of the active layer ACT. The active layer ACT may include a silicon-containing material. The active layer ACT may include a single-crystalline silicon layer, a polysilicon layer, a doped silicon layer, a doped polysilicon layer, or a combination thereof. The first doped portion SR and the second doped portion DR may include an N-type impurity or a P-type impurity. The first doped portion SR and the second doped portion DR may include phosphorus (P), arsenic (As), boron (B), indium (In), or a combination thereof. The first doped portion SR and the second doped portion DR may be doped with the same impurity. The first doped portion SR and the second doped portion DR may also be referred to as a first source / drain and a second source / drain, respectively. The channel portions CH1 and CH2 may include an impurity different from that of the first doped portion SR and the second doped portion DR.

[0039] The first doped portion SR can be connected to the bit line BL via a bit line contact node BLC located between the bit line BL and the first doped portion SR. The bit line contact node BLC and the first doped portion SR can include the same material. For example, the bit line contact node BLC and the first doped portion SR can include, for example, doped polysilicon doped with N-type impurities. Optionally, the first doped portion SR can include first doped polysilicon. The bit line contact node BLC can include a stack of a second doped polysilicon and a metal silicide. The second doped polysilicon can be connected to the first doped portion SR, and the metal silicide can be connected to the bit line BL. According to one embodiment, the bit line contact node BLC and the first doped portion SR can have an overall structure including a single layer of doped polysilicon. The first doped portion SR can be connected to the first edges of the channel portions CH1 and CH2. An ohmic contact layer (such as a metal silicide) can also be formed between the bit line BL and the bit line contact node BLC.

[0040] The second doped portion DR can be connected to the capacitor CAP. The second doped portion DR can be connected to the storage node SN of the capacitor CAP. Refer to Figure 3 , the second doped portion DR can include an open side surface DR1 connected to the channel portions CH1 and CH2. The second doped portion DR can include a closed side surface DR2 connected to the storage node SN of the capacitor. The second doped portion DR can be connected to the second edges of the channel portions CH1 and CH2. The second doped portion DR can be shaped, for example, as a cylinder and can be horizontally oriented along the second direction D2. For example, the open side surface DR1 of the second doped portion DR can correspond to the entrance of the cylinder, while the closed side surface DR2 of the second doped portion DR can correspond to the bottom of the cylinder. The second doped portion DR can also include an outer wall DR3 between the open side surface DR1 and the closed side surface DR2. An internal gap IG can be defined by the outer wall DR3 and the closed side surface. The internal gap IG can be referred to as a recess.

[0041] The channel portions CH1 and CH2 can be horizontally oriented along the second direction D2. The channel portions CH1 and CH2 can be horizontally oriented along the second direction D2 between the first doped portion SR and the second doped portion DR. The channel portions CH1 and CH2 can each be formed as a horizontal flat plate. The length of the channel portions CH1 and CH2 along the second direction D2 can be greater than the length of the channel portions CH1 and CH2 along the third direction D3. The channel portions CH1 and CH2 can also be referred to as nanosheets or nanosheet channels. Since the channel portions CH1 and CH2 are horizontally oriented along the second direction D2, the channel portions CH1 and CH2 can also be referred to as "lateral nanosheets". The channel portions CH1 and CH2 can include at least two channel portions, for example, a first channel portion CH1 and a second channel portion CH2. The first channel portion CH1 and the second channel portion CH2 can be vertically arranged along the first direction D1. The space between the first channel portion CH1 and the second channel portion CH2 can be filled with a portion of the word line WL. The thickness of the first channel portion CH1 can be the same as the thickness of the second channel portion CH2. The thickness refers to the thickness along the first direction D1. The channel portions CH1 and CH2 can include a semiconductor material, a single-crystalline semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor, a metal compound, or a combination thereof. For example, the channel portions CH1 and CH2 can include single-crystalline silicon, polycrystalline silicon, silicon germanium, indium gallium zinc oxide (IGZO), MoS2, and WS2.

[0042] Reference Figure 2A , Figure 4A and Figure 4B, the word line WL may include a surrounding portion SG surrounding the channel portions CH1 and CH2. The word line WL may also include an internal extension portion (IEG) that horizontally extends from a first side surface of the surrounding portion SG along a second direction D2. The internal extension portion IEG may be located near the first doped portion SR. The word line WL may also include an internal buried portion (IBG) that horizontally extends from a second side surface of the surrounding portion SG along the second direction D2. The internal buried portion IBG may fill an internal gap IG of the second doped portion DR. The surrounding portion SG may be referred to as a surrounding gate electrode, and the internal buried portion IBG may be referred to as a buried gate electrode. The internal extension portion IEG and the internal buried portion IBG may be located in a space between the first channel portion CH1 and the second channel portion CH2. The surrounding portion SG, the internal extension portion IEG, and the internal buried portion IBG may be integrally formed and connected to each other. The surrounding portion SG may also be referred to as a gate-all-around (GAA). The length of the surrounding portion SG along the second direction D2 may be greater than the lengths of the internal extension portion IEG and the internal buried portion IBG along the second direction D2. Optionally, the length of the surrounding portion SG along the second direction D2 may be equal to the lengths of the internal extension portion IEG and the internal buried portion IBG along the second direction D2. The word line WL may also include an external extension portion OEG that extends from the surrounding portion SG along a third direction D3. The external extension portion OEG may not surround the channel portions CH1 and CH2. The internal extension portion IEG and the internal buried portion IBG may also not surround the channel portions CH1 and CH2. The internal extension portion IEG, the internal buried portion IBG, and the external extension portion OEG may be collectively referred to as the "non-surrounding portion".

[0043] The word line WL may include a hybrid gate-all-around (GAA) structure. The hybrid GAA structure may include a surrounding portion SG and an internal buried portion IBG.

[0044] The word line WL may include a silicon-containing material, a metal-containing material, or a combination thereof. The word line WL may include polysilicon, metal, metal silicide, metal nitride, or a combination thereof. For example, the word line WL may include a stack of titanium nitride and tungsten.

[0045] Return reference Figure 2A and Figure 2B, a gate insulating layer GD can be formed between the word line WL and the channel portions CH1 and CH2. A part of the gate insulating layer GD can be formed between the internal buried portion IBG and the second doped portion DR. A part of the gate insulating layer GD can be formed between the internal extension portion IEG and the first doped portion SR. The gate insulating layer GD can surround the channel portions CH1 and CH2. The surrounding portion SG of the word line WL can surround the channel portions CH1 and CH2, where the gate insulating layer GD is disposed between the surrounding portion SG and the channel portions CH1 and CH2. The gate insulating layer GD can be shaped to conformally surround the channel portions CH1 and CH2. The gate insulating layer GD can include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof.

[0046] Return reference Figure 1 and Figure 2A , the capacitor CAP can be horizontally disposed starting from the transistor TR. The capacitor CAP can be horizontally oriented along the second direction D2. The capacitor CAP can include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN, the dielectric layer DE, and the plate node PN can be horizontally arranged along the second direction D2. The storage node SN can be shaped, for example, like a cylinder and can be horizontally oriented, and the plate node PN can be shaped like a cylinder surrounding the storage node SN. The dielectric layer DE can be shaped to cover the surface of the cylinder of the storage node SN. The plate node PN can be connected to a plate line PL. Optionally, the plate node PN and the plate line PL can be integrally formed with each other, and the plate node PN can be a part of the plate line PL.

[0047] The storage node SN can have a three-dimensional (3D) structure, and the 3D structure of the storage node SN can be a horizontal 3D structure along the second direction D2. As an example of the 3D structure, the storage node SN can have a cylindrical shape, a columnar shape, or a column-cylindrical shape resulting from combining the cylindrical and columnar shapes. In the illustrated embodiment, the storage node SN can be shaped like a cylinder. The dielectric layer DE can be formed between the storage node SN and the plate node PN. The dielectric layer DE can directly contact the plate node PN.

[0048] The capacitor CAP may include a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node PN may include a metal-based material. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a dielectric constant higher than that of silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of approximately 3.9, while the dielectric layer DE may include a high-k material having a dielectric constant of 4 or greater. The high-k material may have a dielectric constant of about 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). Optionally, the dielectric layer DE may be formed of a composite layer including two or more layers of the above high-k materials.

[0049] The dielectric layer DE can be formed of a zirconium-based oxide (Zr-based oxide). The dielectric layer DE can have a stacked structure including zirconia (ZrO2). The stacked structure including zirconia (ZrO2) can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a stacked structure in which an alumina Al2O3 layer is stacked on zirconia ZrO2. The ZAZ stack can have a stacked structure in which zirconia ZrO2, alumina Al2O3, and zirconia ZrO2 are stacked in sequence. The ZA stack and the ZAZ stack can also be referred to as zirconia-based layers (ZrO2-based layers). According to another embodiment, the dielectric layer DE can be formed of a hafnium-based oxide. The dielectric layer DE can have a stacked structure including hafnia (HfO2). The stacked structure including hafnia (HfO2) can include an HA (HfO2 / Al2O3) stack or an HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack can have a stacked structure in which an alumina Al2O3 layer is stacked on hafnia HfO2. The HAH stack can have a stacked structure in which hafnia HfO2, alumina Al2O3, and hafnia HfO2 are stacked in sequence. The HA stack and the HAH stack can also be referred to as hafnia-based layers (HfO2-based layers). In the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, alumina (Al2O3) can have a larger bandgap than zirconia (ZrO2) and hafnia (HfO2). Alumina (Al2O3) can have a lower dielectric constant than zirconia (ZrO2) and hafnia (HfO2). Thus, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material having a larger bandgap than the high-k material. In addition to alumina Al2O3, the dielectric layer DE can also include silica SiO2 as a high-bandgap material. Since the dielectric layer DE includes a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be extremely thin. In one embodiment, the high-bandgap material can be thinner than the high-k material. The thickness of the high-bandgap material is in to range. According to another embodiment, the dielectric layer DE can include a layered structure in which the high-k material and the high-bandgap material are alternately stacked. For example, the dielectric layer DE can include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAA (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2). In the above layered structure, alumina Al2O3 can be extremely thin. For example, the thickness of alumina Al2O3 is in to range.

[0050] According to another embodiment, the dielectric layer DE may include a stacked structure, a layered structure, or a hybrid structure including zirconia, hafnium oxide, and alumina.

[0051] According to another embodiment, an interface control layer may be further formed between the storage node SN and the dielectric layer DE to reduce leakage current. The interface control layer may include titanium oxide (TiO2). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0052] The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the storage node (SN) and the plate node (PN) may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) stack, or a tungsten nitride / tungsten (WN / W) stack. The plate node PN may include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, the silicon germanium may be a gap-filling material filling the gap of the storage node SN cylinder, the titanium nitride (TiN) may substantially act as the plate node of the capacitor CAP, and the tungsten nitride may be a low-resistance material.

[0053] The plate line PL may be vertically oriented along the first direction D1 while being horizontally oriented along the third direction D3. The plate line PL may be formed as a vertical flat plate extending in the first direction D1 and the third direction D3. The plate node PN and the plate line PL may include the same material.

[0054] Figure 5A is a view schematically showing the configuration of a storage device according to an embodiment of the present disclosure. Figure 5B is along Figure 5A a cross-sectional view taken along line A1 - A1′. Figure 5C is along Figure 5A a cross-sectional view taken along line B1 - B1′. In Figures 5A to 5C the same reference numerals are used to denote the same elements as in Figures 1 to 4B For the same elements that have been described, the detailed description may be omitted. Figures 5A to 5C The storage device 200 shown may include an array of storage cells MC as shown in Figure 1 shown.

[0055] Refer toFigures 5A to 5C , the memory device 200 may include a substrate structure LS and a memory cell array MCA formed on the substrate structure LS. The memory cell array MCA may be vertically oriented along a first direction D1 starting from the substrate structure LS. The memory cell array MCA may include a plurality of memory cells MC. The memory cell array MCA may include a column array of memory cells MC and a row array of memory cells MC. Bit lines BL may be coupled to the memory cells MC of the column array, while word lines WL may be coupled to the memory cells of the row array. In Figures 5A to 5C the illustrated embodiment, the memory cell array MCA may include four memory cells MC. Each memory cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. Each memory cell MC may further include a word line WL extending along a third direction D3. The word line WL may be disposed in a region between the capacitor CAP and the bit line BL. In each memory cell MC, the bit line BL, the transistor TR, and the capacitor CAP may be located in a lateral array (LA) along a second direction D2, where the transistor TR is located between the bit line BL and the capacitor CAP.

[0056] The memory cell array MCA may include a stack of memory cells MC. The memory cells MC may be vertically stacked on the substrate structure LS along the first direction D1. Refer to Figure 5A , the memory cell array MCA may include memory cells horizontally arranged along a third direction D3.

[0057] Each memory cell MC may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. The transistor TR may be the transistor TR as described. The transistor TR may include an active layer ACT and a word line WL. The word line WL may include a gate-all-around (GAA) structure. The transistor TR may include a lateral transistor. The transistor TR may include a gate-all-around (GAA) transistor. The active layer ACT may be horizontally oriented along the second direction D2 starting from the bit line BL. The word line WL may be horizontally oriented along a third direction D3 perpendicular to the first direction D1 and the second direction D2. The active layer ACT may include a first doped portion SR, a second doped portion DR, and at least one channel portion CH1 and CH2 located between the first doped portion SR and the second doped portion DR. A bit line contact node BLC may be located between the bit line BL and the first doped portion SR. The bit line contact node BLC and the first doped portion SR may include the same material.

[0058] The transistor TR may be located between the bit line BL and the capacitor CAP. The transistor TR may be horizontally arranged (LA) along the second direction D2 parallel to the surface of the substrate structure LS. That is, the transistor TR may be horizontally located between the bit line BL and the capacitor CAP.

[0059] The bit line BL can extend along a first direction D1 starting from the substrate structure LS. The plane of the substrate structure LS can be provided by a second direction D2 and a third direction D3. The bit line BL can be vertically oriented starting from the substrate structure LS. The bit line BL can be in direct contact with the substrate structure LS. For example, the bottom of the bit line BL can be in direct contact with the peripheral circuit portion PC formed on the substrate structure LS. The bit line BL can have a vertically raised columnar shape. The bit line BL can have a rectangular cross-section, but it should be understood that the present invention is not limited thereto. The bit line BL can also be referred to as a vertically oriented bit line or a columnar bit line. Memory cells MC stacked vertically on top of each other along the first direction D1 can share one bit line BL.

[0060] The word line WL can extend around along the third direction D3 and around the active layer ACT. Memory cells MC horizontally arranged at the same vertical level along the third direction D3 can share one word line WL. The word lines WL of the memory cells stacked along the first direction D1 can be vertically spaced apart from each other. The insulating layer ILD can be located between the vertically spaced apart word lines WL.

[0061] The capacitors of the memory cells stacked along the first direction D1 can share the plate line PL. In addition, the capacitors of the memory cells horizontally arranged along the third direction D3 can share the plate line PL. The plate line PL can interactively connect the plate nodes PN and be spaced apart from the substrate structure LS and extend vertically along the first direction D1.

[0062] Figure 6 is a view showing a mirror-type memory cell array sharing a bit line. Figure 7 is a view showing a mirror-type memory cell array sharing a plate line. Figure 6 and Figure 7 show application examples of the memory cell array MCA of the memory device 200.

[0063] Reference Figure 6 , a mirror-type memory cell array MCA1 sharing the bit line BL is described. Memory cells MC horizontally arranged along the second direction D2 can be arranged in a mirror-type structure in which they are connected to different plate lines PL and share one bit line BL.

[0064] Reference Figure 7 , a mirror-type memory cell array MCA2 sharing the plate line PL is described. Memory cells MC arranged along the second direction D2 can be arranged in a mirror-type structure in which they are connected to different bit lines BL and share one plate line PL.

[0065] According to another embodiment, the memory device may include both a mirror-type memory cell array MCA1 sharing bit lines BL and a mirror-type memory cell array MCA2 sharing plate lines PL.

[0066] The mirror-type memory cell arrays MCA1 and MCA2 may be located at a position higher than the substrate structure LS and the peripheral circuit portion PC. The bit lines BL of the mirror-type memory cell arrays MCA1 and MCA2 may be connected to the peripheral circuit portion PC.

[0067] Figure 8A is a view schematically showing the configuration of a memory device according to an embodiment of the present disclosure. Figure 8B is a cross-sectional view taken along line A-A′ of Figure 8A . The memory device 300 may include components similar to those of Figures 1 to 4B . In Figure 8A and Figure 8B , the same reference numerals are used to denote the same elements as in Figures 1 to 4B . The detailed description of the same elements described previously may be omitted.

[0068] Referring to Figure 8A and Figure 8B , the memory device 300 may include a memory cell MC located on the substrate structure LS. The memory cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. The bit line BL may be vertically oriented along a first direction D1 starting from the substrate structure LS. The transistor TR may be horizontally oriented along a second direction D2 starting from the bit line BL. The capacitor CAP may be horizontally oriented along the second direction D2 starting from the transistor TR. The transistor TR may include a word line WL horizontally oriented along a third direction D3.

[0069] The transistor TR may include a gate-all-around (GAA) transistor. The transistor TR may include an active layer ACT and a word line WL. The active layer ACT may be horizontally oriented along the second direction D2 starting from the bit line BL. The word line WL may be horizontally oriented along a third direction D3 perpendicular to the first direction D1 and the second direction D2. The active layer ACT may include a first doped portion SR′, a second doped portion DR, and at least one channel portion CH1 and CH2 located between the first doped portion SR′ and the second doped portion DR. The first doped portion SR′ may provide a first edge of the active layer ACT, and the second doped portion DR may provide a second edge of the active layer ACT.

[0070] The first doped portion SR' can be connected to the bit line BL via a bit line contact node BLC located between the bit line BL and the first doped portion SR'. The bit line contact node BLC and the first doped portion SR' can include the same material. For example, the bit line contact node BLC and the first doped portion SR' can include doped polysilicon, and the doped polysilicon can include polysilicon doped with N-type impurities. Optionally, the first doped portion SR' can include first doped polysilicon. The bit line contact node BLC can include a stack of a second doped polysilicon and a metal silicide. The second doped polysilicon can be connected to the first doped portion SR', and the metal silicide can be connected to the bit line BL. According to an embodiment, the bit line contact node BLC and the first doped portion SR' can have an integrated structure including a single layer of doped polysilicon. The first doped portion SR' can be connected to the first edges of the channel portions CH1 and CH2. An ohmic contact layer (such as a metal silicide) can also be formed between the bit line BL and the bit line contact node BLC.

[0071] The second doped portion DR can be connected to the storage node SN of the capacitor CAP. Refer to Figure 3 , the second doped portion DR can include an open side surface DR1 connected to the channel portions CH1 and CH2. The second doped portion DR can include a closed side surface DR2 connected to the storage node SN of the capacitor. The second doped portion DR can be connected to the second edges of the channel portions CH1 and CH2. The second doped portion DR can be shaped, for example, as a cylinder and can be horizontally oriented along the second direction D2. For example, the open side surface DR1 of the second doped portion DR can correspond to the entrance of the cylinder, while the closed side surface DR2 of the second doped portion DR can correspond to the bottom of the cylinder. The second doped portion DR can also include an outer wall DR3 between the open side surface DR1 and the closed side surface DR2. An internal gap IG can be defined by the outer wall DR3 and the closed side surface. The internal gap IG can also be referred to as a recess.

[0072] The channel portions CH1 and CH2 can be horizontally oriented along the second direction D2. The channel portions CH1 and CH2 can be horizontally oriented along the second direction D2 between the first doped portion SR and the second doped portion DR. The channel portions CH1 and CH2 can each be formed as a horizontal flat plate. The length of the channel portions CH1 and CH2 along the second direction D2 can be greater than the length of the channel portions CH1 and CH2 along the third direction D3. The channel portions CH1 and CH2 can also be referred to as nanosheets or nanosheet channels. Since the channel portions CH1 and CH2 are horizontally oriented along the second direction D2, the channel portions CH1 and CH2 can also be referred to as "lateral nanosheets". The channel portions CH1 and CH2 can include at least two channel portions, for example, a first channel portion CH1 and a second channel portion CH2. The first channel portion CH1 and the second channel portion CH2 can be vertically arranged along the first direction D1. The space between the first channel portion CH1 and the second channel portion CH2 can be filled with a part of the word line WL. The thickness of the first channel portion CH1 can be the same as the thickness of the second channel portion CH2. This thickness refers to the thickness along the first direction D1.

[0073] Reference Figure 2A 、 Figure 4A 、 Figure 4B and Figure 8B, the word line WL may include a surrounding portion SG surrounding the channel portions CH1 and CH2. The word line WL may further include an inner extension portion (IEG) that horizontally extends along a second direction D2 from a first side surface of the surrounding portion SG. The inner extension portion IEG may be located near the first doped portion SR'. The word line WL may further include an inner buried portion IBG that horizontally extends along the second direction D2 from a second side surface of the surrounding portion SG. The inner buried portion IBG may fill an inner gap IG of the second doped portion DR. The surrounding portion SG may also be referred to as a surrounding gate electrode, and the inner buried portion IBG may also be referred to as a buried gate electrode. The inner extension portion IEG and the inner buried portion IBG may be located in a space between the first channel portion CH1 and the second channel portion CH2. The surrounding portion SG, the inner extension portion IEG, and the inner buried portion IBG may be integrally formed and connected to each other. The surrounding portion SG may also be referred to as a gate-all-around (GAA). The length of the surrounding portion SG along the second direction D2 may be greater than the lengths of the inner extension portion IEG and the inner buried portion IBG along the second direction D2. Optionally, the length of the surrounding portion SG along the second direction D2 may be equal to the lengths of the inner extension portion IEG and the inner buried portion IBG along the second direction D2. The word line WL may further include an outer extension portion OEG that extends from the surrounding portion SG along a third direction D3. The outer extension portion OEG may not surround the channel portions CH1 and CH2. The inner extension portion IEG and the inner buried portion IBG may also not surround the channel portions CH1 and CH2. The inner extension portion IEG, the inner buried portion IBG, and the outer extension portion OEG may be collectively referred to as a "non-surrounding portion".

[0074] The word line WL may include a hybrid gate-all-around (GAA) structure. The hybrid GAA structure may include a surrounding portion SG and an inner buried portion IBG.

[0075] The gate insulating layer GD may be formed between the word line WL and the channel portions CH1 and CH2. A part of the gate insulating layer GD may be formed between the inner buried portion IBG and the second doped portion DR. A part of the gate insulating layer GD may be formed between the inner extension portion IEG and the first doped portion SR'. The gate insulating layer GD may surround the channel portions CH1 and CH2. The surrounding portion SG of the word line WL may surround the channel portions CH1 and CH2, with the gate insulating layer GD disposed between the surrounding portion SG and the channel portions CH1 and CH2. The gate insulating layer GD may be shaped to conformally surround the channel portions CH1 and CH2. The gate insulating layer GD may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof.

[0076] The capacitor CAP can be horizontally disposed adjacent to the transistor TR. The capacitor CAP can be horizontally oriented along the second direction D2. The capacitor CAP can include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN, the dielectric layer DE, and the plate node PN can be horizontally arranged along the second direction D2. The storage node SN can be shaped, for example, as a cylinder and can be horizontally oriented, and the plate node PN can be shaped as a cylinder surrounding the storage node SN. The dielectric layer DE can be shaped to cover the surface of the cylinder of the storage node SN. The plate node PN can be connected to the plate line PL. Optionally, the plate node PN and the plate line PL can be integrally formed with each other, and the plate node PN can be a part of the plate line PL.

[0077] The storage node SN can have a three-dimensional (3D) structure, and the 3D structure of the storage node SN can be a horizontal 3D structure along the second direction D2. As an example of the 3D structure, the storage node SN can have a cylindrical shape, a columnar shape, or a cylindro-columnar shape resulting from combining a cylindrical shape and a columnar shape. In the illustrated embodiment, the storage node SN can be shaped as a cylinder. The dielectric layer DE can be formed between the storage node SN and the plate node PN. The dielectric layer DE can directly contact the plate node PN.

[0078] The first doped portion SR′ can have a rectangular ring-shaped cross section along the first direction D1. The cross section of the first doped portion SR′ along the first direction D1 can be shaped as a circular ring, an elliptical ring, or a polygonal ring. The first doped portion SR′ can extend around the internal extension portion IEG of the word line WL. The first doped portion SR′ can contact the bit line contact node BLC. The first doped portion SR′ and the bit line contact node BLC can include an integral single layer or different materials.

[0079] Figure 9A is a diagram schematically showing the configuration of a memory device according to an embodiment of the present disclosure. Figure 9B is along Figure 9A The sectional view taken along line A-A′. The memory device 400 can include components similar to those of Figures 1 to 4B . In Figure 9A and Figure 9B , the same reference numerals are used to denote the same elements as those in Figures 1 to 4B . The detailed description of the same elements described previously can be omitted.

[0080] Refer to Figure 9A and Figure 9B, the memory device 400 may include a memory cell MC. The memory cell MC may be located on a substrate structure LS. The memory cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. The bit line BL may be vertically oriented along a first direction D1 starting from the substrate structure LS. The transistor TR may be horizontally oriented along a second direction D2 perpendicular to the first direction D1 starting from the bit line BL. The capacitor CAP may be horizontally oriented along the second direction D2 starting from the transistor TR. The transistor TR may include a word line WL horizontally oriented along a third direction D3.

[0081] The transistor TR may include a gate-all-around (GAA) transistor. The transistor TR may include an active layer ACT and a word line WL. The active layer ACT may be horizontally oriented along the second direction D2 starting from the bit line BL. The word line WL may be horizontally oriented along a third direction D3 perpendicular to the first direction D1 and the second direction D2. The active layer ACT may include a first doped portion SR, a second doped portion DR′, and at least one channel portion CH1 and CH2. The at least one channel portion CH1 and CH2 may be located between the first doped portion SR and the second doped portion DR′. The first doped portion SR may provide a first edge of the active layer ACT, while the second doped portion DR′ may provide a second edge of the active layer ACT.

[0082] The first doped portion SR may be connected to the bit line BL. A bit line contact node BLC may be located between the bit line BL and the first doped portion SR.

[0083] The second doped portion DR′ may be connected to the capacitor CAP. The second doped portion DR′ may be connected to a storage node SN of the capacitor CAP. The second doped portion DR′ may horizontally extend along the second direction D2 starting from the channel portions CH1 and CH2. The upper horizontal second doped portion DR' and the lower horizontal second doped portion DR' may be spaced apart from each other along the first direction D1.

[0084] The channel portions CH1 and CH2 can be horizontally oriented along the second direction D2. The channel portions CH1 and CH2 can be horizontally oriented along the second direction D2 between the first doped portion SR and the second doped portion DR'. The channel portions CH1 and CH2 can each be formed as a horizontal flat plate. The length of the channel portions CH1 and CH2 along the second direction D2 can be greater than the length of the channel portions CH1 and CH2 along the third direction D3. The channel portions CH1 and CH2 can also be referred to as nanosheets or nanosheet channels. Since the channel portions CH1 and CH2 are horizontally oriented along the second direction D2, the channel portions CH1 and CH2 can also be referred to as "lateral nanosheets". The channel portions CH1 and CH2 can include at least two channel portions, for example, a first channel portion CH1 and a second channel portion CH2. The first channel portion CH1 and the second channel portion CH2 can be vertically arranged along the first direction D1. The space between the first channel portion CH1 and the second channel portion CH2 can be filled with a portion of the word line WL.

[0085] The first doped portion SR and the second doped portion DR' can each have a nanosheet shape.

[0086] As Figures 8A to 9B shown, the memory cells 300 and 400 can configure a memory cell array, and the array of memory cells 300 and 400 can be similar to Figures 5A to 7 the shown memory cell array.

[0087] Figure 10 is a perspective view schematically showing the configuration of a memory cell according to an embodiment of the present disclosure. Figure 11A is a cross-sectional view taken along the line A-A' of Figure 10 . Figure 11B is a cross-sectional view taken along the line B-B' of Figure 10 . Figure 12 is a view showing in detail the active layer ACT of Figure 10 . Figure 13 is an exploded perspective view showing the arrangement of the word line WL and the active layer ACT.

[0088] In Figures 10 to 13 , the same reference numerals are used to denote the same elements as those in the elements of Figures 1 to 4B . The memory device 500 can be similar to the memory device 100 of Figures 1 to 4B . For repeated elements, detailed descriptions will not be given.

[0089] Refer to Figures 10 to 13, the memory device 500 may include memory cells MC located on a substrate structure LS. The memory cells MC may include bit lines BL, transistors TR, and capacitors CAP. The bit lines BL may be vertically oriented along a first direction D1 starting from the substrate structure LS. The transistors TR may be horizontally oriented along a second direction D2 perpendicular to the first direction D1 starting from the bit lines BL. The capacitors CAP may be horizontally oriented along the second direction D2 starting from the transistors TR. The transistor TR may include a word line WL horizontally oriented along a third direction D3, at least two channel portions CH1 and CH2, a first doped portion SR″, and a second doped portion DR.

[0090] The first doped portion SR″ may be connected to the bit line BL. The first doped portion SR″ may be connected to the first edges of the channel portions CH1 and CH2. The second doped portion DR may be connected to the capacitor CAP. The second doped portion DR may be connected to the storage node SN of the capacitor CAP. Return reference Figure 3 , the second doped portion DR may include an open side surface DR1 connected to the channel portions CH1 and CH2. The second doped portion DR may include a closed side surface DR2 connected to the storage node SN of the capacitor. The second doped portion DR may be connected to the second edges of the channel portions CH1 and CH2. The second doped portion DR may be shaped, for example, like a cylinder and may be horizontally oriented along the second direction D2. For example, the open side surface DR1 of the second doped portion DR may correspond to the entrance of the cylinder, while the closed side surface DR2 of the second doped portion DR may correspond to the bottom of the cylinder. The second doped portion DR may further include an outer wall DR3 between the open side surface DR1 and the closed side surface DR2. An internal gap IG may be defined by the outer wall DR3 and the closed side surface. The internal gap IG may also be referred to as a recess. Like the second doped portion DR, the first doped portion SR″ may include an open side surface connected to the channel portions CH1 and CH2 and a closed side surface connected to the bit line BL. The first doped portion SR″ may be shaped, for example, like a cylinder and may be horizontally oriented along the second direction D2, and may include an internal gap. The first doped portion SR″ may also be referred to as the first cylinder, and the second doped portion DR may also be referred to as the second cylinder. The first doped portion SR″, the channel portions CH1 and CH2, and the second doped portion DR may configure the entire active layer. The bit line contact node BLC and the first doped portion SR″ may include the same or different materials.

[0091] The first doped portion SR″ and the second doped portion DR may be respectively connected to two edges of the channel portions CH1 and CH2. The first doped portion SR″ and the second doped portion DR may each be shaped, for example, as a cylinder and may be horizontally oriented and face each other, wherein the channel portions CH1 and CH2 are disposed between the first doped portion SR″ and the second doped portion DR.

[0092] The channel portions CH1 and CH2 may be horizontally oriented between the first doped portion SR″ and the second doped portion DR along the second direction D2. The channel portions CH1 and CH2 may each be shaped as a horizontal flat plate. The length of the channel portions CH1 and CH2 along the second direction D2 may be greater than the length of the channel portions CH1 and CH2 along the third direction D3. The channel portions CH1 and CH2 may also be referred to as nanosheets or nanosheet channels. Since the channel portions CH1 and CH2 are horizontally oriented along the second direction D2, the channel portions CH1 and CH2 may also be referred to as "lateral nanosheets". The channel portions CH1 and CH2 may include at least two channel portions, for example, a first channel portion CH1 and a second channel portion CH2. The first channel portion CH1 and the second channel portion CH2 may be vertically arranged along the first direction D1. The space between the first channel portion CH1 and the second channel portion CH2 may be filled with a portion of the word line WL. The thickness of the first channel portion CH1 may be the same as the thickness of the second channel portion CH2. The thickness refers to the thickness along the first direction D1.

[0093] The word line WL may include a surrounding portion SG surrounding the channel portions CH1 and CH2. The word line WL may further include a first internal buried portion IBG1 and a second internal buried portion IBG2, and the first internal buried portion IBG1 and the second internal buried portion IBG2 horizontally extend along a second direction D2 from a first side surface of the surrounding portion SG. The first internal buried portion IBG1 may fill an internal gap of the first doped portion SR″, and the second internal buried portion IBG2 may fill an internal gap IG of the second doped portion DR. The surrounding portion SG may also be referred to as a surrounding gate electrode, and the first internal buried portion IBG1 and the second internal buried portion IBG2 may also be referred to as buried gate electrodes. The surrounding portion SG, the first internal buried portion IBG1, and the second internal buried portion IBG2 may be integrally formed and connected to each other. The surrounding portion SG may also be referred to as a gate-all-around (GAA). The length of the surrounding portion SG along the second direction D2 may be greater than the lengths of the first internal buried portion IBG1 and the second internal buried portion IBG2 along the second direction D2. Optionally, the length of the surrounding portion SG along the second direction D2 may be equal to the lengths of the first internal buried portion IBG1 and the second internal buried portion IBG2 along the second direction D2. The word line WL may further include an external extension portion OEG that extends along a third direction D3 from the surrounding portion SG. The external extension portion OEG may not surround the channel portions CH1 and CH2. The first internal buried portion IBG1 and the second internal buried portion IBG2 may also not surround the channel portions CH1 and CH2. The first internal buried portion IBG1, the second internal buried portion IBG2, and the external extension portion OEG may be collectively referred to as a "non-surrounding portion".

[0094] The word line WL may include a hybrid gate-all-around (GAA) structure. The hybrid GAA structure may include a surrounding portion SG and internal buried portions IBG1 and IBG2.

[0095] As Figures 10 to 13 shown, the memory cell 500 may configure a memory cell array, and the array of memory cells 500 may be similar to Figures 5A to 7 the shown memory cell array. The array of memory cells 500 may be located at a position higher than the substrate structure LS and the peripheral circuit portion PC, and the bit line BL of the array of memory cells 500 may be connected to the peripheral circuit portion PC. Optionally, the array of memory cells 500 may be located at a position lower than the substrate structure LS and the peripheral circuit portion PC, and the bit line BL of the array of memory cells 500 may be connected to the peripheral circuit portion PC.

[0096] In the above embodiments, the word line WL having a gate-all-around structure may electrically shield the two channel portions CH1 and CH2 from the word lines of the vertically adjacent memory cells.

[0097] It will be apparent to those of ordinary skill in the art that the storage devices according to the various embodiments of the present disclosure as described above are not limited to the embodiments shown in the above embodiments and the drawings, and various changes, modifications or substitutions can be made without departing from the scope of the present disclosure.

[0098] The above embodiments of the present invention are intended to illustrate rather than limit the present invention. Various alternatives and equivalent schemes are possible. The present invention is not limited by the embodiments described herein. The present invention is also not limited to any specific type of storage device. Other additions, deletions or modifications that are apparent in view of the present disclosure are intended to fall within the scope of the appended claims.

Claims

1. A memory cell, comprising: A substrate; A bit line vertically oriented along a first direction starting from the substrate; A nanosheet transistor including at least one nanosheet horizontally oriented along a second direction perpendicular to the first direction starting from the bit line; And A capacitor horizontally oriented along the second direction starting from the nanosheet transistor; Wherein, the nanosheet transistor includes a pair of nanosheets spaced apart from each other along the first direction and horizontally oriented along the second direction starting from the bit line.

2. The memory cell according to claim 1, wherein, The at least one nanosheet includes a single-crystal semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor, or a metal compound.

3. The memory cell according to claim 1, wherein, The at least one nanosheet includes a polysilicon nanosheet, a single-crystalline silicon nanosheet, or indium gallium zinc oxide (IGZO).

4. The memory cell according to claim 1, wherein, The at least one nanosheet includes: A first nanosheet; and A second nanosheet spaced apart from the first nanosheet along the first direction, and wherein the horizontal length of the first nanosheet along the second direction is equal to the horizontal length of the second nanosheet along the second direction.

5. The memory cell according to claim 1, wherein, The nanosheet transistor includes a pair of polysilicon nanosheets spaced apart from each other along the first direction and horizontally oriented along the second direction starting from the bit line.

6. The memory cell according to claim 1, wherein, The nanosheet transistor includes: At least a pair of nanosheets spaced apart from each other along the first direction and horizontally oriented along the second direction starting from the bit line; A word line extending along a third direction perpendicular to the first direction and the second direction and surrounding the at least a pair of nanosheets; and A gate insulating layer located between the at least a pair of nanosheets and the word line and surrounding the at least a pair of nanosheets.

7. The memory cell according to claim 6, wherein, The word line includes: A surrounding portion surrounding the at least one nanosheet; and An extending portion extending along the third direction starting from the surrounding portion; and Wherein, the extending portion does not surround the at least one nanosheet.

8. The memory cell according to claim 6, wherein, The word line includes a metal-based material.

9. The memory cell according to claim 1, wherein, The bit line includes a metal-based material.

10. The memory cell according to claim 1, wherein, The capacitor includes: A cylindrical storage node connected to one end of the nanosheet transistor and horizontally oriented along the second direction; A dielectric layer on the cylindrical storage node; and A plate node on the dielectric layer.

11. The memory cell according to claim 1, further comprising: A first doped portion horizontally extending from a first side of the at least one nanosheet; And A second doped portion horizontally extending from a second side of the at least one nanosheet and connected to the capacitor.

12. A memory cell, comprising: A substrate; A bit line vertically oriented along a first direction starting from the substrate; A first cylinder horizontally oriented along a second direction perpendicular to the first direction starting from the bit line; A second cylinder horizontally spaced apart from the first cylinder; At least two nanosheets horizontally oriented between the first cylinder and the second cylinder; A word line buried in the first cylinder and the second cylinder and surrounding the at least two nanosheets; And A capacitor that is horizontally oriented along the second direction starting from the second cylinder.

13. The memory cell according to claim 12, wherein, The word line includes: A surrounding portion that surrounds the at least two nanosheets; and An extending portion that extends from the surrounding portion along a third direction perpendicular to the first direction and the second direction, and wherein the extending portion does not surround the at least two nanosheets.

14. The memory cell according to claim 13, wherein, The word line includes: A first buried portion that extends from the surrounding portion along the second direction into the interior of the first cylinder; and A second buried portion that extends from the surrounding portion along the second direction into the interior of the second cylinder, and wherein the first buried portion and the second buried portion do not surround the at least two nanosheets.

15. The memory cell according to claim 12, wherein, The word line includes a metal-based material.

16. The memory cell according to claim 12, wherein, The at least two nanosheets include a single-crystal semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor, or a metal compound.

17. The memory cell according to claim 12, wherein, The at least two nanosheets include polysilicon nanosheets.

18. The memory cell according to claim 12, wherein, The at least two nanosheets include: A first nanosheet that is horizontally oriented along the second direction; and A second nanosheet that is spaced apart from the first nanosheet along the first direction and is horizontally oriented along the second direction, and wherein the first nanosheet and the second nanosheet each have a first length along the second direction and a second length along a third direction perpendicular to the first direction and the second direction, and the first length is greater than the second length.

19. The memory cell according to claim 12, wherein, At least one of the first cylinder and the second cylinder includes: An open first side surface that is connected to the at least two nanosheets; A closed second side surface that faces the first side surface; and A plurality of outer walls that define an internal gap between the first side surface and the second side surface.

20. The memory cell according to claim 12, wherein, The first cylinder and the second cylinder include source / drain of a transistor.

21. The memory cell according to claim 12, wherein, The substrate includes a peripheral circuit portion, and wherein the bit line extends upward or downward from the peripheral circuit portion.

22. The memory cell according to claim 12, wherein, The at least two nanosheets are vertically arranged along the first direction.

23. A memory cell, comprising: A substrate; A bit line that is vertically oriented along a first direction starting from the substrate; At least two nanosheets that are horizontally oriented along a second direction perpendicular to the first direction starting from the bit line; A word line that includes a surrounding portion surrounding the at least two nanosheets and a first buried portion and a second buried portion that extend from the surrounding portion along the second direction; A first doped portion that is horizontally oriented starting from a first side of the nanosheet, is connected to the bit line, and surrounds the first buried portion; A second doped portion that is horizontally oriented starting from a second side of the nanosheet and surrounds the second buried portion; And A capacitor that is horizontally oriented along the second direction starting from the second doped portion.

24. The memory cell according to claim 23, wherein, At least one of the first doped portion and the second doped portion has a cylindrical shape.

25. The memory cell according to claim 23, wherein, The first doped portion has a cylindrical shape in which the first buried portion is buried, and the second doped portion has an annular shape surrounding an outer wall of the second buried portion.

26. The memory cell according to claim 23, wherein, The first doped portion has an annular shape surrounding the outer wall of the first buried portion, and the second doped portion has a cylindrical shape in which the second buried portion is buried.

27. The memory cell according to claim 23, wherein, The first doped portion has a cylindrical shape in which the first buried portion is buried, and the second doped portion has a cylindrical shape in which the second buried portion is buried.

28. The memory cell according to claim 23, wherein, The at least two nanosheets include a single-crystalline semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor, or a metal compound.

29. A memory device, comprising: a substrate including a peripheral circuit portion; and a memory cell array including a plurality of memory cells vertically arranged in a first direction from the peripheral circuit portion, wherein each of the plurality of memory cells includes: a bit line vertically oriented in the first direction; a nanosheet transistor including at least two nanosheets horizontally oriented in a second direction perpendicular to the first direction from the bit line; and a capacitor horizontally oriented in the second direction from the nanosheet transistor.

30. The memory device according to claim 29, wherein, The nanosheet transistor includes: two nanosheets spaced apart from each other in the first direction and horizontally oriented in the second direction from the bit line; a first cylindrical source / drain connected to a first side of the two nanosheets; a second cylindrical source / drain connected to a second side of the two nanosheets; a word line buried in the first cylindrical source / drain and the second cylindrical source / drain and surrounding the at least two nanosheets; and a gate insulating layer located between the two nanosheets and the word line and surrounding the two nanosheets.

31. The storage device according to claim 30, wherein, The word line includes: a surrounding portion surrounding the two nanosheets; an extending portion extending from the surrounding portion in a third direction perpendicular to the first direction and the second direction; and a buried portion extending from the surrounding portion in the second direction into the respective interiors of the first cylindrical source / drain and the second cylindrical source / drain, wherein the extending portion and the buried portion do not surround the two nanosheets.

32. The memory device according to claim 29, wherein, The at least two nanosheets include a single-crystalline semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor, or a metal compound.

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