Flash memory and method of making the same

Abstract

The application provides a flash memory and a preparation method thereof, and belongs to the technical field of flash memories. The flash memory comprises a substrate, a source region at the bottom of a groove on the substrate, a source line layer in the groove and extending upwards, a metal floating gate structure comprising a polysilicon layer and two metal floating gate layers, the two metal floating gate layers being located in the groove and on both sides of the source line layer respectively, the height of the metal floating gate layer being greater than the height of the source line layer, and the polysilicon layer wrapping at least part of the outer surface of the part of the metal floating gate layer which is higher than the source line layer, and two word line layers located on the outer sides of the metal floating gate respectively. The metal floating gate layer can greatly improve the erasing and writing efficiency, and the polysilicon layer wrapped on at least part of the outer surface of the part of the metal floating gate layer which is higher than the source line layer can reduce the work function and the potential barrier of the whole metal floating gate structure, so that the erasing and writing voltage is lower, and the erasing and writing speed is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, in particular to a flash memory and a preparation method thereof. BACKGROUND

[0002] With the development of microelectronics, flash memory needs to provide higher speed, lower power consumption and higher integration. For the traditional polysilicon floating gate memory, the thickness of the polysilicon floating gate is reduced synchronously with the reduction of the device feature size. When the number of incident electrons with high energy increases, a large number of high-energy incident electrons will cause damage to the blocking oxide layer, resulting in more defects and affecting the reliability of the device. In order to overcome this problem, a scheme of replacing polysilicon with metal as the floating gate is proposed. The new metal floating gate structure uses a metal floating gate to replace the polysilicon floating gate, reducing the size of the floating gate. The metal floating gate uses horizontal electric field for write operation and uses the voltage-free coupling of the metal at the tip of the floating gate for erase operation. However, the power of the metal material is high, the potential barrier is large, and this will cause the problem of high erase and write voltage of the flash memory. SUMMARY

[0003] The purpose of the present application is to provide a flash memory and a preparation method thereof, which solves the problem of high erase and write voltage of the flash memory caused by the high power and large potential barrier of the metal floating gate in the metal floating gate flash memory.

[0004] In order to achieve the above purpose, the present application provides a flash memory, comprising:

[0005] a substrate, the substrate having a trench and a source region at the bottom of the trench;

[0006] a source line layer located in the trench and extending upward;

[0007] a metal floating gate structure comprising a polysilicon layer and two metal floating gate layers, both of the metal floating gate layers being located in the trench and on both sides of the source line layer respectively, and the height of the metal floating gate layer being greater than the height of the source line layer, and the polysilicon layer wrapping at least part of the outer surface of the part of the metal floating gate layer higher than the source line layer;

[0008] two word line layers located on the outside of one of the metal floating gates respectively.

[0009] Optionally, the outer sidewall of the part of the metal floating gate layer higher than the source line layer is wrapped with polysilicon.

[0010] Optionally, the depth of the trench is

[0011] Optionally, the thickness of the metal floating gate layer is and / or the material of the metal floating gate layer is titanium nitride.

[0012] Optionally, the thickness of the polysilicon layer is 10-100nm.

[0013] The application further provides a preparation method of the flash memory, comprising:

[0014] providing a substrate with a trench and a source region at the bottom of the trench;

[0015] forming a source line layer and a metal floating gate structure in the trench, the source line layer being in the trench and extending upward, the metal floating gate structure comprising a polysilicon layer and two metal floating gate layers, both of the metal floating gate layers being in the trench and located at both sides of the source line layer respectively, and the height of the metal floating gate layers being greater than that of the source line layer, and the polysilicon layer wrapping at least part of the outer surface of the part of the metal floating gate layers higher than the source line layer;

[0016] forming two word line layers on the substrate, both of the word line layers being located outside one of the metal floating gates respectively.

[0017] Optionally, before forming the source line layer and the metal floating gate structure, the method further comprises:

[0018] forming a word line polysilicon layer and a mask layer on the substrate, and etching the mask layer and the word line polysilicon layer to form a first opening penetrating through;

[0019] forming a side wall on the sidewall of the first opening;

[0020] using the side wall as a mask, etching the substrate in the first opening to a partial depth to form the trench;

[0021] performing ion implantation on the substrate at the bottom of the trench to form the source region.

[0022] Optionally, the step of forming the source line layer and the metal floating gate structure comprises:

[0023] forming the metal floating gate layer in the first opening, the metal floating gate layer covering the side wall;

[0024] filling the source line layer in a partial depth of the first opening;

[0025] filling a first dielectric layer in the remaining depth of the first opening, and etching to remove part of the height of the first dielectric layer and the side wall to expose at least part of the outer surface of the part of the metal floating gate layer higher than the source line layer;

[0026] forming the polysilicon layer on at least part of the outer surface of the part of the metal floating gate layer higher than the source line layer.

[0027] Optionally, the step of forming the polysilicon layer on at least part of the outer surface of the portion of the metal floating gate layer higher than the source line layer comprises:

[0028] forming the polysilicon material layer and a second dielectric layer on the substrate in sequence;

[0029] etching to remove the mask layer, the sidewall, the first dielectric layer, and the polysilicon material layer and the second dielectric layer on the top of the metal floating gate layer, the polysilicon material layer remaining on the outer sidewall of the metal floating gate layer constitutes the polysilicon layer.

[0030] Optionally, after forming the source line layer and the metal floating gate structure, further comprising:

[0031] forming a third dielectric layer and an erase gate layer on the substrate in sequence;

[0032] etching to remove the third dielectric layer and the erase gate layer directly above the mask layer, forming a second opening;

[0033] removing the mask layer;

[0034] etching the word line polysilicon layer downward along the second opening, the remaining word line polysilicon layer forming the word line layer.

[0035] The present application provides a flash memory and a preparation method thereof, comprising: a substrate, the substrate having a trench and a source region at the bottom of the trench; a source line layer, located in the trench and extending upward; a metal floating gate structure, comprising a polysilicon layer and two metal floating gate layers, both of the metal floating gate layers being located in the trench and on both sides of the source line layer respectively, and the height of the metal floating gate layer being greater than the height of the source line layer, and the polysilicon layer wrapping at least part of the outer surface of the portion of the metal floating gate layer higher than the source line layer; and two word line layers, located on the outer side of one of the metal floating gate layers respectively. The metal floating gate layer in the present application can greatly improve the erase and write efficiency, and at the same time, the polysilicon layer is wrapped on at least part of the outer surface of the portion of the metal floating gate layer higher than the source line layer. Since the work function of the polysilicon layer is low, the work function and the potential barrier of the metal floating gate structure as a whole can be reduced. Compared with the flash memory device with pure metal floating gate, the flash memory and the preparation method thereof provided by the present application can lower the erase and write voltage, and thus improve the erase and write speed. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 a flow chart of a preparation method of a flash memory provided by an embodiment of the present application;

[0037] Figures 2 to 12A corresponding structure diagram corresponding to the steps of a flash memory preparation method provided by the embodiment of the present application is shown in the following figure;

[0038] Figure 13 A barrier curve diagram of a flash memory provided by the embodiment of the present application is shown in the following figure;

[0039] Figure 14 An erase voltage curve diagram of a flash memory provided by the embodiment of the present application is shown in the following figure;

[0040] In the following, the specific embodiments of the present application will be described in more detail with reference to the accompanying drawings. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application.

[0041] 100-substrate; 102-first oxide layer; 104-word line polysilicon layer; 106-second oxide layer; 108-mask layer; 110-first side wall; 112-second side wall; 113-first opening; 114-third oxide layer; 116-metal floating gate layer; 118-third side wall; 200-source region; 202-source line layer; 204-first dielectric layer; 206-polysilicon material layer; 208-second dielectric layer; 209-polysilicon layer; 210-third dielectric layer; 212-erase gate layer; 214-word line layer. DETAILED DESCRIPTION

[0042] The specific embodiments of the present application will be described in more detail with reference to the accompanying drawings. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application.

[0043] In the following, the term "first" "second" and the like are used to distinguish between similar elements, and are not necessarily used to describe a particular order or time sequence. It should be understood that these terms used in this way can be replaced under appropriate circumstances. Similarly, if the method described herein includes a series of steps, and the steps presented herein are not necessarily the only order in which these steps can be performed, and some of the steps described can be omitted and / or other steps not described in the text can be added to the method.

[0044] Figure 1 A flow chart of a flash memory preparation method provided by the embodiment is shown in the following figure, Figure 1 The present application provides a flash memory preparation method, which comprises:

[0045] Step S1: providing a substrate, the substrate having a trench and a source region at the bottom of the trench;

[0046] Step S2: A source line layer and a metal floating gate structure are formed in the trench. The source line layer is located in the trench and extends upward. The metal floating gate structure includes a polysilicon layer and two metal floating gate layers. The two metal floating gate layers are located in the trench and are respectively located on both sides of the source line layer. The height of the metal floating gate layer is greater than the height of the source line layer. The polysilicon layer covers at least a portion of the outer surface of the portion of the metal floating gate layer that is higher than the source line layer.

[0047] Step S3: Two word line layers are formed on the substrate, with each word line layer located outside one of the metal floating gates.

[0048] Figures 2 to 12 This is a schematic diagram of the corresponding steps in the flash memory fabrication method provided in this embodiment. The following is a description of the structure. Figures 2 to 12 A more detailed description of a flash memory fabrication method provided in this embodiment is given, wherein a preferred embodiment of the invention is illustrated.

[0049] like Figure 2 As shown, a substrate 100 is provided, and a first oxide layer 102, a word line polysilicon layer 104, a second oxide layer 106 and a mask layer 108 are sequentially stacked on the substrate 100, wherein the material of the mask layer 108 is silicon nitride.

[0050] like Figure 3 As shown, the mask layer 108 and the second oxide layer 106 are etched until the word line polysilicon layer 104 is exposed, forming a first sidewall 110, which covers the sidewalls of the mask layer 108 and the second oxide layer 106.

[0051] In other alternative embodiments, after exposing the word line polysilicon layer 104, a portion of the word line polysilicon layer 104 can be etched to form a groove within the word line polysilicon layer 104, with the first sidewall 110 extending to cover the sidewall of the groove. It should be noted that, to avoid lateral drilling of the sidewall of the word line polysilicon layer 104 during etching, the depth of the groove should be controlled according to the actual situation.

[0052] like Figure 4 As shown, the word line polysilicon layer 104 and the first oxide layer 102 are etched using the first sidewall 110 as a mask until the substrate 100 is exposed. A through first opening 113 is formed in the mask layer 108, the second oxide layer 106, the word line polysilicon layer 104 and the first oxide layer 102, and a second sidewall 112 is formed. The second sidewall 112 covers the sidewalls of the word line polysilicon layer 104 and the first oxide layer 102. In this embodiment, the second sidewall 112 extends to cover a portion of the first sidewall 110.

[0053] The thickness of the second sidewall 112 is less than the thickness of the first sidewall 110, and the slope of the first sidewall 110 is kept as consistent as possible with the slope of the second sidewall 112 to ensure that the metal floating grid layer 116 formed in subsequent steps is more uniform.

[0054] In other alternative embodiments, the mask layer 108, the second oxide layer 106, the word line polysilicon layer 104 and the first oxide layer 102 can be etched directly in one step to form a through opening, and a sidewall is formed on the sidewall inside the opening.

[0055] like Figure 5 As shown, the substrate 100 is etched using the second sidewall 112 and the first sidewall 110 as masks to form trenches, the depth of which is...

[0056] Furthermore, an ion implantation process is performed on the substrate 100 at the bottom of the trench to form a source region 200 within the substrate 100.

[0057] A third oxide layer 114 is formed within the trench, the third oxide layer 114 covering the inner wall of the trench, and the thickness of the third oxide layer 114 is less than [missing information].

[0058] A metal floating gate layer 116 is formed within the first opening, covering the first sidewall 110 and the second sidewall 112, and extending to cover the sidewall of the third oxide layer 114. The metal floating gate layer 116 is made of a metal such as titanium nitride, and its thickness is [not specified]. Using metal as the floating gate of a flash memory device can reduce the feature size of the device and achieve higher integration.

[0059] A third sidewall 118 is formed on the metal floating grid layer 116, and the first sidewall 110, the second sidewall 112, the third sidewall 118 and the third oxide layer 114 together enclose the metal floating grid layer 116.

[0060] like Figure 6 As shown, using the third sidewall 118 as a mask, the third oxide layer 114 inside the first opening 113 is removed, exposing the source region 200.

[0061] Furthermore, a source line layer 202 is formed within the first opening 113. The source line layer 202 is made of polysilicon and covers the source region 200 and the third sidewall 118. After the source line layer 202 is formed, it is etched back to ensure that the source line layer 202 only fills a portion of the depth of the first opening 113, and the height of the source line layer 202 is lower than the height of the metal floating gate layer 116, which facilitates the formation of a composite structure at the tip of the metal floating gate layer 116 in subsequent processes.

[0062] like Figure 7 As shown, a first dielectric layer 204 is formed on the source line layer 202. The first dielectric layer 204 fills the remaining depth of the first opening 113 and extends to cover the mask layer 108 and the first sidewall 110. The first dielectric layer 204 is subjected to a chemical mechanical polishing process to make the surface of the first dielectric layer 204 flat, which facilitates the next etching process.

[0063] like Figure 8 As shown, the first dielectric layer 204 on the mask layer 108 is removed, and a portion of the first dielectric layer 204 within the first sidewall 110, the first opening 113, and a portion of the third sidewall 118 are removed, so that at least a portion of the outer surface of the metal floating gate layer 116 above the source line layer 202 is exposed.

[0064] In this embodiment, only a portion of the first sidewall 110, a portion of the third sidewall 118, and a portion of the first dielectric layer 204 are removed. In other alternative embodiments, the first sidewall 110, the third sidewall 118, and the first dielectric layer 204 can be etched further according to actual conditions and device performance requirements until the first sidewall 110 is completely removed. The area of ​​the exposed outer surface of the metal floating gate layer 116 can be adjusted by adjusting the etching degree of the first sidewall 110, the third sidewall 118, and the first dielectric layer 204.

[0065] like Figure 9 As shown, a polysilicon material layer 206 is formed conformally on the substrate 100 using a furnace tube oxidation process. The polysilicon material layer 206 covers the mask layer 108, the remaining first sidewall 110, the remaining first dielectric layer 204, the remaining third sidewall 118, and the exposed metal floating gate layer 116. The thickness of the polysilicon material layer 206 is [missing information].

[0066] Furthermore, a second dielectric layer 208 is formed on the polycrystalline silicon material layer 206 by atomic layer deposition. The second dielectric layer 208 covers the polycrystalline silicon material layer 206, and the thickness of the second dielectric layer 208 is [missing information].

[0067] As shown in Figure 10 , etching to remove the mask layer 108, the first sidewall 110, the third sidewall 118, the first dielectric layer 204, and the polysilicon material layer 206 on top of the metal floating gate layer 116, the polysilicon material layer 206 remaining on the outer sidewall of the metal floating gate layer 116 forms the polysilicon layer 209.

[0068] The metal floating gate layer 116 and the polysilicon layer 209 form a composite metal floating gate structure of metal and polysilicon, wherein the metal floating gate layer 116 can greatly improve the erase-write efficiency, and at the same time, the polysilicon layer 209 is wrapped on at least part of the outer surface of the part of the metal floating gate layer 116 higher than the source line layer 202. Since the work function of the polysilicon layer 209 is low, the work function and the potential barrier of the overall metal floating gate structure can be reduced, so that the erase-write voltage is lower, thereby improving the erase-write speed, and at the same time, the stability of the flash memory device is enhanced.

[0069] In other optional embodiments, the polysilicon material layer 206 on top of the metal floating gate layer 116 can be retained, so that the polysilicon layer 209 can cover the top of the metal floating gate layer 116.

[0070] Further, forming the source line layer 202 and the metal floating gate structure in the trench is conducive to reducing the feature size of the flash memory device while not changing the coupling coefficient between the source line layer 202 and the metal floating gate structure.

[0071] As shown in Figure 11 , a third dielectric layer 210 is conformally formed on the substrate, the third dielectric layer 210 fills the remaining depth of the first opening and fills the etched first sidewall 110, and finally extends to cover the mask layer 108.

[0072] Further, an erase gate layer 212 is formed on the third dielectric layer 210.

[0073] As shown in Figure 12 , etching to remove the third dielectric layer 210 and the erase gate layer 212 directly above the mask layer 108 forms a second opening; further removing the mask layer 108 by wet etching; etching the word line polysilicon layer 104 downward along the second opening, and the remaining word line polysilicon layer 104 forms the word line layer 214.

[0074] It should be understood that, while removing the third dielectric layer 210 and the erase gate layer 212 directly above the mask layer 108, the remaining polysilicon material layer 206 and the second dielectric layer 208 on the first sidewall 110 can also be removed. After removing the mask layer 108, the remaining polysilicon material layer 206 and the second dielectric layer 208 on the first sidewall 110 are removed, and etching continues downward to form the word line layer 214.

[0075] Furthermore, word line sidewalls are formed on the substrate 100, the word line sidewalls covering the word line layer 214 and the first oxide layer 102.

[0076] In the flash memory fabrication method provided in this embodiment, only a composite process is added after the metal floating gate layer and the source line layer are formed to form the polysilicon layer at the tip of the metal floating gate. Compared with the fabrication method of pure metal floating gate flash memory, this method effectively reduces the barrier of pure metal floating gate flash memory without adding an additional photomask, and the process is simple.

[0077] like Figure 12 As shown, this embodiment also provides a flash memory, including: a substrate 100 having trenches and a source region 200 located at the bottom of the trenches; a source line layer 202 located in the trenches and extending upwards; a metal floating gate structure including a polysilicon layer 209 and two metal floating gate layers 166, both of the metal floating gate layers 166 being located in the trenches and respectively located on both sides of the source line layer 202, and the height of the metal floating gate layer 166 being greater than the height of the source line layer 202, the polysilicon layer 209 covering at least a portion of the outer surface of the portion of the metal floating gate layer 166 above the source line layer 202; and two word line layers 214, respectively located outside one of the metal floating gates 166.

[0078] In other alternative embodiments, the polysilicon layer is wrapped around the outer sidewall of the metal floating gate layer above the source line layer. The polysilicon layer can effectively reduce the potential barrier of the pure metal floating gate, reduce the erase and write voltage of the flash memory, and thus improve the erase and write speed.

[0079] The material of the metal floating gate layer can be titanium nitride, and the thickness of the metal floating gate layer is [missing information]. The thickness of the polycrystalline silicon layer is Using a metal material for the floating gate layer can effectively reduce the feature size of the flash memory device, while controlling the thickness of the polysilicon layer, thereby minimizing the feature size of the device without affecting its performance.

[0080] Figure 13 The potential barrier curve of the flash memory provided in this embodiment is as follows: Figure 13As shown, the flash memory provided by the embodiment has a barrier different from that of the pure metal floating gate flash memory under the same energy condition, and the barrier of the composite metal floating gate flash memory is smaller than that of the pure metal floating gate flash memory.

[0081] Figure 14 As shown, the erase voltage curve of the flash memory provided by the embodiment is shown in the figure. Figure 14 As shown, the erase voltage of the composite metal floating gate flash memory provided by the embodiment is about 4V smaller than that of the pure metal floating gate flash memory under the same condition.

[0082] In conclusion, the flash memory provided by the embodiment comprises: a substrate 100, which has a groove and a source region 200 at the bottom of the groove; a source line layer 202, which is located in the groove and extends upward; a metal floating gate structure, which comprises a polysilicon layer 209 and two metal floating gate layers 166, both of which are located in the groove and are respectively located on both sides of the source line layer 202, and the height of the metal floating gate layer 166 is greater than that of the source line layer 202, and the polysilicon layer 209 wraps at least part of the outer surface of the part of the metal floating gate layer 166 higher than the source line layer 202; and two word line layers 214, which are respectively located on the outer side of one of the metal floating gate layers 166. The metal and polysilicon composite floating gate structure is formed by the polysilicon layer 209 at the tip of the metal floating gate layer 116. The metal floating gate layer 116 can greatly improve the erase and write efficiency, and the polysilicon layer 209 is wrapped on at least part of the outer surface of the part of the metal floating gate layer 116 higher than the source line layer 202. Since the work function of the polysilicon layer 209 is low, the work function and the barrier of the whole metal floating gate structure can be reduced, the erase and write voltage is lower, and the erase and write speed is improved.

[0083] The above is only the preferred embodiment of the present application, and does not limit the present application in any way. Any person skilled in the art can make any form of equivalent replacement, modification or change to the technical solutions and technical content disclosed by the present application without departing from the scope of the technical solutions of the present application, and such changes still belong to the protection scope of the present application.

Claims

1. A flash memory, characterized in that, include: A substrate having trenches and a source region located at the bottom of the trenches; The source line layer is located within the trench and extends upward; A metal floating gate structure includes a polysilicon layer and two metal floating gate layers. The two metal floating gate layers are located in the trench and are respectively located on both sides of the source line layer. The height of the metal floating gate layer is greater than the height of the source line layer. The polysilicon layer covers at least a portion of the outer surface of the portion of the metal floating gate layer that is higher than the source line layer. Two word line layers are located on the outside of one of the metal floating grids.

2. The flash memory as described in claim 1, characterized in that, The polysilicon layer is wrapped around the outer wall of the portion of the metal floating gate layer that is above the source line layer.

3. The flash memory as described in claim 1, characterized in that, The depth of the trench is 150 Å to 250 Å.

4. The flash memory as described in claim 1, characterized in that, The thickness of the metal floating gate layer is 20 Å to 40 Å; and / or the material of the metal floating gate layer is titanium nitride.

5. The flash memory as described in claim 1, characterized in that, The thickness of the polycrystalline silicon layer is 30 Å to 50 Å.

6. A method for fabricating a flash memory, characterized in that, include: A substrate is provided having trenches therein and a source region located at the bottom of the trenches; A source line layer and a metal floating gate structure are formed in the trench. The source line layer is located in the trench and extends upward. The metal floating gate structure includes a polysilicon layer and two metal floating gate layers. The two metal floating gate layers are located in the trench and are respectively located on both sides of the source line layer. The height of the metal floating gate layer is greater than the height of the source line layer. The polysilicon layer covers at least a portion of the outer surface of the portion of the metal floating gate layer that is higher than the source line layer. Two word line layers are formed on the substrate, each located outside one of the metal floating gates.

7. The method for fabricating a flash memory as described in claim 6, characterized in that, Before forming the source line layer and the metal floating gate structure, the method further includes: A word line polysilicon layer and a mask layer are formed on the substrate, and the mask layer and the word line polysilicon layer are etched to form a through first opening; A sidewall is formed on the sidewall of the first opening; Using the sidewall as a mask, the substrate is etched downwards along the first opening to a certain depth to form the trench; Ion implantation is performed on the substrate at the bottom of the trench to form the source region.

8. The method for fabricating a flash memory as described in claim 7, characterized in that, The steps for forming the source line layer and the metal floating gate structure include: The metal floating grid layer is formed in the first opening, and the metal floating grid layer covers the sidewall; The source line layer is formed by filling a portion of the depth of the first opening; A first dielectric layer is formed by filling the remaining depth of the first opening, and etching is performed to remove part of the height of the first dielectric layer and the sidewall, so that at least a portion of the outer surface of the portion of the metal floating gate layer above the source line layer is exposed. The polysilicon layer is formed on at least a portion of the outer surface of the portion of the metal floating gate layer that is above the source line layer.

9. The method for fabricating a flash memory as described in claim 8, characterized in that, The step of forming the polysilicon layer on at least a portion of the outer surface of the portion of the metal floating gate layer above the source line layer includes: A polycrystalline silicon material layer and a second dielectric layer are sequentially formed conformally on the substrate; Etching is used to remove the polysilicon material layer and the second dielectric layer on top of the mask layer, the sidewalls, the first dielectric layer, and the metal floating gate layer. The polysilicon material layer remaining on the outer sidewall of the metal floating gate layer constitutes the polysilicon layer.

10. The method for fabricating a flash memory as described in claim 8, characterized in that, After forming the source line layer and the metal floating gate structure, the method further includes: A third dielectric layer and an erase gate layer are sequentially formed conformally on the substrate; Etching is used to remove the third dielectric layer and the erase gate layer directly above the mask layer to form a second opening; Remove the mask layer; The word line polysilicon layer is etched downwards along the second opening, and the remaining word line polysilicon layer forms the word line layer.

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