Enhanced-mode GaN-based composite switching device and manufacturing method thereof

Abstract

The present invention discloses an enhancement-mode GaN-based composite switching device and its manufacturing method, which primarily addresses the problem of existing gallium nitride-based enhancement-mode power switching devices being limited to unidirectional conduction and unidirectional blocking. The device comprises, from bottom to top, a substrate, a transition layer, a barrier layer, and a passivation layer. The barrier layer comprises m left and right P-GaN islands on the left and right sides, respectively. The left and right islands are provided with left and right isolation trenches on their front and rear sides, respectively. A left source and a left anode are intersecting on the left side of the left island, connected to the left anode via a left electrode. A right source and a right anode are intersecting on the right side of the right island, connected to the right anode via a right electrode. The left and right islands, respectively, have left and right gates, partially covered by a passivation layer. The left and right islands are connected to their corresponding right and left anodes via a barrier layer, forming a diode-transistor composite structure. The present invention can improve device integration, achieve bidirectional conduction and bidirectional blocking characteristics, and can be used as a power switching device.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and in particular relates to an enhanced GaN-based composite switching device, which can be used as a basic device of a power electronic system. Technical Background

[0002] Green, low-carbon, energy-saving, and emission-reduction initiatives have become key to sustainable development in human society. Vigorously developing high-performance power switching transistors to significantly improve the efficiency and overall performance of power electronics systems is one of the effective ways to achieve sustainable development. Normally-off GaN-based high-electron-mobility transistors based on P-type cap layers, known as GaN-based enhancement-mode power switching transistors, leverage the wide bandgap, high saturated electron drift velocity, strong breakdown electric field, and stable chemical properties of GaN materials to achieve low on-resistance, fast switching speed, and high breakdown voltage, significantly improving the performance of power electronics systems. Therefore, high-performance GaN-based enhancement-mode power switching transistors have very broad and unique application prospects in the national economy and military fields.

[0003] The traditional gallium nitride-based enhancement-mode power switch transistor is based on a GaN-based heterojunction structure, which includes: a substrate 1, a transition layer 2, a barrier layer 3, a P-GaN gate 4, a source 5, a drain 6, and a gate metal 7; the source 5 is deposited on the left side of the upper barrier layer 3, the drain 6 is deposited on the right side of the upper barrier layer 3, the P-GaN gate 4 is deposited in the middle part of the upper barrier layer 3, and the gate metal 7 is deposited on the upper part of the P-GaN gate 4. Figure 1 shown.

[0004] However, in conventional GaN-based enhancement-mode power switching transistors, current can only flow in one direction when in the on-state, and the drain potential of the device can only be higher than the source potential when in the off-state. This means that conventional GaN-based enhancement-mode power switching transistors can only achieve unidirectional conduction and unidirectional blocking (see "Gate and barrier layer design of E-mode GaN HEMT with p-GaN gate structure," 2019 20th International Conference on Electronic Packaging Technology (ICEPT), 2019, 1-4). This fails to meet the current requirements for power switching transistors with bidirectional conduction and bidirectional blocking characteristics in many fields, such as multi-level voltage-source inverters and AC-AC converters. Therefore, it is extremely necessary and urgent to vigorously develop high-performance GaN-based enhancement-mode power switching transistors with simple process technology and bidirectional conduction and bidirectional blocking characteristics. Summary of the Invention

[0005] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and provide an enhanced GaN-based composite switch device and a method for manufacturing the same, so as to achieve bidirectional conduction and bidirectional blocking characteristics, reduce losses, simplify the manufacturing process, and improve integration.

[0006] To achieve the above-mentioned purpose, the enhanced GaN-based composite switching device of the present invention comprises, from bottom to top, a substrate 1, a transition layer 2, a barrier layer 3 and a passivation layer 8; and is characterized in that:

[0007] m left P-GaN islands 4 and m right P-GaN islands 5 are arranged in parallel at equal intervals on the left and right sides of the upper portion of the barrier layer 3, respectively. Left isolation trenches 6 are provided on the front and rear sides of each left P-GaN island 4, and right isolation trenches 7 are provided on the front and rear sides of each right P-GaN island 5. These left P-GaN islands 4 and right P-GaN islands 5 are distributed crosswise.

[0008] A left source 9 is provided on the left side of each of the m left P-GaN islands 4, and a left anode 11 is provided on the left side of each of the m right P-GaN islands 5. A left electrode 13 is provided in parallel on the left side of each left source 9 and each left anode 11. These sources and anodes are partially covered by the left electrode and are electrically connected.

[0009] The right sides of the m left P-GaN islands 4 are each provided with a right anode 12, and the right sides of the m right P-GaN islands 5 are each provided with a right source 10. A right electrode 14 is provided in parallel on the right side of each right source 10 and each right anode 12. These sources and anodes are partially covered by the right electrode and are electrically connected.

[0010] A left gate 15 is provided on the upper portion of each of the m left P-GaN islands 4, and a right gate 16 is provided on the upper portion of each of the m right P-GaN islands 5. Both sides of these left and right gates and the m left and right P-GaN islands are covered by a passivation layer 8. The left P-GaN islands 4 below the left gates 15 and their corresponding right anodes 12, as well as the right P-GaN islands 5 below the right gates 16 and their corresponding left anodes 11 are connected via a barrier layer 3, forming a composite structure of a diode and a transistor.

[0011] Furthermore, the substrate 1 is made of sapphire, silicon carbide, silicon, graphene or other materials;

[0012] Furthermore, the barrier layer 3 has a thickness a of 2 nm to 60 nm;

[0013] Furthermore, the m left P-GaN islands 4 are of the same size and thickness b, and their right edges are aligned, and the distance between two adjacent left P-GaN islands 4 is w;

[0014] Furthermore, the m right P-GaN islands 5 are of the same size and thickness b, and their left edges are aligned. The distance between two adjacent right P-GaN islands 5 is w; the horizontal distance t between the m right P-GaN islands 5 and the m left P-GaN islands 4 is ≥1μm.

[0015] Furthermore, the left isolation trenches 6 are of the same size, the lower ends of the left isolation trenches 6 are all located in the transition layer 2, and the spacing c between the lower end of the left isolation trench 6 and the interface between the barrier layer 3 and the transition layer 2 is greater than 40 nm; the right edge of each left isolation trench 6 is aligned with the right edges of the m left P-GaN islands 4, and the left edge of each left isolation trench 6 is located to the left of the right edge of the left anode 11;

[0016] Furthermore, the right isolation trenches 7 are of the same size, and their lower ends are all located in the transition layer 2. The spacing c between the lower end of each right isolation trench 7 and the interface between the barrier layer 3 and the transition layer 2 is greater than 40 nm. The left edge of each right isolation trench 7 is aligned with the left edges of the m right P-GaN islands 5, and the right edge of each right isolation trench 7 is located to the right of the left edge of the right anode 12.

[0017] Furthermore, the m left source electrodes 9 and the m right source electrodes 10 are all located on the upper portion of the barrier layer 3, and the lower ends of the m left anodes 11 and the m right anodes 12 are all located inside the barrier layer 3 or inside the transition layer 2;

[0018] Furthermore, the m left source electrodes 9 and the m left anode electrodes 11 are arranged alternately, and the right edges of these source electrodes and anode electrodes are located in the same vertical plane;

[0019] Furthermore, the m right source electrodes 10 and the m right anode electrodes 12 are arranged alternately, and the left edges of these source electrodes and anode electrodes are all located in the same vertical plane.

[0020] To achieve the above object, the method of the present invention for manufacturing an enhancement-mode GaN-based composite switching device is characterized by comprising the following steps:

[0021] A) epitaxially growing a GaN-based wide bandgap semiconductor material on a substrate 1 to form a transition layer 2;

[0022] B) epitaxially growing a GaN-based wide bandgap semiconductor material on the transition layer 2 using an epitaxial process to form a barrier layer 3 with a thickness of a;

[0023] C) Fabricating the left P-GaN island 4 and the right P-GaN island 5 on the barrier layer 3:

[0024] C1) epitaxially grow a P-type GaN semiconductor material on the barrier layer 3 using an epitaxial process to form a P-type GaN semiconductor material with a thickness of b and a doping concentration of 1×10 16 ~1×10 22 cm -3 P-type GaN layer;

[0025] C2) forming a mask on the P-GaN layer for the first time, and etching the P-GaN layer using the mask until the upper surface of the barrier layer 3 is reached, thereby forming m left P-GaN islands 4 and m right P-GaN islands 5;

[0026] D) forming a second mask on the barrier layer 3, the left P-GaN island 4, and the right P-GaN island 5, and using the mask to sequentially etch the barrier layer 3 and the transition layer 2 to form a left isolation trench 6 and a right isolation trench 7, with a spacing c between the lower end of each left isolation trench 6 and right isolation trench 7 and the interface between the barrier layer 3 and the transition layer 2 greater than 40 nm;

[0027] E) depositing a passivation layer 8 on the barrier layer 3, the left P-GaN island 4, the right P-GaN island 5, the left isolation trench 6, and the right isolation trench 7;

[0028] F) forming a left source electrode 9 and a right source electrode 10 on the barrier layer 3;

[0029] F1) Making a mask on the passivation layer 8 for the third time, and using the mask to etch the passivation layer 8 on the left and right sides until the upper surface of the barrier layer 3 is reached, forming m source half trenches on the left and m source half trenches on the right;

[0030] F2) Using the mask made for the third time, a multilayer metal is deposited in the source half trenches using a metal deposition process, and then a rapid thermal annealing is performed in an N2 atmosphere for 30 seconds to form m left source electrodes 9 and m right source electrodes 10;

[0031] G) Fabricate the left anode 11 and the right anode 12 on and inside the barrier layer 3:

[0032] G1) forming a mask for the fourth time on the barrier layer 3, the passivation layer 8, the left source electrode 9, and the right source electrode 10, and using the mask to etch the passivation layer 8 on the left and right sides until the upper surface of the barrier layer 3 is reached, forming m anode half-slots on the left side and m anode half-slots on the right side, these anode half-slots being arranged alternately with the source half-slots in F1);

[0033] G2) forming a mask for the fifth time on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the m left anode half grooves, and the m right anode half grooves, and etching the left and right anode half grooves again using the mask to a depth of >0 μm, thereby forming m left anode grooves and m right anode grooves;

[0034] G3) using the mask produced the fifth time again, depositing multiple layers of metal in the anode grooves using a metal deposition process to form Schottky contacts, thereby completing the production of m left anodes 11 and m right anodes 12;

[0035] H) forming a mask for the sixth time on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11, and the right anode 12, and using the mask to deposit metal on the barrier layer 3, the left source electrode 9, the right source electrode 10, the left anode 11, and the right anode 12 using a metal deposition process to form a left electrode 13 and a right electrode 14, wherein the left electrode 13 partially covers and electrically connects each left source electrode 9 and each left anode 11, and the right electrode 14 partially covers and electrically connects each right source electrode 10 and each right anode 12;

[0036] 1) forming a mask for the seventh time on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11, the right anode 12, the left electrode 13, and the right electrode 14, and using the mask to etch the passivation layer 8 on the m left P-GaN islands 4 and the m right P-GaN islands 5 until the upper surfaces of the P-GaN islands are reached, thereby forming m left gate trenches and m right gate trenches;

[0037] J) Using the seventh mask again, a metal deposition process is used to deposit multiple layers of metal in the m left and right gate grooves to form the left gate 15 and the right gate 16, respectively, completing the fabrication of the entire device.

[0038] Compared with traditional GaN-based enhancement-mode power switching devices, the device of the present invention has the following advantages:

[0039] First, in the device of the present invention, since all left anodes and right anodes are Schottky contacts, all left sources and right sources are ohmic contacts, and all left sources are electrically connected to the left anodes, and all right sources are electrically connected to the right anodes, by controlling the voltage on the left gate and the right gate, it is possible to achieve the unidirectional conduction and unidirectional blocking characteristics of the traditional gallium nitride-based enhancement-mode power switching transistor, thereby reducing the conduction loss of the device, and also achieve bidirectional conduction and bidirectional blocking characteristics.

[0040] Secondly, the device of the present invention uses a reused barrier layer active region between the left gate 15 and the right gate 16, thereby greatly saving device area and improving the integration of the switch device.

[0041] Third, the manufacturing process of the device of the present invention is compatible with the manufacturing process of traditional gallium nitride-based enhancement-mode power switching devices, so the manufacturing process is simple.

[0042] Simulation results show that the device of the present invention has good reliability and output power characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a structural diagram of a traditional GaN-based enhancement-mode power switching transistor;

[0044] Figure 2 1. It is a top view of the structure of the enhanced GaN-based composite switch device of the present invention;

[0045] Figure 3 yes Figure 2 Section along AB;

[0046] Figure 4 yes Figure 2 Cross-section along CD;

[0047] Figure 5 yes Figure 2 Section along EF;

[0048] Figure 6 Schematic diagram of the overall process of manufacturing an enhanced-mode GaN-based composite switching device according to the present invention;

[0049] Figure 7 This is a test result diagram of using the device of the present invention to perform chopping modulation on an AC signal. DETAILED DESCRIPTION

[0050] The embodiments and effects of the present invention are further described in detail below with reference to the accompanying drawings.

[0051] Reference Figure 2 、 Figure 3 、 Figure 4 and Figure 5 The enhancement-mode GaN-based composite switch device given in this example includes: a substrate 1, a transition layer 2, a barrier layer 3, m left P-GaN islands 4, m right P-GaN islands 5, a left isolation trench 6, a right isolation trench 7, a passivation layer 8, m left source electrodes 9, m right source electrodes 10, m left anodes 11, m right anodes 12, a left electrode 13, a right electrode 14, m left gates 15, and m right gates 16, where m ≥ 1.

[0052] The substrate 1 is made of sapphire, silicon carbide, silicon, graphene or other materials;

[0053] The transition layer 2 is located on the upper part of the substrate 1 and is composed of several layers of the same or different GaN-based wide bandgap semiconductor materials, with a thickness of 0.5 to 50 μm;

[0054] The barrier layer 3 is located on the upper part of the transition layer 2 and is composed of several layers of the same or different GaN-based wide bandgap semiconductor materials, with a thickness of 2nm to 60nm;

[0055] The m left P-GaN islands 4 are located on the upper left side of the barrier layer 3. Each left P-GaN island 4 has the same size, a thickness b of 5 nm to 200 nm, and a doping concentration of 1×10 16 ~1×10 22 cm -3, and the right edges are aligned, and the spacing between two adjacent left P-GaN islands 4 is w; left isolation trenches 6 are provided on the front and rear sides of each left P-GaN island 4, and these left isolation trenches are of the same size, and the lower ends are all located in the transition layer 2. The spacing c between the lower end of each left isolation trench and the interface between the barrier layer 3 and the transition layer 2 is greater than 40nm, and the right edge of each left isolation trench 6 is aligned with the right edges of m left P-GaN islands 4;

[0056] The m right P-GaN islands 5 are located on the upper right side of the barrier layer 3. Each right P-GaN island 5 has the same size, a thickness b of 5 nm to 200 nm, and a doping concentration of 1×10 16 ~1×10 22 cm -3 , and the left edges are aligned, and the spacing between two adjacent right P-GaN islands 5 is w; right isolation trenches 7 are provided on the front and rear sides of each right P-GaN island 5, and these right isolation trenches are of the same size, and the lower ends are all located in the transition layer 2. The spacing c between the lower end of each right isolation trench and the interface between the barrier layer 3 and the transition layer 2 is greater than 40nm, and the left edge of each right isolation trench 7 is aligned with the left edges of the m right P-GaN islands 5; the horizontal spacing t between the m right P-GaN islands 5 and the m left P-GaN islands 4 is greater than or equal to 1μm;

[0057] The passivation layer 8 is located on the upper portion of the barrier layer 3 and conformally covers the left P-GaN island 4, the right P-GaN island 5, the left isolation trenches 6 and the right isolation trenches 7;

[0058] The m left source electrodes 9 are located on the left side of the left P-GaN island 4, and the m right source electrodes 10 are located on the right side of the right P-GaN island 5. The left source electrodes 9 and the right source electrodes 10 are equal in size, and the spacing between two adjacent left source electrodes 9 is equal to the spacing between two adjacent right source electrodes 10. These source electrodes are all located on the upper portion of the barrier layer 3 and form ohmic contact with the barrier layer 3.

[0059] The m right anodes 12 are located on the right side of the left P-GaN island 4, and the m left anodes 11 are located on the left side of the right P-GaN island 5. The left anodes 11 and the right anodes 12 are equal in size, and the spacing between two adjacent left anodes 11 is equal to the spacing between two adjacent right anodes 12. The lower ends of these anodes are all located inside the barrier layer 3 or the transition layer 2, and form Schottky contacts with the barrier layer 3 and the transition layer 2. The right edge of each left anode 11 is located to the right of the left edge of the left isolation trench 6; the left edge of each right anode 12 is located to the left of the right edge of the right isolation trench 7.

[0060] The m left source electrodes 9 and the m left anode electrodes 11 are arranged alternately, and the right edges of these source electrodes and anode electrodes are located in the same vertical plane;

[0061] The m right source electrodes 10 and the m right anode electrodes 12 are arranged alternately, and the left edges of the source electrodes and the anode electrodes are all located in the same vertical plane;

[0062] The left electrode 13 is located on the left side of each left source 9 and each left anode 11, and partially covers and electrically connects these sources and anodes;

[0063] The right electrode 14 is located on the right side of each right source 10 and each right anode 12, and partially covers and electrically connects these sources and anodes;

[0064] The m left gates 15 are all located on the upper portion of the left P-GaN island 4, and both sides of each left gate 15 are covered by the passivation layer 8;

[0065] The m right gates 16 are all located on the upper portion of the right P-GaN island 5, and both sides of each right gate 16 are covered by the passivation layer 8;

[0066] The left P-GaN islands 4 at the bottom of the m left gates 15 and their corresponding right anodes 12, as well as the right P-GaN islands 5 at the bottom of the m right gates 16 and their corresponding left anodes 11 are connected via the barrier layer 3, forming a composite structure of a diode and a transistor.

[0067] Reference Figure 6 The following three embodiments are given for the enhanced GaN-based composite switching device manufactured by the present invention.

[0068] Example 1: Using a sapphire substrate, the barrier layer 3 is made with a thickness a of 2 nm, the number of the left P-GaN island 4 and the right P-GaN island 5 are both 1, and the thickness b is 5 nm, and the doping concentration is 5×10 17 cm -3 Enhanced-mode GaN-based composite switching device.

[0069] Step 1: epitaxially grow GaN material on a sapphire substrate 1 to form a transition layer 2.

[0070] 1.1) Using metal organic chemical vapor deposition (MOCVD) technology, a 30 nm thick GaN material was grown on a sapphire substrate 1. The process conditions were: temperature of 530°C, pressure of 45 Torr, hydrogen flow rate of 4500 sccm, ammonia flow rate of 4500 sccm, and gallium source flow rate of 20 μmol / min.

[0071] 1.2) Using metal organic chemical vapor deposition technology, a GaN material with a thickness of 0.97 μm was epitaxially grown on the GaN material to form an undoped transition layer 2; the process conditions were: temperature of 960°C, pressure of 45 Torr, hydrogen flow rate of 4400 sccm, ammonia flow rate of 4400 sccm, and gallium source flow rate of 120 μmol / min.

[0072] Step 2. Deposit undoped Al on the undoped GaN transition layer 2 0.4 Ga 0.6 N forms the barrier layer 3.

[0073] Metal organic chemical vapor deposition technology is used to deposit undoped Al with a thickness of 2 nm and an aluminum content of 0.4 on the GaN transition layer 2. 0.4 Ga 0.6 N barrier layer 3; its process conditions are: temperature of 980°C, pressure of 45 Torr, hydrogen flow rate of 4400 sccm, ammonia flow rate of 4400 sccm, gallium source flow rate of 35 μmol / min, and aluminum source flow rate of 7 μmol / min.

[0074] Step 3. Fabricate the left P-GaN island 4 and the right P-GaN island 5 on the barrier layer 3 .

[0075] 3.1) Using molecular beam epitaxy technology, an epitaxial layer with a thickness b of 5 nm and a doping concentration of 5×10 17 cm -3 P-type GaN semiconductor material is used to form a P-type GaN layer; the process conditions of molecular beam epitaxy are: vacuum degree is less than or equal to 1.0×10 -10 mbar, RF power of 400W, N2 as the reactant, and high-purity Ga source;

[0076] 3.2) A mask is first formed on the P-GaN layer formed in 3.1), and the P-GaN layer is etched using the mask until the upper surface of the barrier layer 3 is reached, forming a left P-GaN island 4 and a right P-GaN island 5, and the spacing t between the left P-GaN island 4 and the right P-GaN island 5 is 1 μm; the etching process conditions are: Cl2 flow rate of 15 sccm, pressure of 10 mTorr, and power of 100 W.

[0077] Step 4. Make the left isolation groove 6 and the right isolation groove 7.

[0078] A second mask is formed on the barrier layer 3, the left P-GaN island 4, and the right P-GaN island 5. The barrier layer 3 and the transition layer 2 are sequentially etched using the mask to complete the formation of each left isolation trench 6 and each right isolation trench 7. The lower end of each left isolation trench 6 and each right isolation trench 7 is located in the transition layer 2, and the distance c between the barrier layer 3 and the transition layer 2 is greater than 40nm. The etching process conditions are: Cl2 flow rate of 18sccm, pressure of 14mTorr, and power of 120W.

[0079] Step 5: Forming a passivation layer 8.

[0080] A passivation layer 8 with a thickness of 350 nm is deposited on the barrier layer 3, the left P-GaN island 4, the right P-GaN island 5, the left isolation trench 6 and the right isolation trench 7 using plasma enhanced chemical vapor deposition technology. The process conditions used for depositing the passivation layer 8 are: N2O flow rate of 840 sccm, SiH4 flow rate of 300 sccm, temperature of 250°C, RF power of 10 W, and pressure of 2000 mT.

[0081] Step 6. Fabricate a left source electrode 9 and a right source electrode 10 on the barrier layer 3 .

[0082] 6.1) A third mask is formed on the passivation layer 8. The mask is used to etch the left and right passivation layers 11 until the upper surface of the barrier layer 3 is reached, forming a left source half trench and a right source half trench. The etching process conditions used are: Cl₂ flow rate of 15 sccm, pressure of 10 mTorr, and power of 100 W.

[0083] 6.2) Using the third mask, deposit multiple layers of metal in the two source half trenches on the left and right sides. The deposited metals use a combination of Ti / Al / Au, i.e., Ti, Al, and Au from bottom to top, with thicknesses of 0.012 μm / 0.053 μm / 0.035 μm, respectively. Rapid thermal annealing is then performed to form the left source 9 and the right source 10. The process conditions used for the metal deposition are: vacuum degree of 1.7×10 -3 Pa, power is 400W, evaporation rate is The process conditions adopted for rapid thermal annealing are: temperature of 850°C and time of 35s.

[0084] Step 7. Fabricate the left anode 11 and the right anode 12 on and inside the barrier layer 3 .

[0085] 7.1) A fourth mask is formed on the barrier layer 3, passivation layer 8, left source electrode 9, and right source electrode 10. The mask is used to etch the passivation layer 10 on both sides until the upper surface of the barrier layer 3 is reached, forming one anode half-slot on the left side and one anode half-slot on the right side. These anode half-slots alternate with the source half-slots described in 6.1). The etching process conditions used are: Cl2 flow rate of 15 sccm, pressure of 10 mTorr, and power of 100 W.

[0086] 7.2) A fifth mask was formed over the barrier layer 3, passivation layer 8, left source electrode 9, right source electrode 10, one anode half-slot on the left, and one anode half-slot on the right. The mask was used to etch the left and right anode half-slots again to a depth of 1 nm, forming one anode groove on the left and one anode groove on the right. The etching process conditions used were: Cl₂ flow rate of 20 sccm, pressure of 25 mTorr, and power of 125 W.

[0087] 7.3) The mask is used again to deposit multiple layers of metal in the two anode grooves. The deposited metal is a W / Au metal combination, i.e., the lower layer is W and the upper layer is Au, with thicknesses of 0.025 μm / 0.10 μm, respectively. Schottky contacts are formed between the deposited metal and the barrier layer 3, completing the fabrication of the left anode 11 and the right anode 12. The process conditions for metal deposition are: vacuum degree of 1.7×10 -3 Pa, power is 380W, evaporation rate is

[0088] Step 8. Fabricate the left electrode 13 and the right electrode 14.

[0089] A sixth mask is made on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11, and the right anode 12. The mask is used to deposit metal to cover the barrier layer 3, the left source electrode 9, the right source electrode 10, the left anode 11, and the right anode 12, forming a left electrode 13 and a right electrode 14. The left electrode 13 electrically connects the left source electrode 9 to the left anode 11, and the right electrode 14 electrically connects the right source electrode 10 to the right anode 12. The deposited metal is an Al / Au combination, i.e., the lower layer is Al and the upper layer is Au, with thicknesses of 0.035 μm and 0.015 μm, respectively. The process conditions for depositing the metal are: vacuum degree of 1.6×10 -3 Pa, power is 200W, evaporation rate is

[0090] Step 9. Fabricate the left gate 15 and the right gate 16.

[0091] 9.1) A seventh mask is formed over the barrier layer 3, passivation layer 8, left source electrode 9, right source electrode 10, left anode 11, right anode 12, left electrode 13, and right electrode 14. The mask is used to etch the passivation layer 8 on the left P-GaN island 4 and the right P-GaN island 5, respectively, to the top surface of the P-GaN island, forming a gate trench. The etching process conditions used are: Cl2 flow rate of 18 sccm, pressure of 14 mTorr, and power of 120 W.

[0092] 9.2) Using the seventh mask, a metal combination of Ni / Au is deposited in the above-mentioned gate grooves, i.e., Ni is the lower layer and Au is the upper layer, forming the left gate 15 and the right gate 16 respectively. The process conditions used for metal deposition are: vacuum degree of 1.5×10 - 3 Pa, power is 300W, evaporation rate is Complete the fabrication of the entire device.

[0093] Example 2: Using silicon carbide substrate, the barrier layer 3 is made with a thickness a of 8 nm, the number of the left P-GaN island 4 and the number of the right P-GaN island 5 are both five, the thickness b is 70 nm, and the doping concentration is 1×10 16 cm -3 Enhanced-mode GaN-based composite switching device.

[0094] Step 1. Form a transition layer 2 by epitaxially growing AlN and GaN materials on a silicon carbide substrate 1 from bottom to top.

[0095] 1a) using metal organic chemical vapor deposition technology under the process conditions of temperature of 1000 ° C, pressure of 45 Torr, hydrogen flow rate of 4600 sccm, ammonia flow rate of 4600 sccm, and aluminum source flow rate of 5 μmol / min, epitaxially growing an undoped AlN material with a thickness of 100 nm on the silicon carbide substrate 1;

[0096] 1b) Using metal organic chemical vapor deposition technology under the process conditions of temperature of 1000°C, pressure of 45 Torr, hydrogen flow rate of 4600 seem, ammonia flow rate of 4600 seem, and gallium source flow rate of 120 μmol / min, a GaN material with a thickness of 4.9 μm is epitaxially grown on the AlN material to form a transition layer 2.

[0097] Step 2. Deposit undoped Al on the GaN transition layer 2 0.15 Ga 0.85 N forms the barrier layer 3.

[0098] Using metal organic chemical vapor deposition technology at a temperature of 980 ° C, a pressure of 45 Torr, a hydrogen flow rate of 4600 sccm, an ammonia flow rate of 4600 sccm, a gallium source flow rate of 37 μmol / min, and an aluminum source flow rate of 7 μmol / min, an undoped Al with a thickness of 8 nm and an aluminum content of 0.15 is deposited on the GaN transition layer 2. 0.15 Ga 0.85 N barrier layer 3.

[0099] Step 3. Fabricate a left P-GaN island 4 and a right P-GaN island 5 on the barrier layer 3 .

[0100] 3a) Using molecular beam epitaxy technology, in a vacuum degree of less than or equal to 1.0×10 -10 mbar, RF power of 420W, N2 as the reactant, and high-purity Ga source, the epitaxial thickness b on the barrier layer 3 is 70nm and the doping concentration is 1×10 16 cm -3 P-type GaN semiconductor material to form a P-type GaN layer;

[0101] 3b) A mask is formed on the P-GaN layer formed in 3a) for the first time, and the P-GaN layer is etched using the mask under process conditions of a Cl2 flow rate of 18 sccm, a pressure of 13 mTorr, and a power of 80 W, until the etching reaches the upper surface of the barrier layer 3, forming five left P-GaN islands 4 and five right P-GaN islands 5, and the spacing t between the five left P-GaN islands 4 and the five right P-GaN islands 5 is 5 μm.

[0102] Step 4. Make the left isolation groove 6 and the right isolation groove 7.

[0103] A mask is made on the barrier layer 3, the left P-GaN island 4 and the right P-GaN island 5 for the second time. Using the mask, the barrier layer 3 and the transition layer 2 are etched in sequence under the process conditions of a Cl2 flow rate of 18 sccm, a pressure of 14 mTorr and a power of 120 W to complete the production of each left isolation trench 6 and each right isolation trench 7. The lower ends of each left isolation trench 6 and each right isolation trench 7 are located in the transition layer 2, and the distance c between the barrier layer 3 and the transition layer 2 interface is greater than 40 nm.

[0104] Step 5. Plasma-enhanced chemical vapor deposition technology is used on the barrier layer 3, the left P-GaN island 4, the right P-GaN island 5, the left isolation trench 6 and the right isolation trench 7 to deposit a passivation layer 8 with a thickness of 450 nm under the process conditions of N2O flow rate of 900 sccm, SiH4 flow rate of 340 sccm, temperature of 220°C, RF power of 12 W, and pressure of 2100 mT.

[0105] Step 6. Fabricate a left source electrode 9 and a right source electrode 10 on the barrier layer 3 .

[0106] 6a) A third mask is formed on the passivation layer 8. Using this mask, the passivation layer 11 on the left and right sides is etched to the upper surface of the barrier layer 3 under process conditions of a Cl2 flow rate of 15 sccm, a pressure of 10 mTorr, and a power of 100 W, forming five source half trenches on the left and five source half trenches on the right.

[0107] 6b) Electron beam evaporation technology was used in the left and right source half trenches to obtain a vacuum of 1.7×10 -3 Pa, power is 400W, evaporation rate is Multilayer metals are deposited under process conditions, wherein the deposited metals adopt a Ti / Pd / Au metal combination, i.e., Ti, Pd and Au from bottom to top, with thicknesses of 0.015μm / 0.050μm / 0.035μm respectively, and rapid thermal annealing is performed at a temperature of 850°C for 35s to form five left source electrodes 9 and five right source electrodes 10.

[0108] Step 7. Fabricate the left anode 11 and the right anode 1 on and inside the barrier layer 3 .

[0109] 7a) A fourth mask is formed on the barrier layer 3, the passivation layer 8, the left source electrode 9, and the right source electrode 10. Using this mask, the passivation layer 10 on the left and right sides is etched to the upper surface of the barrier layer 3 under process conditions of a Cl₂ flow rate of 15 sccm, a pressure of 10 mTorr, and a power of 100 W, forming five anode half-slots on the left side and five anode half-slots on the right side. These anode half-slots are arranged alternately with the source half-slots described in 6a);

[0110] 7b) A fifth mask was formed on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the five left anode half grooves, and the five right anode half grooves. The left and right anode half grooves were etched again using the mask under the process conditions of a Cl2 flow rate of 25 sccm, a pressure of 30 mTorr, and a power of 100 W to a depth of 70 nm, forming five anode grooves on the left and five anode grooves on the right.

[0111] 7c) Using the mask again, the vacuum degree is 1.9×10 -3 Pa, power is 350W, evaporation rate is Under the process conditions, a metal Ni / Pt / Au metal combination is deposited in these ten anode grooves, that is, Ni, Pt and Au from bottom to top, with thicknesses of 0.019μm / 0.030μm / 0.031μm respectively, so that Schottky contact is formed between the deposited metal and the barrier layer 3, completing the production of five left anodes 11 and five right anodes 12.

[0112] Step 8. Make the left electrode 13 and the right electrode 14.

[0113] A mask is made for the sixth time on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11, and the right anode 12. The mask is used to form a vacuum layer at a vacuum degree of 1.6×10 -3 Pa, power is 200W, evaporation rate is Under the process conditions, metal is deposited to cover the barrier layer 3, the left source 9, the right source 10, the left anode 11, and the right anode 12 to form a left electrode 13 and a right electrode 14; wherein, the left electrode 13 electrically connects the five left source electrodes 9 with the five left anodes 11, and the right electrode 14 electrically connects the five right source electrodes 10 with the five right anodes 12; wherein the deposited metal is Ti / Au, that is, the lower layer is Ti and the upper layer is Au, and the thicknesses thereof are 0.045μm / 0.025μm respectively.

[0114] Step 9. Make the left gate 15 and the right gate 16.

[0115] 9a) forming a mask for the seventh time on the barrier layer 3, passivation layer 8, left source 9, right source 10, left anode 11, right anode 12, left electrode 13, and right electrode 14. Using the mask, the passivation layer 8 on the five left P-GaN islands 4 and the five right P-GaN islands 5 is etched to the top surfaces of the P-GaN islands using process conditions of 18 sccm Cl2 flow rate, 14 mTorr pressure, and 120 W power, thereby forming gate trenches.

[0116] 9b) The seventh mask is used again to form a vacuum of 1.5×10 -3 Pa, power is 300W, evaporation rate is Under the process conditions, a metal combination W / Au is deposited in the above-mentioned gate groove, that is, the lower layer is W and the upper layer is Au, to form five left gates 15 and five right gates 16 respectively, completing the production of the entire device.

[0117] Example 3: Using silicon substrate, the barrier layer 3 is made with a thickness a of 60 nm, the number of the left P-GaN island 4 and the number of the right P-GaN island 5 are both three, the thickness b is 200 nm, and the doping concentration is 1×10 22 cm -3 Enhanced-mode GaN-based composite switching device.

[0118] Step A: epitaxially grow AlN and GaN materials from bottom to top on the silicon substrate 1 to form a transition layer 2.

[0119] A1) setting process conditions of a temperature of 800° C., a pressure of 40 Torr, a hydrogen flow rate of 4000 sccm, an ammonia flow rate of 4000 sccm, and an aluminum source flow rate of 25 μmol / min, and using metal organic chemical vapor deposition technology to epitaxially grow an AlN material with a thickness of 400 nm on a silicon substrate 1;

[0120] A2) setting the process conditions to 980°C, 45 Torr, 4000 sccm hydrogen flow rate, 4000 sccm ammonia flow rate, and 120 μmol / min gallium source flow rate, using metal organic chemical vapor deposition technology to epitaxially grow GaN material with a thickness of 8.6 μm on the AlN material to complete the formation of transition layer 2.

[0121] Step B. Depositing undoped Al on the GaN transition layer 2 0.1 Ga 0.9 N forms the barrier layer 3.

[0122] The deposition process conditions are set to 980℃, 45Torr, 4500sccm hydrogen flow, 4500sccm ammonia flow, 36μmol / min gallium source flow, and 7μmol / min aluminum source flow. Metal organic chemical vapor deposition technology is used to deposit undoped Al with a thickness of 60nm and an aluminum content of 0.1 on the GaN transition layer 2. 0.1 Ga 0.9 N barrier layer 3.

[0123] Step C: Fabricate the left P-GaN island 4 and the right P-GaN island 5 on the barrier layer 3 .

[0124] C1) Set the molecular beam epitaxy vacuum to be less than or equal to 1.0×10 -10 mbar, RF power of 400W, N2 as the reactant, and high-purity Ga source, the molecular beam epitaxy technology was used to grow the epitaxial thickness b on the barrier layer 3 with a doping concentration of 1×10 22 cm -3 P-type GaN semiconductor material to form a P-type GaN layer;

[0125] C2) Setting the etching process conditions: Cl2 flow rate of 15 sccm, pressure of 10 mTorr, and power of 100 W. A mask is first made on the P-GaN layer formed in C1), and the P-GaN layer is etched using the mask until the upper surface of the barrier layer 3 is reached, forming three left P-GaN islands 4 and three right P-GaN islands 5, with a spacing t of 20 μm between the three left P-GaN islands 4 and the three right P-GaN islands 5.

[0126] Step D: Making the left isolation groove 6 and the right isolation groove 7.

[0127] The etching process conditions were set as follows: Cl2 flow rate of 18 sccm, pressure of 14 mTorr, and power of 120 W. A second mask was made on the barrier layer 3, the left P-GaN island 4, and the right P-GaN island 5. The barrier layer 3 and the transition layer 2 were sequentially etched using the mask to complete the formation of each left isolation trench 6 and each right isolation trench 7. The lower end of each left isolation trench 6 and each right isolation trench 7 was located in the transition layer 2, and the spacing c between the barrier layer 3 and the transition layer 2 interface was greater than 40 nm.

[0128] Step E: forming a passivation layer 8 .

[0129] Under process conditions of 840 sccm N2O flow rate, 300 sccm SiH4 flow rate, 250°C temperature, 10 W RF power, and 2000 mT pressure, a 200 nm thick passivation layer 8 was deposited on the barrier layer 3, the left P-GaN island 4, the right P-GaN island 5, the left isolation trench 6, and the right isolation trench 7 using plasma-enhanced chemical vapor deposition technology.

[0130] Step F: forming a left source electrode 9 and a right source electrode 10 on the barrier layer 3 .

[0131] F1) Setting the etching process conditions: Cl2 flow rate of 15 sccm, pressure of 10 mTorr, and power of 100 W. A third mask is formed on the passivation layer 8. The mask is used to etch the passivation layer 11 on the left and right sides until the upper surface of the barrier layer 3 is reached, forming three source half trenches on the left and three source half trenches on the right.

[0132] F2) Set the vacuum degree to 1.7×10 -3 Pa, power is 400W, evaporation rate is Under the process conditions, multiple layers of metal are deposited in the source half trenches on the left and right sides, wherein the deposited metal adopts a Ta / Pt / Au metal combination, that is, Ta, Pt and Au from bottom to top, with thicknesses of 0.012μm / 0.051μm / 0.037μm respectively, and rapid thermal annealing is performed at a temperature of 870℃ for 30s to form three left source electrodes 9 and three right source electrodes 10.

[0133] Step G: Fabricate the left anode 11 and the right anode 12 on and inside the barrier layer 3 .

[0134] G1) setting etching process conditions of a Cl2 flow rate of 16 sccm, a pressure of 12 mTorr, and a power of 120 W, forming a mask for the fourth time on the barrier layer 3, the passivation layer 8, the left source electrode 9, and the right source electrode 10, and using the mask to etch the passivation layer 10 on the left and right sides until the upper surface of the barrier layer 3 is reached, forming three anode half-slots on the left and three anode half-slots on the right. These anode half-slots are arranged alternately with the source half-slots in F1);

[0135] G2) Setting etching process conditions: Cl2 flow rate of 20 sccm, pressure of 25 mTorr, and power of 125 W, forming a mask for the fifth time on the barrier layer 3, passivation layer 8, left source electrode 9, right source electrode 10, three anode half grooves on the left side, and three anode half grooves on the right side, and etching the anode half grooves on the left and right sides again using this mask to a depth of 70 nm, forming three anode grooves on the left side and three anode grooves on the right side;

[0136] G3) The mask is used again to form a vacuum film at a vacuum degree of 1.7×10-3 Pa, power is 380W, evaporation rate is Under the process conditions, metal Mo is deposited in the six anode grooves with a thickness of 0.13 μm, so that Schottky contacts are formed between the deposited metal and the barrier layer 3, completing the production of three left anodes 11 and three right anodes 12.

[0137] Step H: Making the left electrode 13 and the right electrode 14.

[0138] The process conditions for metal deposition are as follows: vacuum degree is 1.6×10 -3 Pa, power is 200W, evaporation rate is A sixth mask is formed on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11, and the right anode 12. Metal is deposited using the mask to cover the barrier layer 3, the left source electrode 9, the right source electrode 10, the left anode 11, and the right anode 12, forming a left electrode 13 and a right electrode 14. The left electrode 13 electrically connects the three left source electrodes 9 with the three left anodes 11, and the right electrode 14 electrically connects the three right source electrodes 10 with the three right anodes 12. The deposited metal is a Ni / Au combination, i.e., a lower layer of Ni and an upper layer of Au, with thicknesses of 0.06 μm and 0.24 μm, respectively.

[0139] Step I: Fabricate the left gate 15 and the right gate 16.

[0140] I1) setting the etching process conditions to 18 sccm Cl2 flow rate, 14 mTorr pressure, and 120 W power, forming a mask for the seventh time on the barrier layer 3, passivation layer 8, left source 9, right source 10, left anode 11, right anode 12, left electrode 13, and right electrode 14, and using the mask to etch the passivation layer 8 on the three left P-GaN islands 4 and the three right P-GaN islands 5 until the upper surfaces of the P-GaN islands are reached, thereby forming gate trenches;

[0141] I2) Using the mask again, the vacuum degree is 1.5×10 -3 Pa, power is 300W, evaporation rate is Under the process conditions, a metal combination Pt / Au is deposited in the above-mentioned gate groove, that is, the lower layer is Pt and the upper layer is Au, to form three left gates 15 and three right gates 16 respectively, completing the production of the entire device.

[0142] The effects of the present invention can be further illustrated by the following experimental results.

[0143] Experimental content: The device of Example 2 of the present invention is tested for AC voltage signal chopping. The results are as follows: Figure 7 .

[0144] Depend on Figure 7It can be seen that the device of the present invention can effectively chop the AC voltage signal, which proves that the device of the present invention has excellent bidirectional conduction and bidirectional blocking characteristics.

[0145] The above descriptions are only three specific embodiments of the present invention and do not constitute a limitation of the present invention. It is obvious that for professionals in this field, after understanding the content and principles of the present invention, they can make various modifications and changes in form and details according to the method of the present invention without departing from the principles and scope of the present invention. However, these modifications and changes based on the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. An enhancement-mode GaN-based composite switching device, comprising, from bottom to top: A substrate (1), a transition layer (2), a barrier layer (3) and a passivation layer (8); characterized in that: m left P-GaN islands (4) and m right P-GaN islands (5) arranged in parallel at equal intervals are respectively provided on the left and right sides of the upper portion of the barrier layer (3); a left isolation groove (6) is provided on the front and rear sides of each left P-GaN island (4); a right isolation groove (7) is provided on the front and rear sides of each right P-GaN island (5); and the left P-GaN islands (4) and the right P-GaN islands (5) are distributed in a cross manner; The left sides of the m left P-GaN islands (4) are each provided with a left source (9), the left sides of the m right P-GaN islands (5) are each provided with a left anode (11), and a left electrode (13) is provided in parallel on the left side of each left source (9) and each left anode (11), and these sources and anodes are partially covered by the left electrode and are electrically connected; The right sides of the m left P-GaN islands (4) are each provided with a right anode (12), the right sides of the m right P-GaN islands (5) are each provided with a right source (10), and a right electrode (14) is provided in parallel on the right side of each right source (10) and each right anode (12), and these sources and anodes are partially covered by the right electrode and are electrically connected; The m left P-GaN islands (4) are each provided with a left gate (15) on their upper parts, and the m right P-GaN islands (5) are each provided with a right gate (16) on their upper parts. Both sides of the left and right gates and the m left and right P-GaN islands are covered by a passivation layer (8). The left P-GaN islands (4) below the left gates (15) and their corresponding right anodes (12), as well as the right P-GaN islands (5) below the right gates (16) and their corresponding left anodes (11) are connected via a barrier layer (3), thereby forming a composite structure of a diode and a triode.

2. The device according to claim 1, characterized in that The substrate (1) is made of sapphire, silicon carbide, silicon or graphene.

3. The device according to claim 1, characterized in that The barrier layer (3) has a thickness a of 2 nm to 60 nm.

4. The device according to claim 1, wherein: The m left P-GaN islands (4) are of the same size and thickness b, and their right edges are aligned, and the distance between two adjacent left P-GaN islands (4) is w; The m right P-GaN islands (5) are of the same size and thickness b, and their left edges are aligned. The spacing between two adjacent right P-GaN islands (5) is w; and the horizontal spacing t between the m right P-GaN islands (5) and the m left P-GaN islands (4) is ≥1 μm.

5. The device according to claim 1, wherein: The left isolation grooves (6) are of the same size, and their lower ends are all located in the transition layer (2), and the spacing c between the lower end of each left isolation groove (6) and the interface between the barrier layer (3) and the transition layer (2) is greater than 40nm; the right edge of each left isolation groove (6) is aligned with the right edges of the m left P-GaN islands (4), and the left edge of each left isolation groove (6) is located to the left of the right edge of the left anode (11); The right isolation grooves (7) are of the same size, and their lower ends are all located in the transition layer (2), and the spacing c between the lower end of each right isolation groove (7) and the interface between the barrier layer (3) and the transition layer (2) is greater than 40nm; the left edge of each right isolation groove (7) is aligned with the left edges of m right P-GaN islands (5), and the right edge of each right isolation groove (7) is located to the right of the left edge of the right anode (12).

6. The device according to claim 1, wherein: The m left source electrodes (9) and the m right source electrodes (10) are all located on the upper portion of the barrier layer (3), and the lower ends of the m left anodes (11) and the m right anodes (12) are all located inside the barrier layer (3) or inside the transition layer (2); The m left source electrodes (9) and the m left anode electrodes (11) are arranged alternately, and the right edges of the source electrodes and the anode electrodes are all located in the same vertical plane; The m right source electrodes (10) and the m right anode electrodes (12) are arranged alternately, and the left edges of the source electrodes and the anode electrodes are all located in the same vertical plane.

7. The device according to claim 1, wherein: Each left source electrode (9) and each right source electrode (10) forms an ohmic contact with the barrier layer (3); Each left anode (11) and each right anode (12) forms a Schottky contact with the barrier layer (3).

8. A method for manufacturing the enhancement-mode GaN-based composite switching device according to claim 1, characterized in that: The steps include: A) epitaxially growing a GaN-based wide bandgap semiconductor material on a substrate (1) using an epitaxial process to form a transition layer (2); B) epitaxially growing a GaN-based wide bandgap semiconductor material on the transition layer (2) using an epitaxial process to form a barrier layer (3) with a thickness of a; C) Fabricating the left P-GaN island (4) and the right P-GaN island (5) on the barrier layer (3): C1) epitaxially growing a P-type GaN semiconductor material on the barrier layer (3) to form a P-type GaN semiconductor material with a thickness of b and a doping concentration of 1×10 16 ~1×10 22 cm -3 P-type GaN layer; C2) making a mask on the P-GaN layer for the first time, and etching the P-GaN layer using the mask until the upper surface of the barrier layer (3) is reached, thereby forming m left P-GaN islands (4) and m right P-GaN islands (5); D) forming a mask for the second time on the barrier layer (3), the left P-GaN island (4) and the right P-GaN island (5), and etching the barrier layer (3) and the transition layer (2) in sequence using the mask to form a left isolation groove (6) and a right isolation groove (7), wherein the spacing c between the lower end of each left isolation groove (6) and the right isolation groove (7) and the interface between the barrier layer (3) and the transition layer (2) is greater than 40 nm; E) depositing a passivation layer (8) on the barrier layer (3), the left P-GaN island (4), the right P-GaN island (5), the left isolation trench (6) and the right isolation trench (7); F) forming a left source electrode (9) and a right source electrode (10) on the barrier layer (3); F1) making a mask on the passivation layer (8) for the third time, and etching the passivation layer (8) on the left and right sides using the mask until the upper surface of the barrier layer (3) is reached, thereby forming m source half trenches on the left side and m source half trenches on the right side; F2) using the mask made for the third time to deposit multiple layers of metal in these source half trenches using a metal deposition process, and performing rapid thermal annealing in an N2 atmosphere to form m left source electrodes (9) and m right source electrodes (10); G) Making a left anode (11) and a right anode (12) on the upper part and inside the barrier layer (3): G1) making a mask for the fourth time on the barrier layer (3), the passivation layer (8), the left source electrode (9) and the right source electrode (10), and etching the passivation layer (8) on the left and right sides using the mask until the etching reaches the upper surface of the barrier layer (3), thereby forming m anode half slots on the left side and m anode half slots on the right side, wherein these anode half slots are arranged alternately with the source half slots in F1); G2) forming a mask for the fifth time on the barrier layer (3), the passivation layer (8), the left source electrode (9), the right source electrode (10), the m anode half grooves on the left side, and the m anode half grooves on the right side, and etching the anode half grooves on the left and right sides again using the mask, with an etching depth of >0 μm, to form m anode grooves on the left side and m anode grooves on the right side; G3) using the mask made the fifth time again to deposit multiple layers of metal in the anode grooves using a metal deposition process to form Schottky contacts, thereby completing the production of m left anodes (11) and m right anodes (12); H) making a mask for the sixth time on the barrier layer (3), the passivation layer (8), the left source electrode (9), the right source electrode (10), the left anode (11) and the right anode (12); using the mask to deposit metal on the barrier layer (3), the left source electrode (9), the right source electrode (10), the left anode (11) and the right anode (12) using a metal deposition process to form a left electrode (13) and a right electrode (14); the left electrode (13) partially covers and electrically connects each left source electrode (9) and each left anode (11); and the right electrode (14) partially covers and electrically connects each right source electrode (10) and each right anode (12); I) making a mask for the seventh time on the barrier layer (3), the passivation layer (8), the left source electrode (9), the right source electrode (10), the left anode (11), the right anode (12), the left electrode (13) and the right electrode (14), and using the mask to etch the passivation layer (8) on the upper parts of the m left P-GaN islands (4) and the m right P-GaN islands (5) until the upper surfaces of the P-GaN islands are reached, thereby forming m left gate grooves and m right gate grooves; J) Using the mask made for the seventh time, a metal deposition process is used to deposit multiple layers of metal in the m left and right gate grooves to form a left gate (15) and a right gate (16) respectively, thus completing the fabrication of the entire device.

9. The method according to claim 8, characterized in that: The epitaxial processes include: metal organic chemical vapor deposition, hydride vapor phase epitaxy and molecular beam epitaxy; The metal deposition process includes: electron beam evaporation process and sputtering process.

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