Image sensing device

Abstract

The present invention provides an image sensing device, comprising: a plurality of unit pixels, the plurality of unit pixels being included in a first row; and a gain conversion signal line, the gain conversion signal line being configured to send a gain conversion signal to adjust the sensitivity of the unit pixel. Each unit pixel comprises: a first gain conversion transistor, the first gain conversion transistor comprising a first gate coupled to the gain conversion signal line; a second gain conversion transistor, the second gain conversion transistor comprising a second gate coupled to one end of the first gain conversion transistor; and a floating diffusion FD region, the floating diffusion FD region being coupled to the other end of the first gain conversion transistor. The capacitance of the second gain conversion transistor is greater than the capacitance of the first gain conversion transistor.

Description

Technical Field

[0001] The technology and implementation disclosed in this patent document generally relate to an image sensing device, and more particularly, to an image sensing device provided with a gain conversion transistor to reduce banding noise caused by a gain conversion signal line. Background Art

[0002] Image sensing devices are used in electronic devices to convert optical images into electrical signals. Recent developments in the automotive, medical, computer, and communications industries have led to an increased demand for high-performance image sensing devices in various devices such as smartphones, digital cameras, camcorders, personal communication systems (PCS), game consoles, surveillance cameras, medical micro-cameras, robots, infrared (IR) sensing devices, etc.

[0003] Image sensing devices may be roughly classified into charge coupled device (CCD) image sensing devices and complementary metal oxide semiconductor (CMOS) image sensing devices.

[0004] CMOS image sensing devices can be driven more easily than CCD sensing devices. CMOS image sensing devices enable conventional circuits to be integrated into a single chip, so that CMOS image sensing devices can be easily manufactured as small-sized products, and have higher integration and very low power consumption. In addition, CMOS image sensing devices are compatible with CMOS manufacturing technology, thereby reducing production costs. Recently, CMOS image sensing devices have been intensively studied and rapidly widely used. Summary of the invention

[0005] Various embodiments of the disclosed technology are directed to an image sensing device capable of adjusting a sensitivity level of a unit pixel.

[0006] Various embodiments of the disclosed technology are directed to an image sensing device capable of reducing band-shaped noise applied to adjacent pixels through a gain conversion signal line.

[0007] According to one embodiment of the disclosed technology, an image sensing device may include: a plurality of unit pixels, the plurality of unit pixels being included in a first row; and a gain conversion signal line, the gain conversion signal line being configured to send a gain conversion signal to adjust the sensitivity of the unit pixel. Each unit pixel includes: a first gain conversion transistor, the first gain conversion transistor including a first gate coupled to the gain conversion signal line; a second gain conversion transistor, the second gain conversion transistor including a second gate coupled to one end of the first gain conversion transistor; and a floating diffusion (FD) region, the floating diffusion (FD) region being coupled to the other end of the first gain conversion transistor. The capacitance of the second gain conversion transistor may be greater than the capacitance of the first gain conversion transistor.

[0008] In some implementations, the size of the second gate can be larger than the size of the first gate.

[0009] In some implementations, a source of the second gain conversion transistor and a drain of the second gain conversion transistor can be grounded.

[0010] In some implementations, the second gate can be formed to overlap the dielectric layer.

[0011] In some implementations, the second gain-conversion transistor can include an additional doped region coupled to the second gate.

[0012] In some implementations, the additional doped region can be formed deeper in the semiconductor substrate than the channel, source, and drain of the second gain-converting transistor.

[0013] In some implementations, the image sensing device may further include an Nth gain conversion transistor including an Nth gate (where “N” is an integer of 3 or greater) coupled to one end of the first gain conversion transistor.

[0014] In some implementations, the Nth gain conversion transistor may include a channel, a source, and a drain formed in a semiconductor substrate, and a dielectric layer formed to overlap the channel, the source, and the drain.

[0015] In some implementations, a source of the Nth gain-conversion transistor and a drain of the Nth gain-conversion transistor can be grounded.

[0016] In some implementations, the Nth gate may be formed to overlap the dielectric layer.

[0017] In some implementations, the Nth gain-conversion transistor can include an additional doped region coupled to the Nth gate.

[0018] In some implementations, the additional doped region can be formed deeper in the semiconductor substrate than each of the channel, the source, and the drain of the Nth gain-converting transistor.

[0019] In some implementations, the gain conversion signal line may be configured to turn on the first gain conversion transistor by sending a signal having a logic high level, and may be configured to turn off the first gain conversion transistor by sending a signal having a logic low level.

[0020] In some implementations, if the first gain conversion transistor is turned off, a floating diffusion (FD) region and the second gain conversion transistor may be electrically isolated from each other.

[0021] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0023] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0024] Figure 2 is a schematic diagram illustrating an example of a pixel array of an image sensor including first and second unit pixels adjacent to each other in a row based on some implementations of the disclosed technology.

[0025] Figure 3 is a timing diagram illustrating an example of the operation of a transistor included in a first unit pixel based on some implementations of the disclosed technology.

[0026] Figure 4 is a circuit diagram showing an example of an equivalent circuit of a first unit pixel and a second unit pixel based on some implementations of the disclosed technology.

[0027] Figure 5A is a cross-sectional view showing a first gain conversion transistor and a second gain conversion transistor taken along a first cutting line according to some implementations of the disclosed technology.

[0028] Figure 5B is a circuit diagram illustrating an example of equivalent capacitance of a first gain conversion transistor and a second gain conversion transistor based on some implementations of the disclosed technology.

[0029] Figure 6is a schematic diagram showing an example of third unit pixels arranged in a row within a pixel array of an image sensor based on other implementations of the disclosed technology.

[0030] Figure 7 is a circuit diagram showing an example of a third unit pixel based on an implementation of the disclosed technology.

[0031] Fig. 8A is a cross-sectional view showing an example of a first gain conversion transistor and a second gain conversion transistor taken along a second cutting line according to an implementation of the disclosed technology.

[0032] Figure 8B is a circuit diagram illustrating an example of equivalent capacitance of a first gain conversion transistor and a second gain conversion transistor based on an implementation of the disclosed technology.

[0033] Fig. 9 is a schematic diagram showing an example of fourth unit pixels arranged in a row within a pixel array of an image sensor based on an implementation of the disclosed technology. DETAILED DESCRIPTION

[0034] This patent document provides an implementation and example of an image sensing device, which is provided with a gain conversion transistor to reduce the band noise caused by the gain conversion signal line. Some implementations of the disclosed technology relate to an image sensing device that can adjust the sensitivity of a unit pixel of an image sensor while reducing the band noise caused by the use of the gain conversion signal line. The disclosed technology provides various implementations of an image sensing device, which includes a gain conversion transistor that helps reduce the band noise that occurs between pixels arranged in the same row.

[0035] Reference will now be made in detail to embodiments of the disclosed technology, examples of which are illustrated in the accompanying drawings. While the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings.

[0036] The same reference numerals will be used throughout all drawings to denote the same or similar parts as much as possible. In the following description, detailed descriptions of related known configurations or functions incorporated herein will be omitted to avoid confusing the subject matter.

[0037] Figure 1 is a block diagram illustrating an example of an image sensing device 10 based on some implementations of the disclosed technology.

[0038] Reference Figure 1 , the image sensing device 10 may include an image sensor 100 and an image processor 200 .

[0039] The image sensor 100 may include a pixel array 110 including a plurality of pixels arranged in a matrix array, a correlated double sampler (CDS) 120, an analog-to-digital converter (ADC) 130, a buffer 140, a row driver 150, a timing generator 160, a control register 170, and a ramp signal generator 180.

[0040] The image sensor 100 may sense light beams of different wavelengths reflected from an object captured (or focused) by a lens (not shown) when receiving a control signal from the image processor 200. The image processor 200 may transmit an output image sensed by the image sensor 100 to an electronic device provided with a display or the like.

[0041] The image processor 200 may include a camera controller 220, an image signal processor 210, and a PC interface (I / F) (not shown). The camera controller 220 may control the control register 170. In this case, although the camera controller 220 may control the operation of the control register 170 of the image sensor 100 using an inter-integrated circuit (I2C) bus, the scope of the disclosed technology is not limited thereto.

[0042] The image signal processor 210 can receive image information corresponding to the output signal of the buffer 140, and can produce and process the received image information in a manner that a person can recognize and identify the received image with naked eye vision, so that the image signal processor 210 can output the obtained processed image to the display.

[0043] The pixel array 110 may include a plurality of unit pixels 115 arranged in a matrix array. Each of the unit pixels 115 may convert optical image information into an electronic image signal, and may output the electronic image signal to a correlated double sampler (CDS) 120. The pixel array 110 may include a plurality of photosensitive elements that sense light and convert the sensed light into an electrical signal.

[0044] The correlated double sampler (CDS) 120 may hold and sample the electronic image signal received from the pixels of the pixel array 110. For example, the correlated double sampler (CDS) 120 may sample a reference voltage level and a voltage level of the received electronic image signal in response to a clock signal received from the timing generator 160, and may transmit an analog signal corresponding to a difference between the reference voltage level and the voltage level of the received electronic image signal to an analog-to-digital converter (ADC) 130.

[0045] An analog-to-digital converter (ADC) 130 may convert a received analog signal into a digital signal and may transmit the digital signal to a buffer 140 .

[0046] The buffer 140 may store or latch each digital signal received from the analog-to-digital converter (ADC) 300 and may sequentially output the digital signals to the image signal processor. The buffer 140 may include a memory for storing or latching the digital signal and a sense amplifier for amplifying the digital signal.

[0047] The row driver 150 may drive a plurality of pixels of the pixel array 110 in response to an output signal of the timing generator 160. For example, the row driver 150 may generate a selection signal capable of selecting any one of a plurality of row lines and / or a driving signal for driving any one of a plurality of row lines.

[0048] The timing generator 160 may generate timing signals to control the correlated double sampler (CDS) 120 , the analog-to-digital converter (ADC) 130 , the row driver 150 , and the ramp signal generator 180 .

[0049] The control register 170 may generate a control signal to control the buffer 140, the timing generator 160, and the ramp signal generator 180. As a result, the operations of the buffer 140, the timing generator 160, and the ramp signal generator 180 may be controlled by the generated control signal. In this case, the control register 170 may operate under the control of the camera controller.

[0050] The ramp signal generator 180 may generate a ramp signal for controlling the image signal generated from the buffer 140 in response to the control signal of the timing generator 160 .

[0051] Figure 2 20 is a schematic diagram showing an example of a first unit pixel 315 and a second unit pixel 415 adjacent to each other in a row direction. The first unit pixel 315 and the second unit pixel 415 are arranged in the same row within the pixel array 110 of the image sensor 100.

[0052] In some implementations, the first unit pixel 315 may include a photodiode region for converting light into photocharges and a transistor region for collecting the photocharges and converting the photocharges into a unit pixel signal. In this case, the photodiode area may include: a plurality of photodiodes, for example, eight photodiodes PD11 to PD18 in two photodiode groups, wherein four photodiodes PD11 to PD14 form a first photodiode group at a first position, and four photodiodes PD15 to PD18 form a second photodiode group at a second position; eight transfer transistor gates TG11 to TG18, the eight transfer transistor gates TG11 to TG18 being respectively connected to the photodiodes PD11 to PD18 to respectively transfer photocharges out of the photodiodes PD11 to PD18; a floating diffusion (FD) area FD11 at a first position, which is used to receive photocharges from the first photodiode group of the four photodiodes PD11 to PD14 via the transfer transistor gates TG11 to TG14; and a second floating diffusion (FD) area FD12 at a second position, which is used to receive photocharges from the second photodiode group of the four photodiodes PD15 to PD18 via the transfer transistor gates TG15 to TG18. The transistor area may include a reset transistor RX1 for resetting the floating diffusion areas FD11 and FD12 , a first gain conversion transistor DCG11 , a second gain conversion transistor DCG12 , a drive transistor DX1 , and a selection transistor SX1 .

[0053] The second unit pixel 415 may include a photodiode region and a transistor region. The photodiode region may include eight photodiodes PD21-PD28, eight transfer transistor gates TG21-TG28, and two floating diffusion (FD) regions FD21 and FD22. The transistor region may include a reset transistor RX2, a first gain conversion transistor DCG21, a second gain conversion transistor DCG22, a drive transistor DX2, and a select transistor SX2.

[0054] The first unit pixel 315 and the second unit pixel 415 are adjacent to each other in the row direction of the pixel array 110. The first unit pixel 315 and the second unit pixel 415 may be configured to be substantially identical to each other in structure. The following description will focus on the first unit pixel 315 and may also be applied to the second unit pixel 415.

[0055] Although the above implementations have disclosed an example of an 8-shared unit pixel structure including eight photodiodes, other structures such as a 4-shared unit pixel structure or a 2-shared unit pixel structure are also possible. In some implementations, the image sensor may have a non-shared pixel structure.

[0056] The first to eighth photodiodes PD11 to PD18 included in the first unit pixel 315 may be respectively coupled to the first to eighth transfer transistor gates TG11 to TG18, so that the first to eighth photodiodes PD11 to PD18 may be coupled to the first floating diffusion (FD) region FD11 or the second floating diffusion (FD) region FD12 through the first to eighth transfer transistor gates TG11 to TG18. In this case, the floating diffusion (FD) region FD11 or FD12 may operate as a drain of each transfer transistor, and each of the photodiodes PD11 to PD18 may operate as a source of each transfer transistor.

[0057] In more detail, the first to fourth photodiodes PD11-PD14 included in the first unit pixel 315 may be respectively coupled to the first to fourth transfer transistor gates TG11-TG14, so that the first to fourth photodiodes PD11-PD14 can be coupled to the first floating diffusion (FD) region FD11 through the first to fourth transfer transistor gates TG11-TG14. The fifth to eighth photodiodes PD15-PD18 included in the first unit pixel 315 may be respectively coupled to the fifth to eighth transfer transistor gates TG15-TG18, so that the fifth to eighth photodiodes PD15-PD18 can be coupled to the second floating diffusion (FD) region FD12 through the fifth to eighth transfer transistor gates TG15-TG18.

[0058] The first to eighth transmission signal lines (not shown) may be connected to the first to eighth transmission transistor gates TG11 to TG18, respectively. If a transmission signal having an activation level voltage is applied to the first to eighth transmission transistor gates TG11 to TG18, the first to eighth transmission transistors may transmit photocharges from the first to eighth photodiodes PD11 to PD18 to the first floating diffusion (FD) region FD11 or the second floating diffusion (FD) region FD12.

[0059] In some implementations, the first floating diffusion (FD) region FD11 may be formed by a first metal line (M 1 ) is electrically coupled to the second floating diffusion (FD) region FD12, so that the first floating diffusion (FD) region FD11 and the second floating diffusion (FD) region FD12 jointly form a first sensing node of the first unit pixel 315.

[0060] The first and second floating diffusion (FD) regions FD11 and FD12 may share a reset transistor RX1 , a first gain conversion transistor DCG11 , a second gain conversion transistor DCG12 , a drive transistor DX1 , and a select transistor SX1 .

[0061] The reset transistor RX1, the first gain conversion transistor DCG11, the second gain conversion transistor DCG12, the drive transistor DX1 and the selection transistor SX1 may also be referred to as shared transistors. The structural relationship and connection relationship between the shared transistors RX1, DCG11, DCG12, DX1 and SX1 will be described below with reference to the accompanying drawings.

[0062] The reset transistor RX1 may include a first doping region 310, a second doping region 320, and a reset gate 312. Each of the first doping region 310 and the second doping region 320 may include a silicon region doped with impurities different from those of the semiconductor substrate. For example, each of the first doping region 310 and the second doping region 320 formed in a P-type semiconductor substrate may include a silicon region doped with N-type impurities (hereinafter referred to as N-type impurity doped silicon region). The first doping region 310 may operate as a drain of the reset transistor RX1. The second doping region 320 may operate as a source of the reset transistor RX1.

[0063] The first doping region 310 may receive a power supply voltage VDD (not shown) as an input. The reset transistor RX1 may be coupled to the first gain conversion transistor DCG11 through the second doping region 320 .

[0064] The reset gate 312 may include at least one of a metal layer and a doped silicon layer, and may be coupled to a reset signal line (not shown).

[0065] A reset signal line (not shown) may be coupled to a reset gate 412 of another reset transistor RX2 included in a second unit pixel 415 adjacent to the first unit pixel 315. Thus, the reset signal line (not shown) may be coupled to the reset gates 312 and 412 respectively included in the unit pixels 315 and 415 arranged in the same row.

[0066] The reset transistors RX1 and RX2 may be turned on or off in response to a voltage level of a reset signal applied to the reset gates 312 and 412 through a reset signal line (not shown).

[0067] When the reset transistor RX1 included in the first unit pixel 315 is turned on, charges can flow from the second doping region 320 used as a source to the first doping region 310 used as a drain. When the reset transistor RX1 is turned on, the first to eighth transfer transistors and the first gain conversion transistor DCG11 can be turned on at the same time, so that the reset transistor RX1 can be electrically connected to all photodiodes (for example, the first to eighth photodiodes PD11 to PD18), the first sensing node, the first doping region 310, the second doping region 320, and the second gate 332 to reset them to the power supply voltage (VDD) level. This operation resets the photocharges in the photodiodes PD11 to PD18 after completing the readout of the photocharges generated by the first to eighth photodiodes PD11 to PD18, so that the amount of photocharges generated by the first to eighth photodiodes PD11 to PD18 can be accurately measured in the subsequent readout process.

[0068] The first gain conversion transistor DCG11 for the first unit pixel 315 may include a third doping region 330, a second doping region 320 shared with the reset transistor RX1, and a first gate 322. The first sensing node linking the two floating diffusion regions FD11 and FD12 may be connected to the third doping region 330 corresponding to one end of the first gain conversion transistor DCG11. Each of the third doping region 330 and the second doping region 320 may include a silicon region doped with impurities different from those of the semiconductor substrate. For example, each of the third doping region 330 and the second doping region 320 formed in a P-type semiconductor substrate may include an N-type impurity doped silicon region. The first gate 322 may include at least one of a metal and doped silicon, and may be connected to a gain conversion signal line (DCG signal line) 300. Under this design, the second doping region 320 may operate as a drain of the first gain conversion transistor DCG11. The third doping region 330 may operate as a source of the first gain conversion transistor DCG11.

[0069] The gain conversion signal line 300 may be coupled to a first gate 422 of a first gain conversion transistor DCG21 included in a second unit pixel 415 adjacent to the first unit pixel 315. Thus, the gain conversion signal line (DCG signal line) 300 may be coupled to first gates 322 and 422 of first gain conversion transistors DCG11 and DCG12 included in the first unit pixel 315 and the second unit pixel 415 arranged in the same row.

[0070] The first gain conversion transistor DCG11 can be turned on or off in response to the voltage level of the gain conversion signal applied to the first gate 322, so that the sensitivity of the image sensor 100 can be adjusted by turning on or off the first gain conversion transistor DCG11. This is because DCG12 is connected to DCG11 as an additional capacitance element in the following manner: by turning on and off DCG11, the capacitance of DCG12 can be added to the total capacitance coupled to the first sensing node or eliminated from the total capacitance coupled to the first sensing node, thereby changing the unit pixel gain for generating a pixel output signal by the first unit pixel 315. When the incident light is bright, since the bright incident light can generate sufficient photocharge, DCG11 can be turned on, thereby setting the gain of the first unit pixel to a low gain. When the incident light is dim, since the dim incident light can generate relatively insufficient photocharge, DCG11 can be turned off, thereby setting the gain to a high gain. When a signal having a voltage of an activation level is applied to the first gate 322, the second gate 332 can be electrically coupled to the first sensing node.

[0071] When the first gain conversion transistor DCG11 is turned on, the total capacitance of the first sensing node can be represented by the sum of the equivalent capacitances of the first floating diffusion (FD) region FD11, the second floating diffusion (FD) region FD12, the first gain conversion transistor DCG11 and the second gain conversion transistor DCG12.

[0072] When the first gain conversion transistor DCG11 is turned off, the total capacitance of the first sensing node may be represented by the sum of the equivalent capacitances of the first floating diffusion (FD) region FD11, the second floating diffusion (FD) region FD12, and the first gain conversion transistor DCG11. When the first gain conversion transistor DCG11 is turned off, the second gain conversion transistor DCG12 may be disconnected from the first gain conversion transistor DCG11, and the capacitance of the second gain conversion transistor DCG12 may not be added to the total capacitance of the first sensing node.

[0073] The on / off operation of the first transfer transistor DCG11 may be controlled to adjust the sensitivity of the image sensor 100 .

[0074] The sensitivity of the image sensor 100 is reduced, thereby preventing overflow and blooming phenomena in a high illumination environment.

[0075] The first gain conversion transistor DCG21 included in the second unit pixel 415 may also perform a similar operation to the first gain conversion transistor DCG11 included in the first unit pixel 315 .

[0076] The gain conversion signal line 300 is shared by the unit pixels 315 and 415 arranged in the same row, so that the same gain conversion signal can be applied to the unit pixels 315 and 415 arranged in the same row.

[0077] Returning to the first unit pixel 315, the second gain conversion transistor DCG12 may include a fifth doping region 350, a fourth doping region 340, and a second gate 332. Each of the fifth doping region 350 and the fourth doping region 340 may include a silicon region doped with impurities different from those of the semiconductor substrate. For example, each of the fifth doping region 350 and the fourth doping region 340 formed in a P-type semiconductor substrate may include an N-type impurity doped silicon region. The fourth doping region 340 may operate as a drain of the second gain conversion transistor DCG12. The fifth doping region 350 may operate as a source of the second gain conversion transistor DCG12.

[0078] The second gate 332 of DCG 12 can be connected by a second metal line (M 2 ) is coupled to the second doping region 320 (shared by DCG11 and reset transistor RX1). The ground voltage GND can be applied to the fifth doping region 350 and the fourth doping region 340, the drain and source of DCG12. In this configuration, the second gain conversion transistor DCG12 can operate as a capacitive element. The second gain conversion transistor DCG12 can be formed by a manufacturing process similar to that of the first gain conversion transistor DCG11.

[0079] The equivalent capacitance of the second gain conversion transistor DCG12 can be determined by the overlap capacitance between the fifth doping region 350 and the second gate 332, the overlap capacitance between the second gate 332 and the second channel region, the overlap capacitance between the fourth doping region 340 and the second gate 332, the junction capacitance between the semiconductor substrate and the fifth doping region 350, the junction capacitance between the semiconductor substrate and the fourth doping region 340, and the junction capacitance between the second channel region and the semiconductor substrate. Figure 5A and Figure 5B The detailed equivalent capacitance of the second gain conversion transistor DCG12 will be described.

[0080] The equivalent capacitance of the second gain conversion transistor DCG12 may be greater than the equivalent capacitance of the first gain conversion transistor DCG11. In some implementations, the size of the second gate 332 is greater than the first gate 322, so that the capacitance of the second gain conversion transistor DCG12 may be increased much more than the capacitance of the first gain conversion transistor DCG11.

[0081] Each capacitance of the capacitor including a pair of spaced apart conductor plates may be proportional to the width of each conductor plate and may be inversely proportional to the distance between the conductor plates. Therefore, when the size of the second gate 332 is larger than the first gate 322, the equivalent capacitance of the second gain conversion transistor DCG12 may be larger than the equivalent capacitance of the first gain conversion transistor DCG11.

[0082] In some other implementations, a capacitive element (not shown) may be additionally coupled to the second gain conversion transistor DCG12 so that the capacitance of the second gain conversion transistor DCG12 may be much increased than the capacitance of the first gain conversion transistor DCG11 .

[0083] As the capacitance of the second gain conversion transistor DCG12 increases compared to the first gain conversion transistor DCG11 , the sensitivity control characteristic and band noise of the image sensor 100 can be improved.

[0084] Band noise may be caused by a phenomenon in which a floating diffusion (FD) region is electrically coupled to an adjacent signal line so that a voltage change occurs in a floating diffusion (FD) region of another unit pixel coupled to the adjacent signal line. Since a voltage change occurs in a floating diffusion (FD) region included in another unit pixel coupled to the adjacent signal line, noise may occur in a signal read out from another unit pixel coupled to the adjacent signal line.

[0085] In some implementations, such band noise may occur due to the gain conversion signal line 300 commonly coupled to the first gate 322 of the first unit pixel 315 and the first gate 422 of the second unit pixel 415 .

[0086] A process of generating such band noise will be described below with reference to an example in which light from a high-illuminance light source is incident on a region in which the first unit pixel 315 is located.

[0087] The first to eighth photodiodes PD11-PD18 included in the first unit pixel 315 may convert incident light into photocharges, which may flow into the first floating diffusion (FD) region FD11 or the second floating diffusion (FD) region FD12 through the first to eighth transfer transistor gates TG11-TG18.

[0088] A first sensing node formed by the first and second floating diffusion (FD) regions FD11 and FD12 may be coupled to the third doping region 330 , and the gain conversion signal line 300 may be coupled to the first gate 322 .

[0089] The first gain conversion transistor DCG21 included in the second unit pixel 415 may be coupled to the first and second floating diffusion (FD) regions FD21 and FD22 included in the second unit pixel 415. The first and second floating diffusion (FD) regions FD21 and FD22 of the second unit pixel 415 may form a second sensing node.

[0090] The first and second floating diffusion (FD) regions FD11 and FD12 included in the first unit pixel 315 may be electrically coupled to the gain conversion signal line 300. The first and second floating diffusion (FD) regions FD21 and FD22 included in the second unit pixel 415 may be electrically coupled to the gain conversion signal line 300.

[0091] Therefore, when photo charges generated from light from a high-illuminance light source incident on the first unit pixel 315 are applied to the first floating diffusion (FD) region FD11 and the second floating diffusion (FD) region FD12, the band noise caused by the gain conversion signal line may affect the voltage levels of the first floating diffusion (FD) region FD21 and the second floating diffusion (FD) region FD22 of the second unit pixel 415.

[0092] The size of the band noise generated between adjacent unit pixels can be changed according to the ratio between the equivalent capacitance of the first element directly connected to the floating diffusion (FD) area and the equivalent capacitance of the second element connected to the first element. Since the first element is directly connected to the floating diffusion (FD) area, the capacitance of the first element is directly added to the capacitance of the floating diffusion (FD) area. As the total capacitance of the floating diffusion (FD) area increases, the band noise of other floating diffusion areas connected to the floating diffusion (FD) area through the gain conversion signal line can increase.

[0093] The first element directly connected to the floating diffusion (FD) region may include a transistor, a capacitor or others. For example, a transistor may be configured such that its source, drain or gate is connected to the floating diffusion (FD) region, and a capacitor may be configured such that one end thereof is connected to the floating diffusion (FD) region.

[0094] For example, the first gain conversion transistor DCG11 included in the first unit pixel 315 may correspond to a first element directly coupled to the first and second floating diffusion (FD) regions FD11 and FD12. Also, the second gain conversion transistor DCG12 may correspond to a second element.

[0095] The voltage applied to the coupled signal line may vary in proportion to the capacitance of the element coupled to the floating diffusion (FD) region. Therefore, as the capacitance of the element directly coupled to the floating diffusion (FD) region increases, the influence of band noise affecting adjacent pixels may also increase.

[0096] When the equivalent capacitance of the second gain conversion transistor DCG12 is less than the equivalent capacitance of the first gain conversion transistor DCG11, the voltage variation of the first floating diffusion (FD) region FD11 and the second floating diffusion (FD) region FD12 caused by photo charges may result in larger band noise in the second unit pixel 415.

[0097] When the capacitance of a gain conversion transistor coupled to a floating diffusion (FD) region is not sufficiently secured, it may be difficult to adjust the sensitivity of an image sensor in a high illumination environment.

[0098] Since some implementations of the disclosed technology propose to implement two separate gain conversion transistors (ie, a first gain conversion transistor DCG11 and a second gain conversion transistor DCG12) instead of a single gain conversion transistor, the influence of band noise can be minimized and the sensitivity can be adjusted in a high illumination environment.

[0099] Compared to the case where the unit pixel includes a single gain conversion transistor having a large capacitance, the first unit pixel 315 includes a first gain conversion transistor DCG11 and a second gain conversion transistor DCG12. The second gain conversion transistor DCG12 may be configured to include a second gate 332 coupled to the second doping region 320 and the fifth doping region 350 and the fourth doping region 340 to which a ground voltage is applied. Therefore, the first unit pixel 315 can obtain the capacitance required to adjust the sensitivity and minimize the band noise in a high illumination environment.

[0100] The first sensing node may be coupled to the driving gate 352 of the driving transistor DX1 . The driving transistor DX1 may include an eighth doping region 380 , a seventh doping region 370 , and the driving gate 352 .

[0101] Each of the seventh doping region 370 and the eighth doping region 380 may include a silicon region doped with impurities different from those of the semiconductor substrate. For example, each of the seventh doping region 370 and the eighth doping region 380 formed in a P-type semiconductor substrate may include an N-type impurity doped silicon region.

[0102] The seventh doping region 370 may operate as a drain of the driving transistor DX1. The eighth doping region 380 may operate as a source of the driving transistor DX1.

[0103] A power supply voltage VDD (not shown) may be applied to the eighth doping region 380. The seventh doping region 370 may be included in the selection transistor SX1. Therefore, the driving transistor DX1 may be coupled to the selection transistor SX1.

[0104] The driving gate 352 of the driving transistor DX1 may include at least one of a metal layer and a doped silicon layer.

[0105] The driving transistor DX1 may operate as a source follower transistor. The driving transistor DX1 may amplify a voltage level change of the first sensing node.

[0106] The selection transistor SX1 may include a seventh doping region 370, a sixth doping region 360, and a selection gate 342. The selection transistor SX1 may selectively output a signal amplified by the driving transistor DX1 in response to a voltage signal received through a selection signal line (not shown) coupled to the selection gate 342.

[0107] Figure 3 is a timing diagram illustrating an operation example of a transistor included in a first unit pixel based on some implementations of the disclosed technology.

[0108] Figure 3 Shown are the signal levels applied to the transistors depending on the sensitivity level or operation stage.

[0109] In some implementations, the image sensor 100 may adjust the sensitivity level according to the image capturing (shooting) environment or the image capturing (shooting) mode.

[0110] The gain conversion signal DCGS may have a logic high level or a logic low level according to an image capture environment or an image capture mode. If the gain conversion signal DCGS is at a logic high level, the first gain conversion transistors DCG11 and DCG21 may be turned on. If the gain conversion signal DCGS is at a logic low level, the first gain conversion transistors DCG11 and DCG21 may be turned off.

[0111] In low-light environments or general capture (shooting) mode, image capture may require a high conversion gain. This is because when the sum of the capacitances of the sensing nodes decreases, the sensitivity increases. In low-light environments, the gain conversion signal DCGS in the sensing phase can be set to zero "0" corresponding to a logic low level.

[0112] In high illumination environments or high dynamic range (HDR) capture mode, image capture may require low conversion gain. This is because when the sum of the capacitances of the sensing nodes increases, the sensitivity decreases. In high illumination environments, the gain conversion signal DCGS of the sensing phase can be set to "1" corresponding to a logic high level.

[0113] The output signal read out from the unit pixel included in the image sensor can be roughly divided into a reset output signal and a sensing output signal. The reset output signal may refer to a signal output from the time period T2 in the reset phase. The sensing output signal may refer to a signal output from the time period T4 in the sensing phase.

[0114] Regardless of the image capture environment, the timing of measuring the reset output signal and the sense output signal is the same. Therefore, although reference is made to the timing diagram with low conversion gain for ease of description (see Figure 3 The following description is given for the timing diagram with “low conversion gain” in FIG. 1 , but the same description can be applied to the timing diagram with high conversion gain.

[0115] In time period T1, in order to remove residual charge of the unit pixel, each of the reset signal RS, the transfer signal TS and the gain conversion signal DCG can be at a logic high level. In time period T1, the reset transistor, the transfer transistor and the first gain conversion transistor are turned on, so that the charge stored in the unit pixel can be removed.

[0116] The reset output signal may be measured immediately after the time period T1 has passed. Since the reset output signal is a signal measured by removing photocharges of the sensing node, noise caused by residual charges remaining in the floating diffusion (FD) region may be removed from the sensing output signal by the reset output signal.

[0117] After measuring the reset output signal, the photodiode may generate photocharges from incident light during a time period T2.

[0118] In time period T3, the transfer transistor may be turned on to move the photocharges generated by the photodiode to the floating diffusion (FD) region. The photocharges that have moved to the floating diffusion (FD) region may change the voltage of the sensing node. The size of the sensing output signal may change according to the voltage level of the sensing node.

[0119] In the time period T4, the voltage level of the sensing node may be sensed to measure the amount of photocharges generated by the photodiode. In this case, the output signal in the time period T4 may be referred to as a sensing output signal.

[0120] If a voltage level variation of a floating diffusion (FD) region affected by such band noise affects a reset output signal, an image measured by the image sensor 100 may appear darker than an actual image.

[0121] If the band noise affects the floating diffusion (FD) region of the adjacent unit pixel during the reset phase, the voltage of the floating diffusion (FD) region may not be sufficiently reset to the power supply voltage VDD. If the voltage of the floating diffusion (FD) region of the adjacent unit pixel is not sufficiently reset to the power supply voltage VDD, the amount of residual charge remaining in the floating diffusion (FD) region of the adjacent unit pixel may be measured to be greater than the amount of actual charge stored in the floating diffusion (FD) region of the adjacent unit pixel.

[0122] Therefore, when band noise affects adjacent unit pixels in the reset phase, a signal corresponding to a charge amount greater than an actual amount of residual charge may be subtracted from a sensing output signal, and an image measured by the image sensor 100 may appear darker than an actual image.

[0123] In contrast to the above-described example, when a voltage level variation of a floating diffusion (FD) region affected by band-shaped noise affects a sensing output signal, an image measured by the image sensor 100 may appear brighter than an actual image.

[0124] When band noise affects the floating diffusion (FD) region of an adjacent unit pixel during the sensing phase, the voltage of the floating diffusion (FD) region may be measured as lower than the actual voltage of the floating diffusion (FD) region due to the influence of such band noise. If the voltage of the floating diffusion (FD) region of the adjacent unit pixel is measured as lower than the actual voltage of the floating diffusion (FD) region, much more charge than the charge actually generated by the photodiode may be measured.

[0125] Therefore, when band noise affects adjacent unit pixels in the sensing stage, the sensing output signal may be detected as a signal corresponding to a much larger amount of charge than the actual amount of charge, and an image measured by the image sensor 100 may appear brighter than the actual image.

[0126] In some implementations, the image sensor 100 may reduce the capacitance of an element directly coupled to a floating diffusion (FD) region, so that the image sensor 100 can prevent image distortion caused by banding noise. The image sensor 100 may reduce the capacitance of an element directly coupled to a floating diffusion (FD) region, so that the image sensor 100 can prevent signal distortion in a time period T2 for measuring a reset output signal or in a time period T4 for measuring a sensing output signal.

[0127] Figure 4 Some implementations based on the disclosed technology are shown Figure 2 An example of an equivalent circuit of the first unit pixel 315 and the second unit pixel 415 is shown in circuit diagram 40 .

[0128] Figure 4An example of a connection relationship between constituent elements (eg, photodiodes, floating diffusion (FD) regions, transistors, etc.) included in two adjacent unit pixels 315 and 415 is shown. Figure 2 The functions of constituent elements (eg, photodiodes, floating diffusion (FD) regions, transistors, etc.) are described, and thus redundant descriptions will be omitted for the sake of brevity.

[0129] The first unit pixel 315 and the second unit pixel 415 are substantially identical in structure to each other. Therefore, the following description given with reference to the first unit pixel 315 can also be applied to the second unit pixel 415.

[0130] The first to fourth photodiodes PD11-PD14 may be coupled to the first floating diffusion (FD) region through the first to fourth transfer transistor gates TG11-TG14. The fifth to eighth photodiodes PD15-PD18 may be coupled to the second floating diffusion (FD) region through the fifth to eighth transfer transistor gates TG15-TG18.

[0131] The first floating diffusion (FD) region and the second floating diffusion (FD) region may be coupled to each other through a metal line, thereby forming a first sensing node SN1.

[0132] The first gain conversion transistor DCG11 may be coupled to the first sensing node SN1. The first gain conversion transistor DCG11 may receive a gain conversion signal DCGS through a gain conversion signal line. Whether the second gain conversion transistor DCG12 is coupled to the first floating diffusion (FD) region FD11 and the second floating diffusion (FD) region FD12 may be determined based on the level of the gain conversion signal DCGS.

[0133] The sum of the capacitances of the sensing node SN1 may be determined based on whether the second gain conversion transistor DCG12 is coupled to the first sensing node SN1 .

[0134] Figure 5A is a diagram showing some implementations based on the disclosed technology. Figure 2 The cross-sectional view 50 a of the first gain conversion transistor DCG11 and the second gain conversion transistor DCG12 taken along the first cutting line AA′ is shown.

[0135] Figure 5B Some implementations based on the disclosed technology are shown Figure 2 A circuit diagram of an example of equivalent capacitance of the first gain conversion transistor DCG11 and the second gain conversion transistor DCG12 is shown.

[0136] Figure 5AThe capacitance C caused by the doped region or gate of the first gain conversion transistor DCG11 is shown. OD1 , C OG1 , C OS1 , C JD1 , C JC1 and C JS1 .also, Figure 5A The capacitance C caused by the doped region or gate of the second gain conversion transistor DCG12 is shown. OD2 , C OG2 and C OS2 .

[0137] The first gain conversion transistor DCG11 may include a first gate 322, a third doping region 330, and a second doping region 320. The third doping region 330 may operate as a source of the first gain conversion transistor, and the second doping region 320 may operate as a drain of the first gain conversion transistor. Each of the third doping region 330 and the second doping region 320 may include a region doped with a conductivity type opposite to that of the semiconductor substrate 500.

[0138] The first channel region 512 of the first gain conversion transistor DCG11 may be formed in the semiconductor substrate 500 between the third doping region 330 and the second doping region 320. The first channel region 512 may be a region doped with a doping density different from that of the third doping region 330 and the second doping region 320, or may be a region doped with a conductivity type different from that of the third doping region 330 and the second doping region 320.

[0139] The first dielectric layer 510 may be formed to overlap the third doping region 330 serving as the source of the first gain conversion transistor DCG11, the second doping region 320 serving as the drain of the first gain conversion transistor DCG11, and the first channel region 512. In addition, the first gate 322 may be formed to overlap the first dielectric layer 510.

[0140] If a gain conversion signal DCGS having a voltage of a logic high level is applied to the first gate 322 , photo charges may move from the third doping region 330 to the second doping region 320 through the first channel region 512 .

[0141] The total equivalent capacitance of the first gain conversion transistor DCG11 can be calculated by the overlap capacitance (C OD1 ), the overlap capacitance (C OG11 ), the overlap capacitance (C OS11), the junction capacitance (C JD1 ), the junction capacitance (C JC1 ) and the junction capacitance (C JS1 ) is used to represent it. Figure 5B The total capacitance of the first gain conversion transistor DCG11 is described.

[0142] The second gain conversion transistor DCG12 may include a second gate 332, a fifth doping region 350, and a fourth doping region 340. The fifth doping region 350 may operate as a source of the second gain conversion transistor DCG12, and the fourth doping region 340 may operate as a drain of the second gain conversion transistor DCG12. Each of the fifth doping region 350 and the fourth doping region 340 may include a region doped with a conductivity type opposite to that of the semiconductor substrate 500.

[0143] The second channel region 522 of the second gain conversion transistor DCG12 may be formed in the semiconductor substrate 500 between the fifth doping region 350 and the fourth doping region 340. The second channel region 522 may be a region doped with a doping density different from that of the fifth doping region 350 and the fourth doping region 340, or may be a region doped with a conductivity type different from that of the fifth doping region 350 and the fourth doping region 340.

[0144] The second dielectric layer 520 may be formed to overlap the fifth doping region 350 serving as the source of the second gain conversion transistor DCG12, the fourth doping region 340 serving as the drain of the second gain conversion transistor DCG12, and the second channel region 522. In addition, the second gate 332 may be formed to overlap the second dielectric layer 520.

[0145] The total equivalent capacitance of the second gain conversion transistor DCG12 can be calculated by the overlap capacitance (C OD2 ), the overlap capacitance (C OG2 ) and the overlap capacitance (C OS2 ) to indicate.

[0146] Since the fifth doping region 350 and the fourth doping region 340 are grounded and the semiconductor substrate 500 is grounded, the junction capacitance between the fifth doping region 350, the fourth doping region 340, the second channel region 522 and the semiconductor substrate 500 may not contribute to the capacitance of the second gain conversion transistor DCG12. Figure 5BThe total capacitance of the second gain conversion transistor DCG12 is described.

[0147] In some implementations, the second gain conversion transistor DCG12 may be formed by the same process as the first gain conversion transistor DCG11. For example, each of the fifth doping region 350 and the fourth doping region 340 of the second gain conversion transistor DCG12 may include an impurity region having the same density and conductivity type as the impurity regions of the third doping region 330 and the second doping region 320 of the first gain conversion transistor DCG11. In addition, the impurity region may have the same doping depth as the impurity regions of the third doping region 330 and the second doping region 320 of the first gain conversion transistor DCG11. Similarly, the second dielectric layer 520 and the first dielectric layer 510 may be formed to have the same thickness.

[0148] The equivalent capacitance of the second gain conversion transistor DCG12 may be greater than the equivalent capacitance of the first gain conversion transistor DCG11 .

[0149] In a capacitor including a pair of spaced apart conductor plates, if the distance between the conductor plates is constant and a dielectric layer disposed between the conductor plates is formed of the same material, the capacitance of the capacitor may be proportional to the width of the conductor plates. Therefore, when the second gain conversion transistor DCG12 is formed by the same process as that of the first gain conversion transistor DCG11, the capacitance (C OG2 ) may be greater than the capacitance (C OG1 ).

[0150] Figure 5B is an equivalent circuit 50 b showing the total capacitance of the first gain conversion transistor DCG11 and the second gain conversion transistor DCG12 .

[0151] It can be seen that in the capacitor formed in the first gain conversion transistor DCG11, there is an overlap capacitance C OD1 , C OG1 and C OS1 The capacitor is connected in parallel to the first gate 322 of the first gain conversion transistor DCG11.

[0152] In addition, it can be seen that in the capacitor formed in the first gain conversion transistor DCG11, there is a junction capacitance C JD1 , C JC1 and C JS1 The capacitor is coupled in parallel to the first channel region 512 of the first gain conversion transistor DCG11. This is because when a voltage having an activation level is applied to the first gate 322, the source 330 and the drain 320 are electrically coupled to each other through the first channel region 512.

[0153] Therefore, the total capacitance of the first gain conversion transistor DCG11 associated with the first sensing node SN1 coupled to the source 330 of the first gain conversion transistor DCG11 may be determined by the overlap capacitance C OD1 , C OG1 and C OS1 and junction capacitance C JD1 , C JC1 and C JS1 It is represented by the sum of .

[0154] In contrast, since the fourth and fifth doping regions 340 and 350 are grounded and the semiconductor substrate 500 is grounded, the capacitor having the junction capacitance among the capacitors formed in the second gain conversion transistor DCG12 may not affect the total capacitance of the second gain conversion transistor DCG12 .

[0155] Therefore, the total capacitance of the second gain conversion transistor DCG12 associated with the second gate 332 can be given by the overlap capacitance C OD2 , C OG2 and C OS2 It is represented by the sum of .

[0156] As previously in Figure 5A As described above, when the capacitance (C OG1 ) is less than the capacitance (C OG2 ), the overlap capacitance C of the first gain conversion transistor DCG11 directly connected to the first sensing node SN1 OD1 , C OG1 and C OS1 and junction capacitance C JD1 , C JC1 and C JS1 The sum of the capacitance C of the second gain conversion transistor DCG12 may be less than the overlap capacitance C of the second gain conversion transistor DCG12. OD2 , C OG2 and C OS2 The sum of .

[0157] When the total capacitance of the first gain conversion transistor DCG11 is smaller than the total capacitance of the first gain conversion transistor DCG12 , the amount of band noise applied through the gain conversion signal line can be reduced.

[0158] When the gain conversion signal DCGS having an activation level is applied to the first gate 322 , the second gate 332 and the first sensing node SN1 may be electrically coupled to each other.

[0159] When the second gate 332 is electrically coupled to the first sensing node SN1 , the sum of the capacitance of the first sensing node SN1 may increase, so that the conversion gain of the image sensor 100 can be reduced.

[0160] Figure 6 is a schematic diagram 60 showing an example of third unit pixels 615 arranged in a row within the pixel array 110 of the image sensor 100 based on other implementations of the disclosed technology.

[0161] In some other implementations, Figure 2 The third unit pixel 615 may include a photodiode region and a transistor region in the same manner as the first unit pixel 315 and the second unit pixel 415 shown. In this case, the photodiode region may include eight photodiodes PD1 to PD8, eight transfer transistor gates TG1 to TG8, and two floating diffusion (FD) regions FD11 and FD12. The transistor region may include a reset transistor RX1, a first gain conversion transistor DCG1, a second gain conversion transistor DCG2, a drive transistor DX1, and a select transistor SX1.

[0162] However, the second gain conversion transistor DCG2 of the third unit pixel 615 may also include a 2 ) is coupled to an additional doped region 690 of the second gate 632 of the second gain conversion transistor DCG2.

[0163] because Figure 6 The other components included in the third unit pixel 615 are structurally similar to those in FIG. Figure 2 The first unit pixel 315 and the second unit pixel 415 are substantially the same, so for ease of description, the following description will be given around the additional doping region 690. Due to the presence of the additional doping region 690, Figure 6 The total equivalent capacitance of the second gain conversion transistor DCG2 shown may be different from the total equivalent capacitance of the above-described implementation.

[0164] The first to eighth photodiodes PD1-PD8 included in the third unit pixel 615 may be coupled to the first floating diffusion (FD) region FD11 or the second floating diffusion (FD) region FD2 through the first to eighth transfer transistor gates TG1-TG8. In this case, the floating diffusion (FD) region FD1 or FD2 may operate as a drain of each transfer transistor, and the photodiodes PD1-PD8 may operate as a source of each transfer transistor.

[0165] The first to eighth transmission signal lines (not shown) may be connected to the first to eighth transmission transistor gates TG1 to TG8, respectively. When a transmission signal having an activation level voltage is applied to each of the first to eighth transmission transistor gates TG1 to TG8, the first to eighth transmission transistors may transfer photocharges from each of the first to eighth photodiodes PD1 to PD8 to the first floating diffusion (FD) region FD1 or the second floating diffusion (FD) region FD2.

[0166] The first floating diffusion (FD) region FD1 is connected to the first metal line (M 1 ) is electrically coupled to a second floating diffusion (FD) region FD2, thereby forming a first sensing node.

[0167] The first and second floating diffusion (FD) regions FD1 and FD2 may share a reset transistor RX1 , a first gain conversion transistor DCG1 , a second gain conversion transistor DCG2 , a drive transistor DX1 , and a select transistor SX1 .

[0168] The reset transistor RX1, the first gain conversion transistor DCG11, the second gain conversion transistor DCG12, the drive transistor DX1 and the selection transistor SX1 can be referred to as shared transistors. The structural relationship and connection relationship between the shared transistors RX1, DCG1, DCG2, DX1 and SX1 can be similar to Figure 2 The structural relationships and connection relationships are basically the same.

[0169] The reset transistor RX1 may include a first doping region 610, a second doping region 620, and a reset gate 612. The first doping region 610 may operate as a drain of the reset transistor RX1. The second doping region 620 may operate as a source of the reset transistor RX1.

[0170] A power supply voltage VDD (not shown) may be applied to the first doping region 610. The reset transistor RX1 may be coupled to the first gain conversion transistor DCG1 through the second doping region 620.

[0171] The reset gate 612 may include at least one of a metal layer and a doped silicon layer, and may be coupled to a reset signal line (not shown).

[0172] The first gain conversion transistor DCG1 may include a third doping region 630, a second doping region 620, and a first gate 622. The first sensing node may be coupled to the third doping region 630 corresponding to one end of the first gain conversion transistor DCG1.

[0173] The second doping region 620 may operate as a drain of the first gain conversion transistor DCG1. The third doping region 630 may operate as a source of the first gain conversion transistor DCG1.

[0174] The first gate 622 may include at least one of a metal layer and a doped silicon layer, and may be coupled to the gain conversion signal line 600 .

[0175] The second gain conversion transistor DCG2 may include a fifth doping region 650 , a fourth doping region 640 , and a second gate 632 , and may further include an additional doping region 690 .

[0176] The fourth doping region 640 may operate as a drain of the second gain conversion transistor DCG2. The fifth doping region 650 may operate as a source of the second gain conversion transistor DCG2.

[0177] The additional doping region 690 may be a doping region that does not operate as a source or drain of a transistor. The additional doping region 690 may be a doping region formed deeper than each of the first to eighth doping regions 610 to 680 and may operate as a capacitor. Fig. 8A The detailed structure of the additional doping region 690 is described.

[0178] The second gate 632 can be connected by a second metal line (M 2 ) is coupled to the second doping region 620. A ground voltage GND may be applied to the fifth doping region 650 and the fourth doping region 640.

[0179] The second gate 632 may be coupled to the second doping region 620 , and a ground voltage GND may be applied to the fifth doping region 650 and the fourth doping region 640 , so that the second gain conversion transistor DCG2 may operate as a capacitive element.

[0180] In addition, the second gate 632 can be connected through the second metal line (M 2 ) is connected to the additional doping region 690. The ground voltage GND may also be applied to the additional doping region 690, so that the second gain conversion transistor DCG2 can obtain additional capacitance due to the existence of the additional doping region 690.

[0181] Due to the presence of the additional doped region 690, the equivalent capacitance of the second gain conversion transistor DCG2 can be Figure 2 The first unit pixel 315 and Figure 2 The equivalent capacitance of the second unit pixel 415 is shown to be different.

[0182] The equivalent capacitance of the second gain conversion transistor DCG2 can be determined by the overlap capacitance between the fifth doping region 650 and the second gate 632, the overlap capacitance between the second gate 632 and the second channel region, the overlap capacitance between the fourth doping region 640 and the second gate 632, the junction capacitance between the additional doping region 690 and the semiconductor substrate, etc. Fig. 8A and Figure 8B A detailed equivalent capacitance of the second gain conversion transistor DCG2 is described.

[0183] The first sensing node of the third unit pixel 615 may be coupled to the driving gate 652 of the driving transistor DX1. The driving transistor DX1 may include an eighth doping region 680, a seventh doping region 670, and a driving gate 652.

[0184] The seventh doping region 670 may operate as a drain of the driving transistor DX1. The eighth doping region 680 may operate as a source of the driving transistor DX1.

[0185] A power supply voltage VDD (not shown) may be applied to the eighth doping region 680. The seventh doping region 670 may be included in the selection transistor SX1. Therefore, the driving transistor DX1 may be coupled to the selection transistor SX1.

[0186] The driving gate 652 of the driving transistor DX1 may include at least one of a metal layer and a doped silicon layer.

[0187] The driving transistor DX1 may operate as a source follower transistor. The driving transistor DX1 may amplify a voltage level change of the first sensing node.

[0188] The selection transistor SX1 may include a seventh doping region 670, a sixth doping region 660, and a selection gate 642. The selection transistor SX1 may selectively output a signal amplified by the driving transistor SX1 in response to a voltage received through a selection signal line (not shown) coupled to the selection gate 642.

[0189] Figure 7 Some implementations based on the disclosed technology are shown Figure 6 An example circuit diagram 70 of a third unit pixel 615 is shown.

[0190] Figure 7 A connection relationship between constituent elements (eg, a photodiode, a floating diffusion (FD) region, a transistor, etc.) included in the third unit pixel 615 is shown. Figure 7 The constituent elements (eg, photodiodes, floating diffusion (FD) regions, transistors, etc.) shown in FIG. 1 can be similar to those in FIG. 1 in terms of functions and connection relationships. Figure 2 and Figure 4The constituent elements of are substantially the same. Therefore, for the sake of brevity, redundant descriptions will be omitted.

[0191] and Figure 4 different, Figure 7 The second gain conversion transistor DCG2 shown may include a capacitive element C formed by an additional doping region 690 and may be formed by Figure 7 The equivalent circuit diagram shown is shown.

[0192] Whether the second gain conversion transistor DCG2 is coupled to the first sensing node SN1 is determined based on the gain conversion signal DCGS applied to the first gain conversion transistor DCG1. The sum of the capacitances of the sensing node SN1 may be changed based on whether the second gain conversion transistor DCG2 is coupled to the first sensing node SN1.

[0193] Fig. 8A is a diagram showing some implementations based on the disclosed technology. Figure 6 The cross-sectional view 80 a of an example of the first gain conversion transistor DCG1 and the second gain conversion transistor DCG2 is taken along the second cutting line BB′.

[0194] Figure 8B Some implementations based on the disclosed technology are shown Figure 6 A circuit diagram of an example of equivalent capacitance of the first gain conversion transistor DCG1 and the second gain conversion transistor DCG2 is shown.

[0195] Fig. 8A The capacitance C caused by the doped region or gate of the first gain conversion transistor DCG1 is shown. OD1 , C OG1 , C OS1 , C JD1 , C JC1 and C JS1 .also, Fig. 8A The capacitance C caused by the doped region or gate of the second gain conversion transistor DCG2 is shown. OD2 , C OG2 and C OS2 , and the capacitance C caused by the additional doped region 690 JE .

[0196] The first gain conversion transistor DCG1 may include a first gate 622, a third doping region 630, and a second doping region 620. The third doping region 630 may operate as a source of the first gain conversion transistor DCG1, and the second doping region 620 may operate as a drain of the first gain conversion transistor DCG1. Each of the third doping region 630 and the second doping region 620 may include a region doped with a conductivity type opposite to that of the semiconductor substrate 800.

[0197] The first channel region 812 of the first gain conversion transistor DCG1 may be formed in the semiconductor substrate 800 between the third doping region 630 and the second doping region 620. The first channel region 812 may be a region doped with a doping density different from that of the third doping region 630 and the second doping region 620, or may be a region doped with a conductivity type different from that of the third doping region 630 and the second doping region 620.

[0198] The first dielectric layer 810 may be formed to overlap the third doping region 630, the second doping region 620, and the first channel region 812. In addition, the first gate 622 may be formed to overlap the first dielectric layer 810.

[0199] If a gain conversion signal DCGS having a voltage of a logic high level is applied to the first gate 622 , photo charges may move from the third doping region 630 to the second doping region 620 through the first channel region 812 .

[0200] The total equivalent capacitance of the first gain conversion transistor DCG1 can be calculated by the overlap capacitance (C OD1 ), the overlap capacitance (C OG1 ), the overlap capacitance (C OS1 ), the junction capacitance (C JD1 ), the junction capacitance (C JC1 ) and the junction capacitance (C JS1 ) is used to represent it. Figure 8B Describe the total capacitance of the first gain conversion transistor DCG1.

[0201] The second gain conversion transistor DCG2 may include a second gate 632, a fifth doping region 650, a fourth doping region 640, and an additional doping region 690. The fifth doping region 650 may operate as a source of the second gain conversion transistor DCG2, and the fourth doping region 640 may operate as a drain of the second gain conversion transistor DCG2. Each of the fifth doping region 650 and the fourth doping region 640 may include a region doped with a conductivity type opposite to that of the semiconductor substrate 800.

[0202] The additional doping region 690 may include a region doped with a conductivity type opposite to that of the semiconductor substrate 800. The additional doping region 690 may be formed deeper in the semiconductor substrate 800 than other doping regions.

[0203] The second channel region 822 of the second gain conversion transistor DCG2 may be formed in the semiconductor substrate 800 between the fifth doping region 650 and the fourth doping region 640. The second channel region 822 may be a region doped with a doping density different from that of the fifth doping region 650 and the fourth doping region 640, or may be a region doped with a conductivity type different from that of the fifth doping region 650 and the fourth doping region 640.

[0204] The second dielectric layer 820 may be formed to overlap the fifth doping region 650 serving as the source of the second gain conversion transistor DCG2, the fourth doping region 640 serving as the drain of the second gain conversion transistor DCG2, and the second channel region 822. In addition, the second gate 632 may be formed to overlap the second dielectric layer 820.

[0205] The additional doping region 690 included in the second gain conversion transistor DCG2 may operate as a capacitive element. The capacitance of the additional doping region 690 may vary according to a doping profile of the additional doping region 690. In this case, the doping profile may include a shape and depth of the doping region, a density of doping impurities, and the like.

[0206] The total capacitance of the second gain conversion transistor DCG2 can be calculated by the overlap capacitance (C OD2 ), the overlap capacitance (C OG2 ), the overlap capacitance (C OS2 ) and the junction capacitance (C JE ) to indicate.

[0207] The additional doped region 690 is coupled to the second gate 632, so that the junction capacitance (C JE ) can be added to the total capacitance of the second gain conversion transistor DCG2. Figure 8B Describe the total capacitance of the second gain conversion transistor DCG2.

[0208] Figure 8B is an equivalent circuit diagram 80b showing the total capacitance of the first gain conversion transistor DCG1 and the second gain conversion transistor DCG2.

[0209] The capacitor formed by the first gain conversion transistor DCG1 has an overlap capacitance C OD1 , C OG1 and C OS1 The capacitor may be coupled in parallel to the first gate 622 of the first gain conversion transistor DCG1.

[0210] In addition, the capacitor formed in the first gain conversion transistor DCG1 has a junction capacitance C JD1 , C JC1 and C JS1 The capacitor may be coupled in parallel to the first channel region 812 of the first gain conversion transistor DCG1. This is because when a voltage having an activation level is applied to the first gate 622, the source 630 and the drain 620 are electrically coupled to each other through the first channel region 812.

[0211] Therefore, the total capacitance of the first gain conversion transistor DCG1 associated with the first sensing node SN1 coupled to the source 630 of the first gain conversion transistor DCG1 may be determined by the overlap capacitance C OD1 , C OG1 and C OS1 and junction capacitance C JD1 , C JC1 and C JS1 It is represented by the sum of .

[0212] When a voltage having an activation level is applied to the first gate 622 , the second gate 632 may be electrically coupled to the first sensing node SN1 .

[0213] As previously in Figure 5B As described above, when the fourth doping region 640 and the fifth doping region 650 are grounded and the semiconductor substrate 800 is grounded, capacitors each having a junction capacitance among capacitors formed in the second gain conversion transistor DCG2 may not affect the total capacitance of the second gain conversion transistor DCG2.

[0214] However, the second gain conversion transistor DCG2 includes the additional doping region 690 , so that the equivalent capacitance of the second gain conversion transistor DCG2 with respect to the first sensing node SN1 may be increased.

[0215] The additional doping region 690 is coupled to the second gate 632, so that a capacitor (e.g., a capacitive element) coupled in parallel with the capacitor formed in the second gain conversion transistor DCG2 may be additionally formed. In this case, the capacitance of the additionally formed element may be determined by the junction capacitance (C JE ) to indicate.

[0216] Therefore, the total capacitance of the second gain conversion transistor DCG2 associated with the second gate 632 can be given by the overlap capacitance C OD2 , C OG2 and C OS2 and the junction capacitance (C JE ) is expressed as the sum of .

[0217] The equivalent capacitance of the second gain conversion transistor DCG2 is greater than the equivalent capacitance of the first gain conversion transistor DCG1 , so that the influence of band noise can be reduced and the gain conversion control characteristic of the image sensor 100 can be improved.

[0218] Fig. 9 is a schematic diagram 90 showing an example of fourth unit pixels 915 arranged in a row within the pixel array 110 of the image sensor 100 based on yet another implementation of the disclosed technology.

[0219] In some other implementations, Figure 2 In the same manner as the first unit pixel 315 and the second unit pixel 415 shown, the fourth unit pixel 915 may include a photodiode region and a transistor region. In this case, the photodiode region may include eight photodiodes PD1 to PD8, eight transfer transistor gates TG1 to TG8, and two floating diffusion (FD) regions FD1 and FD2. The transistor region may include a reset transistor RX1, a first gain conversion transistor DCG1, a second gain conversion transistor DCG2, a drive transistor DX1, and a select transistor SX1.

[0220] However, the fourth unit pixel 915 may further include a third gain conversion transistor DCG3 . A third gate 942 of the third gain conversion transistor DCG3 may be coupled to the second doping region 920 .

[0221] The other components included in the fourth unit pixel 915 may be similar in structure to Figure 2 The components of the first unit pixel 315 and the second unit pixel 415 are substantially the same, so for ease of description, the following description will be given around the third gain conversion transistor DCG3. Due to the presence of the third gain conversion transistor DCG3, the conversion gain of the image sensor 100 can be adjusted.

[0222] The first to eighth photodiodes PD1 to PD8 included in the fourth unit pixel 915 may be coupled to the first floating diffusion (FD) region FD1 or the second floating diffusion (FD) region FD2 through the first to eighth transfer transistor gates TG1 to TG8. In this case, the floating diffusion (FD) region FD1 or FD2 may operate as a drain of each transfer transistor and may operate as a source of each photodiode PD1 to PD8.

[0223] The first to eighth transmission signal lines (not shown) may be connected to the first to eighth transmission transistor gates TG1 to TG8, respectively. When a transmission signal having an activation level voltage is applied to each of the first to eighth transmission transistor gates TG1 to TG8, the first to eighth transmission transistors may transfer photocharges from each of the first to eighth photodiodes PD1 to PD8 to the first floating diffusion (FD) region FD1 or the second floating diffusion (FD) region FD2.

[0224] The first floating diffusion (FD) region FD1 is connected to the first metal line (M 1 ) is electrically coupled to a second floating diffusion (FD) region FD2, thereby forming a first sensing node.

[0225] The first and second floating diffusion (FD) regions FD1 and FD2 may share a reset transistor RX1 , a first gain conversion transistor DCG1 , a second gain conversion transistor DCG2 , a third gain conversion transistor DCG3 , a drive transistor DX1 , and a select transistor SX1 .

[0226] The reset transistor RX1, the first gain conversion transistor DCG1, the second gain conversion transistor DCG2, the third gain conversion transistor DCG3, the drive transistor DX1 and the selection transistor SX1 can be referred to as shared transistors. The structural relationship and connection relationship between the shared transistors RX1, DCG1, DCG2, DCG3, DX1 and SX1 can be similar to Figure 2 The structural relationship and connection relationship are basically the same.

[0227] The reset transistor RX1 may include a first doping region 910, a second doping region 920, and a reset gate 912. The first doping region 910 may operate as a drain of the reset transistor RX1. The second doping region 920 may operate as a source of the reset transistor RX1.

[0228] A power supply voltage VDD (not shown) may be applied to the first doping region 910. The reset transistor RX1 may be coupled to the first gain conversion transistor DCG1 through the second doping region 920.

[0229] The reset gate 912 may include at least one of a metal layer and a doped silicon layer, and may be coupled to a reset signal line (not shown).

[0230] The first gain conversion transistor DCG1 may include a third doping region 930, a second doping region 920, and a first gate 922. The first sensing node may be coupled to the third doping region 930 corresponding to one end of the first gain conversion transistor DCG1.

[0231] The second doping region 920 may operate as a drain of the first gain conversion transistor DCG1. The third doping region 930 may operate as a source of the first gain conversion transistor DCG1.

[0232] The first gate 922 may include at least one of a metal layer and a doped silicon layer, and may be coupled to the gain conversion signal line 900 .

[0233] The second gain conversion transistor DCG2 may include a fifth doping region 950 , a fourth doping region 940 , and a second gate 932 .

[0234] The fourth doping region 940 may operate as a drain of the second gain conversion transistor DCG2. The fifth doping region 950 may operate as a source of the second gain conversion transistor DCG2.

[0235] The second gate 932 may be coupled to the second doping region 920. A ground voltage GND may be applied to the fifth doping region 950 and the fourth doping region 940.

[0236] The second gate 932 may be coupled to the second doping region 920 , and a ground voltage GND may be applied to the fifth doping region 950 and the fourth doping region 940 , so that the second gain conversion transistor DCG2 may operate as a capacitive element.

[0237] The second gain conversion transistor DCG2 may be formed by a process similar to that of the first gain conversion transistor DCG1 .

[0238] In some other implementations, the image sensor may further include a third gain conversion transistor DCG3.

[0239] The third gain conversion transistor DCG3 may include a sixth doping region 960 , a fifth doping region 950 , and a third gate 942 .

[0240] The fifth doping region 950 may operate as a drain of the third gain conversion transistor DCG3. The sixth doping region 960 may operate as a source of the third gain conversion transistor DCG3.

[0241] The third gate 942 may be coupled to the second doping region 920. A ground voltage GND may be applied to the sixth doping region 960 and the fifth doping region 950.

[0242] The third gate 942 may be coupled to the second doping region 920 , and a ground voltage GND may be applied to the sixth doping region 960 and the fifth doping region 950 , so that the third gain conversion transistor DCG3 may operate as a capacitive element.

[0243] The third gain conversion transistor DCG3 may be formed by a process similar to that of the first gain conversion transistor DCG1 and the second gain conversion transistor DCG2 .

[0244] If the third gate 942 is coupled to the second doping region 920 and a gain conversion signal having an activation level or higher voltage is applied to the gate 922 of the first gain conversion transistor DCG1, the first, second and third gain conversion transistors DCG1, DCG2 and DCG3 may be electrically coupled to each other.

[0245] The fifth doped region 950 can operate as the source of the second gain conversion transistor DCG2 and can also operate as the drain of the third gain conversion transistor DCG3. However, in some other implementations, the drain of the third gain conversion transistor DCG3 and the source of the second gain conversion transistor DCG2 can also be isolated from each other as needed.

[0246] In addition, although for ease of description, Fig. 9 An example of a layout structure that also includes a third gain conversion transistor DCG3 is shown in FIG, but other implementations are also possible. For example, Fig. 9 The layout structure shown may be formed to be extended to an Nth gain conversion transistor (where "N" is an integer of 3 or greater) as desired.

[0247] The capacitance caused by the transistor coupled to the first sensing node through the first gain conversion transistor DCG1 may be controlled by adjusting the number of gain conversion transistors formed in the transistor region of the unit pixel.

[0248] The capacitance of the third gain conversion transistor DCG3 can be determined by the overlapping capacitance between the sixth doping region 960 and the third gate 942, the overlapping capacitance between the third gate 942 and the third channel region, the overlapping capacitance between the fifth doping region 950 and the third gate 942, the junction capacitance between the semiconductor substrate and the sixth doping region 960, the junction capacitance between the semiconductor substrate and the fifth doping region 950, and the junction capacitance between the third channel region and the semiconductor substrate.

[0249] The first sensing node of the fourth unit pixel 915 may be coupled to the driving gate 962 of the driving transistor DX1. The driving transistor DX1 may include a ninth doping region 990, an eighth doping region 980, and a driving gate 962.

[0250] The eighth doping region 980 may operate as a drain of the driving transistor DX1. The ninth doping region 990 may operate as a source of the driving transistor DX1.

[0251] A power supply voltage VDD (not shown) may be applied to the ninth doping region 990. The eighth doping region 980 may be included in the selection transistor SX1. Therefore, the driving transistor DX1 may be coupled to the selection transistor SX1.

[0252] The driving gate 962 of the driving transistor DX1 may include at least one of a metal layer and a doped silicon layer.

[0253] The driving transistor DX1 may operate as a source follower transistor. The driving transistor DX1 may amplify a voltage level change of the first sensing node.

[0254] The selection transistor SX1 may include an eighth doping region 980, a seventh doping region 970, and a selection gate 952. The selection transistor SX1 may selectively output a signal amplified by the driving transistor DX1 in response to a voltage signal received through a selection signal line (not shown) coupled to the selection gate 952.

[0255] As is apparent from the above description, the image sensing device including the gain conversion transistor can reduce band noise between pixels belonging to the same row.

[0256] Those skilled in the art will appreciate that the disclosed technology can be implemented in other ways than those set forth herein. Certain features described in the context of separate embodiments in this patent document can also be implemented in combination in a single embodiment. Relatively, the various features described in the context of a single embodiment can also be implemented separately in multiple embodiments or in any suitable sub-combination.

[0257] Although a number of illustrative embodiments of the disclosed technology have been described, various modifications or enhancements to the disclosed embodiments, as well as other embodiments, can be devised based on what is described and / or illustrated in this patent document.

[0258] CROSS-REFERENCE TO RELATED APPLICATIONS

[0259] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2020-0112606, filed on September 3, 2020, the disclosure of which is incorporated by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: a plurality of unit pixels, wherein the plurality of unit pixels are arranged in a first row; as well as a gain conversion signal line coupled to each of the plurality of unit pixels and transmitting a gain conversion signal to each of the plurality of unit pixels, in, Each of the plurality of unit pixels comprises: a first gain conversion transistor including a first drain region, a first source region, and a first gate arranged and coupled to form a transistor, the first gate coupled to the gain conversion signal line, the first source region coupled to a sense node; a second gain conversion transistor, the second gain conversion transistor comprising a second drain region, a second source region, and a second gate arranged and coupled to form a transistor, wherein the second gate is coupled to the first drain region of the first gain conversion transistor, and the second gain conversion transistor exhibits a capacitance greater than a capacitance of the first gain conversion transistor, Wherein, the second gain conversion transistor includes a channel region, the second source region and the second drain region arranged in a semiconductor substrate; a floating diffusion region coupled to the first source region of the first gain conversion transistor, wherein the second gain conversion transistor comprises an additional doped region coupled to the second gate, wherein the additional doped region is spaced apart from the second source region and the second drain region, wherein the additional doped region is disposed in the semiconductor substrate at a position deeper than the channel region, the second source region, and the second drain region of the second gain conversion transistor, and The first gain conversion transistor is turned on or off in response to a voltage level of a gain conversion signal applied to the first gate, so as to control the capacitance of the sensing node by adjusting the number of gain conversion transistors connected to the sensing node.

2. The image sensing device according to claim 1, wherein: The size of the second gate is larger than that of the first gate.

3. The image sensing device according to claim 1, wherein: The second gain conversion transistor comprises: A dielectric layer overlaps the channel, the second source region, and the second drain region.

4. The image sensing device according to claim 3, wherein: The second source region of the second gain conversion transistor and the second drain region of the second gain conversion transistor are grounded.

5. The image sensing device according to claim 3, wherein: The second gate overlaps the dielectric layer.

6. The image sensing device according to claim 1, further comprising: an Nth gain conversion transistor, the Nth gain conversion transistor comprising an Nth gate coupled to the first drain region of the first gain conversion transistor, wherein “N” is an integer of 3 or greater, The first gain conversion transistor, the second gain conversion transistor and the Nth gain conversion transistor are electrically coupled to each other in response to the first gain conversion transistor being turned on.

7. The image sensing device according to claim 6, wherein: The Nth gain conversion transistor comprises: a channel, an Nth source region, and an Nth drain region disposed in a semiconductor substrate; and A dielectric layer overlaps the channel, the Nth source region, and the Nth drain region.

8. The image sensing device according to claim 7, wherein: The Nth source region of the Nth gain conversion transistor and the Nth drain region of the Nth gain conversion transistor are grounded.

9. The image sensing device according to claim 7, wherein: The Nth gate overlaps the dielectric layer.

10. The image sensing device according to claim 7, wherein: The Nth gain conversion transistor further includes: An additional doped region is coupled to the Nth gate.

11. The image sensing device according to claim 10, wherein: The additional doping region is formed in the semiconductor substrate at a position deeper than each of the channel, the Nth source region, and the Nth drain region of the Nth gain conversion transistor.

12. The image sensing device according to claim 1, wherein: The gain conversion signal line turns on the first gain conversion transistor by transmitting a signal having a logic high level; and The gain conversion signal line turns off the first gain conversion transistor by transmitting a signal having a logic low level.

13. The image sensing device according to claim 12, wherein: The floating diffusion region and the second gain conversion transistor are electrically isolated from each other in response to turning off of the first gain conversion transistor.

14. An image sensing device, comprising: a plurality of unit pixels, the plurality of unit pixels including a first unit pixel and a second unit pixel arranged in the same row; as well as a gain conversion signal line coupled to the first unit pixel and the second unit pixel, in, Each of the first unit pixel and the second unit pixel includes: a first gain conversion transistor including a first terminal, a second terminal coupled to a sensing node, and a first gate coupled to the gain conversion signal line; a second gain conversion transistor, the second gain conversion transistor comprising a second gate, wherein the second gate is coupled to the first end of the first gain conversion transistor and the second gain conversion transistor exhibits a capacitance greater than a capacitance of the first gain conversion transistor, Wherein, the second gain conversion transistor includes a channel region, a second source region and a second drain region arranged in a semiconductor substrate; a floating diffusion region coupled to the second end of the first gain conversion transistor, wherein the second gain conversion transistor comprises an additional doped region coupled to the second gate, wherein the additional doped region is spaced apart from the second source region and the second drain region, wherein the additional doped region is disposed in the semiconductor substrate at a position deeper than the channel region, the second source region, and the second drain region of the second gain conversion transistor, and The first gain conversion transistor is turned on or off in response to a voltage level of a gain conversion signal applied to the first gate, so as to control the capacitance of the sensing node by adjusting the number of gain conversion transistors connected to the sensing node.

15. The image sensing device according to claim 14, wherein: Each of the first unit pixel and the second unit pixel further includes an additional floating diffusion region.

16. The image sensing device according to claim 15, wherein: For each of the first unit pixel and the second unit pixel, the floating diffusion region and the additional floating diffusion region are coupled to each other to provide the sensing node.

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