IC package with top-side memory module

Abstract

A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip electrically coupled to a top surface of the package substrate, iii) a first contact structure disposed on a bottom surface of the package substrate and electrically coupled to the first PCB, and iv) a second contact structure disposed on the top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips disposed on the second PCB, and iii) a third contact structure disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structure of the IC package with the third contact structure of the memory module.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 859,560, filed June 10, 2019, entitled “Ball Grid Array (BGA) Package Upper Connection to Memory Module,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention generally relates to integrated circuit (IC) packaging technology, and more particularly to IC packages having electrical connections on both the bottom and top surfaces of the IC package. Background Technology

[0004] Integrated circuit (IC) packaging involves a semiconductor die (also known as an IC chip) of an integrated circuit encased in a housing that protects the IC chip from physical damage, corrosion, etc. Additionally, electrical connection points, such as pins or pads, are provided outside the housing to allow electrical connections to the IC chip inside. The IC chip, housing, and electrical connection points are sometimes referred to as an IC package.

[0005] Ball grid array (BGA) is a surface-mount IC package in which an array of pads on the bottom surface of the BGA package allows for electrical connection to a printed circuit board (PCB). Each pad has an attached solder ball. The density of solder balls on a BGA package (sometimes measured by the distance between adjacent balls (pitch dimension)) has an upper limit. As a result, for larger, more complex IC chips with a greater number of input / output (I / O) connections, and a greater number of I / O connections requiring a greater number of solder balls, the overall size of the BGA package increases, which in turn increases its cost. Summary of the Invention

[0006] In one embodiment, a printed circuit board (PCB) system includes: a first PCB; an integrated circuit (IC) package including: i) a package substrate, ii) a main IC chip electrically coupled to a top surface of the package substrate, iii) a first contact structure disposed on a bottom surface of the package substrate and electrically coupled to the first PCB, and iv) a second contact structure disposed on the top surface of the package substrate; a memory module including: i) a second PCB, ii) one or more memory IC chips disposed on the top surface of the second PCB, and iii) a third contact structure disposed on the bottom surface of the second PCB; and an interposer disposed between the second contact structure of the IC package and the third contact structure of the memory module to electrically couple the second contact structure of the IC package to the third contact structure of the memory module.

[0007] In another embodiment, a method for assembling a PCB system includes: mounting an IC package onto a first PCB to electrically couple a first contact structure on a bottom surface of a package substrate of the IC package to the first PCB, the IC package including a main IC chip; stacking and aligning a memory module on the IC package, the memory module including: i) a second PCB, ii) one or more memory IC chips disposed on the second PCB, and iii) a second contact structure disposed on a bottom surface of the second PCB; and electrically coupling the second contact structure disposed on the bottom surface of the second PCB of the memory module to a third contact structure disposed on a top surface of the package substrate. Attached Figure Description

[0008] Figure 1A This is a top view illustration of an example printed circuit board (PCB) having an integrated circuit (IC) package disposed on a PCB according to one embodiment.

[0009] Figure 1B This illustrates a configuration according to one embodiment to be set in Figure 1A A top view of an exemplary memory module on an IC package.

[0010] Figure 1C This is a top view diagram illustrating an example PCB system according to one embodiment, the example PCB system including a top view diagram of a PCB system comprising ... Figure 1A The IC package shown Figure 1B The memory module.

[0011] Figures 2A to 2C According to one embodiment Figure 1C Different views of an example PCB system.

[0012] Figure 3 This is a flowchart of an example of assembling a PCB system according to one embodiment. Detailed Implementation

[0013] In the embodiments described below, a printed circuit board (PCB) system includes a first PCB and an integrated circuit (IC) package having i) a package substrate, ii) a main IC chip electrically coupled to a top surface of the package substrate, iii) a first contact structure disposed on a bottom surface of the package substrate and electrically coupled to the first PCB, and iv) a second contact structure disposed on the top surface of the package substrate. The PCB system also includes a memory module having i) a second PCB, ii) one or more memory IC chips disposed on the second PCB, and iii) a third contact structure disposed on the bottom surface of the second PCB. The PCB system further includes an interposer disposed between the second contact structure of the IC package and the third contact structure of the memory module to electrically couple the second contact structure of the IC package to the third contact structure of the memory module.

[0014] In some embodiments, because some input / output (I / O) connections for the IC chip are disposed on the top surface of the package substrate (e.g., the second contact structure), the number of I / O connections (e.g., the first contact structure) for the IC chip disposed on the bottom surface of the package substrate is less than if all I / O connections were disposed on the bottom surface of the package substrate, and thus the overall size of the IC package is reduced. For example, for ball grid array (BGA) packages, there is a practical upper limit to the density of solder balls, and therefore a large number of solder balls requires a larger IC package size. Therefore, in some embodiments where BGA packaging technology is used for the first contact structure in IC packaging, reducing the number of first contact structures helps to reduce the overall size of the IC package, thereby reducing the cost of the IC package.

[0015] Furthermore, according to some embodiments, since the number of I / O connections (e.g., first contact structures) of the IC chip disposed on the bottom surface of the package substrate is smaller (compared to if all I / O connections were disposed on the bottom surface of the package substrate), the number of traces electrically coupled to the first contact structures of the IC package is smaller. Therefore, according to some embodiments, the complexity of the first PCB is reduced (e.g., the number of layers is reduced) compared to a package substrate in which all I / O connections are disposed on the bottom surface of the package substrate, thereby reducing the cost of the first PCB.

[0016] Figure 1AThis is a top view illustration of an exemplary PCB 100 (sometimes referred to herein as a "main PCB") according to one embodiment. According to one embodiment, the PCB 100 includes an IC package 104 mounted on a top surface 108 of the PCB 100. The IC package 104 includes a substrate 112 having a top surface 116 and a bottom surface (not shown) opposite the top surface 116. An IC chip 120 is coupled to the top surface 116 of the substrate 112.

[0017] According to various embodiments, substrate 112 includes a suitable insulating material (also referred to as a dielectric material), such as an epoxy-based laminated substrate, a resin-based bismaleimide triazine (BT) substrate, etc. Substrate 112 is relatively rigid to provide mechanical support to IC chip 120. In some examples, substrate 112 includes multiple layers of metal traces, such as copper wires, with an insulating material between the multiple layers of metal traces. In different embodiments, traces on different layers are connected via conductive vias.

[0018] In one embodiment, electrical contact structures are formed on both the top surface 116 and the bottom surface to electrically connect the IC chip to electronic components outside the IC package 120, such as electronic components on the main PCB 100 and referenced components. Figure 1B The electronic components on the memory module are discussed.

[0019] The bottom surface of substrate 112 includes a plurality of I / O pads (not shown) serving as electronic contact structures, which allow electrical connection of PCB 100 to a first I / O of IC chip 120. In one embodiment, IC package 104 uses BGA technology, and a plurality of I / O pads (not shown) are arranged in an array, wherein solder balls (not shown) are connected to the plurality of I / O pads.

[0020] IC chip 120 can be any suitable integrated circuit chip, such as an integrated circuit processor, controller, transceiver, switching device, system-on-a-chip, etc. IC chip 120 includes various circuits for providing computing and / or processing functions. In some examples, IC chip 120 receives suitable signals, such as analog signals, digital signals, control signals, and data signals, from components outside IC package 104 and processes the received signals. In some examples, IC chip 120 generates suitable signals, such as analog signals, digital signals, control signals, and data signals, and outputs the generated signals to components outside IC package 104.

[0021] In one embodiment, IC package 104 is used in a high-speed network switching device for packet switching. For example, IC chip 120 includes core circuitry for packet processing and peripheral circuitry for interface (input / output) processing (e.g., receiving and / or transmitting signals carrying packets). In one example, IC chip 120 includes one or more packet processors configured to perform packet processing, including but not limited to packet forwarding. IC chip 120 also includes interface circuitry, such as modulation / demodulation circuitry, memory circuitry for queuing packets, etc.

[0022] Substrate 112 provides interconnects from the inputs / outputs of IC chip 121 to contact structures formed on the bottom and top surfaces 116 of substrate 112. According to one embodiment, IC chip 120 includes I / O pads (not shown) electrically connected to internal circuitry formed on IC chip 120, and the top surface 116 of substrate 112 includes solder bumps (not shown) that match bump structures on IC chip 120. IC chip 120 is disposed on top surface 116 such that the bump structures on IC chip 120 are aligned with the solder bumps on the top surface 116 of substrate 112. A reflow process is then performed to form the connection between the bump structures and the solder bumps.

[0023] In other embodiments, the IC chip 120 is wire-bonded to form an electrical connection with the substrate 112.

[0024] PCB 100 includes a plurality of pads (not shown) disposed on a top surface 108 of PCB 100. These pads are positioned corresponding to and electrically connected to a plurality of I / O pads (not shown) on the bottom surface of IC package 104. In embodiments where IC package 104 uses BGA technology, the plurality of pads (not shown) disposed on the top surface 108 of PCB 100 are electrically connected to the plurality of I / O pads (not shown) on the bottom surface of IC package 104 using a plurality of solder balls.

[0025] PCB 100 also includes multiple traces 124 electrically coupled to multiple pads (not shown) disposed on the top surface 108 of PCB 100 and electrically connected to multiple I / O pads (not shown) on the bottom surface of IC package 104. The traces 124 electrically couple other electronic components (not shown) disposed on PCB 100 to the first I / O of IC chip 120.

[0026] IC package 104 also includes a cover 140 that covers IC chip 120 while leaving the peripheral portion of the top surface 116 of substrate 112 uncovered. In one embodiment, cover 140 includes a heat slug that facilitates heat dissipation from IC chip 120 during operation. In some embodiments, cover 140 includes a metallic material covering IC chip 120, for example, to protect IC chip 120 and aid in heat dissipation during operation when IC chip 120 is powered on.

[0027] Multiple interposers 152 are disposed on the top surface 116 of the substrate 112 of the IC package 104. In one embodiment, each interposer 152 includes multiple contact structures electrically connected to multiple traces (not shown) on the substrate 112. The multiple traces (not shown) on the substrate 112 electrically couple a second I / O of the IC chip 120 to the contact structures of the interposer 152. In an illustrative example, according to one embodiment, each interposer 152 includes multiple compression contacts on at least one side of the interposer 152, which allow (combined) Figure 1B and Figure 1C The described memory module is electrically coupled to a second I / O of the IC chip 120. For example, according to one embodiment, the PCB system 100 includes components configured to connect to the PCB 100 and (in conjunction with...) Figure 1B and Figure 1C The force component described applies compressive force to the memory module to electrically couple the memory module to the second I / O of the IC chip 120.

[0028] Figure 1B This is a top view of an exemplary memory module 156 according to one embodiment, the memory module 156 being configured to be installed in... Figure 1A The IC is packaged on top of the IC 104 and connected via multiple interpolators 152. Figure 1A Electrically coupled to IC chip 120 ( Figure 1A ).

[0029] Memory module 156 includes one or more memory ICs 160 disposed on PCB 164, which is sometimes referred to herein as "memory module PCB 164". Memory module PCB 164 has a top surface 166 and a bottom surface (not shown). In one embodiment, one or more memory ICs 160 are disposed on the top surface 166 of memory module PCB 164. In another embodiment, one or more memory ICs 160 are disposed on the bottom surface 166 of memory module PCB 164.

[0030] In some embodiments, no processor IC is disposed on the memory module PCB 164, and the memory module 156 is free from any processor IC. In some embodiments, no ICs other than the memory IC are disposed on the memory module PCB 164, and the memory module 156 is free from any ICs other than the memory IC. In other embodiments, a processor IC is disposed on the memory module PCB 164 in addition to one or more memory ICs 160. In some embodiments, in addition to one or more memory ICs 160, one or more ICs different from the memory IC and the processor IC are disposed on the memory module PCB 164.

[0031] The memory module PCB 164 includes multiple outer edges 168 and multiple inner edges 172 forming openings 176 in the PCB memory module 164. The openings 176 are sized to accommodate an IC package 104. Figure 1A ) of the cover 140, such as combining Figure 1C As described. PCB memory module 164 includes a plurality of electrical contact structures 180 disposed on the bottom surface of memory module PCB 164 adjacent to the inner edge 172 of PCB memory module 164. In one embodiment, the electrical contact structures 180 are disposed around an opening 176. The electrical contact structures 180 are configured to contact the IC package 104 when memory module 156 is mounted on IC package 104. Figure 1A The internal connector 152 is electrically connected as follows: Figure 1C The subject of discussion.

[0032] The memory module PCB 164 includes multiple traces 184 that electrically couple the memory IC 160 to the electrical contact structure 180.

[0033] According to some embodiments, the memory module PCB 164 has significantly fewer components than the main PCB 100, and is therefore smaller and has fewer layers. As a result, according to some embodiments, the cost of the memory module PCB 164 is significantly lower than that of the main PCB 100. Furthermore, by placing the memory IC 160 on the memory module PCB 164 instead of the main PCB 100, the number of layers on the main PCB 100 can be reduced (compared to the main PCB on which the memory IC 160 is located), thereby reducing the cost of the main PCB 100 at least in some embodiments. Moreover, at least in some embodiments, by placing the memory IC 160 on the memory module PCB 164 instead of the main PCB 100, the memory IC 160 can be positioned closer to the IC chip 120 (compared to the main PCB on which the memory IC 160 is located), thereby improving performance.

[0034] According to one embodiment, the density of electrical contacts 180 is higher than the density of BGA solder balls on the bottom surface of IC package 104.

[0035] Figure 1C This illustrates a method including, according to one embodiment Figure 1A A top view of an example PCB system 192 of PCB 100, wherein Figure 1B Example memory module 156 is mounted on IC package 104. Electrical contact structure 180 is electrically connected to interposer 152. Figure 1A ,and Figure 1C (Not shown in the diagram). As a result, the second I / O of IC chip 120 is connected via interposer 152, electrical contact structure 180 and trace 124 of memory module PCB 164. Figure 1B Now Figure 1C (As shown in the diagram) Electrically coupled to memory IC 160. The cover 140 of IC package 104 is housed within opening 176. Figure 1B Now Figure 1C (as shown in the image).

[0036] Although memory module 156 is described above as a corresponding monolithic module including an integrated memory module PCB 164, in other embodiments, memory module 156 includes multiple separate sub-modules, each with a corresponding PCB, such as... Figure 1B and Figure 1C As indicated by the dashed line 192 in the middle.

[0037] Figures 2A to 2C According to one embodiment Figure 1C Different views of the PCB system 192 are shown, but only a portion of the memory module 156 (or just a single memory submodule) is shown to help illustrate the PCB system 192. Figure 2A A perspective view of the PCB system 192 is shown (but only a portion of the memory module 156 is shown, or only a single memory sub-module is shown). Figure 2B A cross-sectional view of the PCB system 192 is shown (but only a portion of the memory module 156 is shown), and Figure 1C A top view of the PCB system 192 is shown (but only a portion of the memory module 156 is shown, or only a single memory sub-module is shown).

[0038] exist Figures 2A to 2C In the example shown, substrate 112 includes contact structures 204 formed on the top surface 116 of substrate 112. In one embodiment, substrate 112 includes metal traces (not shown) that electrically connect solder bumps (on which IC chip 120 is attached) to contact structures 204.

[0039] According to one aspect of this disclosure, the contact structure 204 and the IC chip 120 are disposed on the same surface side of the substrate 112. In some embodiments, the contact structure 204 is disposed in a peripheral region surrounding the substrate 112 of the IC chip 120, such as the region between the cover 140 of the IC chip 120 and the edge of the substrate 112.

[0040] Contact structure 204 is any suitable contact structure. In one embodiment, each of at least some of the contact structures 204 includes a pad and a solder ball deposited on the pad. In another embodiment, each of at least some of the contact structures 204 includes a pad. In yet another embodiment, each of at least some of the contact structures 204 includes a pin.

[0041] exist Figure 2A In this embodiment, contact structure 204 is shown as circular. In other embodiments, contact structure 204 may have other suitable shapes, such as spherical, square, pin-shaped, etc.

[0042] Contact structure 204 is configured to be electrically connected to other components using appropriate technology. For example, in one embodiment, contact structure 204 is configured to be electrically connected to electrical contacts 180 on memory module 156 via interposer 152.

[0043] More specifically, the interposer 152 includes a plurality of interconnect structures 212 to electrically connect corresponding contact structures 216 of the electrical contacts 180 on the memory module 156 to contact structures 204 of the IC package 104. Each interconnect structure 212 is configured to form a first connection with the second contact structure 204 and a second connection with the contact structure 216 using appropriate techniques. In one embodiment, each interconnect structure 212 is a dual compression structure using compression connections for the first and second connections. In another embodiment, each interconnect structure 212 is a single compression structure with solder balls, the single compression connection using solder balls for the first connection and compression connections for the second connection.

[0044] Figure 2A This includes a close-up view of one side of an interconnect structure 212 configured for clamping connections according to one embodiment. According to one embodiment, the interconnect structure 212 includes a metal tongue 220 projecting from the surface of an inserter 152, and the metal tongue 220 can be pushed into the surface under compressive force. In other embodiments, other suitable interconnect structures different from the interconnect structure 212 are used.

[0045] In one embodiment, the PCB system 100 includes a force-generating component that applies a compressive force to cause the interposer 152 to interconnect the memory module 156 with the contact structure 204. For example, the main PCB 100 and the memory module 156 are designed and manufactured with holes that can be aligned to accommodate bolts. After the IC package 104 is mounted on the main PCB 100, the interposer 152 and the memory module 156 are aligned and stacked. Note that suitable spacers 224 can be inserted to level the memory module 156 on the main PCB 100. Bolts 228 and 232 are then tightened to corresponding nuts 236 and 240 to lock the stacked first PCB 110, interposer 130, and PCB module 140 into place and apply a compressive force to cause the interposer 152 to interconnect the contact structure 216 of the memory module 156 with the contact structure 204 of the IC package 104.

[0046] In various embodiments, the main PCB 100 and the memory module PCB 164 each include multiple layers of metal traces, such as copper wires, disposed on a multilayer sandwich structure of dielectric material. In some examples, the main PCB 100 and the memory module PCB 164 have different numbers of metal layers. For example, the main PCB 100 has more metal layers than the memory module PCB 164. The memory module PCB 164 provides additional electrical connection support for the memory IC 160 and any other suitable electronic components (if any), such as other IC packages, resistors, diodes, capacitors, transistors, etc.

[0047] According to one aspect of the invention, the interpolator 152 has a high density and low profile. In one example, the interpolator 152 has a 0.80 mm pitch grid (e.g., smaller than the solder ball pitch for a typical BGA) and a 1 mm body height (0.33 mm for the shortest signal path). Therefore, in one example, the distance between the main PCB 100 and the memory module PCB 164 is less than the height of the IC package 104.

[0048] In one embodiment, the pitch grid of the interposer 152 is smaller than the BGA solder ball pitch requirement. In one example, the density of contact structures 204 on the top surface 116 of the IC package 104 is higher than the density of BGA solder balls on the bottom surface of the IC package 104. In some embodiments, the smaller pitch grid and / or density of contact structures 204 of the interposer 152 allows for a smaller size of the IC package substrate 112, thus reducing the cost of the IC package 104, compared to the case where the density of the pitch grid and / or the density of the contact structures 204 of the interposer 152 is the same as the BGA solder ball pitch requirement.

[0049] In one embodiment, the electrical connection from the contact structure 204 of the IC package 104 to the memory module 156 via the interposer 130 provides a relatively short signal path compared to electrical connection technologies such as plated through-hole (PTH) vias, PCB PTHs, PCBs, etc. Therefore, the electrical connection from the contact structure 204 via the interposer 152 to the memory module 156 has less attenuation than other interconnect technologies and can therefore be used for higher speed signals.

[0050] like Figure 2B As shown, substrate 112 includes contact structures 260 formed on the bottom surface 264 of substrate 112. In one embodiment, substrate 112 includes metal traces (not shown) that electrically connect solder bumps (on which IC chip 120 is attached) to the contact structures 260. In one embodiment, IC package 104 is a BGA package, and each first contact structure 260 includes a pad and solder balls deposited on the pad. In another embodiment, IC package 104 is a planar grid array (LGA) package, and each first contact structure 260 includes a pad. In yet another embodiment, IC package 104 is a pin grid array (PGA) package, and each first contact structure 260 includes a pin.

[0051] Note that in some embodiments, the second contact structure 204 on the top surface 116 of the substrate 112 is implemented using a different technique than the contact structure 260 on the bottom surface 264 of the substrate 112. For example, according to one embodiment, the contact structure 260 is implemented using pads and solder balls, and the contact structure 204 is implemented using pads without solder.

[0052] According to one aspect of this disclosure, the contact structures 260 are configured to be electrically connected to components using suitable techniques. In one example, the contact structures 260 are configured to achieve electrical connections to the main PCB 100 using soldering techniques. For example, when the IC package 104 is mounted on the main PCB 100, a reflow soldering process is performed to form solder joints, thus connecting the contact structures 260 to corresponding contact structures on the main PCB 100.

[0053] Now for reference Figures 1A to 1C and Figures 2A to 2BIn some embodiments, IC chip 120 includes a processor (such as a packet processor for switching devices, a central processing unit (CPU), a digital signal processor (DSP), etc.), and memory IC 160 includes memory devices (e.g., random access memory (RAM), read-only memory (ROM), solid-state memory such as flash memory, etc.) that are used by the processor when performing processing tasks, operations, etc. The processor on IC chip 120 accesses memory IC 160 via contact structure 204, interposer 152, and electrical contact 180.

[0054] Because the memory IC 160 is disposed on the memory module 156, and the IC chip 120 can access the memory IC 160 via contact structures 204 on the top surface 116 of the package substrate 112 instead of via contact structures 260 on the bottom surface 264 of the package substrate 112, the number of contact structures 260 on the bottom surface 264 of the package substrate 112 is reduced, which allows for a reduction in the size of the package substrate 112. The manufacture of the package substrate 112 is typically relatively expensive (compared to a typical PCB and memory module PCB 164), and the cost of the substrate 112 increases with its size. Therefore, according to some embodiments, reducing the size of the package substrate 112 reduces its cost. Furthermore, because the memory IC 160 is disposed on the memory module 156, and the IC chip 120 can access the memory IC 160 via contact structures 204 on the top surface 116 of the package substrate 112 instead of via contact structures 260 on the bottom surface 264 of the package substrate 112, the number of I / Os in the BGA on the bottom side of the package substrate 112 is reduced. This reduces the number of vias in the package substrate 112 from the top side 166 to the bottom side of the package substrate 112. Additionally, at least in some embodiments, the number of layers in the package substrate 112 is reduced because of the number of vias passing through multiple layers of the package substrate 112. According to some embodiments, the relaxation of the required number of vias and / or the reduction of the number of layers in the package substrate 112 also reduces the cost of the package substrate 112.

[0055] Furthermore, according to some embodiments, because the memory IC 160 is disposed on the memory module 156 instead of the main PCB 100, the complexity of the main PCB 100 is also reduced, for example, by reducing the number of layers in the PCB 100. The cost of the PCB 100 typically increases with the number of layers. Therefore, according to some embodiments, reducing the number of layers in the PCB 100 reduces the cost of the PCB 100.

[0056] Furthermore, according to some embodiments, because the memory IC 160 is disposed on the memory module 156 rather than on the main PCB 100 having other components electrically coupled to the IC package 104, the memory IC 160 can be positioned closer to the IC package 104 compared to if the memory IC 160 were disposed on the main PCB 100. For example, if the memory IC 160 were disposed on the main PCB 100, the memory IC 160 would need to be located further away from the IC package 104 (compared to PCB system 192) to allow wiring traces between the IC package 104 and other components on the main PCB 100. At least in some embodiments, performance is improved by positioning the memory IC closer to the IC package 104.

[0057] Figure 3 This is a flowchart of an example method 300 for assembling a PCB system according to one embodiment. In one embodiment, method 300 is performed to assemble a PCB system, as shown in the above reference. Figures 1A to 1C and Figures 2A to 2C The exemplary PCB system 192 described herein, and referenced herein. Figures 1A to 1C and Figures 2A to 2C Method 300 is described for illustrative purposes only. In other embodiments, method 300 is performed to assemble a suitable PCB system different from the exemplary PCB system 192.

[0058] In block 304, the IC package is mounted to the first PCB by coupling a first contact structure of the IC package to the first PCB. For example, according to one embodiment, the IC package 104 is mounted on a main PCB 100. More specifically, according to one embodiment, contact structure 260 is aligned with and connected to a corresponding contact structure on the main PCB 100. In the example, a reflow soldering process is performed to form a solder joint that forms an electrical connection between the IC package 104 and the main PCB 100, wherein contact structure 260 is connected to a corresponding contact structure on the main PCB 100.

[0059] In block 308, memory modules are stacked on and aligned with an IC package. In one embodiment, block 308 includes an interposer (e.g., interposer 152) disposed between the memory module (e.g., memory module 156) and the IC package (e.g., IC package 104). In one embodiment, block 308 includes aligning the interposer 152 with a contact structure 204 on the IC package 104. In one embodiment, the memory module PCB 164 and main PCB 100 of memory module 156 are designed and manufactured to have holes that can be aligned to accommodate bolts or other suitable fasteners.

[0060] At block 312, the memory module is electrically connected to the IC package. In one embodiment, electrically connecting the memory module to the IC package at block 312 includes pressing the memory module to the IC package together using mechanical fasteners to apply a clamping force to an interposer positioned between the memory module and the IC package. For example, bolts 112 and 114 are fastened to corresponding nuts 113 and 115 to press the main PCB 110 and the memory module 156 together to apply a force compressing the interposer 152, which causes the interposer 152 to interconnect the contact structure 216 of the memory module 156 with the contact structure 204 of the IC package 104.

[0061] Note that in various embodiments, other suitable method actions may be performed before method 300, between steps in method 300, and / or after method 300 for semiconductor device fabrication. As an illustrative example, according to one embodiment, a memory module 156 is mounted to IC package 104 before IC package 104 is mounted to main PCB 100.

[0062] Example 1: A printed circuit board (PCB) system includes: a first PCB; an integrated circuit (IC) package, the IC package including: i) a package substrate, ii) a main IC chip electrically coupled to the top surface of the package substrate, iii) a first contact structure disposed on the bottom surface of the package substrate and electrically coupled to the first PCB, and iv) a second contact structure disposed on the top surface of the package substrate; a memory module including: i) a second PCB, ii) one or more memory IC chips disposed on the top surface of the second PCB, and iii) a third contact structure disposed on the bottom surface of the second PCB; and an interposer disposed between the second contact structure of the IC package and the third contact structure of the memory module to electrically couple the second contact structure of the IC package to the third contact structure of the memory module.

[0063] Example 2: According to the PCB system of Example 1, wherein the interposer is configured to provide a compression contact on at least one side of the interposer to electrically couple the second contact structure of the IC package to the third contact structure of the memory module.

[0064] Example 3: A PCB system according to any one of Examples 1 or 2, wherein: the memory module includes a plurality of separate memory sub-modules; and the second PCB includes a plurality of separate second PCBs respectively corresponding to the plurality of separate memory sub-modules, each separate second PCB having one or more memory IC chips disposed on the top surface of the separate second PCB, and iii) a subset of the third contact structures disposed on the bottom surface of the separate second PCB.

[0065] Example 4: A PCB system according to any one of Examples 1 or 2, wherein the memory module includes an integral second PCB.

[0066] Example 5: A PCB system according to any one of Examples 1-4, wherein: the IC package includes a cover surrounding the main IC chip and covering the second contact structure disposed on the top surface of the package substrate; the second PCB of the memory module includes: i) a plurality of outer edges and ii) a plurality of inner edges defining openings; and wherein the cover of the IC package is disposed within the openings defined by the plurality of inner edges of the second PCB.

[0067] Example 6: The PCB system according to Example 5, wherein: the cover surrounding the main IC chip includes a heat sink; wherein the heat sink is disposed within the opening defined by the plurality of inner edges of the second PCB.

[0068] Example 7: According to the PCB system of Example 5, wherein: the third contact structure of the memory module is disposed on the second PCB near the plurality of inner edges; the PCB system includes a plurality of interposers disposed around the main IC chip between the second contact structure of the IC package and the third contact structure of the memory module.

[0069] Example 8: A PCB system according to any one of Examples 1-7, wherein: the second contact structure of the IC package is disposed on the package substrate surrounding the IC chip.

[0070] Example 9: A PCB system according to any one of Examples 1-8, wherein: the first PCB has a first number of layers; and the second PCB includes a second number of layers, the second number being less than the first number.

[0071] Example 10: A PCB system according to any one of Examples 1-9, wherein: the main IC chip includes: a processor; a plurality of electrical components disposed on the first PCB; and the processor i) is interfaced with one or more memory IC chips of the memory module via a second contact structure disposed on the top surface of the package substrate and the interposer, and ii) is interfaced with the plurality of electrical components disposed on the first PCB via the second contact structure disposed on the bottom surface of the package substrate.

[0072] Example 11: The PCB system according to any one of Examples 1-10, wherein: the first contact structure disposed on the bottom surface of the packaging substrate includes a ball grid array (BGA) contact structure.

[0073] Example 12: According to the PCB system of Example 11, wherein: the first density of the BGA contact structure disposed on the bottom surface of the packaging substrate is less than the second density of the second contact structure disposed on the top surface of the packaging substrate.

[0074] Example 13: A method for assembling a printed circuit board (PCB) system, comprising: mounting an integrated circuit (IC) package onto a first PCB to electrically couple a first contact structure on the bottom surface of a package substrate of the IC package to the first PCB, the IC package including a main IC chip; stacking and aligning a memory module on the IC package, the memory module including: i) a second PCB, ii) one or more memory IC chips disposed on the second PCB, and iii) a second contact structure disposed on the bottom surface of the second PCB; and electrically coupling the second contact structure disposed on the bottom surface of the second PCB of the memory module to a third contact structure disposed on the top surface of the package substrate.

[0075] Example 14: The method according to Example 13 further includes: providing an interposer between the second contact structure and the third contact structure on the bottom surface of the second PCB of the memory module to interconnect the second contact structure of the memory module with the third contact structure on the top surface of the packaging substrate.

[0076] Example 15: The method according to Example 14 further includes: applying a compressive force to press the memory module and the IC package together, so that the interposer electrically connects the second contact structure of the memory module to the third contact structure of the IC package.

[0077] Example 16: The method according to Example 15, wherein applying the compressive force includes: tightening the bolts to apply the compressive force.

[0078] Example 17: The method according to any one of Examples 13-16, wherein: the first contact structure disposed on the bottom surface of the package substrate includes a ball grid array (BGA) contact structure; and mounting the IC package to the first PCB includes: performing a reflow soldering process to connect the BGA contact structure to the first PCB.

[0079] Example 18: The method according to any one of Examples 13-17, wherein: the memory module includes a plurality of individual memory sub-modules, and the second PCB includes a plurality of individual second PCBs respectively corresponding to the plurality of individual memory sub-modules, each individual second PCB having one or more memory IC chips disposed on the individual second PCB, and each individual second PCB having a subset of the second contact structures disposed on the bottom surface of the individual second PCB; stacking and aligning the memory modules on the IC package includes stacking and aligning each individual memory sub-module on the IC package; and electrically coupling the second contact structures of the memory modules to the third contact structures of the package substrate includes: electrically coupling each subset of the second contact structures of each memory sub-module to a corresponding subset of the third contact structures of the package substrate.

[0080] Example 19: The method according to any one of Examples 13-17, wherein: the memory module includes an integral second PCB, wherein the second contact structure is disposed on the bottom surface of the integral second PCB; and the third contact structure for electrically coupling the second contact structure of the memory module to the packaging substrate includes: electrically coupling the second contact structure disposed on the bottom surface of the integral second PCB of the memory module to the third contact structure of the packaging substrate.

[0081] Example 20: The method according to any one of Examples 13-19, wherein: stacking and aligning memory modules on an IC package includes stacking and aligning processor-free memory modules on an IC package.

[0082] Although the invention has been described with reference to specific embodiments, these embodiments are merely illustrative and not limiting of the invention. Changes, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention.

Claims

1. A printed circuit board (PCB) system, comprising: A first PCB having a first number of layers; An integrated circuit (IC) package includes: i) a package substrate, ii) a main IC chip electrically coupled to the top surface of the package substrate, iii) a first contact structure disposed on the bottom surface of the package substrate and electrically coupled to the first PCB, and iv) a second contact structure disposed on the top surface of the package substrate. A memory module includes: i) a second PCB having a second number of layers, the second number being less than the first number; ii) one or more memory IC chips disposed on the top surface of the second PCB; and iii) a third contact structure disposed on the bottom surface of the second PCB; and An interposer is disposed between the second contact structure of the IC package and the third contact structure of the memory module for electrically coupling the second contact structure of the IC package to the third contact structure of the memory module.

2. The PCB system of claim 1, wherein the interposer is configured to provide a compression contact on at least one side of the interposer to electrically couple the second contact structure of the IC package to the third contact structure of the memory module.

3. The PCB system according to claim 1, wherein: The memory module includes multiple separate memory sub-modules; as well as The second PCB includes a plurality of separate second PCBs corresponding to the plurality of separate memory sub-modules, each separate second PCB having one or more memory IC chips disposed on the top surface of the separate second PCB, and iii) a subset of third contact structures disposed on the bottom surface of the separate second PCB.

4. The PCB system of claim 1, wherein the memory module comprises an integral second PCB.

5. The PCB system according to claim 1, wherein: The IC package includes a cover that surrounds the main IC chip and leaves the second contact structure disposed on the top surface of the package substrate uncovered; The second PCB of the memory module includes: i) a plurality of outer edges and ii) a plurality of inner edges, the plurality of inner edges defining openings; as well as The cover of the IC package is disposed within the opening defined by the plurality of inner edges of the second PCB.

6. The PCB system according to claim 5, wherein: The cover surrounding the main IC chip includes a heat sink; The heat sink is disposed within the opening defined by the plurality of inner edges of the second PCB.

7. The PCB system according to claim 5, wherein: The third contact structure of the memory module is disposed on the second PCB, close to the plurality of inner edges; as well as The PCB system includes multiple interposers disposed around the main IC chip between the second contact structure of the IC package and the third contact structure of the memory module.

8. The PCB system according to claim 7, wherein: The second contact structure of the IC package is disposed on the package substrate around the IC chip.

9. The PCB system according to claim 1, wherein: The main IC chip includes a processor; Multiple electrical components are mounted on the first PCB; as well as The processor i) is connected to one or more memory IC chips of the memory module via the second contact structure and the interposer disposed on the top surface of the package substrate, and ii) is connected to a plurality of electrical components disposed on the first PCB via the second contact structure disposed on the bottom surface of the package substrate.

10. The PCB system according to claim 1, wherein: The first contact structure disposed on the bottom surface of the packaging substrate includes a ball grid array (BGA) contact structure.

11. The PCB system according to claim 10, wherein: The first density of the BGA contact structure disposed on the bottom surface of the packaging substrate is less than the second density of the second contact structure disposed on the top surface of the packaging substrate.

12. A method for assembling a printed circuit board (PCB) system, comprising: An integrated circuit (IC) package is mounted onto a first PCB to electrically couple a first contact structure on the bottom surface of the package substrate of the IC package to the first PCB, the IC package including a main IC chip, wherein the first PCB has a first number of layers; The memory modules are stacked and aligned on the IC package, the memory modules comprising: i) a second PCB having a second number of layers, the second number being less than a first number; ii) one or more memory IC chips disposed on the second PCB; and iii) a second contact structure disposed on the bottom surface of the second PCB, wherein a third contact structure is disposed on the top surface of the package substrate. as well as An interpolator is provided between the second contact structure and the third contact structure to electrically interconnect the second contact structure of the memory module with the third contact structure disposed on the top surface of the packaging substrate.

13. The method of claim 12, further comprising: A compressive force is applied to press the memory module and the IC package together so that the interposer electrically connects the second contact structure of the memory module to the third contact structure of the IC package.

14. The method of claim 13, wherein applying the compressive force comprises: Tighten the bolts to apply the compressive force.

15. The method of claim 12, wherein: The first contact structure disposed on the bottom surface of the packaging substrate includes: a ball grid array (BGA) contact structure; and Mounting the IC package onto the first PCB includes performing a reflow soldering process to connect the BGA contact structure to the first PCB.

16. The method of claim 12, wherein: The memory module includes multiple individual memory sub-modules, and the second PCB includes multiple individual second PCBs corresponding to the multiple individual memory sub-modules respectively. Each individual second PCB has one or more memory IC chips disposed on the individual second PCB, and each individual second PCB has a subset of the second contact structures disposed on the bottom surface of the individual second PCB. Stacking and aligning the memory modules on the IC package includes: stacking and aligning each individual memory sub-module on the IC package; and Electrically coupling the second contact structure of the memory module to the third contact structure of the packaging substrate includes electrically coupling each subset of the second contact structure of each memory submodule to a corresponding subset of the third contact structure of the packaging substrate.

17. The method of claim 12, wherein: The memory module includes an integral second PCB, and the second contact structure is disposed on the bottom surface of the integral second PCB; as well as Electrically coupling the second contact structure of the memory module to the third contact structure of the packaging substrate includes: electrically coupling the second contact structure disposed on the bottom surface of the second PCB of the integral memory module to the third contact structure of the packaging substrate.

18. The method according to claim 12, wherein: Stacking and aligning the memory modules on the IC package includes stacking and aligning processor-free memory modules on the IC package.

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