Power supply semiconductor integrated circuits

Abstract

The present invention provides a semiconductor integrated circuit for power supply. In a power supply IC having a circuit for detecting short-circuit anomalies and a thermal shutdown circuit, it is possible to avoid missing a notification when an external resistor falls off a terminal. The power supply semiconductor integrated circuit is provided with: a first transistor, which forms a current mirror circuit with an output transistor; a short-circuit anomaly detection circuit, which detects the short-circuit state of a voltage output terminal based on the voltage of a resistor element connected in series with the first transistor; and a first output terminal, which is used to output the detection result of the short-circuit anomaly detection circuit to the outside. Even if the current limit value of the current limiting circuit is set within the current detection range of the short-circuit anomaly detection circuit, the short-circuit anomaly detection circuit can detect the short-circuit state of the voltage output terminal even when the current limiting circuit limits the current.

Description

Technical Field

[0001] The present invention relates to a technology effectively utilized in a power supply semiconductor integrated circuit (power supply IC) constituting a voltage regulator such as a series regulator that converts a DC voltage or a power switch that directly supplies or cuts off the voltage of a power supply device to a load. Background Art

[0002] As a power supply device that controls a transistor provided between a DC voltage input terminal and an output terminal to output a DC voltage of a desired potential, there is a series regulator (hereinafter simply referred to as a regulator).

[0003] In-vehicle regulators typically connect to in-vehicle electronic devices such as car navigation systems via connectors. Consequently, the connectors can become dislodged due to vehicle body vibration, causing the power supply output terminals to open or shorting within the electronic device serving as the load. Therefore, in-vehicle regulators are required to have a function for detecting these abnormal conditions.

[0004] So, for example Figure 8 As shown, an invention related to a semiconductor integrated circuit for a regulator (regulator IC) is proposed, in which a comparator CMP1 for detecting an open-circuit abnormality detection for detecting an open-circuit state of an output terminal and a comparator CMP2 for detecting a short-circuit abnormality detection are provided, and abnormality detection signals Err_op and Err_sc are generated and output from the output terminals (Patent Documents 1 and 2).

[0005] Furthermore, the inventions described in Patent Documents 1 and 2 also disclose embodiments of a regulator IC ( Figure 8 ), the output of the comparator CMP2 for short-circuit abnormality detection and the output of the thermal shutdown circuit TSD are obtained through an OR gate 18, and the transistor Q6 is turned on / off, thereby outputting the abnormality detection signal Err_sc.

[0006] exist Figure 8 The regulator IC shown is provided with terminals P1 and P2 for connecting an external resistor Rop for open-circuit abnormality detection and an external resistor Rsc for short-circuit abnormality detection. When resistors Rop and Rsc are normally connected to terminals P1 and P2, abnormality detection signals Err_op and Err_sc as shown in Table 1 below are output according to the detection status.

[0007] However, if the external resistor Rop for open circuit abnormality detection is disconnected from the terminal P1, abnormality detection signals Err_op and Err_sc as shown in Table 2 are output. If the external resistor Rsc for short circuit abnormality detection is short-circuited, abnormality detection signals Err_op and Err_sc as shown in Table 3 are output.

[0008] [Table 1]

[0009]

[0010] [Table 2]

[0011]

[0012] [Table 3]

[0013]

[0014] Comparing Table 1 with Table 2 and Table 3 reveals that when the thermal shutdown circuit TSD operates with the external resistor Rop disconnected from terminal P1, the abnormality detection signals Err_op and Err_sc output "H, L" as shown in Table 1, where they should output "L, L." Furthermore, when the external resistor Rsc for short-circuit abnormality detection is short-circuited, and a short-circuit abnormality occurs in the output terminal or load device, the abnormality detection signals Err_op and Err_sc output "H, H" as shown in Table 3, where they should output "H, L" as shown in Table 1. This clearly presents a problem of falsely notifying the system of normal operation despite the presence of an abnormality.

[0015] Failure to accurately report that the thermal shutdown circuit TSD is operating or that a short-circuit anomaly has occurred at the output terminal could lead to fatal damage to the power supply, and is therefore desirable to avoid. On the other hand, referring to Table 2, even if an open-circuit anomaly occurs at the output terminal while the external resistor Rop is open, "H, H" will be output where "L, H" should be. However, an open-circuit anomaly at the output terminal only causes the load device to stop operating and does not cause fatal damage to the power supply, so this is tolerated.

[0016] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-45096

[0017] Patent Document 2: Japanese Patent Application Laid-Open No. 2018-55545 Summary of the Invention

[0018] The present invention has been developed with the aforementioned challenges in mind. Its purpose is to prevent omission of notification regarding the operation of the thermal shutdown circuit and the occurrence of a short circuit in an output terminal in a power supply IC such as a regulator IC or a power switch IC that includes a circuit for detecting short-circuit abnormalities in the output terminal and a thermal shutdown circuit, if an external resistor is removed from the terminal.

[0019] Another object of the present invention is to enable a circuit having a finite element characteristic to be used as the current limiting circuit in a power supply IC (regulator IC, power switch IC) having a current limiting circuit.

[0020] To achieve the above-mentioned object, the present invention provides a semiconductor integrated circuit for power supply, comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; a control circuit for controlling the output transistor based on an output feedback voltage; and a current limiting circuit for limiting an output current flowing through the output transistor so that the output current does not exceed a predetermined value. The semiconductor integrated circuit for power supply comprises:

[0021] a first transistor, which forms a current mirror circuit with the output transistor;

[0022] a short-circuit abnormality detection circuit that detects a short-circuit state of the voltage output terminal based on a voltage of a resistance element connected in series with the first transistor; and

[0023] a first output terminal for outputting the detection result of the short-circuit abnormality detection circuit to the outside;

[0024] The current limit value of the current limiting circuit is set within the current detection range of the short-circuit abnormality detection circuit. Even in a state where the current limiting circuit limits the current, the short-circuit abnormality detection circuit can detect the short-circuit state of the voltage output terminal.

[0025] With the power supply semiconductor integrated circuit having the above-described structure, even if a resistor connected in series with a transistor constituting a current mirror circuit with an output transistor short-circuits, the current limiting circuit can detect the short-circuit condition and notify the external user of the abnormality. Furthermore, the short-circuit abnormality detection circuit can detect the short-circuit condition of the voltage output terminal even when the current limiting circuit is limiting current. This allows the use of a circuit having a "f"-shaped characteristic as the current limiting circuit, thereby protecting load equipment. Furthermore, the detection value or detection range of the short-circuit abnormality detection circuit can be set to a higher current, thereby expanding the practical range of the output current.

[0026] Another invention of the present application is a semiconductor integrated circuit for power supply, comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; a control circuit for controlling the output transistor based on an output feedback voltage; and a current limiting circuit for limiting an output current flowing through the output transistor so that the output current does not exceed a predetermined value. The semiconductor integrated circuit for power supply comprises:

[0027] a first transistor, which forms a current mirror circuit with the output transistor;

[0028] a short-circuit abnormality detection circuit that detects a short-circuit state of the voltage output terminal based on a voltage of a resistance element connected in series with the first transistor; and

[0029] a first output terminal, configured to output a detection result of the short-circuit abnormality detection circuit to the outside;

[0030] a second transistor, which forms a current mirror circuit with the output transistor;

[0031] an open-circuit abnormality detection circuit that detects an open state of the voltage output terminal based on a voltage of a resistance element connected in series with the second transistor;

[0032] a second output terminal for outputting a detection result of the open circuit abnormality detection circuit to the outside; and

[0033] a thermal shutdown circuit that stops the operation of the control circuit when the detected temperature is higher than a predetermined temperature;

[0034] outputting a signal indicating an abnormality from the first output terminal based on a signal obtained by taking a logical sum of an output signal of the thermal shutdown circuit and an output signal of the short-circuit abnormality detection circuit,

[0035] A signal obtained by taking a logical sum of an output signal of the thermal shutdown circuit and an output signal of the open abnormality detection circuit is output from the second output terminal.

[0036] According to the power supply semiconductor integrated circuit having the above configuration, even if the resistor connected in series with the second transistor is open, the abnormal state output from the first and second output terminals can be accurately notified as desired when the thermal shutdown circuit is activated.

[0037] In addition, preferably, the semiconductor integrated circuit for power supply has: a delay circuit, which delays the output of the short-circuit abnormality detection circuit, and outputs a signal indicating abnormality from the first output terminal based on a signal obtained by taking the output of the delay circuit and the output of the short-circuit abnormality detection circuit before the delay.

[0038] According to this configuration, it is possible to prevent the short-circuit abnormality detection circuit from erroneously detecting the inrush current flowing to charge the output capacitor when the power supply semiconductor integrated circuit starts operating as a short-circuit abnormality of the output terminal.

[0039] Furthermore, it is preferable that the power supply semiconductor integrated circuit includes a delay circuit that delays the output of the short-circuit abnormality detection circuit and the output of the open-circuit abnormality detection circuit.

[0040] outputting a signal indicating an abnormality from the first output terminal based on a signal obtained by taking a logical sum of the output of the delay circuit and the output of the short-circuit abnormality detection circuit before the delay,

[0041] A signal indicating an abnormality is output from the second output terminal based on a signal obtained by taking a logical product of an output of the delay circuit and an output of the open abnormality detection circuit before delay.

[0042] With the above configuration, in a power supply semiconductor integrated circuit including an output terminal short-circuit abnormality detection circuit and an open-circuit abnormality detection circuit, it is possible to prevent the short-circuit abnormality detection circuit from erroneously detecting an inrush current as an output terminal short-circuit abnormality.

[0043] Furthermore, preferably, the power supply semiconductor integrated circuit includes: a first overvoltage protection circuit that detects an abnormal state and stops output;

[0044] When the first overvoltage protection circuit is actuated, the first output terminal and the second output terminal are changed to a state indicating an abnormality based on a signal indicating an actuation state outputted from the first overvoltage protection circuit.

[0045] According to this configuration, in a power supply semiconductor integrated circuit equipped with an overvoltage protection circuit, when the overvoltage protection circuit is activated, the occurrence of an abnormality can be notified to the outside via the first output terminal and the second output terminal. Here, as an example of an overvoltage protection circuit, there is an output overvoltage protection circuit that detects an overvoltage state of the output voltage outputted from the voltage output terminal and stops the output.

[0046] Furthermore, it is preferable that the power supply semiconductor integrated circuit includes: an external terminal to which the feedback voltage is input; and

[0047] The second overvoltage protection circuit detects an overvoltage state of the feedback voltage and stops the output.

[0048] When the second overvoltage protection circuit is activated, the first output terminal and the second output terminal are changed to a state indicating an abnormality based on a signal indicating an activation state output from the second overvoltage protection circuit.

[0049] According to this configuration, in a power supply semiconductor integrated circuit including an overvoltage protection circuit that detects an overvoltage state of a feedback voltage and stops output, when the overvoltage protection circuit is activated, occurrence of an abnormality can be reported externally through the first and second output terminals.

[0050] According to the present invention, a power supply semiconductor integrated circuit having a circuit for detecting short-circuit and open-circuit abnormalities at output terminals and a thermal shutdown circuit can avoid missing a notification regarding the operation of the thermal shutdown circuit or a short-circuit at the output terminals when an external resistor is removed from the terminals. Furthermore, a power supply semiconductor integrated circuit having a current limiting circuit can utilize a circuit having a "f"-shaped characteristic as the current limiting circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a circuit configuration diagram showing one embodiment of a regulator IC to which the present invention is applied.

[0052] Figure 2 (A) is a characteristic diagram showing the characteristics of a current limiting circuit in a conventional regulator IC, and (B) is a characteristic diagram showing the characteristics of a current limiting circuit constituting the regulator IC according to the embodiment.

[0053] Figure 3 (A) is a diagram showing the relationship between the short-circuit abnormality detection range and the current limit value of a conventional regulator IC, and (B) is a diagram showing the relationship between the short-circuit abnormality detection range and the current limit value of a regulator IC according to an embodiment.

[0054] Figure 4 This is a circuit diagram showing a specific example of a current limiting circuit constituting the regulator IC according to the embodiment.

[0055] Figure 5 This is a circuit configuration diagram showing a first modified example of the regulator IC according to the embodiment.

[0056] Figure 6 This is a circuit configuration diagram showing a second modified example of the regulator IC according to the embodiment.

[0057] Figure 7 (A) is a circuit diagram showing a structural example of a power switch IC, and (B) is a circuit diagram showing a structural example of an IC in the case where the present invention is applied to a power switch IC having an open circuit abnormality detection circuit and a short circuit abnormality detection circuit.

[0058] Figure 8 This is a circuit configuration diagram showing a configuration example of a conventional regulator IC.

[0059] Explanation of symbols

[0060] 10...Regulator IC, 11...Error amplifier, 12...Reference voltage circuit, 13...Bias circuit, 14...Current limiter circuit, 15...Thermal shutdown circuit, 16...Delay circuit, 19A, 19B...Overvoltage protection circuit, CMP1...Open-circuit abnormality detection comparator, CMP2...Short-circuit abnormality detection comparator, Q1...Voltage control transistor (output transistor), Q2, Q3...Current mirror transistors, Cd...Delay capacitor DETAILED DESCRIPTION

[0061] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0062] Figure 1 An embodiment of a series regulator as a DC power supply device to which the present invention is applied is shown. Figure 1 In FIG. 1 , a portion surrounded by a chain line is formed as a semiconductor integrated circuit (regulator IC) 10 on a semiconductor chip such as single crystal silicon. A capacitor Co is connected to an output terminal OUT of the regulator IC 10 to function as a DC power supply device that supplies a stable DC voltage.

[0063] In the regulator IC10 of this embodiment, as shown in FIG. Figure 1 As shown, a voltage control transistor Q1, composed of a P-channel MOS transistor, is connected between a voltage input terminal IN, to which a DC voltage VDD is applied, and an output terminal OUT. Bleeder resistors R1 and R2 are connected in series between the output terminal OUT and a ground line, to which a ground potential GND is applied, to divide the output voltage Vout. Furthermore, the reference voltages for CMP1 and CMP2 can be configured to be different voltages.

[0064] The voltage VFB divided by the output voltage dividing resistors R1 and R2 is fed back to the non-inverting input terminal of the error amplifier 11, which serves as an error amplifier circuit for controlling the gate terminal of the voltage control transistor Q1. The error amplifier 11 then controls the voltage control transistor Q1 based on the potential difference between the output feedback voltage VFB and a predetermined reference voltage Vref, thereby controlling the output voltage Vout to a desired potential.

[0065] The regulator IC 10 of this embodiment also includes a reference voltage circuit 12 for generating a reference voltage Vref applied to the inverting input terminal of the error amplifier 11; a bias circuit 13 for directing an operating current through the error amplifier 11 and the reference voltage circuit 12; a current limiter 14 connected to the gate terminal of the voltage control transistor Q1 to limit the output current; and a thermal shutdown circuit 15 for stopping the operation of the error amplifier 11 and turning off the transistor Q1 if the chip temperature rises above a predetermined temperature. CE is an external terminal for inputting a signal that turns the IC on / off.

[0066] The reference voltage circuit 12 can be composed of a series resistor and a Zener diode, etc. The bias circuit 13 is provided with a function for supplying or cutting off the bias current to the error amplifier 11 based on a control signal input to the external terminal CE from an external microcomputer (CPU), etc. When the output current increases and the output voltage decreases due to a load abnormality, etc., and the error amplifier 11 attempts to reduce the gate voltage to allow more current to flow through the transistor Q1, the current limiting circuit 14 applies a clamp to limit the output current Io so that the drain current does not increase beyond a predetermined level.

[0067] Furthermore, in the regulator IC 10 of this embodiment, transistors Q2 and Q3 are provided in parallel with the voltage control transistor Q1, forming a current mirror circuit with Q1. The gate terminals of these transistors Q2 and Q3, which serve as control terminals, are applied with the same voltage as the voltage applied to the gate terminal of the voltage control transistor Q1. Consequently, a current proportional to the drain current of Q1 (a current of 1 / N) flows through Q2 and Q3, based on the element size ratio N. If transistor Q1 is formed by connecting N transistors of the same size in parallel, and Q2 and Q3 each consist of a single transistor, currents proportional to the number of elements flow through them.

[0068] In addition, in the regulator IC10 of this embodiment, an external terminal P1 is provided for connecting a resistor Rop for performing current-voltage conversion outside the chip, and an external terminal P2 is provided for connecting a resistor Rsc. The drain terminal of the current mirror transistor Q2 is connected to the external terminal P1, and the drain terminal of the current mirror transistor Q3 is connected to the external terminal P2.

[0069] Furthermore, there are provided an open-circuit abnormality detection comparator CMP1, whose inverting input terminal is connected to the external terminal P1 and whose non-inverting input terminal has a reference voltage Vref1 applied thereto; and a short-circuit abnormality detection comparator CMP2, whose non-inverting input terminal is connected to the external terminal P2 and whose inverting input terminal has a reference voltage Vref1 applied thereto. While not particularly limited, comparators with hysteresis characteristics are used for the open-circuit abnormality detection comparator CMP1 and the short-circuit abnormality detection comparator CMP2.

[0070] The resistance value of the external resistor Rop is set so that when a relatively small open-circuit abnormality detection current flows through the voltage control transistor Q1, the voltage across the terminals of the resistor becomes equal to the reference voltage Vref1. On the other hand, the resistance value of the external resistor Rsc is set so that when a relatively large short-circuit abnormality detection current flows through the voltage control transistor Q1, the voltage across the terminals of the resistor becomes equal to the reference voltage Vref1.

[0071] Thus, in this embodiment, the current value for detecting open circuit anomalies and short circuit anomalies is set by external resistors Rop and Rsc, so the detection current value (threshold) can be arbitrarily set according to the system used, and the same voltage value can be used as the reference voltage Vref1 used by comparators CMP1 and CMP2, which can simplify the circuit for generating the reference voltage.

[0072] Furthermore, the regulator IC 10 of this embodiment includes an OR gate G1 that obtains the logical OR of the output OP_OUT of the comparator CMP1 and the output TSD_OUT of the thermal shutdown circuit 15, and an OR gate G2 that obtains the logical OR of the output SC_OUT of the comparator CMP2, the output CL_OUT of the current limiter circuit 14, and the output TSD_OUT of the thermal shutdown circuit 15. Here, the output CL_OUT of the current limiter circuit 14 is a signal indicating that the current limiter circuit 14 is operating, and the output TSD_OUT of the thermal shutdown circuit 15 is a signal indicating that the thermal shutdown circuit 15 is operating.

[0073] Furthermore, an N-channel MOS transistor Q5 is provided, the gate terminal of which receives the output of the OR gate G1, and an N-MOS transistor Q6 is provided, the gate terminal of which receives the output of the OR gate G2. Furthermore, the regulator IC is provided with external terminals P3 and P4 for outputting signals to an external CPU, etc., in an open-drain manner. The drain terminal of the transistor Q5 is connected to the external terminal P3, and the drain terminal of the transistor Q6 is connected to the external terminal P4.

[0074] exist Figure 8In the existing IC, when the thermal shutdown circuit TSD is activated, the abnormality detection signals Err_op and Err_sc should output "L, L" as shown in Table 1. When the thermal shutdown circuit TSD is activated in the state where the position resistor Rop for open circuit abnormality detection is detached from the terminal P1, the output is "H, L" as shown in Table 2.

[0075] In contrast, in the regulator IC10 of the present embodiment, as described above, an OR gate G1 is provided for taking the logical OR of the output OP_OUT of the comparator CMP1 and the output TSD_OUT of the thermal shutdown circuit 15. Therefore, when the thermal shutdown circuit is activated with the external resistor Rop disconnected from the terminal P1, "L, L" can be output as the abnormality detection signals Err_op and Err_sc, as shown in Table 4.

[0076] In addition, Figure 8 In conventional ICs, when a short-circuit abnormality occurs at the output terminal, "H" and "L" should be output as abnormality detection signals Err_op and Err_sc, as shown in Table 1. However, when a short-circuit abnormality occurs while the external resistor Rsc for short-circuit abnormality detection is short-circuited, "H" and "H" are output, as shown in Table 3. In contrast, in the regulator IC10 of this embodiment, as described above, the output CL_OUT of the current limiter circuit 14 is input to the OR gate G2. Therefore, regardless of the output SC_OUT of the comparator CMP2, the current limiter circuit 14 operates when the output terminal OUT is short-circuited, allowing "H" and "L" to be output as abnormality detection signals Err_op and Err_sc, as shown in Table 5.

[0077] [Table 4]

[0078]

[0079] [Table 5]

[0080]

[0081] Furthermore, in the regulator IC 10 of this embodiment, even if the current limiting circuit 14 Figure 2 The "F"-shaped characteristic shown in (B) of FIG1 is used to reduce the output current Io. Even when the current limiting circuit 14 is activated when the output terminal OUT is short-circuited, a low-level abnormality detection signal Err_sc can be outputted via the output CL_OUT. Furthermore, this can expand the practical operating range of the output current Io. The reasons for this are explained below.

[0082] exist Figure 8In the conventional regulator IC shown in FIG. 1 , if the current limit value is within the detection range of the short-circuit abnormality detection circuit (comparator CMP2) having a hysteresis characteristic, the current limit circuit will operate and cannot accurately detect and notify the short-circuit abnormality of the output terminal. Figure 3 As shown in (A), the current limit value needs to be set to a larger current value away from the short-circuit detection range, and as a characteristic of the current limiting circuit, it is set to Figure 2 The drooping characteristics shown in (A) are shown.

[0083] In contrast, in the regulator IC 10 of this embodiment, even if the current limiting circuit 14 is in operation, the short-circuit abnormality of the output terminal can be accurately detected and notified, so the current limit value can be set within the short-circuit abnormality detection range. Figure 3 As shown in (B), the actual use range of the output current Io can be expanded. In addition, by using a circuit having a "フ"-shaped characteristic as the current limiting circuit 14, the load device can be protected from the influence of overcurrent.

[0084] Figure 4 2 shows a specific example of the current limiting circuit 14 that outputs a signal CL_OUT having a "F"-shaped characteristic and changes to a high level during circuit operation. Figure 4 The current limiting circuit 14 includes: a main circuit portion 14A that performs the original operation of the current limiting circuit; and a signal generating portion 14B that generates and outputs a signal CL_OUT that notifies the main circuit portion 14A that it is operating. Figure 4 The current mirror circuit shown is an example and is not limited to the above-described configuration.

[0085] like Figure 4 As shown, the main circuit portion 14A of the current limiting circuit 14 of this embodiment includes a MOS transistor Q11 and a resistor R11 connected in series between a power supply voltage terminal VDD and a ground point; a resistor R12 and a MOS transistor Q12 connected in series between the power supply voltage terminal VDD and a ground point; and a MOS transistor Q13 connected in series between the power supply voltage terminal VDD and the gate terminal of the MOS transistor Q11, with the gate terminal connected to a connection node N2 between R12 and Q12. Of these transistors, Q12 is an N-MOS transistor, while Q11 and Q13 are P-MOS transistors.

[0086] MOS transistor Q11 is connected to Figure 1 The voltage control transistor Q1 is connected to form a current mirror circuit, allowing a current to flow that is proportionally reduced to the current (Io) flowing through Q1. Furthermore, the gate terminal of MOS transistor Q12 is connected to the connection node N1 between transistor Q11 and resistor R11, and Q12 and resistor R12 operate as a source-grounded amplifier circuit.

[0087] When output current Io increases in main circuit unit 14A, the current flowing through resistor R11 increases, raising the voltage at connection node N1. This voltage is amplified by the source-grounded amplifier circuit formed by Q12 and resistor R12. Furthermore, when transistor Q13 turns on, it increases the gate voltage of voltage control transistor Q1, reducing the output current and thus providing overcurrent protection.

[0088] Signal generating unit 14B includes a MOS transistor Q14 and a constant current source I1 connected in series between a power supply voltage terminal VDD and a ground point; and inverters INV1 and INV2 connected to a connection node N3 between transistor Q14 and constant current source I1. Transistor Q14 and the gate terminal of transistor Q13 of main circuit unit 14A are connected to each other to form a current mirror circuit. During current limiting operation in main circuit unit 14A, transistor Q14 turns on, increasing the potential at node N3. The output CL_OUT of inverter INV2 goes high, providing a signal indicating that current limiting circuit 14 is operating.

[0089] (Variation)

[0090] Next, use Figure 5 as well as Figure 6 A modification of the regulator IC of the above embodiment will be described.

[0091] Figure 5 2 shows the structure of a regulator IC according to a first modification. Figure 5 The modified example shown is provided with a delay circuit 16 for delaying the abnormal detection signals OP_OUT and SC_OUT, an OR gate G3 for obtaining the logical OR of the output SC_OUT of the above-mentioned comparator CMP2 and the output CL_OUT of the current limiting circuit 14, and a NOR gate G4 for obtaining the logical OR of the output of the OR gate G3 and the output OP_OUT of the comparator CMP1, and is configured to input the signal obtained by obtaining the logical AND of the signal after delay by the delay circuit 16 and the signal before delay into the OR gates G1 and G2.

[0092] Thus, by providing the delay circuit 16 , it is possible to prevent an erroneous detection pulse from occurring in the output of the comparator CMP2 for detecting a short-circuit abnormality due to a relatively large inrush current flowing through the capacitor Co at the output terminal when the IC is started.

[0093] Delay circuit 16 comprises a constant current source I2, a switching transistor Qs connected in series with constant current source I2, and a comparator CMP3 that receives the potential at a connection node N0 between constant current source I2 and transistor Qs and a predetermined reference voltage Vref2. The output voltage of NOR gate G4 is input to the gate terminal of transistor Qs. Furthermore, an external terminal CD connected to connection node N0 is provided. By connecting an external capacitor Cd charged by constant current source I1 to this terminal CD, the delay time can be increased without increasing chip size.

[0094] In addition, the delay circuit 16 is followed by an AND gate G5 that obtains the logical AND of the output of the delay circuit 16 and the output OP_OUT of the comparator CMP1 before the delay; and an AND gate G6 that obtains the logical AND of the output of the delay circuit 16 and the output of the OR gate G3.

[0095] In the normal operating state of the delay circuit 16, in which the outputs of the comparators CMP1 and CMP2 and the output CL_OUT of the current limiting circuit 14 are low, the output of the OR gate G3 is low, and the output of the NOR gate G4 is high. A high level is applied to the gate terminal of the transistor Qs through the NOR gate G4, causing the transistor to be in a conductive state, and the capacitor Cd to be discharged.

[0096] Then, when comparator CMP1 detects an open state at its output terminal or comparator CMP2 detects a short state at its output terminal, and the output of either comparator changes to a high level, the output of NOR gate G4 changes to a low level, turning off transistor Qs. Furthermore, when current limiter circuit 14 operates and its output CL_OUT changes to a high level, the output of NOR gate G4 also changes to a low level, turning off transistor Qs.

[0097] As a result, capacitor Cd is gradually charged, and the potential of connection node N0 gradually rises. Then, after a predetermined period of time, when the potential of connection node N0 becomes higher than reference voltage Vref2 of comparator CMP3, the output of comparator CMP3 changes from low to high. Furthermore, when comparator CMP1 detects an open-circuit abnormality at its output terminal, the output of AND gate G5 changes to high, turning on transistor Q5 and causing the open-circuit abnormality detection signal Err_op output from external terminal P3 to change from high to low.

[0098] Furthermore, when comparator CMP2 detects a short-circuit abnormality at its output terminal or current limiter circuit 14 activates, the output of AND gate G6 changes to a high level, transistor Q6 turns on, and the short-circuit abnormality detection signal Err_sc output from external terminal P4 changes from a high level to a low level. Furthermore, the delay time of delay circuit 16 is set to a time slightly longer than the period during which the inrush current flows. By providing delay circuit 16 and AND gates G3 and G4 as described above, erroneous detection pulses associated with inrush current detection are prevented in short-circuit abnormality detection comparator CMP2.

[0099] Figure 6 The structure of a regulator IC according to a second modified example is shown.

[0100] Figure 6 The second variant shown is the same as Figure 5 The first modified example shown has three differences.

[0101] The first difference is that Figure 6 In the second modified example, resistors R1 and R2 for output voltage division, which divide the output voltage Vout to generate the feedback voltage VFB, are connected to the output terminal OUT as external components. The IC is provided with an external terminal FB for inputting the feedback voltage VFB. By making resistors R1 and R2 external components, the ratio of resistors R1 and R2 can be changed externally from the IC, thereby adjusting the voltage value of the output voltage Vout.

[0102] The second difference from the first variant is that Figure 6 In the second variant example, an overvoltage protection circuit (OVP) 19A is provided for detecting an overvoltage state of the output voltage Vout and stopping the output, and an overvoltage protection circuit (FB_OVP) 19B is provided for detecting an overvoltage state of the voltage VFB of the external terminal FB and stopping the output. By providing these circuits, the IC can be protected from the influence of the overvoltage state of the external terminal FB.

[0103] The third difference is that Figure 6 In the second modified example, an OR gate G7 is provided that receives as inputs a signal OVP_OUT indicating that overvoltage protection circuit 19A has activated, a signal FB_OVP_OUT indicating that overvoltage protection circuit 19B has activated, and the output TSD_OUT of thermal shutdown circuit 15. The output of OR gate G7 is input to OR gates G1 and G2. This allows notification to the outside that overvoltage protection circuit 19A or 19B has activated.

[0104] Table 6 below shows the relationship between each state of the regulator IC and the abnormality detection signals Err_op and Err_sc according to the second modification.

[0105] [Table 6]

[0106]

[0107] In addition, in the above embodiment, an example in which the present invention is applied to a regulator IC is shown, but the present invention can also be applied to Figure 7 As shown in (A), a power switch IC 20 is used to directly supply or cut off the voltage of a power supply device (battery, etc.) to a load. Figure 7 The power switch IC shown in (A) includes a gate control circuit 21 instead of an error amplifier. The gate control circuit 21 is designed to control the output transistor Q1 to be fully on or fully off depending on whether the control terminal CE is at a high level or a low level.

[0108] Figure 7 (B) indicates that the present invention is applied to Figure 7 (A) Example of a power switch IC. Figure 7 Similarly, (B) can also be Figure 5 、 Figure 6 The structure of the regulator IC shown is used in Figure 7 The power switch IC of (A) can also obtain the same effects as those described in the above embodiment in such a power switch IC 20 .

[0109] The invention developed by the present inventors has been described above in detail based on the embodiments. However, the present invention is not limited to the aforementioned embodiments. For example, in the second modified example of the aforementioned embodiment, an overvoltage protection circuit (OVP) 19A for the output voltage Vout and an overvoltage protection circuit (FB_OVP) 19B for the voltage VFB at the external terminal P6 are provided. However, the present invention can also be applied to power supply ICs that include either overvoltage protection circuit. Furthermore, in the aforementioned embodiment, the comparator CMP1 for detecting an open circuit anomaly and the comparator CMP2 for detecting a short circuit anomaly have hysteresis characteristics, but comparators without hysteresis characteristics may also be used.

[0110] Furthermore, while the above embodiment shows the use of MOS transistors as transistors constituting the internal circuits of the regulator IC 10 and the power switch IC 20, bipolar transistors may be used instead of MOS transistors. Furthermore, the delay capacitor Cd may be formed on the IC chip rather than as an external component.

[0111] In addition, in the above-mentioned embodiment, as the protection circuit of the IC, the case of providing the current limiting circuit 14, the thermal shutdown circuit 15, the output voltage overvoltage protection circuit 19A and the feedback voltage overvoltage protection circuit 19B is described, but it can also be applied to a regulator IC or a power switch IC that has other protection circuits such as a circuit that detects the overvoltage state of the input voltage and stops the operation.

Claims

1. A semiconductor integrated circuit for a power supply, comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; a control circuit for controlling the output transistor based on an output feedback voltage; and a current limiting circuit for limiting an output current flowing through the output transistor so that the output current does not exceed a predetermined value, wherein: The semiconductor integrated circuit for power supply comprises: a first transistor, which forms a current mirror circuit with the output transistor; a short-circuit abnormality detection circuit that detects a short-circuit state of the voltage output terminal based on a voltage of a resistance element connected in series with the first transistor; as well as a first output terminal for outputting the detection result of the short-circuit abnormality detection circuit to the outside; The current limit value of the current limiting circuit is set within the current detection range of the short-circuit abnormality detection circuit. Even in a state where the current limiting circuit limits the current, the short-circuit abnormality detection circuit can detect the short-circuit state of the voltage output terminal.

2. A semiconductor integrated circuit for a power supply, comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; a control circuit for controlling the output transistor based on an output feedback voltage; and a current limiting circuit for limiting an output current flowing through the output transistor so that the output current does not exceed a predetermined value, wherein: The semiconductor integrated circuit for power supply comprises: a first transistor, which forms a current mirror circuit with the output transistor; a short-circuit abnormality detection circuit that detects a short-circuit state of the voltage output terminal based on a voltage of a resistance element connected in series with the first transistor; a first output terminal, configured to output a detection result of the short-circuit abnormality detection circuit to the outside; a second transistor, which forms a current mirror circuit with the output transistor; an open-circuit abnormality detection circuit that detects an open state of the voltage output terminal based on a voltage of a resistance element connected in series with the second transistor; a second output terminal, configured to output a detection result of the open circuit abnormality detection circuit to the outside; as well as a thermal shutdown circuit that stops the operation of the control circuit when the detected temperature is higher than a predetermined temperature; outputting a signal indicating an abnormality from the first output terminal based on a signal obtained by taking a logical sum of an output signal of the thermal shutdown circuit and an output signal of the short-circuit abnormality detection circuit, A signal obtained by taking a logical sum of an output signal of the thermal shutdown circuit and an output signal of the open abnormality detection circuit is output from the second output terminal.

3. The semiconductor integrated circuit for power supply according to claim 1, wherein: The power supply semiconductor integrated circuit includes a delay circuit that delays the output of the short-circuit abnormality detection circuit. A signal indicating an abnormality is output from the first output terminal based on a signal obtained by taking a logical product of an output of the delay circuit and an output of the short-circuit abnormality detection circuit before delay.

4. The semiconductor integrated circuit for power supply according to claim 2, wherein: The power supply semiconductor integrated circuit includes a delay circuit that delays the output of the short-circuit abnormality detection circuit and the output of the open-circuit abnormality detection circuit. outputting a signal indicating an abnormality from the first output terminal based on a signal obtained by taking a logical sum of the output of the delay circuit and the output of the short-circuit abnormality detection circuit before the delay, A signal indicating an abnormality is output from the second output terminal based on a signal obtained by taking a logical product of an output of the delay circuit and an output of the open abnormality detection circuit before delay.

5. The semiconductor integrated circuit for power supply according to any one of claims 1 to 4, wherein: The power supply semiconductor integrated circuit includes: a first overvoltage protection circuit that detects an abnormal state and stops output; When the first overvoltage protection circuit is actuated, the first output terminal and the second output terminal are changed to a state indicating an abnormality based on a signal indicating an actuation state outputted from the first overvoltage protection circuit.

6. The semiconductor integrated circuit for power supply according to claim 5, wherein: The first overvoltage protection circuit is an output overvoltage protection circuit that detects an overvoltage state of the output voltage output from the voltage output terminal and stops the output.

7. The semiconductor integrated circuit for power supply according to any one of claims 1 to 4, wherein: The semiconductor integrated circuit for power supply comprises: an external terminal to which the feedback voltage is input; and The second overvoltage protection circuit detects an overvoltage state of the feedback voltage and stops the output. When the second overvoltage protection circuit is activated, the first output terminal and the second output terminal are changed to a state indicating an abnormality based on a signal indicating an activation state output from the second overvoltage protection circuit.

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